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* MFC r271595, r271601, r271607, r271630:ian2014-10-261-0/+2
| | | | | | | | | | | | | | | Add compat strings for all the flavors of GIC this driver should support. Also allow the driver to attach to ofwbus as well as simplebus, some FDT data puts the root interrupt controller on the root bus. Add a common routine for parsing FDT data describing an ARM GIC interrupt. Use gic_decode_fdt() rather than a local routine to parse fdt interrupt properties. Move fdt_pic_table and fdt_fixup_table into imx6_machdep.c, which means imx6 doesn't need imx_common.c anymore. The private peripheral interrupts start at offset 16, not 0. Also, use names rather than inline mystery constants for these offsets.
* MFC 266621: Eliminte spurious interrupts caused by ARM weak memory ordering.ian2014-05-271-0/+2
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* MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,ian2014-05-141-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373, r260374, r260375 Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs. Correct license statements to reflect the fact that these files were all derived from sys/arm/mv/bus_space.c. In pmap_unmapdev(), remember the size, and use that as an argument to kva_free(), or we'd end up always passing it a size of 0 In pmap_mapdev(), first check whether a static mapping exists, Convert TI static device mapping to use the new arm_devmap_add_entry(), Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy. Eliminate use of fdt_immr_addr(), it's not needed for tegra Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make static device mappings. Retire machine/fdt.h as a header used by MI code, as its function is now obsolete. This involves the following pieces: - Remove it entirely on PowerPC, where it is not used by MD code either - Remove all references to machine/fdt.h in non-architecture-specific code (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat non-arch-specific). - Fix code relying on header pollution from machine/fdt.h includes - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource requests to its parent (nexus). This allows x86 FDT devices to allocate both memory and IO requests and removes the last notionally MI use of fdtbus_bs_tag. - On those architectures that retain a machine/fdt.h, unused bits like FDT_MAP_IRQ and FDT_INTR_MAX have been removed. Add #include <machine/fdt.h> to a few files that used to get it via pollution Enable the mv cesa security/crypto device by providing the required property in the dts source, and adding the right devices to the kernel config. Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs, related to setting up static device mappings. Since it was only used by arm/mv/mv_pci.c, it's now just static functions within that file, plus one public function that gets called only from arm/mv/mv_machdep.c. Switch RPi to using arm_devmap_add_entry() to set up static device mapping. Allow 'no static device mappings' to potentially work. Don't try to find a static mapping before calling pmap_mapdev(), that logic is now part of pmap_mapdev() and doesn't need to be duplicated here. Switch a10 to using arm_devmap_add_entry() to set up static device mapping.
* MFC r260161, r260163, r260165, r260166, r260189ian2014-05-141-0/+3
| | | | | | | | | | Add polarity and level support to ARM GIC Do not attach to PCI bridges in AHCI driver Use only mapped BIOs on ARM Fix race condition in DELAY for SP804 timer.
* MFC r258359, r258742, r258845, r259936, r259640ian2014-05-141-0/+2
| | | | | | | | | | | Apply access flags for managed and unmanaged pages properly on ARMv6/v7 Set the PGA_WRITEABLE flag when the protections indicate write access, not just when the current access is a write. Enable missing Access Flag for secondary cores on ARMv6/v7 Add identification and necessary type checks for Krait CPU cores.
* Bump max number of IRQs for Cortex-Ax family to cover Exynos5 requirement.ray2013-06-281-1/+1
| | | | Submitted by: Ruslan Bukin <br@bsdpad.com>
* Eliminate the need for an intermediate array of indices into the arrays ofian2013-01-191-0/+1
| | | | | | | | | | | interrupt counts and names, by making the names into an array of fixed-length strings that can be directly indexed. This eliminates extra memory accesses on every interrupt to increment the counts. As a side effect, it also fixes a bug that would corrupt the names data if a name was longer than MAXCOMLEN, which led to incorrect vmstat -i output. Approved by: cognet (mentor)
* Replace generic ARM11 option with more specificgonzo2012-12-201-1/+1
| | | | | | | support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
* Add support for MSI in interrupt controlller.gber2012-09-141-1/+6
| | | | | | | | MSI are implemented via software interrupt. PCIe cards will write into software interrupt register which will cause inbound shared interrupt which will be interpreted as a MSI. Obtained from: Marvell, Semihalf
* Add support for Armada XP A0.gber2012-09-141-0/+2
| | | | | | | | | | - Add functions to calculate clocks instead using hardcoded values - Update reset and timers functions - Update number of interrupts - Change name of platform from db88f78100 to db78460 - Correct DRAM size and PCI IRQ routing in dts file. Obtained from: Semihalf
* ARM11 might have more then 32 interrupts, e.g. BCM2835: 72 interruptsgonzo2012-08-251-0/+2
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* Merging projects/armv6, part 1gonzo2012-08-151-0/+5
| | | | | | | | | Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
* trim trailing whitespaceimp2012-06-131-2/+2
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* Pass the previously returned IRQ back to arm_get_next_irq() so thatmarcel2009-06-091-1/+1
| | | | | | | | | the implementation can guarantee forward progress in the event of a stuck interrupt or interrupt storm. This is especially critical for fast interrupt handlers, as they can cause a hard hang in that case. When first called, arm_get_next_irq() is passed -1. Obtained from: Juniper Networks, Inc.
* Merge WIP from p4:sam2008-12-131-1/+3
| | | | | | | | | | | | | | | | | | o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
* Introduce basic support for Marvell families of system-on-chip ARM devices:raj2008-10-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Orion - 88F5181 - 88F5182 - 88F5281 * Kirkwood - 88F6281 * Discovery - MV78100 The above families of SOCs are built around CPU cores compliant with ARMv5TE instruction set architecture definition. They share a number of integrated peripherals. This commit brings support for the following basic elements: * GPIO * Interrupt controller * L1, L2 cache * Timers, watchdog, RTC * TWSI (I2C) * UART Other peripherals drivers will be introduced separately. Reviewed by: imp, marcel, stass (Thanks guys!) Obtained from: Marvell, Semihalf
* ARM interrupts improvements.raj2008-09-111-1/+1
| | | | | | | | | | | | | - Fix nexus_setup_intr() abuse of setting up multiple IRQs in one go. Calling arm_setup_irqhandler() in loop is bogus, as there's just one cookie given from the caller and it is overwritten in each iteration so that only the last handler's cookie value prevails. - Proper intr masking/unmasking handling: the IRQ source is masked at PIC level only after the last handler has been removed from the list. Reviewed by: cognet, imp, sam, stass Obtained from: Grzegorz Bernacki gjb ! semihalf dot com
* Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connexbenno2008-06-061-0/+3
| | | | | | | | | | | | | boards. This is enough to net-boot to multiuser. Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC add-on boards. I'll be putting some instructions on how to boot this on the Gumstix boards online soon. This is still fairly rough and will be refined over time but I felt it was better to get this out there where other people can help out.
* On the AT91, we need to write on the EOI register after we handle ancognet2008-04-201-0/+1
| | | | | | | | interrupt. So, add a new function pointer, arm_post_filter, which defaults to NULL, and which will be used as the post_filter arg for intr_event_create(). Set it properly for the AT91, so that it boots again. Reported by: hps
* The iop34x has 128 interrupts.cognet2007-06-161-1/+3
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* o break newbus api: add a new argument of type driver_filter_t topiso2007-02-231-2/+2
| | | | | | | | | | | | | bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
* - MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32cognet2005-06-091-4/+4
| | | | | interrupts. - Implement teardown methods where appropriate.
* Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores providescognet2005-02-131-0/+4
| | | | | 64 irqs. This should be re-thought later.
* Start all license statements with /*-imp2005-01-051-1/+1
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* Add new functions to know which irqs are pending, and to mask and unmaskcognet2004-09-231-35/+4
| | | | | | interrupts, as these are CPU specific. If the interrupt handler is not marked as INTR_FAST, don't unmask the interrupt until it as been serviced.
* Import FreeBSD/arm kernel bits.cognet2004-05-141-0/+83
It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
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