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* opt_global.h is included automatically in the build. No need toimp2014-11-181-1/+0
| | | | | | explicitly include it in these places. Sponsored by: Netflix
* Add an elf not so kgdb detects the kernel as a FreeBSD elf file. Theandrew2014-10-181-0/+12
| | | | | | ELFNOTE macro is based on one from the FreeBSD/ARM Xen tree [1]. Obtained from: Julien Grall <julien.grall AT linaro.org> [1]
* Remove the unreferenced DATA() macro. That leaves only GET_CURTHREAD_PTR()ian2014-03-111-26/+8
| | | | | | | which was added by cognet in 2012, so remove the no-longer-applicable license stuff that referred to all the old contents, and put in a standard 2-clause BSD license (to cover the 6 lines of useful code left in here).
* Arrange for arm fork_trampoline() to return to userland via the standardian2014-03-101-208/+0
| | | | | | | swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. That means that now all references to the PUSH/PULLFRAME and DO_AST macros are localized to exception.S, so move the macros themselves into there and remove them from asmacros.h
* Change the way the asm GET_CURTHREAD_PTR() macro is defined so that codeian2014-03-101-7/+4
| | | | using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.
* Add missing semicolon.ian2014-02-021-1/+1
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* Change the way pcpu and curthread are stored per-core:cognet2014-02-021-4/+3
| | | | | | | | | the old way was to store pcpu in a register, and get curthread from pcpu, which is not very atomic, and led to issues if the thread was migrated to another core between the time we got the pcpu address and the time we got curthread. Instead, we now store curthread where pcpu used to be store, and we calculate the pcpu address based on the cpu id.
* Update all arm code that manipulates the PSR registers to use modern syntax.ian2014-02-021-10/+10
| | | | | | | | | | | | It turns out the version of gas we're using interprets the old '_all' mask as 'fc' instead of 'fsxc'. That is, "all" doesn't really mean "all". This was the cause of the "wrong-endian register restore" bug that's been causing problems with some cortex-a9 chips. The 'endian' bit in the spsr register would never get changed (it falls into the 'x' mask group) and the first return-from-exception would fail if the chip had powered on with garbage in the spsr register that included the big-endian bit. It's unknown why this affected only certain cortex-a9 chips.
* Correct the alignment of sp through functions that use UNWINDSVCFRAME. Weandrew2014-01-241-1/+6
| | | | | were incorrectly adding the trap frame padding to the stack pointer after reading it's value and unaligning it.
* When entering exception handlers we may not have an aligned stack. This isandrew2013-08-051-2/+11
| | | | | | | | | | | | | | | because an exception may happen at any time. The stack alignment rules on ARM EABI state the only place the stack must be 8-byte aligned is on a function boundary. If an exception happens while a function is setting up or tearing down it's stack frame it may not be correctly aligned. There is also no requirement for it to be when the function is a leaf node. The fix is to align the stack after we have stored a backup of the old stack pointer, but before we have stored anything in the trapframe. Along with this we need to adjust the size of the trapframe by 4 bytes to ensure the stack below it is also correctly aligned.
* Add UNWINDSVCFRAME to provide the unwind pseudo ops to allow us to unwindandrew2013-06-271-1/+10
| | | | | | | past a trapframe. Use this macro in exception_exit as it is the function the unwinder enters as the functions that store the frame setting lr to point to it.
* Merging projects/armv6, part 1gonzo2012-08-151-10/+76
| | | | | | | | | Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
* trim trailing whitespaceimp2012-06-131-1/+1
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* Fix 2 bugs :cognet2011-10-161-16/+14
| | | | | | | | | | | | | | - A race condition could happen if two threads were using RAS at the same time as the code didn't reset RAS_END, the RAS code could believe we were not in a RAS, when we were in fact. - Using signed value logic to compare addresses wasn't such a good idea. Many thanks to Ian to investigate on these issues. Pointy hat to: cognet PR: arm/161498 Submitted by: Ian Lepore <freebsd At damnhippie DOT dyndns dot org MFC after: 1 week
* Improve ARM_TP_ADDRESS and RAS area.raj2008-02-051-4/+4
| | | | | | | | | | | | | | De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this special purpose page to a more convenient place i.e. after the vectors high page, more towards the end of address space. Previous location (0xe000_0000) caused grief if KVA was to go beyond the default limit. Note that ARM world rebuilding is required after this change since the location of ARM_TP_ADDRESS is shared between kernel and userland. Submitted by: Grzegorz Bernacki (gjb AT semihalf dot com) Reviewed by: imp Approved by: cognet (mentor)
* Close a race.cognet2007-12-021-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RAS implementation would set the end address, then the start address. These were used by the kernel to restart a RAS sequence if it was interrupted. When the thread switching code ran, it would check these values and adjust the PC and clear them if it did. However, there's a small flaw in this scheme. Thread T1, sets the end address and gets preempted. Thread T2 runs and also does a RAS operation. This resets end to zero. Thread T1 now runs again and sets start and then begins the RAS sequence, but is preempted before the RAS sequence executes its last instruction. The kernel code that would ordinarily restart the RAS sequence doesn't because the PC isn't between start and 0, so the PC isn't set to the start of the sequence. So when T1 is resumed again, it is at the wrong location for RAS to produce the correct results. This causes the wrong results for the atomic sequence. The window for the first race is 3 instructions. The window for the second race is 5-10 instructions depending on the atomic operation. This makes this failure fairly rare and hard to reproduce. Mutexs are implemented in libthr using atomic operations. When the above race would occur, a lock could get stuck locked, causing many downstream problems, as you might expect. Also, make sure to reset the start and end address when doing a syscall, or a malicious process could set them before doing a syscall. Reviewed by: imp, ups (thanks guys) Pointy hat to: cognet MFC After: 3 days
* Twist the RAS logic a bit to avoid branching.cognet2007-09-221-12/+9
| | | | | MFC After: 1 week Approved by: re (blanket)
* Disable/enable fiqs as well as irqs.cognet2006-04-131-3/+3
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* Import a basic implementation of the restartable atomic sequences to providecognet2005-04-071-1/+15
| | | | | atomic operations to userland (this is OK for UP only, but SMP is still so far away).
* Start all license statements with /*-imp2005-01-051-1/+1
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* Rename macroes, as we don't need to mess with alignment faults.cognet2004-09-231-41/+14
| | | | Call ast() if TDF_NEEDRESCHED is set too, not just TDF_ASTPENDING.
* Import FreeBSD/arm kernel bits.cognet2004-05-141-0/+204
It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
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