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* MFC r306756:mmel2016-10-151-1/+2
| | | | | ARM: SEV/WFE instructions are implemented starting from ARMv6K, use it directly.
* Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machineandrew2016-04-151-1/+1
| | | | | | | independent code that needs to know about INTRNG such as PCI drivers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
* Implement bcm2836 interrupt controller for INTRNG and enable itskra2016-04-051-0/+2
| | | | | | on RPI2 by default. Differential Revision: https://reviews.freebsd.org/D5822
* Almost all copies of platform_mp_init_secondary just calledandrew2016-02-261-6/+0
| | | | | | | | | intr_pic_init_secondary. Replace them with a direct call. On BCM2836 and ARMADA XP we need to add this function, but it can be empty. Reviewed by: ian, imp Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D5460
* Remove platform_mp_probe as it's almost identical on most ARM SoCs, andandrew2016-02-261-11/+0
| | | | | | | | | | slightly wrong on the others. We should just check if mp_ncpus is set to more than one CPU as we may wish to run on a single core even when SMP is available. Reviewed by: ian Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D5458
* Remove platform_ipi_send, it's an unneeded as all implementations areandrew2016-02-251-7/+0
| | | | | | identical. Sponsored by: ABT Systems Ltd
* ARM: Use new ARMv6 naming conventions for cache and TLB functionsmmel2016-02-051-2/+2
| | | | | | in all but ARMv4 specific files. Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address in L2 cache functions if ARM_L2_PIPT is defined.
* An IPI must be cleared before it is handled otherwise next IPI could beandrew2015-10-011-6/+2
| | | | | | | | | | | | | | | | | | | | | missed. In other words, if a new request for an IPI is sent while the previous request is being handled but the IPI is not cleared yet, the clearing of the previous IPI request also clears the new one and the handling is missed. There are only three MP interrupt controllers in ARM now. Two of them are fixed by this change, the third one is correct, probably only just by accident. The fix is minimalistic as new interrupt framework is awaited. It was debugged on RPi2 where missing IPI handling together with SCHED_ULE led to situation in which tdq_ipipending was not cleared and so IPI_PREEMPT was stopped to be sent. Various odditys were found related to slow system response time like various events timed out, and slow console response. Submitted by: Svatopluk Kraus <onwahe@gmail.com> Reviewed by: loos, kib MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D3722
* Fix the SMP initialization on RPi 2 (BCM2836).loos2015-05-131-3/+2
| | | | | | Invalidate the CPU cache before start the others CPUs. Submitted by: Michal Meloun <meloun@miracle.cz>
* Add the SMP support for Raspberry Pi 2 (BCM2836).loos2015-05-071-0/+207
Tested with the build of some ports and a buildworld. Submitted by: Daisuke Aoyama <aoyama@peach.ne.jp>
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