An IPI must be cleared before it is handled otherwise next IPI could be

missed. In other words, if a new request for an IPI is sent while the
previous request is being handled but the IPI is not cleared yet, the
clearing of the previous IPI request also clears the new one and the
handling is missed.

There are only three MP interrupt controllers in ARM now. Two of them are
fixed by this change, the third one is correct, probably only just by
accident. The fix is minimalistic as new interrupt framework is awaited.

It was debugged on RPi2 where missing IPI handling together with SCHED_ULE
led to situation in which tdq_ipipending was not cleared and so IPI_PREEMPT
was stopped to be sent. Various odditys were found related to slow system
response time like various events timed out, and slow console response.

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>
Reviewed by:	loos, kib
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D3722

1 files changed, 2 insertions, 6 deletions

diff --git a/sys/arm/broadcom/bcm2835/bcm2836_mp.c b/sys/arm/broadcom/bcm2835/bcm2836_mp.c
index 717f242..93cc0d8 100644
--- a/sys/arm/broadcom/bcm2835/bcm2836_mp.c
+++ b/sys/arm/broadcom/bcm2835/bcm2836_mp.c
@@ -182,6 +182,8 @@ pic_ipi_read(int i)
 		if (val == 0)
 			return (0);
 		ipi = ffs(val) - 1;
+		BSWR4(MBOX0CLR_CORE(cpu), 1 << ipi);
+		dsb();
 		return (ipi);
 	}
 	return (0x3ff);
@@ -190,12 +192,6 @@ pic_ipi_read(int i)
 void
 pic_ipi_clear(int ipi)
 {
-	int cpu;
-
-	cpu = PCPU_GET(cpuid);
-	dsb();
-	BSWR4(MBOX0CLR_CORE(cpu), 1 << ipi);
-	wmb();
 }
 
 void