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* Revert "Revert "MFC r319873:""Luiz Souza2018-02-231-5/+6
| | | | This reverts commit 4c9907d21517c211b27a3cf5b7a2a976623820cc.
* Revert "MFC r319873:"Luiz Souza2018-02-211-6/+5
| | | | This reverts commit 5dad0dd804a33b8a372d49fa342b24c67b1c2fb3.
* MFC r319873:kib2018-02-191-5/+6
| | | | | | | Move struct syscall_args syscall arguments parameters container into struct thread. (cherry picked from commit 985b26c6741218c134a15526fd32b736bd73fa8a)
* Enable L1 and L2 prefetch when possible for Cortex processorsZbigniew Bodek2017-09-181-0/+18
| | | | | | | | | | Enable Dcache prefetching for both cache levels if possible. Introduce new kernel option ARM_L2_PREFETCH to be used along with the supported L2 cache controller. This option should be enabled only if the slave cache controller connected to the Cortex AXI master port supports it (such as PL310). (cherry picked from commit 7ad029753b2b3af6b3c87cc5d6912d04efb3fe03)
* Do no reuse sysctl OIDs.Luiz Souza2017-09-061-1/+1
| | | | (cherry picked from commit 42e25c991c02726cfca043536568db688293238e)
* Increase number of L2 tables required for kernel bootstrapzbb2017-09-061-2/+3
| | | | | | | | | | | | | | | | | | | | Memory space reserved for pmap_kernel_l2dtable_kva and pmap_kernel_l2ptp_kva has not been taken into account in original code. All the memory reserved from kernel space by pmap_alloc_specials() function called in pmap_bootstrap() should be mapped initially by initarm(). To create initial mapping initarm() function reserves proper number of l2 page tables. However the number of the l2 page tables does not take into account memory for: pmap_kernel_l2ptp_kva, pmap_kernel_l2dtable_kva, crashdumpmap, etc. Submitted by: Grzegorz Bernacki <gjb@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: meloun-miracle-cz Differential revision: https://reviews.freebsd.org/D10217 (cherry picked from commit 2f72ed7d5a00369d3e7f83466fca58ff94b1c3a4)
* Fix building for ARM kernel that have FLASHADDR, PHYSADDR and LOADERRAMADDR ↵manu2017-09-061-1/+1
| | | | | | | | | | defined. Pointy Hat: myself Reported by: bz (cherry picked from commit 88b4a48518f9e0ebff21d16d2b163aa092b548da)
* Keep boot parameters in ARM trampoline codemanu2017-09-061-4/+31
| | | | | | | | | | | | | Currently boot parameters (r0 - r3) are forgotten in ARM trampoline code. This patch save them at startup and restore them before jumping into kernel _start() routine. This is usefull when booting with Linux ABI and/or custom bootloader. Submitted by: Grégory Soutadé <soutade@gmail.com> Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D7395 (cherry picked from commit 5292986b0f168ac2b020244298b5801430a851df)
* Fix TEX index acquisition using L2 attributeszbb2017-09-061-2/+2
| | | | | | | | | | The TEX index is selected using (TEX0 C B) bits from the L2 descriptor. Use correct index by masking and shifting those bits accordingly. Differential Revision: https://reviews.freebsd.org/D11703 (cherry picked from commit 90fde46fef4df1269c1855372f80834ea8e50143)
* [arm] Use correct index value when checking range validitygonzo2017-09-061-2/+2
| | | | | | | | Reviewed by: andrew MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D9145 (cherry picked from commit fd5dc900256d4f0edb75e5334e7e648cb613779d)
* Enable setting the dma tag at the nexus levelzbb2017-09-062-0/+61
| | | | | | | | | | | | | | Allow to set the dma tag for nexus in the platform init code, so that all busses and devices would be able to inherit it. This change is useful e.g. for setting coherent dma tag for the platforms with hardware IO cache coherency. Submitted by: ian Michal Mazur <mkm@semihalf.com> Reviewed by: ian Differential revision: https://reviews.freebsd.org/D11202 (cherry picked from commit 0b32b9947ce18e8f69828c42aa5a9ba8cc027857)
* Introduce support for DMA coherent ARM platformszbb2017-09-061-13/+27
| | | | | | | | | | | | | | | | - Inherit BUS_DMA_COHERENT flag from parent buses - Use cacheable memory attributes on dma coherent platform - Disable cache synchronization on coherent platform Changes are based on ARMv8 busdma code and commit r299683. Submitted by: Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: ian Differential revision: https://reviews.freebsd.org/D11201 (cherry picked from commit dbbf5a80043fca8abfaa7ea9e855a468d0c44e88)
* Disable PL310 outer cache sync for IO coherent platformszbb2017-09-061-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe or Crypto controllers and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note, that other outer-cache operations are not removed, as they may be needed for certain situations, such as booting secondary CPUs. Moreover, in order to enable IO coherent operation, the decision whether to use L2 cache maintenance callbacks is done in busdma layer, which was enabled in one of the previous commits. Submitted by: Michal Mazur <mkm@semihalf.com> Marcin Wojtas <mw@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Differential revision: https://reviews.freebsd.org/D11245 (cherry picked from commit d4d94445f1fd0de66e64fd589865b027eab17726)
* Manually load tunable CPU quirks.mmel2017-09-061-0/+9
| | | | | | | | | | | These are needed too early, far before SYSINIT is processed. Reported by: zbb Pointy hat to: mmel MFC after: 3 weeks MFC with: r319896 (cherry picked from commit d425ca179a9613f12f17d5f283bac1eb5b85abe5)
* Revert change to description introduced in r320002zbb2017-09-061-1/+1
| | | | | | | | | | | Currently some ARM platforms implement their own platform_probe_and_attach() function and other use common routine that calls platform's PLATFORM_ATTACH method. Keep the old description to match the preferred way of naming things. Pointed out by: andrew (cherry picked from commit f914f0a2493da296ffd18fba31afc1f58b99b17b)
* Minor style improvements to pmap_remap_vm_attr()zbb2017-09-061-3/+3
| | | | | | | Use correct platform_ function name in the comment and remove redundant tabs. (cherry picked from commit 42b0dad3ee3dc59d7fcbd3b2d709cd2ba6f424da)
* Fix typo in "Marvell" stringzbb2017-09-061-2/+2
| | | | | | | | Change Marwell to Marvell Pointed out by: Ravi Pokala <rpokala@mac.com> (cherry picked from commit e23bb21bd5292f970933c1e4cad5fcb0b5d91e35)
* Add detection of CPU class for ARMv6/v7zbb2017-09-061-17/+36
| | | | | | | | | | Submitted by: Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: andrew Differential revision: https://reviews.freebsd.org/D10909 (cherry picked from commit e843e48d3646bd18f8480005464fe31a71692d13)
* Implement tunable CPU quirks.mmel2017-09-063-7/+50
| | | | | | | | | | These quirks are intended for optimizing CPU performance, not for applying errata workarounds. Nobody can expect that CPU with unfixed errata is stable enough to execute the kernel until quirks are applied. MFC after: 3 weeks (cherry picked from commit 1065b8567421165a5e65e3ad5d8fa4bc348efdea)
* Use the modern spelling of ofw_bus_node_is_compatible in sys/arm.andrew2017-09-061-1/+1
| | | | | | Sponsored by: ABT Systems Ltd (cherry picked from commit 7168ae84d82220caac0bb5f5f5d68ccc4e20915b)
* Simplify the code a little bit.Luiz Otavio O Souza2017-07-201-7/+2
| | | | (cherry picked from commit f1822df9cc80865c3b217672604413386aa953fe)
* Export the CPU model as hw.model.Luiz Otavio O Souza2017-07-201-0/+10
| | | | (cherry picked from commit 3a10a90e55b9cd00bf9c1343ff5df940cdd16a19)
* Revert this change.Luiz Souza2017-07-201-1/+1
| | | | (cherry picked from commit 8cb13627f08ff256fa4ed312ff6c27f62518ad65)
* Export more information about ARM CPUs and SoCs.Luiz Souza2017-07-201-4/+13
| | | | (cherry picked from commit 98135cfa4ef6f8bed339d3994e69b2cc6fb7a343)
* Remove the extra '\n' at end of the sysctl string.Luiz Souza2017-07-201-1/+1
| | | | (cherry picked from commit bb384dc82cb142648a128a751b58a93bda0adcd3)
* Fix hw.model sysctl on ARM.Luiz Souza2017-07-201-9/+7
| | | | (cherry picked from commit 639922d983d98cee86e2d1f67672baae4c7d7b61)
* Reimplement the commit 3a10a90e55b9cd00bf9c1343ff5df940cdd16a19 to export ↵Luiz Souza2017-07-201-1/+13
| | | | | | the ARM CPU model as hw.model. (cherry picked from commit bb5db9ebc2bdf0bd680ae3efcc59150e0c0bbae5)
* MFC r317428 (cognet): fix arm64 MSIemaste2017-06-131-2/+4
| | | | | | | | | | | | In arm_gicv2m_alloc_msi(), if we found a suitable irq range, leave the loop before we increase irq again, or we'd end up choosing an irq, and then really using the next one, even if it's not available. Also in the inner loop, correct the end check so that we check every irq, even the last one. This makes the msk(4) adapter able to use MSI on Softiron Overdrive 1000. PR: 219956 Approved by: re (gjb)
* MFC r318353:hselasky2017-05-272-5/+11
| | | | | | | | | | | | | | | | | | | | | Avoid use of contiguous memory allocations in busdma when possible. This patch improves the boundary checks in busdma to allow more cases using the regular page based kernel memory allocator. Especially in the case of having a non-zero boundary in the parent DMA tag. For example AMD64 based platforms set the PCI DMA tag boundary to PCI_DMA_BOUNDARY, 4GB, which before this patch caused contiguous memory allocations to be preferred when allocating more than PAGE_SIZE bytes. Even if the required alignment was less than PAGE_SIZE bytes. This patch also fixes the nsegments check for using kmem_alloc_attr() when the maximum segment size is less than PAGE_SIZE bytes. Updated some comments describing the code in question. Differential Revision: https://reviews.freebsd.org/D10645 Reviewed by: kib, jhb, gallatin, scottl Sponsored by: Mellanox Technologies
* MFC r318021,r318251:mmel2017-05-231-0/+36
| | | | | | | | r318021: Introduce pmap_remap_vm_attr(), it allows to remap one VM memattr class to another. r318251: Clarify usage rules for pmap_remap_vm_attr(). Not a functional change.
* MFC r310791:gonzo2017-05-081-0/+11
| | | | | | | | | | [qemu] Fix VERSATILEPB kernel boot in QEMU broken by r300968 QEMU does not implement hardware debug registers so when dbg_monitor_is_enabled is called kernel receives "invalid instruction" exception. QEMU implements only DIDR register and on read returns all zeroes to indicate that it doesn't support other registers. Real hardware has Version bits set.
* MFC r308569,r308570:skra2017-04-201-15/+9
| | | | | | | | | | | | | r308569: Always call PHYS_TO_VM_PAGE() in is_managed(). Fast road for addresses under first_page cannot be taken as this variable is connected only to vm_page_array segment. There could be more segments in system like the ones for various fictitious page ranges. These can be situated under vm_page_array segment and so, they could be skipped before this fix. However, as far as I know, there is no report associated with it. r308570: The return type of is_managed() was changed from boolean_t to bool type in r308569. Now, propagate this change further for consistency sake.
* MFC r315900,r315973,r315974:mmel2017-04-163-102/+185
| | | | | | | | | | | | | | | r315900: Cleanup structures related to VFP and/or mcontext_t. - in mcontext_t, rename newer used 'union __vfp' to equaly sized 'mc_spare'. Space allocated by 'union __vfp' is too small and cannot hold full VFP context. - move structures defined in fp.h to more appropriate headers. - remove all unused VFP structures. r315973: Save VFP state on fork(). Update the copy of VFP state in PCB before it is cloned for new process. r315974: Preserve VFP state across signal delivery.
* MFC r303261,r315059:mmel2017-04-164-877/+995
| | | | | | | | r303261: Add more UEFI/e820 memory types from latest specifications. r315059: Split overbloated machep.c to multiple files and do basic cleanup of these fragments.
* MFC r306704,r308406:mmel2017-04-162-13/+4
| | | | | | | r306704: ARM: Remove next bunch of unused cpu_functions from ARMv6. r308406: Only include sys/boot.h if LINUX_BOOT_ABI is defined
* MFC r306631,r306640,r306641,r306650,r306656:mmel2017-04-162-118/+35
| | | | | | | | | | | | | | | | | | r306631: Use C99 designated initializers to create the armv6 cpu_functions structs. This will help with a later cleanup of what functions we implement. r306640: Only define the CF_* macros on ARMv4/v5. They are unused on armv6. r306641: Remove the parts of cpu_functions from armv6 that are unused on that architecture. r306650: Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit code so could run a 32-bit kernel. r306656: Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs. This list is incomplete, however we don't have the ID values for the missing Cortex-A32 or A35.
* MFC r312292, r313573:ian2017-03-027-8/+3
| | | | | | | | | | | | | | | Stop including sys/types.h from arm's machine/atomic.h, fix the places where atomic.h was being included without ensuring that types.h (via param.h) was included first, as required by atomic(9). Remove arm's cpuconf.h, and references to it, after moving a few lines from it into pmap-v4.h where they are used. Other than those few lines of support for different MMU types, nothing in cpuconf.h has been used in our code for quite a while. The file existed to set up a variety of symbols to describe the architecture. Over the past few years we have converted all of our source to use the new architecture symbols standardized by ARM Inc, and predefined by both clang and gcc.
* MFC r312251:ian2017-03-011-4/+0
| | | | | Remove a bit of armv6 support that didn't get deleted when this file was split from trap.c into trap-v4.c and trap-v6.c.
* MFC r306901:ian2017-03-013-194/+411
| | | | | | ARM: Split identify_arm_cpu() into ARMv4 and ARMv6 variant. On ARMv6, be more verbose about supported CPU features and/or optional instructions.
* MFC r306262, r306267, r310021: (needed to avoid conflicts on later merges)ian2017-03-016-49/+5
| | | | | | | | | | Remove bus_dma_get_range and bus_dma_get_range_nb on armv6. We only need this on a few earlier arm SoCs. Restrict where we need to define fdt_fixup_table to just PowerPC and Marvell. Add the missing void to function signatures in much of the arm code.
* MFC r313933, r313939, r313966:kib2017-02-261-3/+2
| | | | | Microoptimize pmap_protect_pde() on amd64, i386 and pmap_protect_pte1() on armv6.
* MFC r312610, r312792jah2017-02-151-126/+146
| | | | | | | | | | | | | | | | | | | | | | | r312610: Like r310481 for i386, move the objects used to create temporary mappings for armv6 pmap zero and copy operations to the MD PCPU region. Change sysmap initialization to only allocate KVA pages for CPUs that are actually present. While here, collapse CMAP3 into CMAP2 (their use was mutually exclusive anyway) and "recover" some space in PCPU padding that has always been available due to 64-byte cacheline padding. r312792: Further cleanup of per-CPU armv6 pmap data: - Replace pcpu_find(curcpu) with get_pcpu(), which is much more direct. - Remove armv4 pcpu fields which I added in r286296 but never needed to use. - armv6 pc_qmap_addr was leftover from the old armv6 pmap implementation. Rename it and put it to use in the new one.
* MFC 307332,312086: Drop support for using mmap() with /dev/kmem.jhb2017-01-181-5/+4
| | | | | | | | | | | | | | | | | | | 307332: Drop support for using mmap() with /dev/kmem. Using the device pager with /dev/kmem is not stable since KVA mappings are transient, but the device pager caches the PA associated with a given offset forever. Interestingly, mips' implementation of memmap() already refused requests for /dev/kmem. Note that kvm_read/kvm_write do not use mmap, but use read and write on /dev/kmem, so this should not affect libkvm users. 312086: Trim a few comments on platforms that did not implement mmap of /dev/kmem. After r307332, no platforms implement mmap for /dev/kmem, so the lack of it for these platforms is no longer unique.
* MFC r306899, r307059, r307151gonzo2016-11-062-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | r306899: Fix release MSI method for ARM GIC r307059: INTRNG - fix MSI/MSIX release path Use isrc in attached MSI data structure instead of using map's isrc directly. map's isrc is set to NULL on IRQ deactivation which happens prior to pci_release_msi so MSI_RELEASE_MSI receives array of NULLs Reviewed by: mmel Differential Revision: https://reviews.freebsd.org/D8206 r307151: INTRNG: Propagate IRQ activation error to API consumer Keep resource state consistent with INTRNG state - if intr_activate_irq fails - deactivate resource and propagate error to calling function Reviewed by: mmel
* MFC r304459,r305527:mmel2016-11-051-13/+36
| | | | | | | | | | | | | | | | | | r304459: INTRNG: Rework handling with resources. Partially revert r301453. - Read interrupt properties at bus enumeration time and store it into global mapping table. - At bus_activate_resource() time, given mapping entry is resolved and connected to real interrupt source. A copy of mapping entry is attached to given resource. - At bus_setup_intr() time, mapping entry stored in resource is used for delivery of requested interrupt configuration. - For MSI/MSIX interrupts, mapping entry is created within pci_alloc_msi()/pci_alloc_msix() call. - For legacy PCI interrupts, mapping entry must be created within pcib_route_interrupt() by pcib driver itself. r305527: Fix MIPS INTRNG (both FDT and non-FDT) behaviour broken by r304459
* MFC r306759:mmel2016-10-151-6/+1
| | | | | ARM: Remove ARMv4 #defines from busdma_machdep-v6.c, it's ARMv6 specific file. Consistently use BUSDMA_DCACHE_ALIGN for cache line alignment.
* MFC r306756:mmel2016-10-152-10/+2
| | | | | ARM: SEV/WFE instructions are implemented starting from ARMv6K, use it directly.
* MFC r306755:mmel2016-10-151-1/+5
| | | | | ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores. Not a functional change.
* MFC r306754:mmel2016-10-151-3/+0
| | | | ARM: Remove unused variable. Not a functional change.
* MFC r306162:ed2016-10-124-15/+27
| | | | | | | | | | | | | | | | | | | | | | Make it possible to safely use TPIDRURW from userspace. On amd64, arm64 and i386, we have the possibility to switch between TLS areas in userspace. The nice thing about this is that it makes it easier to do light-weight threading, if we ever feel like doing that. On armv6, let's go into the same direction by making it possible to safely use the TPIDRURW register, which is intended for this purpose. Clean up the ARMv6 code to remove md_tp entirely. Simply add a dedicated field to the PCB to hold the value of TPIDRURW across context switches, like we do for any other register. As userspace currently uses the read-only TPIDRURO register, simply ensure that we keep both values in sync where possible. The system calls for modifying the read-only register will simply write the intended value into both registers, so that it lazily ends up in the PCB during the next context switch. Approved by: andrew Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D7951
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