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path: root/sys/arm/arm/pl310.c
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* Disable PL310 outer cache sync for IO coherent platformszbb2017-09-011-0/+14
* Make pl310_print_config static, it's not called out of pl310.candrew2015-11-171-1/+1
* Remove trailing whitespace from sys/arm/armandrew2015-05-241-15/+15
* - Make interrupt resource optional: some upstream FDT blobs (e.g. TI's) dogonzo2015-04-021-8/+13
* Accept the documented FDT compatible string for the PL310 cache controllerian2014-10-241-2/+7
* Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.ian2014-08-051-27/+49
* Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().ian2014-05-111-0/+13
* Add a public routine to set the L2 cache ram latencies. This can beian2014-05-061-0/+29
* Call platform_pl310_init() before enabling the controller, and handle theian2014-05-061-33/+36
* Break out the code that figures out the L2 cache geometry to its ownian2014-05-061-10/+20
* Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minorian2014-05-061-4/+7
* Move duplicated code to print l2 cache config into the common code.ian2014-04-271-0/+43
* Follow r261352 by updating all drivers which are children of simplebusian2014-02-021-0/+3
* Invalidate the entire L2 cache before enabling it. Say whether itian2013-10-161-0/+6
* The errata 727915 requires a different workaround for r2p0, we have tocognet2013-07-291-13/+26
* Remove old declarations.cognet2013-01-081-7/+0
* Release version check for erratum 727915 workaround ingonzo2013-01-071-6/+2
* Fix the build:andrew2013-01-061-11/+11
* Only work around errata when we are on a part where the erratum applies.andrew2013-01-061-19/+31
* PL310 driver update:gonzo2012-12-311-106/+166
* Make sure the address starts on a cache line boundary.cognet2012-11-211-1/+13
* Merging projects/armv6, part 1gonzo2012-08-151-0/+321
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