| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Enable L1 and L2 prefetch when possible for Cortex processors | Zbigniew Bodek | 2017-09-18 | 1 | -0/+18 |
| * | MFC r306704,r308406: | mmel | 2017-04-16 | 1 | -12/+0 |
| * | MFC r306631,r306640,r306641,r306650,r306656: | mmel | 2017-04-16 | 1 | -118/+33 |
| * | MFC r312292, r313573: | ian | 2017-03-02 | 1 | -1/+0 |
| * | MFC r306262, r306267, r310021: (needed to avoid conflicts on later merges) | ian | 2017-03-01 | 1 | -2/+2 |
| * | Start to clean MIDR values using the CPUID scheme. We don't need to know | andrew | 2016-06-07 | 1 | -16/+10 |
| * | Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't | ian | 2016-05-25 | 1 | -1/+0 |
| * | Use the new(-ish) CP15_SCTLR macro to generate system control reg accesses | ian | 2016-05-23 | 1 | -1/+1 |
| * | The cpu_reset_needs_v4_MMU_disable variable is only used in locore-v4.S, | andrew | 2016-03-02 | 1 | -3/+4 |
| * | ARM: For ARMv6/v7, code in locore.S initializes SCTLR and ACTRL registers. | mmel | 2016-02-04 | 1 | -112/+0 |
| * | ARM: Don't use ugly (and hidden) global variable, control register is | mmel | 2016-02-04 | 1 | -9/+0 |
| * | ARM: Replace only once used cpu_icache_sync_all() by ranged equivalent. | mmel | 2016-02-03 | 1 | -9/+0 |
| * | ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single | mmel | 2016-02-03 | 1 | -36/+8 |
| * | ARM: All remaining functions in cpufunc_asm_arm10.S are identical with | mmel | 2016-02-02 | 1 | -4/+4 |
| * | ARM: Remove last unused function, cpu_flush_prefetchbuf(), | mmel | 2016-02-02 | 1 | -9/+0 |
| * | ARM: Rename remaining instances of cpufunc_id() to cpu_ident(), | mmel | 2016-02-01 | 1 | -2/+0 |
| * | ARM: Remove never used cpu_tlb_flushI and cpu_tlb_flushI_SE() functions | mmel | 2016-02-01 | 1 | -16/+0 |
| * | ARM: cpufunc_domains, cpufunc_faultstatus and cpufunc_faultaddress | mmel | 2016-01-31 | 1 | -39/+3 |
| * | ARM: Next round of cpufunc.* cleaning. Nobody uses flush_brnchtgt* functions, | mmel | 2016-01-31 | 1 | -18/+0 |
| * | ARM: First round of cpufunc.* cleaning. All abort_fixup functions are | mmel | 2016-01-31 | 1 | -48/+0 |
| * | Retire pmap_pte_init_mmu_v6() which was used by old pmap-v6. | skra | 2016-01-29 | 1 | -6/+0 |
| * | ARM: Add support for new KRAIT 300 CPU revision. | mmel | 2015-11-28 | 1 | -1/+2 |
| * | Set the correct values in the arm aux control register, based on chip type. | ian | 2015-10-19 | 1 | -1/+1 |
| * | The Broadcom BCM56060 chip has a Cortex-A9R4 core. | marcel | 2015-08-13 | 1 | -0/+1 |
| * | Remove trailing whitespace from sys/arm/arm | andrew | 2015-05-24 | 1 | -50/+50 |
| * | Add more cp15_ functions, and use them in cpufunc.c where possible. | andrew | 2015-05-24 | 1 | -30/+12 |
| * | It appears to be armv7_sleep is a duplication of armv7_cpu_sleep. | ganbold | 2015-05-15 | 1 | -1/+1 |
| * | Delete cpu_do_powersave which is set but never used/tested | ganbold | 2015-05-13 | 1 | -15/+0 |
| * | Use ARMv7 style unaligned access on ARMv6. We set this bit in locore, but | andrew | 2015-04-26 | 1 | -1/+2 |
| * | Restore setting cpufuncs on arm1176, it was removed by accident with the | andrew | 2015-03-30 | 1 | -0/+1 |
| * | Remove support for CPU_XSCALE_80200. None of our configs support it, and | andrew | 2015-03-30 | 1 | -51/+5 |
| * | Remove support for CPU_FA626TE. It's unused by any of our kernel configs. | andrew | 2015-03-30 | 1 | -7/+7 |
| * | Remove arm1136 support. We don't have any configs that use it, and I don't | andrew | 2015-03-29 | 1 | -97/+9 |
| * | Remove the bootconfig parsing. We never used it and always passed either an | andrew | 2015-03-29 | 1 | -138/+7 |
| * | Remove ARM9_CACHE_WRITE_THROUGH, none of our configs define it. | andrew | 2015-03-29 | 1 | -4/+0 |
| * | Remove support for CPU_ARM10. No kernel configs could possibly use this as | andrew | 2015-03-29 | 1 | -92/+8 |
| * | Resolve cache line size from CP15 | zbb | 2015-02-10 | 1 | -0/+11 |
| * | Correct cpu type, it was rather Cortex A12 R0. | ganbold | 2015-01-14 | 1 | -1/+1 |
| * | Add CPU ID for ARM Cortex A17. | ganbold | 2015-01-13 | 1 | -0/+1 |
| * | Different versions of the ARM processor use different registers. | tuexen | 2014-06-17 | 1 | -1/+17 |
| * | Fix context switch on PJ4Bv7 and remove obsolete pj4b_/arm11 functions | zbb | 2014-05-25 | 1 | -7/+7 |
| * | Give suitably-endowed ARMs a register similar to the x86 TSC register. | markm | 2014-05-14 | 1 | -0/+37 |
| * | Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier(). | ian | 2014-05-11 | 1 | -0/+11 |
| * | Provide a proper armv7 implementation of icache_sync_all rather than | ian | 2014-04-27 | 1 | -1/+1 |
| * | Add Cortex-A15 cpu id revisions. | br | 2014-04-01 | 1 | -1/+4 |
| * | Use armv7 TLB flush code, not arm11, for cortex-a processors. | ian | 2014-03-16 | 1 | -5/+9 |
| * | Remove all traces of support for ARM chips prior to the arm9 series. We | ian | 2014-03-09 | 1 | -1081/+5 |
| * | Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementation | ian | 2014-02-28 | 1 | -1/+1 |
| * | Add a new cache maintenance function, idcache_inv_all, to the table, and | ian | 2014-02-24 | 1 | -0/+16 |
| * | Add identification and necessary type checks for Krait CPU cores. Krait CPU i... | ganbold | 2013-12-20 | 1 | -5/+6 |
