| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | MFC r278518: Resolve cache line size from CP15 instead of hard-coded 32. | ian | 2015-05-23 | 1 | -0/+11 |
| * | MFC r266083, r267597: | ian | 2015-02-13 | 1 | -0/+53 |
| * | MFC 265861, 265870: | ian | 2014-05-18 | 1 | -0/+11 |
| * | MFC 264990, 264994, 265020, 265025: | ian | 2014-05-17 | 1 | -1/+1 |
| * | MFC 263910, 263913, 263914, 263933, 263934, 263935, 263936, 263981, 263982, | ian | 2014-05-17 | 1 | -1/+4 |
| * | MFC 263250, 263251, 263424, 263425, 263426, 263427, 263430, 263431 | ian | 2014-05-17 | 1 | -5/+9 |
| * | MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997, | ian | 2014-05-17 | 1 | -1081/+5 |
| * | MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584, | ian | 2014-05-16 | 1 | -1/+1 |
| * | MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456, | ian | 2014-05-16 | 1 | -0/+16 |
| * | MFC r258359, r258742, r258845, r259936, r259640 | ian | 2014-05-14 | 1 | -5/+6 |
| * | MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281, | ian | 2014-05-14 | 1 | -112/+2 |
| * | MFC r257199, r257200, r257217: | ian | 2013-12-13 | 1 | -2/+2 |
| * | Add identification for Cortex-A7 (R0) cores. | ganbold | 2013-08-01 | 1 | -1/+2 |
| * | Add identification for Cortex-A15 (R0) cores. | ray | 2013-06-28 | 1 | -1/+2 |
| * | Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port. | wkoszek | 2013-04-27 | 1 | -1/+2 |
| * | Use armv7_drain_writebuf() and armv7_context_switch, instead of the arm11 | cognet | 2013-01-15 | 1 | -2/+2 |
| * | Replace generic ARM11 option with more specific | gonzo | 2012-12-20 | 1 | -45/+177 |
| * | Don't include arm/xscale/i8134x/i81342reg.h when we're compiling LINT. | marcel | 2012-11-27 | 1 | -1/+7 |
| * | Make it clear the L2 ops are filled for any cpu using a PL310 cache, not just | cognet | 2012-11-14 | 1 | -1/+2 |
| * | Use the arrmv7 version for flushID too, as it does something different for SMP. | cognet | 2012-11-14 | 1 | -1/+1 |
| * | Support identification of new PJ4B cores. | gber | 2012-09-14 | 1 | -2/+3 |
| * | Add support for ARM11 cpufunc | gonzo | 2012-08-26 | 1 | -17/+86 |
| * | Merging projects/armv6, part 1 | gonzo | 2012-08-15 | 1 | -76/+450 |
| * | Final whitespace trim. | imp | 2012-06-13 | 1 | -17/+17 |
| * | Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's | mav | 2010-09-18 | 1 | -1/+4 |
| * | Add support for FA626TE. | kevlo | 2010-05-04 | 1 | -51/+48 |
| * | Show the cpu info for fa526 | kevlo | 2010-02-20 | 1 | -1/+2 |
| * | Add support for Cavium Econa CNS11XX ARM boards. These boards were | rpaulo | 2010-01-04 | 1 | -1/+139 |
| * | Remove remaining bits of performance counter support. | rpaulo | 2009-10-03 | 1 | -24/+0 |
| * | Remove performance counter headers. This code came from NetBSD, but our | rpaulo | 2009-10-02 | 1 | -29/+0 |
| * | Make dcache_inv_range() point to the proper routines on ARM9 and ARM9E/ARM10. | raj | 2009-07-21 | 1 | -2/+2 |
| * | - Add support for PXA270 cpu. | stas | 2009-05-05 | 1 | -0/+1 |
| * | Fix confusing naming of Marvell ARM CPU specific routines. | raj | 2009-01-09 | 1 | -13/+13 |
| * | Merge WIP from p4: | sam | 2008-12-13 | 1 | -1/+1 |
| * | Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571. | raj | 2008-10-13 | 1 | -3/+90 |
| * | Fixes for ARM9/ARM10 : | cognet | 2007-11-28 | 1 | -1/+4 |
| * | Add entries for the L2 cache-related functions for armv5. | cognet | 2007-11-08 | 1 | -0/+5 |
| * | Don't define get_cachetype() for CPU_ARM9E unless it's going to be used. | kevlo | 2007-10-31 | 1 | -1/+1 |
| * | Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not | imp | 2007-10-18 | 1 | -4/+124 |
| * | Add cast to silent gcc warnings. | cognet | 2007-08-07 | 1 | -24/+24 |
| * | Add a new set of functions to handle L2 cache. Make them no-op for every | cognet | 2007-07-27 | 1 | -7/+47 |
| * | Use uma_set_align(). | cognet | 2007-02-11 | 1 | -13/+17 |
| * | First bits of Xscale core 3 support (the VM bits are far from being optimal | cognet | 2006-11-30 | 1 | -0/+4 |
| * | Gateworks Avila board support: | sam | 2006-11-19 | 1 | -1/+0 |
| * | Identify the xscale 81342. | cognet | 2006-11-07 | 1 | -5/+77 |
| * | style(9) cleanup. | kevlo | 2006-10-21 | 1 | -3/+0 |
| * | Finally bring it support for the i80219 XScale processor. | cognet | 2006-08-24 | 1 | -15/+26 |
| * | MFp4: Use CPU_CONTROL_ROUNDROBIN for arm9, it seems to give marginally | cognet | 2006-04-09 | 1 | -1/+2 |
| * | Remove bits specific to CPUs we won't support (< armv4). | cognet | 2005-05-25 | 1 | -328/+10 |
| * | MFp4: Setup arm9 to write back by default. | cognet | 2005-05-24 | 1 | -13/+17 |
