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path: root/sys/amd64/vmm/vmm_instruction_emul.c
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* MFC r284539, r284630, r284688, r284877, r285217, r285218,grehan2016-02-011-12/+51
* MFC r282209:neel2015-06-281-84/+153
* MFC r279444:neel2015-06-281-72/+214
* MFC r276428:neel2015-06-271-4/+267
* MFC r273375neel2014-12-301-2/+9
* MFC r270326neel2014-12-281-62/+143
* MFC r270689:grehan2014-09-161-13/+91
* MFC r267921, r267934, r267949, r267959, r267966, r268202, r268276,grehan2014-08-191-144/+528
* MFC 266424,266476,266524,266573,266595,266626,266627,266633,266641,266642,jhb2014-07-221-48/+311
* MFC 261504:jhb2014-06-121-25/+77
* MFC 261503,264501:jhb2014-06-121-0/+123
* MFC 257297:jhb2014-02-221-1/+0
* Merge projects/bhyve_npt_pmap into head.neel2013-10-051-13/+15
* Fix a bug in decoding an instruction that has an SIB byte as well as anneel2013-09-171-6/+6
* Add support for emulating the byte move instruction "mov r/m8, r8".neel2013-08-271-2/+10
* Add support for emulation of the "or r/m, imm8" instruction.neel2013-07-231-3/+60
* Verify that all bytes in the instruction buffer are consumed during decoding.neel2013-07-031-0/+16
* Switch to standard copyright license textemaste2013-05-021-2/+2
* Add RIP-relative addressing to the instruction decoder.grehan2013-04-251-33/+29
* Allow caller to skip 'guest linear address' validation when doing instructionneel2013-03-281-5/+4
* Add emulation support for instruction "88/r: mov r/m8, r8".neel2013-01-301-0/+58
* Properly screen for the AND 0x81 instruction from the setgrehan2012-11-301-0/+7
* Remove debug printf.grehan2012-11-291-1/+0
* Add support for the 0x81 AND instruction, now generatedgrehan2012-11-291-0/+29
* Revamp the x86 instruction emulation in bhyve.neel2012-11-281-49/+432
* Get rid of assumptions in the hypervisor that the host physical memoryneel2012-10-031-2/+3
* Intel VT-x provides the length of the instruction at the time of the nestedneel2012-09-271-8/+14
* Add support for trapping MMIO writes to local apic registers and emulating them.neel2012-09-251-0/+385
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