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path: root/sys/amd64/pci/pci_cfgreg.c
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* Remove duplicate code. Reduce diff between amd64 and i386.jkim2012-12-011-6/+7
* Use volatile keywords properly.jkim2012-11-301-11/+11
* Tidy up inline assembly. No functional change.jkim2012-11-301-8/+8
* pciereg_cfg*: use assembly to access the mem-mapped cfg spaceavg2012-10-141-6/+19
* number of cleanups in i386 and amd64 pci md codeavg2009-09-241-8/+8
* Add a read-only sysctl hw.pci.mcfg to mirror the tunable by the same name.jhb2009-05-181-0/+5
* Fall back to using configuration type 1 accesses for PCI config requests ifjhb2009-03-241-0/+2
* Add a 'hw.pci.mcfg' tunable. It can be set to 0 to disable memory-mappedjhb2008-09-111-0/+6
* Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIejhb2008-09-101-14/+48
* Extend the support for PCI-e memory mapped configuration space access:jhb2008-08-221-3/+137
* Adjust the code to probe for the PCI config mechanism to use.jhb2007-11-281-167/+11
* Modify the pci_cfgdisable() routine to bring it more in line withwpaul2005-10-251-2/+6
* MFi386: whitespace, copyright header, etc updatespeter2005-01-211-1/+0
* Begin all license/copyright comments with /*-imp2005-01-051-1/+1
* MFi386: nuke pci_cfgintrpeter2004-03-131-22/+1
* MFi386: change an outb to a DELAY()peter2004-01-281-1/+1
* Various whitespace and cosmetic sync-up's with i386.peter2003-12-061-0/+1
* Use __FBSDID().obrien2003-07-251-3/+3
* Commit MD parts of a loosely functional AMD64 port. This is based onpeter2003-05-011-489/+15
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenpeter2003-02-181-129/+28
* MFp4:imp2002-11-141-1/+1
* MFp4:imp2002-11-021-10/+34
* Use 0xffffffff instead of -1 for id to compare against.imp2002-11-021-10/+11
* o go ahead and route the interupt, even if it is supposedly unique.imp2002-10-071-7/+12
* Don't call function in return() for a void function.phk2002-09-281-3/+5
* Put verbose printf's in the PCI BIOS interrupt routing code underjhb2002-09-231-1/+4
* Axe unused include.jhb2002-09-201-1/+0
* Make sure a $PIR table header has a valid length before accepting the tablejhb2002-09-091-1/+2
* Add a function pci_probe_route_table() that returns true if our PCI BIOSjhb2002-09-061-0/+19
* Dump the $PIR table if booting verbose.jhb2002-09-061-0/+3
* - Add a pci_cfgintr_valid() function to see if a given IRQ is a validjhb2002-09-061-1/+33
* Add support for printing out the contents of a PCI BIOS $PIR interruptjhb2002-09-061-2/+54
* Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,jhb2002-09-051-2/+2
* style(9)ize the whole fileimp2002-07-211-474/+492
* Use a common function to map the bogus intlines.imp2002-06-011-11/+17
* Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just havingbrooks2002-05-291-0/+8
* o Work around bugs in the powerof2 macro: It thinks that 0 is a power ofimp2002-04-241-12/+18
* Don't call the bios if the interrupt appaers to be already routed. Someimp2002-03-161-3/+3
* The Libretto L series has no $PIR table, but does have a _PIR table.imp2002-01-201-13/+22
* MFS: I was confused. This code wasn't in -current after all.imp2001-11-261-5/+14
* It turns out that while Toshiba laptops don't want to route interruptsimp2001-08-281-17/+10
* MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.imp2001-08-271-30/+60
* The general conesnsus on irc was that pci bios for config registersimp2001-08-211-2/+25
* Detect a certain type of PCIBIOS brain damage. For some reason,peter2001-08-211-0/+13
* Un-swap irq/link byte values so that printf works.msmith2001-05-111-1/+1
* Free the memory we get from devclass_get_devices and device_get_children.msmith2001-02-081-3/+8
* Fix a warning due to missing prototype.peter2001-01-191-1/+1
* Remove declaration of airq variable from outer block. There were twobmilekic2001-01-121-1/+1
* Next phase in the PCI subsystem cleanup.msmith2000-12-081-2/+52
* Improve the PCI interrupt routing code. Now the process is as follows:msmith2000-11-021-16/+162
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