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* Copy i386 specialreg.h to x86 and merge with amd64 specialreg.h. Replacetijl2012-03-191-594/+3
* Add definitions related to XCR0.kib2012-01-171-0/+13
* Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features.jkim2011-05-171-1/+12
* prepare code that does topology detection for amd cpus for bulldozeravg2011-05-061-0/+2
* Define "Hypervisor Present" bit. This bit is used by several hypervisors tojkim2011-04-281-0/+1
* Add definitions for CPUID instruction 6, ECX information.jkim2011-04-121-0/+6
* specialreg.h: add definitions for some useful bits found in CPUID.6 EAX and ECXavg2010-11-231-0/+9
* specialreg.h: add definitions for MPERF/APERF pair of MSRsavg2010-11-191-0/+2
* specialreg.h: add AMD-specific "Hardware Configuration Register" MSRavg2010-11-191-0/+1
* specialreg.h: add definition for AMD Core Performance Boost bitavg2010-11-191-0/+1
* Display PCID capability of CPU and add CPUID define for it.kib2010-10-051-0/+1
* Improve cputemp(4) driver wrt newer Intel processors, especiallydelphij2010-07-291-0/+1
* The corrected error count field is dependent on CMCI, not TES.jhb2010-07-281-3/+3
* Add support for corrected machine check interrupts. CMCI is a new localjhb2010-05-241-1/+1
* Add definitions for Intel AESNI CPUID bits and print the capabilitieskib2010-05-051-0/+2
* Remove unneeded type specifiers from 64-bit constants. The compilerjhb2010-03-221-30/+30
* I am told by AMD that the machine check hardware on the instruction TLBalc2010-03-211-1/+0
* - Extend the machine check record structure to include several fields usefuljhb2010-03-161-0/+12
* Implement AMD's recommended workaround for Erratum 383 on Family 10halc2010-03-091-0/+2
* x86 cpu features: add MOVBE reporting and flagavg2009-11-301-0/+1
* Consolidate CPUID to CPU family/model macros for amd64 and i386 to reducejkim2009-09-101-2/+2
* Implement simple machine check support for amd64 and i386.jhb2009-05-131-0/+28
* - Add support for cpuid leaf 0xb. This allows us to determine thejeff2009-04-291-0/+7
* Add basic amd64 support for VIA Nano processors.jkim2009-01-121-0/+36
* Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.jkim2009-01-051-0/+1
* Add more CPUID bits from AMD CPUID Specification Rev. 2.28.jkim2008-12-121-0/+8
* Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").jkim2008-11-261-2/+2
* Simplify AMD64_CPU_MODEL() and AMD64_CPU_FAMILY() macros as the base familyjkim2008-10-221-4/+2
* Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higherjkim2008-10-221-0/+17
* Detect Advanced Power Management Information for AMD CPUs.jkim2008-10-211-0/+13
* - Add cpuctl(4) pseudo-device driver to provide access to some low-levelstas2008-08-081-0/+7
* The variable MTRR registers actually have variable-sized PhysBase andjhb2008-03-121-2/+2
* Add constants for the various fields in MTRR registers.jhb2008-03-111-0/+15
* Add a few more CPUID feature bits while here. We don't support thesedas2008-02-021-0/+2
* SSE4 CPUID bitsdas2008-02-021-0/+3
* Recognize architectural support for 1GB virtual pages.alc2007-12-081-0/+1
* Add a driver for the on-die digital thermal sensor found on Intel Coredes2007-08-151-0/+1
* Add CPUID2_PDCMdes2007-05-311-0/+1
* - Add macros for newly added CPUID bits in the corresponding header files.jkim2007-03-201-0/+2
* Add another CPUID for AMD CPUs and fix style(9) while I am here.jkim2007-03-121-82/+83
* Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.jkim2007-01-091-1/+2
* Sync specialreg.h changes between amd64 and i386 with few fixes.jkim2006-07-131-2/+5
* Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.jkim2006-07-121-0/+2
* Add various constants for the PAT MSR and the PAT PTE and PDE flags.jhb2006-05-011-0/+12
* Correct few MSR addresses.jkim2005-10-151-8/+8
* - Print number of physical/logical cores and more CPUID info.jkim2005-10-141-0/+14
* Initial PG_NX support (no-execute page bit)peter2004-06-081-0/+16
* Remove advertising clause from University of California Regent's license,imp2004-04-051-4/+0
* MFi386: add THERMTRIP msr valuespeter2004-01-281-0/+3
* Cosmetic and/or trivial sync up with i386.peter2003-11-211-3/+3
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