| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features. | jkim | 2011-05-17 | 1 | -27/+26 |
| * | Define "Hypervisor Present" bit. This bit is used by several hypervisors to | jkim | 2011-04-28 | 1 | -1/+1 |
| * | Probe capability to find effective frequency. When the TSC is P-state | jkim | 2011-04-12 | 1 | -1/+4 |
| * | Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta | jkim | 2011-03-26 | 1 | -20/+2 |
| * | Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq because | jkim | 2011-03-10 | 1 | -4/+6 |
| * | Remove stale comments about P-state invariant TSC and fix style(9) nits. | jkim | 2010-12-07 | 1 | -4/+2 |
| * | Do not register a event handler for CPU freqency changes when it is found | jkim | 2010-12-07 | 1 | -4/+16 |
| * | Probe P-state invariant TSC from rightful place. | jkim | 2010-12-07 | 1 | -22/+0 |
| * | Display PCID capability of CPU and add CPUID define for it. | kib | 2010-10-05 | 1 | -1/+1 |
| * | When compat32 binary asks for the value of hw.machine_arch, report the | kib | 2010-07-22 | 1 | -2/+24 |
| * | Add definitions for Intel AESNI CPUID bits and print the capabilities | kib | 2010-05-05 | 1 | -2/+2 |
| * | Print out the family and model from the cpu_id. This is especially useful | jhb | 2010-03-11 | 1 | -1/+3 |
| * | Introduce the new kernel sub-tree x86 which should contain all the code | attilio | 2010-02-25 | 1 | -1/+1 |
| * | x86 cpu features: add MOVBE reporting and flag | avg | 2009-11-30 | 1 | -1/+1 |
| * | Strip from messages for users external URLs the project cannot directly | attilio | 2009-11-05 | 1 | -4/+1 |
| * | Opteron rev E family of processor expose a bug where, in very rare | attilio | 2009-11-04 | 1 | -0/+18 |
| * | Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce | jkim | 2009-09-10 | 1 | -7/+7 |
| * | remove unused/unneeded extern declarations | avg | 2009-06-30 | 1 | -3/+0 |
| * | Unlock the largest standard CPUID on Intel CPUs for both amd64 and i386 and | jkim | 2009-05-04 | 1 | -0/+16 |
| * | - Add support for cpuid leaf 0xb. This allows us to determine the | jeff | 2009-04-29 | 1 | -26/+0 |
| * | VIA Nano processor has a special MSR (CENT_HARDWARECTRL3) bit 32 to determine | jkim | 2009-01-22 | 1 | -1/+2 |
| * | Add basic amd64 support for VIA Nano processors. | jkim | 2009-01-12 | 1 | -11/+65 |
| * | Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support. | jkim | 2009-01-05 | 1 | -0/+1 |
| * | Add more CPUID bits from AMD CPUID Specification Rev. 2.28. | jkim | 2008-12-12 | 1 | -8/+8 |
| * | According to "Intel 64 and IA-32 Architectures Software Developer's Manual | mav | 2008-11-30 | 1 | -1/+5 |
| * | Use newly introduced cpu_vendor_id to make invariant TSC detection more | jkim | 2008-11-26 | 1 | -7/+13 |
| * | Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "..."). | jkim | 2008-11-26 | 1 | -15/+36 |
| * | Add AMD Family 0Fh, Model 6Bh, Stepping 2 to the list of invariant TSCs | jkim | 2008-10-22 | 1 | -2/+7 |
| * | Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher | jkim | 2008-10-22 | 1 | -1/+3 |
| * | Turn off CPU frequency change notifiers when the TSC is P-state invariant | jkim | 2008-10-21 | 1 | -2/+11 |
| * | Detect Advanced Power Management Information for AMD CPUs. | jkim | 2008-10-21 | 1 | -0/+4 |
| * | - Recognize SAVE and OSXSAVE extended processor features. | stas | 2008-09-18 | 1 | -2/+2 |
| * | The VM system no longer uses setPQL2(). Remove it and its helpers. | alc | 2008-05-23 | 1 | -29/+0 |
| * | - Remove the old smp cpu topology specification with a new, more flexible | jeff | 2008-03-02 | 1 | -1/+7 |
| * | Add a few more CPUID feature bits while here. We don't support these | das | 2008-02-02 | 1 | -2/+2 |
| * | SSE4 CPUID bits | das | 2008-02-02 | 1 | -3/+3 |
| * | Recognize architectural support for 1GB virtual pages. | alc | 2007-12-08 | 1 | -1/+1 |
| * | MFi386: PDCM, remove pointless message | des | 2007-05-30 | 1 | -7/+2 |
| * | Add an interface for drivers to be notified of changes to CPU frequency. | njl | 2007-03-26 | 1 | -0/+17 |
| * | - Add macros for newly added CPUID bits in the corresponding header files. | jkim | 2007-03-20 | 1 | -2/+2 |
| * | MFi386 1.173: Display two new Intel feature bits. | jhb | 2007-03-20 | 1 | -2/+2 |
| * | Add another CPUID for AMD CPUs and fix style(9) while I am here. | jkim | 2007-03-12 | 1 | -1/+1 |
| * | Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors. | jkim | 2007-01-09 | 1 | -2/+2 |
| * | Correct spelling of 3DNow!. | obrien | 2006-08-01 | 1 | -2/+2 |
| * | Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register. | jkim | 2006-07-12 | 1 | -2/+2 |
| * | Add another Intel CPU feature flag, xTPR (Send Task Priority Messages). | jkim | 2006-04-24 | 1 | -1/+1 |
| * | Check if deterministic cache parameters leaf is valid before use. | jkim | 2006-04-24 | 1 | -1/+2 |
| * | It seems bit 5 of cpu_feature2 is the VMX (Virtual Machine Extensions) | dwmalone | 2006-02-15 | 1 | -2/+2 |
| * | Unbreak kernel build. | netchild | 2006-01-01 | 1 | -3/+3 |
| * | MI changes: | netchild | 2005-12-31 | 1 | -0/+32 |
