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Diffstat (limited to 'usr.bin/clang/lli/lli.1')
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diff --git a/usr.bin/clang/lli/lli.1 b/usr.bin/clang/lli/lli.1 index 87f4cf8..e018a95 100644 --- a/usr.bin/clang/lli/lli.1 +++ b/usr.bin/clang/lli/lli.1 @@ -1,310 +1,326 @@ .\" $FreeBSD$ -.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) -.\" -.\" Standard preamble: -.\" ======================================================================== -.de Sp \" Vertical space (when we can't use .PP) -.if t .sp .5v -.if n .sp -.. -.de Vb \" Begin verbatim text -.ft CW -.nf -.ne \\$1 -.. -.de Ve \" End verbatim text -.ft R -.fi +.TH "LLI" "1" "2012-08-16" "3.2" "LLVM" +.SH NAME +lli \- directly execute programs from LLVM bitcode +. +.nr rst2man-indent-level 0 +. +.de1 rstReportMargin +\\$1 \\n[an-margin] +level \\n[rst2man-indent-level] +level margin: \\n[rst2man-indent\\n[rst2man-indent-level]] +- +\\n[rst2man-indent0] +\\n[rst2man-indent1] +\\n[rst2man-indent2] .. -.\" Set up some character translations and predefined strings. \*(-- will -.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left -.\" double quote, and \*(R" will give a right double quote. \*(C+ will -.\" give a nicer C++. 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Of course, you'll have to process the -.\" output yourself in some meaningful fashion. -.ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +.de1 INDENT +.\" .rstReportMargin pre: +. RS \\$1 +. nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin] +. nr rst2man-indent-level +1 +.\" .rstReportMargin post: .. -. nr % 0 -. rr F -.\} -.el \{\ -. de IX +.de UNINDENT +. RE +.\" indent \\n[an-margin] +.\" old: \\n[rst2man-indent\\n[rst2man-indent-level]] +.nr rst2man-indent-level -1 +.\" new: \\n[rst2man-indent\\n[rst2man-indent-level]] +.in \\n[rst2man-indent\\n[rst2man-indent-level]]u .. -.\} -.\" -.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). -.\" Fear. Run. Save yourself. No user-serviceable parts. -. \" fudge factors for nroff and troff -.if n \{\ -. ds #H 0 -. ds #V .8m -. ds #F .3m -. ds #[ \f1 -. ds #] \fP -.\} -.if t \{\ -. ds #H ((1u-(\\\\n(.fu%2u))*.13m) -. ds #V .6m -. ds #F 0 -. ds #[ \& -. ds #] \& -.\} -. \" simple accents for nroff and troff -.if n \{\ -. ds ' \& -. ds ` \& -. ds ^ \& -. ds , \& -. ds ~ ~ -. ds / -.\} -.if t \{\ -. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" -. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' -. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' -. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' -. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' -. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' -.\} -. \" troff and (daisy-wheel) nroff accents -.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' -.ds 8 \h'\*(#H'\(*b\h'-\*(#H' -.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] -.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' -.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' -.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] -.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] -.ds ae a\h'-(\w'a'u*4/10)'e -.ds Ae A\h'-(\w'A'u*4/10)'E -. \" corrections for vroff -.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' -.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' -. \" for low resolution devices (crt and lpr) -.if \n(.H>23 .if \n(.V>19 \ -\{\ -. ds : e -. ds 8 ss -. ds o a -. ds d- d\h'-1'\(ga -. ds D- D\h'-1'\(hy -. ds th \o'bp' -. ds Th \o'LP' -. ds ae ae -. ds Ae AE -.\} -.rm #[ #] #H #V #F C -.\" ======================================================================== -.\" -.IX Title "LLI 1" -.TH LLI 1 "2012-04-05" "LLVM 3.1" "LLVM Command Guide" -.\" For nroff, turn off justification. Always turn off hyphenation; it makes -.\" way too many mistakes in technical documents. -.if n .ad l -.nh -.SH "NAME" -lli \- directly execute programs from LLVM bitcode -.SH "SYNOPSIS" -.IX Header "SYNOPSIS" -\&\fBlli\fR [\fIoptions\fR] [\fIfilename\fR] [\fIprogram args\fR] -.SH "DESCRIPTION" -.IX Header "DESCRIPTION" -\&\fBlli\fR directly executes programs in \s-1LLVM\s0 bitcode format. It takes a program -in \s-1LLVM\s0 bitcode format and executes it using a just-in-time compiler, if one is -available for the current architecture, or an interpreter. \fBlli\fR takes all of -the same code generator options as llc, but they are only effective when -\&\fBlli\fR is using the just-in-time compiler. -.PP -If \fIfilename\fR is not specified, then \fBlli\fR reads the \s-1LLVM\s0 bitcode for the +.\" Man page generated from reStructuredText. +. +.SH SYNOPSIS +.sp +\fBlli\fP [\fIoptions\fP] [\fIfilename\fP] [\fIprogram args\fP] +.SH DESCRIPTION +.sp +\fBlli\fP directly executes programs in LLVM bitcode format. It takes a program +in LLVM bitcode format and executes it using a just\-in\-time compiler, if one is +available for the current architecture, or an interpreter. \fBlli\fP takes all of +the same code generator options as llc|llc, but they are only effective when +\fBlli\fP is using the just\-in\-time compiler. +.sp +If \fIfilename\fP is not specified, then \fBlli\fP reads the LLVM bitcode for the program from standard input. -.PP -The optional \fIargs\fR specified on the command line are passed to the program as +.sp +The optional \fIargs\fP specified on the command line are passed to the program as arguments. -.SH "GENERAL OPTIONS" -.IX Header "GENERAL OPTIONS" -.IP "\fB\-fake\-argv0\fR=\fIexecutable\fR" 4 -.IX Item "-fake-argv0=executable" -Override the \f(CW\*(C`argv[0]\*(C'\fR value passed into the executing program. -.IP "\fB\-force\-interpreter\fR=\fI{false,true}\fR" 4 -.IX Item "-force-interpreter={false,true}" -If set to true, use the interpreter even if a just-in-time compiler is available +.SH GENERAL OPTIONS +.sp +\fB\-fake\-argv0\fP=\fIexecutable\fP +.INDENT 0.0 +.INDENT 3.5 +Override the \fBargv[0]\fP value passed into the executing program. +.UNINDENT +.UNINDENT +.sp +\fB\-force\-interpreter\fP=\fI{false,true}\fP +.INDENT 0.0 +.INDENT 3.5 +If set to true, use the interpreter even if a just\-in\-time compiler is available for this architecture. Defaults to false. -.IP "\fB\-help\fR" 4 -.IX Item "-help" +.UNINDENT +.UNINDENT +.sp +\fB\-help\fP +.INDENT 0.0 +.INDENT 3.5 Print a summary of command line options. -.IP "\fB\-load\fR=\fIpuginfilename\fR" 4 -.IX Item "-load=puginfilename" -Causes \fBlli\fR to load the plugin (shared object) named \fIpluginfilename\fR and use +.UNINDENT +.UNINDENT +.sp +\fB\-load\fP=\fIpuginfilename\fP +.INDENT 0.0 +.INDENT 3.5 +Causes \fBlli\fP to load the plugin (shared object) named \fIpluginfilename\fP and use it for optimization. -.IP "\fB\-stats\fR" 4 -.IX Item "-stats" -Print statistics from the code-generation passes. This is only meaningful for -the just-in-time compiler, at present. -.IP "\fB\-time\-passes\fR" 4 -.IX Item "-time-passes" -Record the amount of time needed for each code-generation pass and print it to +.UNINDENT +.UNINDENT +.sp +\fB\-stats\fP +.INDENT 0.0 +.INDENT 3.5 +Print statistics from the code\-generation passes. This is only meaningful for +the just\-in\-time compiler, at present. +.UNINDENT +.UNINDENT +.sp +\fB\-time\-passes\fP +.INDENT 0.0 +.INDENT 3.5 +Record the amount of time needed for each code\-generation pass and print it to standard error. -.IP "\fB\-version\fR" 4 -.IX Item "-version" -Print out the version of \fBlli\fR and exit without doing anything else. -.SH "TARGET OPTIONS" -.IX Header "TARGET OPTIONS" -.IP "\fB\-mtriple\fR=\fItarget triple\fR" 4 -.IX Item "-mtriple=target triple" -Override the target triple specified in the input bitcode file with the +.UNINDENT +.UNINDENT +.sp +\fB\-version\fP +.INDENT 0.0 +.INDENT 3.5 +Print out the version of \fBlli\fP and exit without doing anything else. +.UNINDENT +.UNINDENT +.SH TARGET OPTIONS +.sp +\fB\-mtriple\fP=\fItarget triple\fP +.INDENT 0.0 +.INDENT 3.5 +Override the target triple specified in the input bitcode file with the specified string. This may result in a crash if you pick an architecture which is not compatible with the current system. -.IP "\fB\-march\fR=\fIarch\fR" 4 -.IX Item "-march=arch" +.UNINDENT +.UNINDENT +.sp +\fB\-march\fP=\fIarch\fP +.INDENT 0.0 +.INDENT 3.5 Specify the architecture for which to generate assembly, overriding the target -encoded in the bitcode file. See the output of \fBllc \-help\fR for a list of +encoded in the bitcode file. See the output of \fBllc \-help\fP for a list of valid architectures. By default this is inferred from the target triple or autodetected to the current architecture. -.IP "\fB\-mcpu\fR=\fIcpuname\fR" 4 -.IX Item "-mcpu=cpuname" +.UNINDENT +.UNINDENT +.sp +\fB\-mcpu\fP=\fIcpuname\fP +.INDENT 0.0 +.INDENT 3.5 Specify a specific chip in the current architecture to generate code for. -By default this is inferred from the target triple and autodetected to +By default this is inferred from the target triple and autodetected to the current architecture. For a list of available CPUs, use: -\&\fBllvm-as < /dev/null | llc \-march=xyz \-mcpu=help\fR -.IP "\fB\-mattr\fR=\fIa1,+a2,\-a3,...\fR" 4 -.IX Item "-mattr=a1,+a2,-a3,..." -Override or control specific attributes of the target, such as whether \s-1SIMD\s0 +\fBllvm\-as < /dev/null | llc \-march=xyz \-mcpu=help\fP +.UNINDENT +.UNINDENT +.sp +\fB\-mattr\fP=\fIa1,+a2,\-a3,...\fP +.INDENT 0.0 +.INDENT 3.5 +Override or control specific attributes of the target, such as whether SIMD operations are enabled or not. The default set of attributes is set by the -current \s-1CPU\s0. For a list of available attributes, use: -\&\fBllvm-as < /dev/null | llc \-march=xyz \-mattr=help\fR -.SH "FLOATING POINT OPTIONS" -.IX Header "FLOATING POINT OPTIONS" -.IP "\fB\-disable\-excess\-fp\-precision\fR" 4 -.IX Item "-disable-excess-fp-precision" +current CPU. For a list of available attributes, use: +\fBllvm\-as < /dev/null | llc \-march=xyz \-mattr=help\fP +.UNINDENT +.UNINDENT +.SH FLOATING POINT OPTIONS +.sp +\fB\-disable\-excess\-fp\-precision\fP +.INDENT 0.0 +.INDENT 3.5 Disable optimizations that may increase floating point precision. -.IP "\fB\-enable\-no\-infs\-fp\-math\fR" 4 -.IX Item "-enable-no-infs-fp-math" +.UNINDENT +.UNINDENT +.sp +\fB\-enable\-no\-infs\-fp\-math\fP +.INDENT 0.0 +.INDENT 3.5 Enable optimizations that assume no Inf values. -.IP "\fB\-enable\-no\-nans\-fp\-math\fR" 4 -.IX Item "-enable-no-nans-fp-math" -Enable optimizations that assume no \s-1NAN\s0 values. -.IP "\fB\-enable\-unsafe\-fp\-math\fR" 4 -.IX Item "-enable-unsafe-fp-math" -Causes \fBlli\fR to enable optimizations that may decrease floating point +.UNINDENT +.UNINDENT +.sp +\fB\-enable\-no\-nans\-fp\-math\fP +.INDENT 0.0 +.INDENT 3.5 +Enable optimizations that assume no NAN values. +.UNINDENT +.UNINDENT +.sp +\fB\-enable\-unsafe\-fp\-math\fP +.INDENT 0.0 +.INDENT 3.5 +Causes \fBlli\fP to enable optimizations that may decrease floating point precision. -.IP "\fB\-soft\-float\fR" 4 -.IX Item "-soft-float" -Causes \fBlli\fR to generate software floating point library calls instead of +.UNINDENT +.UNINDENT +.sp +\fB\-soft\-float\fP +.INDENT 0.0 +.INDENT 3.5 +Causes \fBlli\fP to generate software floating point library calls instead of equivalent hardware instructions. -.SH "CODE GENERATION OPTIONS" -.IX Header "CODE GENERATION OPTIONS" -.IP "\fB\-code\-model\fR=\fImodel\fR" 4 -.IX Item "-code-model=model" +.UNINDENT +.UNINDENT +.SH CODE GENERATION OPTIONS +.sp +\fB\-code\-model\fP=\fImodel\fP +.INDENT 0.0 +.INDENT 3.5 Choose the code model from: -.Sp -.Vb 5 -\& default: Target default code model -\& small: Small code model -\& kernel: Kernel code model -\& medium: Medium code model -\& large: Large code model -.Ve -.IP "\fB\-disable\-post\-RA\-scheduler\fR" 4 -.IX Item "-disable-post-RA-scheduler" +.sp +.nf +.ft C +default: Target default code model +small: Small code model +kernel: Kernel code model +medium: Medium code model +large: Large code model +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +\fB\-disable\-post\-RA\-scheduler\fP +.INDENT 0.0 +.INDENT 3.5 Disable scheduling after register allocation. -.IP "\fB\-disable\-spill\-fusing\fR" 4 -.IX Item "-disable-spill-fusing" +.UNINDENT +.UNINDENT +.sp +\fB\-disable\-spill\-fusing\fP +.INDENT 0.0 +.INDENT 3.5 Disable fusing of spill code into instructions. -.IP "\fB\-enable\-correct\-eh\-support\fR" 4 -.IX Item "-enable-correct-eh-support" -Make the \-lowerinvoke pass insert expensive, but correct, \s-1EH\s0 code. -.IP "\fB\-jit\-enable\-eh\fR" 4 -.IX Item "-jit-enable-eh" -Exception handling should be enabled in the just-in-time compiler. -.IP "\fB\-join\-liveintervals\fR" 4 -.IX Item "-join-liveintervals" +.UNINDENT +.UNINDENT +.sp +\fB\-enable\-correct\-eh\-support\fP +.INDENT 0.0 +.INDENT 3.5 +Make the \-lowerinvoke pass insert expensive, but correct, EH code. +.UNINDENT +.UNINDENT +.sp +\fB\-jit\-enable\-eh\fP +.INDENT 0.0 +.INDENT 3.5 +Exception handling should be enabled in the just\-in\-time compiler. +.UNINDENT +.UNINDENT +.sp +\fB\-join\-liveintervals\fP +.INDENT 0.0 +.INDENT 3.5 Coalesce copies (default=true). -.IP "\fB\-nozero\-initialized\-in\-bss\fR Don't place zero-initialized symbols into the \s-1BSS\s0 section." 4 -.IX Item "-nozero-initialized-in-bss Don't place zero-initialized symbols into the BSS section." -.PD 0 -.IP "\fB\-pre\-RA\-sched\fR=\fIscheduler\fR" 4 -.IX Item "-pre-RA-sched=scheduler" -.PD +.UNINDENT +.UNINDENT +.sp +\fB\-nozero\-initialized\-in\-bss\fP Don\(aqt place zero\-initialized symbols into the BSS section. +.sp +\fB\-pre\-RA\-sched\fP=\fIscheduler\fP +.INDENT 0.0 +.INDENT 3.5 Instruction schedulers available (before register allocation): -.Sp -.Vb 7 -\& =default: Best scheduler for the target -\& =none: No scheduling: breadth first sequencing -\& =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization -\& =simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency -\& =list\-burr: Bottom\-up register reduction list scheduling -\& =list\-tdrr: Top\-down register reduction list scheduling -\& =list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code -.Ve -.IP "\fB\-regalloc\fR=\fIallocator\fR" 4 -.IX Item "-regalloc=allocator" +.sp +.nf +.ft C +=default: Best scheduler for the target +=none: No scheduling: breadth first sequencing +=simple: Simple two pass scheduling: minimize critical path and maximize processor utilization +=simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency +=list\-burr: Bottom\-up register reduction list scheduling +=list\-tdrr: Top\-down register reduction list scheduling +=list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +\fB\-regalloc\fP=\fIallocator\fP +.INDENT 0.0 +.INDENT 3.5 Register allocator to use (default=linearscan) -.Sp -.Vb 3 -\& =bigblock: Big\-block register allocator -\& =linearscan: linear scan register allocator =local \- local register allocator -\& =simple: simple register allocator -.Ve -.IP "\fB\-relocation\-model\fR=\fImodel\fR" 4 -.IX Item "-relocation-model=model" +.sp +.nf +.ft C +=bigblock: Big\-block register allocator +=linearscan: linear scan register allocator =local \- local register allocator +=simple: simple register allocator +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +\fB\-relocation\-model\fP=\fImodel\fP +.INDENT 0.0 +.INDENT 3.5 Choose relocation model from: -.Sp -.Vb 3 -\& =default: Target default relocation model -\& =static: Non\-relocatable code =pic \- Fully relocatable, position independent code -\& =dynamic\-no\-pic: Relocatable external references, non\-relocatable code -.Ve -.IP "\fB\-spiller\fR" 4 -.IX Item "-spiller" +.sp +.nf +.ft C +=default: Target default relocation model +=static: Non\-relocatable code =pic \- Fully relocatable, position independent code +=dynamic\-no\-pic: Relocatable external references, non\-relocatable code +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +\fB\-spiller\fP +.INDENT 0.0 +.INDENT 3.5 Spiller to use (default=local) -.Sp -.Vb 2 -\& =simple: simple spiller -\& =local: local spiller -.Ve -.IP "\fB\-x86\-asm\-syntax\fR=\fIsyntax\fR" 4 -.IX Item "-x86-asm-syntax=syntax" +.sp +.nf +.ft C +=simple: simple spiller +=local: local spiller +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +\fB\-x86\-asm\-syntax\fP=\fIsyntax\fP +.INDENT 0.0 +.INDENT 3.5 Choose style of code to emit from X86 backend: -.Sp -.Vb 2 -\& =att: Emit AT&T\-style assembly -\& =intel: Emit Intel\-style assembly -.Ve -.SH "EXIT STATUS" -.IX Header "EXIT STATUS" -If \fBlli\fR fails to load the program, it will exit with an exit code of 1. +.sp +.nf +.ft C +=att: Emit AT&T\-style assembly +=intel: Emit Intel\-style assembly +.ft P +.fi +.UNINDENT +.UNINDENT +.SH EXIT STATUS +.sp +If \fBlli\fP fails to load the program, it will exit with an exit code of 1. Otherwise, it will return the exit code of the program it executes. -.SH "SEE ALSO" -.IX Header "SEE ALSO" -llc -.SH "AUTHOR" -.IX Header "AUTHOR" -Maintained by the \s-1LLVM\s0 Team (<http://llvm.org/>). +.SH SEE ALSO +.sp +llc|llc +.SH AUTHOR +Maintained by The LLVM Team (http://llvm.org/). +.SH COPYRIGHT +2012, LLVM Project +.\" Generated by docutils manpage writer. +. |