diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/tsec/if_tsec.c | 1648 | ||||
| -rw-r--r-- | sys/dev/tsec/if_tsec.h | 284 | ||||
| -rw-r--r-- | sys/dev/tsec/if_tsecreg.h | 355 |
3 files changed, 2287 insertions, 0 deletions
diff --git a/sys/dev/tsec/if_tsec.c b/sys/dev/tsec/if_tsec.c new file mode 100644 index 0000000..8ea171a --- /dev/null +++ b/sys/dev/tsec/if_tsec.c @@ -0,0 +1,1648 @@ +/*- + * Copyright (C) 2006-2008 Semihalf + * All rights reserved. + * + * Written by: Piotr Kruszynski <ppk@semihalf.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. + */ +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/endian.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/socket.h> +#include <sys/sysctl.h> + +#include <net/if.h> +#include <net/if_dl.h> +#include <net/if_media.h> + +#include <net/bpf.h> +#include <sys/sockio.h> +#include <sys/bus.h> +#include <machine/bus.h> +#include <sys/rman.h> +#include <machine/resource.h> + +#include <net/ethernet.h> +#include <net/if_arp.h> + +#include <net/if_types.h> +#include <net/if_vlan_var.h> + +#include <dev/mii/mii.h> +#include <dev/mii/miivar.h> + +#include <machine/ocpbus.h> + +#include <dev/tsec/if_tsec.h> +#include <dev/tsec/if_tsecreg.h> + +#include "miibus_if.h" + +#define TSEC_DEBUG + +#ifdef TSEC_DEBUG +#define PDEBUG(a) {printf("%s:%d: ", __func__, __LINE__), printf a; printf("\n");} +#else +#define PDEBUG(a) /* nop */ +#endif + +static int tsec_probe(device_t dev); +static int tsec_attach(device_t dev); +static int tsec_setup_intr(device_t dev, struct resource **ires, + void **ihand, int *irid, driver_intr_t handler, const char *iname); +static void tsec_release_intr(device_t dev, struct resource *ires, + void *ihand, int irid, const char *iname); +static void tsec_free_dma(struct tsec_softc *sc); +static int tsec_detach(device_t dev); +static void tsec_shutdown(device_t dev); +static int tsec_suspend(device_t dev); /* XXX */ +static int tsec_resume(device_t dev); /* XXX */ + +static void tsec_init(void *xsc); +static void tsec_init_locked(struct tsec_softc *sc); +static void tsec_set_mac_address(struct tsec_softc *sc); +static void tsec_dma_ctl(struct tsec_softc *sc, int state); +static void tsec_intrs_ctl(struct tsec_softc *sc, int state); +static void tsec_reset_mac(struct tsec_softc *sc); + +static void tsec_watchdog(struct ifnet *ifp); +static void tsec_start(struct ifnet *ifp); +static void tsec_start_locked(struct ifnet *ifp); +static int tsec_encap(struct tsec_softc *sc, + struct mbuf *m_head); +static void tsec_setfilter(struct tsec_softc *sc); +static int tsec_ioctl(struct ifnet *ifp, u_long command, + caddr_t data); +static int tsec_ifmedia_upd(struct ifnet *ifp); +static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); +static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, + struct mbuf **mbufp, uint32_t *paddr); +static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, + int nseg, int error); +static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, + bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, + const char *dname); +static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, + void *vaddr); + +static void tsec_stop(struct tsec_softc *sc); + +static void tsec_receive_intr(void *arg); +static void tsec_transmit_intr(void *arg); +static void tsec_error_intr(void *arg); + +static void tsec_tick(void *arg); +static int tsec_miibus_readreg(device_t dev, int phy, int reg); +static void tsec_miibus_writereg(device_t dev, int phy, int reg, int value); +static void tsec_miibus_statchg(device_t dev); + +static struct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */ + +static device_method_t tsec_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, tsec_probe), + DEVMETHOD(device_attach, tsec_attach), + DEVMETHOD(device_detach, tsec_detach), + DEVMETHOD(device_shutdown, tsec_shutdown), + DEVMETHOD(device_suspend, tsec_suspend), + DEVMETHOD(device_resume, tsec_resume), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, tsec_miibus_readreg), + DEVMETHOD(miibus_writereg, tsec_miibus_writereg), + DEVMETHOD(miibus_statchg, tsec_miibus_statchg), + { 0, 0 } +}; + +static driver_t tsec_driver = { + "tsec", + tsec_methods, + sizeof(struct tsec_softc), +}; + +static devclass_t tsec_devclass; + +DRIVER_MODULE(tsec, ocpbus, tsec_driver, tsec_devclass, 0, 0); +DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); +MODULE_DEPEND(tsec, ether, 1, 1, 1); +MODULE_DEPEND(tsec, miibus, 1, 1, 1); + +static void +tsec_get_hwaddr(struct tsec_softc *sc, uint8_t *addr) +{ + union { + uint32_t reg[2]; + uint8_t addr[6]; + } curmac; + uint32_t a[6]; + int count, i; + char *cp; + + /* Use the currently programmed MAC address by default. */ + curmac.reg[0] = TSEC_READ(sc, TSEC_REG_MACSTNADDR1); + curmac.reg[1] = TSEC_READ(sc, TSEC_REG_MACSTNADDR2); + for (i = 0; i < 6; i++) + a[5-i] = curmac.addr[i]; + + cp = getenv("ethaddr"); + if (cp != NULL) { + count = sscanf(cp, "%x:%x:%x:%x:%x:%x", &a[0], &a[1], &a[2], + &a[3], &a[4], &a[5]); + freeenv(cp); + } + + addr[0] = a[0]; + addr[1] = a[1]; + addr[2] = a[2]; + addr[3] = a[3]; + addr[4] = a[4]; + addr[5] = a[5]; +} + +static void +tsec_init(void *xsc) +{ + struct tsec_softc *sc = xsc; + + TSEC_GLOBAL_LOCK(sc); + tsec_init_locked(sc); + TSEC_GLOBAL_UNLOCK(sc); +} + +static void +tsec_init_locked(struct tsec_softc *sc) +{ + struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; + struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; + struct ifnet *ifp = sc->tsec_ifp; + uint32_t timeout; + uint32_t val; + uint32_t i; + + TSEC_GLOBAL_LOCK_ASSERT(sc); + tsec_stop(sc); + + /* + * These steps are according to the MPC8555E PowerQUICCIII RM: + * 14.7 Initialization/Application Information + */ + + /* Step 1: soft reset MAC */ + tsec_reset_mac(sc); + + /* Step 2: Initialize MACCFG2 */ + TSEC_WRITE(sc, TSEC_REG_MACCFG2, + TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ + TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ + TSEC_MACCFG2_GMII | /* I/F Mode bit */ + TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ + ); + + /* Step 3: Initialize ECNTRL + * While the documentation states that R100M is ignored if RPM is + * not set, it does seem to be needed to get the orange boxes to + * work (which have a Marvell 88E1111 PHY). Go figure. + */ + + /* + * XXX kludge - use circumstancial evidence to program ECNTRL + * correctly. Ideally we need some board information to guide + * us here. + */ + i = TSEC_READ(sc, TSEC_REG_ID2); + val = (i & 0xffff) + ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ + : TSEC_ECNTRL_R100M; /* Orange + CDS */ + TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); + + /* Step 4: Initialize MAC station address */ + tsec_set_mac_address(sc); + + /* + * Step 5: Assign a Physical address to the TBI so as to not conflict + * with the external PHY physical address + */ + TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); + + /* Step 6: Reset the management interface */ + TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); + + /* Step 7: Setup the MII Mgmt clock speed */ + TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); + + /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ + timeout = TSEC_READ_RETRY; + while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) & + TSEC_MIIMIND_BUSY)) + DELAY(TSEC_READ_DELAY); + if (timeout == 0) { + if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); + return; + } + + /* Step 9: Setup the MII Mgmt */ + mii_mediachg(sc->tsec_mii); + + /* Step 10: Clear IEVENT register */ + TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); + + /* Step 11: Initialize IMASK */ + tsec_intrs_ctl(sc, 1); + + /* Step 12: Initialize IADDRn */ + TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); + TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); + TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); + TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); + TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); + TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); + TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); + TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); + + /* Step 13: Initialize GADDRn */ + TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); + TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); + TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); + TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); + TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); + TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); + TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); + TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); + + /* Step 14: Initialize RCTRL */ + TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); + + /* Step 15: Initialize DMACTRL */ + tsec_dma_ctl(sc, 1); + + /* Step 16: Initialize FIFO_PAUSE_CTRL */ + TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); + + /* + * Step 17: Initialize transmit/receive descriptor rings. + * Initialize TBASE and RBASE. + */ + TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); + TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); + + for (i = 0; i < TSEC_TX_NUM_DESC; i++) { + tx_desc[i].bufptr = 0; + tx_desc[i].length = 0; + tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC-1) ? TSEC_TXBD_W : 0); + } + bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, BUS_DMASYNC_PREREAD | + BUS_DMASYNC_PREWRITE); + + for (i = 0; i < TSEC_RX_NUM_DESC; i++) { + rx_desc[i].bufptr = sc->rx_data[i].paddr; + rx_desc[i].length = 0; + rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | + ((i == TSEC_RX_NUM_DESC-1) ? TSEC_RXBD_W : 0); + } + bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, BUS_DMASYNC_PREREAD | + BUS_DMASYNC_PREWRITE); + + /* Step 18: Initialize the maximum and minimum receive buffer length */ + TSEC_WRITE(sc, TSEC_REG_MRBLR, TSEC_DEFAULT_MAX_RX_BUFFER_SIZE); + TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_DEFAULT_MIN_RX_BUFFER_SIZE); + + /* Step 19: Enable Rx and RxBD sdata snooping */ + TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); + TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); + + /* Step 20: Reset collision counters in hardware */ + TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); + + /* Step 21: Mask all CAM interrupts */ + TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); + TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); + + /* Step 22: Enable Rx and Tx */ + val = TSEC_READ(sc, TSEC_REG_MACCFG1); + val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); + TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); + + /* Step 23: Reset TSEC counters for Tx and Rx rings */ + TSEC_TX_RX_COUNTERS_INIT(sc); + + /* Step 24: Activate timer for PHY */ + callout_reset(&sc->tsec_tick_ch, hz, tsec_tick, sc); + + /* Step 25: Activate network interface */ + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + ifp->if_timer = 0; + sc->tsec_if_flags = ifp->if_flags; +} + +static void +tsec_set_mac_address(struct tsec_softc *sc) +{ + uint32_t macbuf[2] = { 0, 0 }; + int i; + char *macbufp; + char *curmac; + + TSEC_GLOBAL_LOCK_ASSERT(sc); + + KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), + ("tsec_set_mac_address: (%d <= %d", + ETHER_ADDR_LEN, sizeof(macbuf))); + + macbufp = (char *)macbuf; + curmac = (char *)IF_LLADDR(sc->tsec_ifp); + + /* Correct order of MAC address bytes */ + for (i = 1; i <= ETHER_ADDR_LEN; i++) + macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; + + /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ + TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); + TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); +} + +/* + * DMA control function, if argument state is: + * 0 - DMA engine will be disabled + * 1 - DMA engine will be enabled + */ +static void +tsec_dma_ctl(struct tsec_softc *sc, int state) +{ + device_t dev; + uint32_t dma_flags; + uint32_t timeout; + + dev = sc->dev; + + dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); + + switch (state) { + case 0: + /* Temporarily clear stop graceful stop bits. */ + tsec_dma_ctl(sc, 1000); + + /* Set it again */ + dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); + break; + case 1000: + case 1: + /* Set write with response (WWR), wait (WOP) and snoop bits */ + dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | + DMACTRL_WWR | DMACTRL_WOP); + + /* Clear graceful stop bits */ + dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); + break; + default: + device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", + state); + } + + TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); + + switch (state) { + case 0: + /* Wait for DMA stop */ + timeout = TSEC_READ_RETRY; + while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & + (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) + DELAY(TSEC_READ_DELAY); + + if (timeout == 0) + device_printf(dev, "tsec_dma_ctl(): timeout!\n"); + break; + case 1: + /* Restart transmission function */ + TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); + } +} + +/* + * Interrupts control function, if argument state is: + * 0 - all TSEC interrupts will be masked + * 1 - all TSEC interrupts will be unmasked + */ +static void +tsec_intrs_ctl(struct tsec_softc *sc, int state) +{ + device_t dev; + + dev = sc->dev; + + switch (state) { + case 0: + TSEC_WRITE(sc, TSEC_REG_IMASK, 0); + break; + case 1: + TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | + TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | + TSEC_IMASK_EBERREN | TSEC_IMASK_BTEN | + TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | + TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | + TSEC_IMASK_RXFEN + ); + break; + default: + device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", + state); + } +} + +static void +tsec_reset_mac(struct tsec_softc *sc) +{ + uint32_t maccfg1_flags; + + /* Set soft reset bit */ + maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); + maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; + TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); + + /* Clear soft reset bit */ + maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); + maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; + TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); +} + +static void +tsec_watchdog(struct ifnet *ifp) +{ + struct tsec_softc *sc = ifp->if_softc; + + TSEC_GLOBAL_LOCK(sc); + + ifp->if_oerrors++; + if_printf(ifp, "watchdog timeout\n"); + + tsec_stop(sc); + tsec_init_locked(sc); + + TSEC_GLOBAL_UNLOCK(sc); +} + +static void +tsec_start(struct ifnet *ifp) +{ + struct tsec_softc *sc = ifp->if_softc; + + TSEC_TRANSMIT_LOCK(sc); + tsec_start_locked(ifp); + TSEC_TRANSMIT_UNLOCK(sc); +} + + +static void +tsec_start_locked(struct ifnet *ifp) +{ + struct tsec_softc *sc; + struct mbuf *m0; + struct mbuf *mtmp; + unsigned int queued = 0; + + sc = ifp->if_softc; + + TSEC_TRANSMIT_LOCK_ASSERT(sc); + + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING) + return; + + if (sc->tsec_link == 0) + return; + + bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + for (;;) { + /* Get packet from the queue */ + IF_DEQUEUE(&ifp->if_snd, m0); + if (m0 == NULL) + break; + + mtmp = m_defrag(m0, M_DONTWAIT); + if (mtmp) + m0 = mtmp; + + if (tsec_encap(sc, m0)) { + IF_PREPEND(&ifp->if_snd, m0); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + queued++; + BPF_MTAP(ifp, m0); + } + bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + if (queued) { + /* Enable transmitter and watchdog timer */ + TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); + ifp->if_timer = 5; + } +} + +static int +tsec_encap(struct tsec_softc *sc, struct mbuf *m0) +{ + struct tsec_desc *tx_desc = NULL; + struct ifnet *ifp; + bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; + bus_dmamap_t *mapp; + int error; + int seg, nsegs; + + TSEC_TRANSMIT_LOCK_ASSERT(sc); + + ifp = sc->tsec_ifp; + + if (TSEC_FREE_TX_DESC(sc) == 0) { + /* No free descriptors */ + return (-1); + } + + /* Fetch unused map */ + mapp = TSEC_ALLOC_TX_MAP(sc); + + /* Create mapping in DMA memory */ + error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, + *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); + if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { + bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); + TSEC_FREE_TX_MAP(sc, mapp); + return ((error != 0) ? error : -1); + } + bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); + + if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) + if_printf(ifp, "TX buffer has %d segments\n", nsegs); + + /* Everything is ok, now we can send buffers */ + for (seg = 0; seg < nsegs; seg++) { + tx_desc = TSEC_GET_CUR_TX_DESC(sc); + + tx_desc->length = segs[seg].ds_len; + tx_desc->bufptr = segs[seg].ds_addr; + + tx_desc->flags = + (tx_desc->flags & TSEC_TXBD_W) | /* wrap */ + TSEC_TXBD_I | /* interrupt */ + TSEC_TXBD_R | /* ready to send */ + TSEC_TXBD_TC | /* transmit the CRC sequence + * after the last data byte */ + ((seg == nsegs-1) ? TSEC_TXBD_L : 0);/* last in frame */ + } + + /* Save mbuf and DMA mapping for release at later stage */ + TSEC_PUT_TX_MBUF(sc, m0); + TSEC_PUT_TX_MAP(sc, mapp); + + return (0); +} + +static void +tsec_setfilter(struct tsec_softc *sc) +{ + struct ifnet *ifp; + uint32_t flags; + + ifp = sc->tsec_ifp; + flags = TSEC_READ(sc, TSEC_REG_RCTRL); + + /* Promiscuous mode */ + if (ifp->if_flags & IFF_PROMISC) + flags |= TSEC_RCTRL_PROM; + else + flags &= ~TSEC_RCTRL_PROM; + + TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); +} + +static int +tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct tsec_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *)data; + device_t dev; + int error = 0; + + dev = sc->dev; + + switch (command) { + case SIOCSIFFLAGS: + TSEC_GLOBAL_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + if ((sc->tsec_if_flags ^ ifp->if_flags) & + IFF_PROMISC) + tsec_setfilter(sc); + } else + tsec_init_locked(sc); + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + tsec_stop(sc); + } + sc->tsec_if_flags = ifp->if_flags; + TSEC_GLOBAL_UNLOCK(sc); + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, + command); + break; + default: + error = ether_ioctl(ifp, command, data); + } + + /* Flush buffers if not empty */ + if (ifp->if_flags & IFF_UP) + tsec_start(ifp); + return (error); +} + +static int +tsec_ifmedia_upd(struct ifnet *ifp) +{ + struct tsec_softc *sc = ifp->if_softc; + struct mii_data *mii; + + TSEC_TRANSMIT_LOCK(sc); + + mii = sc->tsec_mii; + mii_mediachg(mii); + + TSEC_TRANSMIT_UNLOCK(sc); + return (0); +} + +static void +tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct tsec_softc *sc = ifp->if_softc; + struct mii_data *mii; + + TSEC_TRANSMIT_LOCK(sc); + + mii = sc->tsec_mii; + mii_pollstat(mii); + + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + + TSEC_TRANSMIT_UNLOCK(sc); +} + +static int +tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, + uint32_t *paddr) +{ + struct mbuf *new_mbuf; + bus_dma_segment_t seg[1]; + int error; + int nsegs; + + KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); + + new_mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (new_mbuf == NULL) + return (ENOBUFS); + new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; + + if (*mbufp) { + bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(tag, map); + } + + error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, + BUS_DMA_NOWAIT); + KASSERT(nsegs == 1, ("Too many segments returned!")); + if (nsegs != 1 || error) + panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); + +#if 0 + if (error) { + printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", + error); + m_freem(new_mbuf); + return (ENOBUFS); + } +#endif + +#if 0 + KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, + ("Wrong alignment of RX buffer!")); +#endif + bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); + + (*mbufp) = new_mbuf; + (*paddr) = seg->ds_addr; + return (0); +} + +static void +tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + u_int32_t *paddr; + + KASSERT(nseg == 1, ("wrong number of segments, should be 1")); + paddr = arg; + *paddr = segs->ds_addr; +} + +static int +tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, + bus_size_t dsize, void **vaddr, void *raddr, const char *dname) +{ + int error; + + /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ + error = bus_dma_tag_create(NULL, /* parent */ + PAGE_SIZE, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filtfunc, filtfuncarg */ + dsize, 1, /* maxsize, nsegments */ + dsize, 0, /* maxsegsz, flags */ + NULL, NULL, /* lockfunc, lockfuncarg */ + dtag); /* dmat */ + + if (error) { + device_printf(dev, "failed to allocate busdma %s tag\n", dname); + (*vaddr) = NULL; + return (ENXIO); + } + + error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, + dmap); + if (error) { + device_printf(dev, "failed to allocate %s DMA safe memory\n", + dname); + bus_dma_tag_destroy(*dtag); + (*vaddr) = NULL; + return (ENXIO); + } + + error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, tsec_map_dma_addr, + raddr, BUS_DMA_NOWAIT); + if (error) { + device_printf(dev, "cannot get address of the %s descriptors\n", + dname); + bus_dmamem_free(*dtag, *vaddr, *dmap); + bus_dma_tag_destroy(*dtag); + (*vaddr) = NULL; + return (ENXIO); + } + + return (0); +} + +static void +tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) +{ + + if (vaddr == NULL) + return; + + /* Unmap descriptors from DMA memory */ + bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(dtag, dmap); + + /* Free descriptors memory */ + bus_dmamem_free(dtag, vaddr, dmap); + + /* Destroy descriptors tag */ + bus_dma_tag_destroy(dtag); +} + +static int +tsec_probe(device_t dev) +{ + struct tsec_softc *sc; + device_t parent; + uintptr_t devtype; + int error; + uint32_t id; + + parent = device_get_parent(dev); + + error = BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_DEVTYPE, &devtype); + if (error) + return (error); + if (devtype != OCPBUS_DEVTYPE_TSEC) + return (ENXIO); + + sc = device_get_softc(dev); + + sc->sc_rrid = 0; + sc->sc_rres = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->sc_rrid, + 0ul, ~0ul, TSEC_IO_SIZE, RF_ACTIVE); + if (sc->sc_rres == NULL) + return (ENXIO); + + sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); + sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); + + /* Check that we actually have a TSEC at this address */ + id = TSEC_READ(sc, TSEC_REG_ID) | TSEC_READ(sc, TSEC_REG_ID2); + + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, sc->sc_rres); + + if (id == 0) + return (ENXIO); + + device_set_desc(dev, "Three-Speed Ethernet Controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +tsec_attach(device_t dev) +{ + uint8_t hwaddr[ETHER_ADDR_LEN]; + struct tsec_softc *sc; + struct ifnet *ifp; + bus_dmamap_t *map_ptr; + bus_dmamap_t **map_pptr; + int error = 0; + int i; + + sc = device_get_softc(dev); + sc->dev = dev; + + if (device_get_unit(dev) == 0) + tsec0_sc = sc; /* XXX */ + + callout_init(&sc->tsec_tick_ch, 1); + mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "TSEC TX lock", + MTX_DEF); + mtx_init(&sc->receive_lock, device_get_nameunit(dev), "TSEC RX lock", + MTX_DEF); + + /* Reset all TSEC counters */ + TSEC_TX_RX_COUNTERS_INIT(sc); + + /* Allocate IO memory for TSEC registers */ + sc->sc_rrid = 0; + sc->sc_rres = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->sc_rrid, + 0ul, ~0ul, TSEC_IO_SIZE, RF_ACTIVE); + if (sc->sc_rres == NULL) { + device_printf(dev, "could not allocate IO memory range!\n"); + tsec_detach(dev); + return (ENXIO); + } + sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); + sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); + + /* Stop DMA engine if enabled by firmware */ + tsec_dma_ctl(sc, 0); + + /* Reset MAC */ + tsec_reset_mac(sc); + + /* Disable interrupts for now */ + tsec_intrs_ctl(sc, 0); + + /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ + error = tsec_alloc_dma_desc(dev, &sc->tsec_tx_dtag, &sc->tsec_tx_dmap, + sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, + (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); + if (error) { + tsec_detach(dev); + return (ENXIO); + } + + /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ + error = tsec_alloc_dma_desc(dev, &sc->tsec_rx_dtag, &sc->tsec_rx_dmap, + sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, + (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); + if (error) { + tsec_detach(dev); + return (ENXIO); + } + + /* Allocate a busdma tag for TX mbufs. */ + error = bus_dma_tag_create(NULL, /* parent */ + TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filtfunc, filtfuncarg */ + MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ + TSEC_TX_NUM_DESC - 1, /* nsegments */ + MCLBYTES, 0, /* maxsegsz, flags */ + NULL, NULL, /* lockfunc, lockfuncarg */ + &sc->tsec_tx_mtag); /* dmat */ + if (error) { + device_printf(dev, "failed to allocate busdma tag(tx mbufs)\n"); + tsec_detach(dev); + return (ENXIO); + } + + /* Allocate a busdma tag for RX mbufs. */ + error = bus_dma_tag_create(NULL, /* parent */ + TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filtfunc, filtfuncarg */ + MCLBYTES, /* maxsize */ + 1, /* nsegments */ + MCLBYTES, 0, /* maxsegsz, flags */ + NULL, NULL, /* lockfunc, lockfuncarg */ + &sc->tsec_rx_mtag); /* dmat */ + if (error) { + device_printf(dev, "failed to allocate busdma tag(rx mbufs)\n"); + tsec_detach(dev); + return (ENXIO); + } + + /* Create TX busdma maps */ + map_ptr = sc->tx_map_data; + map_pptr = sc->tx_map_unused_data; + + for (i = 0; i < TSEC_TX_NUM_DESC; i++) { + map_pptr[i] = &map_ptr[i]; + error = bus_dmamap_create(sc->tsec_tx_mtag, 0, + map_pptr[i]); + if (error) { + device_printf(dev, "failed to init TX ring\n"); + tsec_detach(dev); + return (ENXIO); + } + } + + /* Create RX busdma maps and zero mbuf handlers */ + for (i = 0; i < TSEC_RX_NUM_DESC; i++) { + error = bus_dmamap_create(sc->tsec_rx_mtag, 0, + &sc->rx_data[i].map); + if (error) { + device_printf(dev, "failed to init RX ring\n"); + tsec_detach(dev); + return (ENXIO); + } + sc->rx_data[i].mbuf = NULL; + } + + /* Create mbufs for RX buffers */ + for (i = 0; i < TSEC_RX_NUM_DESC; i++) { + error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, + &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); + if (error) { + device_printf(dev, "can't load rx DMA map %d, error = " + "%d\n", i, error); + tsec_detach(dev); + return (error); + } + } + + /* Create network interface for upper layers */ + ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "if_alloc() failed\n"); + tsec_detach(dev); + return (ENOMEM); + } + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_mtu = ETHERMTU; + ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST; + ifp->if_init = tsec_init; + ifp->if_start = tsec_start; + ifp->if_watchdog = tsec_watchdog; + ifp->if_ioctl = tsec_ioctl; + + IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); + ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; + IFQ_SET_READY(&ifp->if_snd); + + /* XXX No special features of TSEC are supported currently */ + ifp->if_capabilities = 0; + ifp->if_capenable = ifp->if_capabilities; + + /* Probe PHY(s) */ + error = mii_phy_probe(dev, &sc->tsec_miibus, tsec_ifmedia_upd, + tsec_ifmedia_sts); + if (error) { + device_printf(dev, "MII failed to find PHY!\n"); + if_free(ifp); + sc->tsec_ifp = NULL; + tsec_detach(dev); + return (error); + } + sc->tsec_mii = device_get_softc(sc->tsec_miibus); + + tsec_get_hwaddr(sc, hwaddr); + ether_ifattach(ifp, hwaddr); + + /* Interrupts configuration (TX/RX/ERR) */ + sc->sc_transmit_irid = OCP_TSEC_RID_TXIRQ; + error = tsec_setup_intr(dev, &sc->sc_transmit_ires, + &sc->sc_transmit_ihand, &sc->sc_transmit_irid, + tsec_transmit_intr, "TX"); + if (error) { + tsec_detach(dev); + return (error); + } + + sc->sc_receive_irid = OCP_TSEC_RID_RXIRQ; + error = tsec_setup_intr(dev, &sc->sc_receive_ires, + &sc->sc_receive_ihand, &sc->sc_receive_irid, + tsec_receive_intr, "RX"); + if (error) { + tsec_detach(dev); + return (error); + } + + sc->sc_error_irid = OCP_TSEC_RID_ERRIRQ; + error = tsec_setup_intr(dev, &sc->sc_error_ires, + &sc->sc_error_ihand, &sc->sc_error_irid, + tsec_error_intr, "ERR"); + if (error) { + tsec_detach(dev); + return (error); + } + + return (0); +} + +static int +tsec_setup_intr(device_t dev, struct resource **ires, void **ihand, int *irid, + driver_intr_t handler, const char *iname) +{ + struct tsec_softc *sc; + int error; + + sc = device_get_softc(dev); + + (*ires) = bus_alloc_resource_any(dev, SYS_RES_IRQ, irid, RF_ACTIVE); + if ((*ires) == NULL) { + device_printf(dev, "could not allocate %s IRQ\n", iname); + return (ENXIO); + } + error = bus_setup_intr(dev, *ires, INTR_TYPE_NET | INTR_MPSAFE, + NULL, handler, sc, ihand); + if (error) { + device_printf(dev, "failed to set up %s IRQ\n", iname); + if (bus_release_resource(dev, SYS_RES_IRQ, *irid, *ires)) + device_printf(dev, "could not release %s IRQ\n", iname); + (*ires) = NULL; + return (error); + } + return (0); +} + +static void +tsec_release_intr(device_t dev, struct resource *ires, void *ihand, int irid, + const char *iname) +{ + int error; + + if (ires == NULL) + return; + + error = bus_teardown_intr(dev, ires, ihand); + if (error) + device_printf(dev, "bus_teardown_intr() failed for %s intr" + ", error %d\n", iname, error); + + error = bus_release_resource(dev, SYS_RES_IRQ, irid, ires); + if (error) + device_printf(dev, "bus_release_resource() failed for %s intr" + ", error %d\n", iname, error); +} + +static void +tsec_free_dma(struct tsec_softc *sc) +{ + int i; + + /* Free TX maps */ + for (i = 0; i < TSEC_TX_NUM_DESC; i++) + if (sc->tx_map_data[i] != NULL) + bus_dmamap_destroy(sc->tsec_tx_mtag, + sc->tx_map_data[i]); + /* Destroy tag for Tx mbufs */ + bus_dma_tag_destroy(sc->tsec_tx_mtag); + + /* Free RX mbufs and maps */ + for (i = 0; i < TSEC_RX_NUM_DESC; i++) { + if (sc->rx_data[i].mbuf) { + /* Unload buffer from DMA */ + bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->tsec_rx_mtag, sc->rx_data[i].map); + + /* Free buffer */ + m_freem(sc->rx_data[i].mbuf); + } + /* Destroy map for this buffer */ + if (sc->rx_data[i].map != NULL) + bus_dmamap_destroy(sc->tsec_rx_mtag, + sc->rx_data[i].map); + } + /* Destroy tag for Rx mbufs */ + bus_dma_tag_destroy(sc->tsec_rx_mtag); + + /* Unload TX/RX descriptors */ + tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, + sc->tsec_tx_vaddr); + tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, + sc->tsec_rx_vaddr); +} + +static int +tsec_detach(device_t dev) +{ + struct tsec_softc *sc; + int error; + + sc = device_get_softc(dev); + + /* Stop TSEC controller and free TX queue */ + if (sc->sc_rres && sc->tsec_ifp) + tsec_shutdown(dev); + + /* Wait for stopping TSEC ticks */ + callout_drain(&sc->tsec_tick_ch); + + /* Stop and release all interrupts */ + tsec_release_intr(dev, sc->sc_transmit_ires, sc->sc_transmit_ihand, + sc->sc_transmit_irid, "TX"); + tsec_release_intr(dev, sc->sc_receive_ires, sc->sc_receive_ihand, + sc->sc_receive_irid, "RX"); + tsec_release_intr(dev, sc->sc_error_ires, sc->sc_error_ihand, + sc->sc_error_irid, "ERR"); + + /* Detach network interface */ + if (sc->tsec_ifp) { + ether_ifdetach(sc->tsec_ifp); + if_free(sc->tsec_ifp); + sc->tsec_ifp = NULL; + } + + /* Free DMA resources */ + tsec_free_dma(sc); + + /* Free IO memory handler */ + if (sc->sc_rres) { + error = bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, + sc->sc_rres); + if (error) + device_printf(dev, "bus_release_resource() failed for" + " IO memory, error %d\n", error); + } + + /* Destroy locks */ + mtx_destroy(&sc->receive_lock); + mtx_destroy(&sc->transmit_lock); + return (0); +} + +static void +tsec_shutdown(device_t dev) +{ + struct tsec_softc *sc; + + sc = device_get_softc(dev); + + TSEC_GLOBAL_LOCK(sc); + tsec_stop(sc); + TSEC_GLOBAL_UNLOCK(sc); +} + +static int +tsec_suspend(device_t dev) +{ + + /* TODO not implemented! */ + return (ENODEV); +} + +static int +tsec_resume(device_t dev) +{ + + /* TODO not implemented! */ + return (ENODEV); +} + +static void +tsec_stop(struct tsec_softc *sc) +{ + struct ifnet *ifp; + struct mbuf *m0; + bus_dmamap_t *mapp; + uint32_t tmpval; + + TSEC_GLOBAL_LOCK_ASSERT(sc); + + ifp = sc->tsec_ifp; + + /* Stop PHY tick engine */ + callout_stop(&sc->tsec_tick_ch); + + /* Disable interface and watchdog timer */ + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + ifp->if_timer = 0; + + /* Disable all interrupts and stop DMA */ + tsec_intrs_ctl(sc, 0); + tsec_dma_ctl(sc, 0); + + /* Remove pending data from TX queue */ + while (!TSEC_EMPTYQ_TX_MBUF(sc)) { + m0 = TSEC_GET_TX_MBUF(sc); + mapp = TSEC_GET_TX_MAP(sc); + + bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); + + TSEC_FREE_TX_MAP(sc, mapp); + m_freem(m0); + } + + /* Disable Rx and Tx */ + tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); + tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); + TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); + DELAY(10); +} + +static void +tsec_receive_intr(void *arg) +{ + struct mbuf *rcv_mbufs[TSEC_RX_NUM_DESC]; + struct tsec_softc *sc = arg; + struct tsec_desc *rx_desc; + struct ifnet *ifp; + struct rx_data_type *rx_data; + struct mbuf *m; + device_t dev; + uint32_t i; + int count; + int c1 = 0; + int c2; + uint16_t flags; + uint16_t length; + + ifp = sc->tsec_ifp; + rx_data = sc->rx_data; + dev = sc->dev; + + /* Confirm the interrupt was received by driver */ + TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); + + TSEC_RECEIVE_LOCK(sc); + + bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, BUS_DMASYNC_POSTREAD | + BUS_DMASYNC_POSTWRITE); + + for (count = 0; /* count < TSEC_RX_NUM_DESC */; count++) { + rx_desc = TSEC_GET_CUR_RX_DESC(sc); + flags = rx_desc->flags; + + /* Check if there is anything to receive */ + if ((flags & TSEC_RXBD_E) || (count >= TSEC_RX_NUM_DESC)) { + /* + * Avoid generating another interrupt + */ + if (flags & TSEC_RXBD_E) + TSEC_WRITE(sc, TSEC_REG_IEVENT, + TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); + /* + * We didn't consume current descriptor and have to + * return it to the queue + */ + TSEC_BACK_CUR_RX_DESC(sc); + break; + } + + if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | + TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { + rx_desc->length = 0; + rx_desc->flags = (rx_desc->flags & + ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; + continue; + } + + if ((flags & TSEC_RXBD_L) == 0) + device_printf(dev, "buf is not the last in frame!\n"); + + /* Ok... process frame */ + length = rx_desc->length - ETHER_CRC_LEN; + i = TSEC_GET_CUR_RX_DESC_CNT(sc); + + m = rx_data[i].mbuf; + + if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, + &rx_data[i].mbuf, &rx_data[i].paddr)) { + ifp->if_ierrors++; + continue; + } + /* Attach new buffer to descriptor, and clear flags */ + rx_desc->bufptr = rx_data[i].paddr; + rx_desc->length = 0; + rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | + TSEC_RXBD_E | TSEC_RXBD_I; + + /* Prepare buffer for upper layers */ + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = length; + + /* Save it for push */ + rcv_mbufs[c1++] = m; + } + + bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + TSEC_RECEIVE_UNLOCK(sc); + + /* Push it now */ + for (c2 = 0; c2 < c1; c2++) + (*ifp->if_input)(ifp, rcv_mbufs[c2]); +} + +static void +tsec_transmit_intr(void *arg) +{ + struct tsec_softc *sc = arg; + struct tsec_desc *tx_desc; + struct ifnet *ifp; + struct mbuf *m0; + bus_dmamap_t *mapp; + int send = 0; + + ifp = sc->tsec_ifp; + + /* Confirm the interrupt was received by driver */ + TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); + + TSEC_TRANSMIT_LOCK(sc); + + /* Update collision statistics */ + ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); + + /* Reset collision counters in hardware */ + TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); + TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); + + bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, BUS_DMASYNC_POSTREAD | + BUS_DMASYNC_POSTWRITE); + + while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { + tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); + if (tx_desc->flags & TSEC_TXBD_R) { + TSEC_BACK_DIRTY_TX_DESC(sc); + break; + } + + if ((tx_desc->flags & TSEC_TXBD_L) == 0) + continue; + + /* + * This is the last buf in this packet, so unmap and free it. + */ + m0 = TSEC_GET_TX_MBUF(sc); + mapp = TSEC_GET_TX_MAP(sc); + + bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); + + TSEC_FREE_TX_MAP(sc, mapp); + m_freem(m0); + + ifp->if_opackets++; + send = 1; + } + bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + if (send) { + /* Now send anything that was pending */ + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + tsec_start_locked(ifp); + + /* Stop wathdog if all sent */ + if (TSEC_EMPTYQ_TX_MBUF(sc)) + ifp->if_timer = 0; + } + TSEC_TRANSMIT_UNLOCK(sc); +} + +static void +tsec_error_intr(void *arg) +{ + struct tsec_softc *sc = arg; + struct ifnet *ifp; + uint32_t eflags; + + ifp = sc->tsec_ifp; + + eflags = TSEC_READ(sc, TSEC_REG_IEVENT); + + if (ifp->if_flags & IFF_DEBUG) + if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", eflags); + + /* Clear events bits in hardware */ + TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | + TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | + TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | + TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); + + if (eflags & TSEC_IEVENT_EBERR) + if_printf(ifp, "System bus error occurred during" + " a DMA transaction (flags: 0x%x)\n", eflags); + + /* Check transmitter errors */ + if (eflags & TSEC_IEVENT_TXE) { + ifp->if_oerrors++; + + if (eflags & TSEC_IEVENT_LC) + ifp->if_collisions++; + + TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); + } + if (eflags & TSEC_IEVENT_BABT) + ifp->if_oerrors++; + + /* Check receiver errors */ + if (eflags & TSEC_IEVENT_BSY) { + ifp->if_ierrors++; + ifp->if_iqdrops++; + + /* Get data from RX buffers */ + tsec_receive_intr(arg); + + /* Make receiver again active */ + TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); + } + if (eflags & TSEC_IEVENT_BABR) + ifp->if_ierrors++; +} + +static void +tsec_tick(void *arg) +{ + struct tsec_softc *sc = arg; + struct ifnet *ifp; + int link; + + TSEC_TRANSMIT_LOCK(sc); + + ifp = sc->tsec_ifp; + link = sc->tsec_link; + + mii_tick(sc->tsec_mii); + + if (link == 0 && sc->tsec_link == 1 && (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) + tsec_start_locked(ifp); + + callout_reset(&sc->tsec_tick_ch, hz, tsec_tick, sc); + TSEC_TRANSMIT_UNLOCK(sc); +} + +static int +tsec_miibus_readreg(device_t dev, int phy, int reg) +{ + struct tsec_softc *sc; + uint32_t timeout; + + sc = device_get_softc(dev); + + if (device_get_unit(dev) != phy) + return (0); + + sc = tsec0_sc; + + TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); + TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0); + TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); + + timeout = TSEC_READ_RETRY; + while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) & + (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) + DELAY(TSEC_READ_DELAY); + + if (timeout == 0) + device_printf(dev, "Timeout while reading from PHY!\n"); + + return (TSEC_READ(sc, TSEC_REG_MIIMSTAT)); +} + +static void +tsec_miibus_writereg(device_t dev, int phy, int reg, int value) +{ + struct tsec_softc *sc; + uint32_t timeout; + + sc = device_get_softc(dev); + + if (device_get_unit(dev) != phy) + device_printf(dev, "Trying to write to an alien PHY(%d)\n", phy); + + sc = tsec0_sc; + + TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); + TSEC_WRITE(sc, TSEC_REG_MIIMCON, value); + + timeout = TSEC_READ_RETRY; + while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & TSEC_MIIMIND_BUSY)) + DELAY(TSEC_READ_DELAY); + + if (timeout == 0) + device_printf(dev, "Timeout while writing to PHY!\n"); +} + +static void +tsec_miibus_statchg(device_t dev) +{ + struct tsec_softc *sc; + struct mii_data *mii; + uint32_t ecntrl, id, tmp; + int link; + + sc = device_get_softc(dev); + mii = sc->tsec_mii; + link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); + + tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; + + if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) + tmp |= TSEC_MACCFG2_FULLDUPLEX; + else + tmp &= ~TSEC_MACCFG2_FULLDUPLEX; + + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_1000_T: + case IFM_1000_SX: + tmp |= TSEC_MACCFG2_GMII; + sc->tsec_link = link; + break; + case IFM_100_TX: + case IFM_10_T: + tmp |= TSEC_MACCFG2_MII; + sc->tsec_link = link; + break; + case IFM_NONE: + if (link) + device_printf(dev, "No speed selected but link active!\n"); + sc->tsec_link = 0; + return; + default: + sc->tsec_link = 0; + device_printf(dev, "Unknown speed (%d), link %s!\n", + IFM_SUBTYPE(mii->mii_media_active), + ((link) ? "up" : "down")); + return; + } + TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); + + /* XXX kludge - use circumstantial evidence for reduced mode. */ + id = TSEC_READ(sc, TSEC_REG_ID2); + if (id & 0xffff) { + ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; + ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; + TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); + } +} diff --git a/sys/dev/tsec/if_tsec.h b/sys/dev/tsec/if_tsec.h new file mode 100644 index 0000000..38c4e3d --- /dev/null +++ b/sys/dev/tsec/if_tsec.h @@ -0,0 +1,284 @@ +/*- + * Copyright (C) 2006-2007 Semihalf + * All rights reserved. + * + * Written by: Piotr Kruszynski <ppk@semihalf.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#define TSEC_RX_NUM_DESC 256 +#define TSEC_TX_NUM_DESC 256 + +#define OCP_TSEC_RID_TXIRQ 0 +#define OCP_TSEC_RID_RXIRQ 1 +#define OCP_TSEC_RID_ERRIRQ 2 + +struct tsec_softc { + /* XXX MII bus requires that struct ifnet is first!!! */ + struct ifnet *tsec_ifp; + + struct mtx transmit_lock; /* transmitter lock */ + struct mtx receive_lock; /* receiver lock */ + + device_t dev; + device_t tsec_miibus; + struct mii_data *tsec_mii; /* MII media control */ + struct callout tsec_tick_ch; + int tsec_link; + + bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */ + bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */ + struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */ + uint32_t tsec_tx_raddr; /* real adress of TX descriptors */ + + bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */ + bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */ + struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */ + uint32_t tsec_rx_raddr; /* real adress of RX descriptors */ + + bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */ + bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */ + + struct rx_data_type { + bus_dmamap_t map; /* mbuf map */ + struct mbuf *mbuf; + uint32_t paddr; /* DMA addres of buffer */ + } rx_data[TSEC_RX_NUM_DESC]; + + uint32_t tx_cur_desc_cnt; + uint32_t tx_dirty_desc_cnt; + uint32_t rx_cur_desc_cnt; + + struct resource *sc_rres; /* register resource */ + int sc_rrid; /* register rid */ + struct { + bus_space_tag_t bst; + bus_space_handle_t bsh; + } sc_bas; + + struct resource *sc_transmit_ires; + void *sc_transmit_ihand; + int sc_transmit_irid; + struct resource *sc_receive_ires; + void *sc_receive_ihand; + int sc_receive_irid; + struct resource *sc_error_ires; + void *sc_error_ihand; + int sc_error_irid; + + int tsec_if_flags; + + /* TX maps */ + bus_dmamap_t tx_map_data[TSEC_TX_NUM_DESC]; + + /* unused TX maps data */ + uint32_t tx_map_unused_get_cnt; + uint32_t tx_map_unused_put_cnt; + bus_dmamap_t *tx_map_unused_data[TSEC_TX_NUM_DESC]; + + /* used TX maps data */ + uint32_t tx_map_used_get_cnt; + uint32_t tx_map_used_put_cnt; + bus_dmamap_t *tx_map_used_data[TSEC_TX_NUM_DESC]; + + /* mbufs in TX queue */ + uint32_t tx_mbuf_used_get_cnt; + uint32_t tx_mbuf_used_put_cnt; + struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC]; +}; + +/* interface to get/put generic objects */ +#define TSEC_CNT_INIT(cnt, wrap) ((cnt) = ((wrap) - 1)) + +#define TSEC_INC(count, wrap) (count = ((count) + 1) & ((wrap) - 1)) + +#define TSEC_GET_GENERIC(hand, tab, count, wrap) \ + ((hand)->tab[TSEC_INC((hand)->count, wrap)]) + +#define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \ + ((hand)->tab[TSEC_INC((hand)->count, wrap)] = val) + +#define TSEC_BACK_GENERIC(sc, count, wrap) do { \ + if ((sc)->count > 0) \ + (sc)->count--; \ + else \ + (sc)->count = (wrap) - 1; \ +} while (0) + +/* TX maps interface */ +#define TSEC_TX_MAP_CNT_INIT(sc) do { \ + TSEC_CNT_INIT((sc)->tx_map_unused_get_cnt, TSEC_TX_NUM_DESC); \ + TSEC_CNT_INIT((sc)->tx_map_unused_put_cnt, TSEC_TX_NUM_DESC); \ + TSEC_CNT_INIT((sc)->tx_map_used_get_cnt, TSEC_TX_NUM_DESC); \ + TSEC_CNT_INIT((sc)->tx_map_used_put_cnt, TSEC_TX_NUM_DESC); \ +} while (0) + +/* interface to get/put unused TX maps */ +#define TSEC_ALLOC_TX_MAP(sc) \ + TSEC_GET_GENERIC(sc, tx_map_unused_data, tx_map_unused_get_cnt, \ + TSEC_TX_NUM_DESC) + +#define TSEC_FREE_TX_MAP(sc, val) \ + TSEC_PUT_GENERIC(sc, tx_map_unused_data, tx_map_unused_put_cnt, \ + TSEC_TX_NUM_DESC, val) + +/* interface to get/put used TX maps */ +#define TSEC_GET_TX_MAP(sc) \ + TSEC_GET_GENERIC(sc, tx_map_used_data, tx_map_used_get_cnt, \ + TSEC_TX_NUM_DESC) + +#define TSEC_PUT_TX_MAP(sc, val) \ + TSEC_PUT_GENERIC(sc, tx_map_used_data, tx_map_used_put_cnt, \ + TSEC_TX_NUM_DESC, val) + +/* interface to get/put TX mbufs in send queue */ +#define TSEC_TX_MBUF_CNT_INIT(sc) do { \ + TSEC_CNT_INIT((sc)->tx_mbuf_used_get_cnt, TSEC_TX_NUM_DESC); \ + TSEC_CNT_INIT((sc)->tx_mbuf_used_put_cnt, TSEC_TX_NUM_DESC); \ +} while (0) + +#define TSEC_GET_TX_MBUF(sc) \ + TSEC_GET_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_get_cnt, \ + TSEC_TX_NUM_DESC) + +#define TSEC_PUT_TX_MBUF(sc, val) \ + TSEC_PUT_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_put_cnt, \ + TSEC_TX_NUM_DESC, val) + +#define TSEC_EMPTYQ_TX_MBUF(sc) \ + ((sc)->tx_mbuf_used_get_cnt == (sc)->tx_mbuf_used_put_cnt) + +/* interface for manage tx tsec_desc */ +#define TSEC_TX_DESC_CNT_INIT(sc) do { \ + TSEC_CNT_INIT((sc)->tx_cur_desc_cnt, TSEC_TX_NUM_DESC); \ + TSEC_CNT_INIT((sc)->tx_dirty_desc_cnt, TSEC_TX_NUM_DESC); \ +} while (0) + +#define TSEC_GET_CUR_TX_DESC(sc) \ + &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_cur_desc_cnt, \ + TSEC_TX_NUM_DESC) + +#define TSEC_GET_DIRTY_TX_DESC(sc) \ + &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_dirty_desc_cnt, \ + TSEC_TX_NUM_DESC) + +#define TSEC_BACK_DIRTY_TX_DESC(sc) \ + TSEC_BACK_GENERIC(sc, tx_dirty_desc_cnt, TSEC_TX_NUM_DESC) + +#define TSEC_CUR_DIFF_DIRTY_TX_DESC(sc) \ + ((sc)->tx_cur_desc_cnt != (sc)->tx_dirty_desc_cnt) + +#define TSEC_FREE_TX_DESC(sc) \ + (((sc)->tx_cur_desc_cnt < (sc)->tx_dirty_desc_cnt) ? \ + ((sc)->tx_dirty_desc_cnt - (sc)->tx_cur_desc_cnt - 1) \ + : \ + (TSEC_TX_NUM_DESC - (sc)->tx_cur_desc_cnt \ + + (sc)->tx_dirty_desc_cnt - 1)) + +/* interface for manage rx tsec_desc */ +#define TSEC_RX_DESC_CNT_INIT(sc) do { \ + TSEC_CNT_INIT((sc)->rx_cur_desc_cnt, TSEC_RX_NUM_DESC); \ +} while (0) + +#define TSEC_GET_CUR_RX_DESC(sc) \ + &TSEC_GET_GENERIC(sc, tsec_rx_vaddr, rx_cur_desc_cnt, \ + TSEC_RX_NUM_DESC) + +#define TSEC_BACK_CUR_RX_DESC(sc) \ + TSEC_BACK_GENERIC(sc, rx_cur_desc_cnt, TSEC_RX_NUM_DESC) + +#define TSEC_GET_CUR_RX_DESC_CNT(sc) \ + ((sc)->rx_cur_desc_cnt) + +/* init all counters (for init only!) */ +#define TSEC_TX_RX_COUNTERS_INIT(sc) do { \ + TSEC_TX_MAP_CNT_INIT(sc); \ + TSEC_TX_MBUF_CNT_INIT(sc); \ + TSEC_TX_DESC_CNT_INIT(sc); \ + TSEC_RX_DESC_CNT_INIT(sc); \ +} while (0) + +/* read/write bus functions */ +#define TSEC_READ(sc, reg) \ + bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) +#define TSEC_WRITE(sc, reg, val) \ + bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) + +/* Lock for transmitter */ +#define TSEC_TRANSMIT_LOCK(sc) do { \ + mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ + mtx_lock(&(sc)->transmit_lock); \ +} while (0) + +#define TSEC_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) +#define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) + +/* Lock for receiver */ +#define TSEC_RECEIVE_LOCK(sc) do { \ + mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ + mtx_lock(&(sc)->receive_lock); \ +} while (0) + +#define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) +#define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) + +/* Global tsec lock (with all locks) */ +#define TSEC_GLOBAL_LOCK(sc) do { \ + if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ + (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ + panic("tsec deadlock possibility detection!"); \ + } \ + mtx_lock(&(sc)->transmit_lock); \ + mtx_lock(&(sc)->receive_lock); \ +} while (0) + +#define TSEC_GLOBAL_UNLOCK(sc) do { \ + TSEC_RECEIVE_UNLOCK(sc); \ + TSEC_TRANSMIT_UNLOCK(sc); \ +} while (0) + +#define TSEC_GLOBAL_LOCK_ASSERT(sc) do { \ + TSEC_TRANSMIT_LOCK_ASSERT(sc); \ + TSEC_RECEIVE_LOCK_ASSERT(sc); \ +} while (0) + +/* From global to {transmit,receive} */ +#define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \ + mtx_unlock(&(sc)->receive_lock);\ +} while (0) + +#define TSEC_GLOBAL_TO_RECEIVE_LOCK(sc) do { \ + mtx_unlock(&(sc)->transmit_lock);\ +} while (0) + +struct tsec_desc { + volatile uint16_t flags; /* descriptor flags */ + volatile uint16_t length; /* buffer length */ + volatile uint32_t bufptr; /* buffer pointer */ +}; + +#define TSEC_READ_RETRY 10000 +#define TSEC_READ_DELAY 100 diff --git a/sys/dev/tsec/if_tsecreg.h b/sys/dev/tsec/if_tsecreg.h new file mode 100644 index 0000000..1fe263d --- /dev/null +++ b/sys/dev/tsec/if_tsecreg.h @@ -0,0 +1,355 @@ +/*- + * Copyright (C) 2006-2007 Semihalf + * All rights reserved. + * + * Written by: Piotr Kruszynski <ppk@semihalf.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#define TSEC_REG_ID 0x000 /* Controller ID register #1. */ +#define TSEC_REG_ID2 0x004 /* Controller ID register #2. */ + +/* TSEC General Control and Status Registers */ +#define TSEC_REG_IEVENT 0x010 /* Interrupt event register */ +#define TSEC_REG_IMASK 0x014 /* Interrupt mask register */ +#define TSEC_REG_EDIS 0x018 /* Error disabled register */ +#define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */ +#define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */ +#define TSEC_REG_PTV 0x028 /* Pause time value register */ +#define TSEC_REG_DMACTRL 0x02c /* DMA control register */ +#define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */ + +/* TSEC FIFO Control and Status Registers */ +#define TSEC_REG_FIFO_PAUSE_CTRL 0x04c /* FIFO pause control register */ +#define TSEC_REG_FIFO_TX_THR 0x08c /* FIFO transmit threshold register */ +#define TSEC_REG_FIFO_TX_STARVE 0x098 /* FIFO transmit starve register */ +#define TSEC_REG_FIFO_TX_STARVE_SHUTOFF 0x09c /* FIFO transmit starve shutoff + * register */ + +/* TSEC Transmit Control and Status Registers */ +#define TSEC_REG_TCTRL 0x100 /* Transmit control register */ +#define TSEC_REG_TSTAT 0x104 /* Transmit Status Register */ +#define TSEC_REG_TBDLEN 0x10c /* TxBD data length register */ +#define TSEC_REG_TXIC 0x110 /* Transmit interrupt coalescing + * configuration register */ +#define TSEC_REG_CTBPTR 0x124 /* Current TxBD pointer register */ +#define TSEC_REG_TBPTR 0x184 /* TxBD pointer register */ +#define TSEC_REG_TBASE 0x204 /* TxBD base address register */ +#define TSEC_REG_OSTBD 0x2b0 /* Out-of-sequence TxBD register */ +#define TSEC_REG_OSTBDP 0x2b4 /* Out-of-sequence Tx data buffer pointer + * register */ + +/* TSEC Receive Control and Status Registers */ +#define TSEC_REG_RCTRL 0x300 /* Receive control register */ +#define TSEC_REG_RSTAT 0x304 /* Receive status register */ +#define TSEC_REG_RBDLEN 0x30c /* RxBD data length register */ +#define TSEC_REG_RXIC 0x310 /* Receive interrupt coalescing + * configuration register */ +#define TSEC_REG_CRBPTR 0x324 /* Current RxBD pointer register */ +#define TSEC_REG_MRBLR 0x340 /* Maximum receive buffer length register */ +#define TSEC_REG_RBPTR 0x384 /* RxBD pointer register */ +#define TSEC_REG_RBASE 0x404 /* RxBD base address register */ + +/* TSEC MAC Registers */ +#define TSEC_REG_MACCFG1 0x500 /* MAC configuration 1 register */ +#define TSEC_REG_MACCFG2 0x504 /* MAC configuration 2 register */ +#define TSEC_REG_IPGIFG 0x508 /* Inter-packet gap/inter-frame gap + * register */ +#define TSEC_REG_HAFDUP 0x50c /* Half-duplex register */ +#define TSEC_REG_MAXFRM 0x510 /* Maximum frame length register */ +#define TSEC_REG_MIIMCFG 0x520 /* MII Management configuration register */ +#define TSEC_REG_MIIMCOM 0x524 /* MII Management command register */ +#define TSEC_REG_MIIMADD 0x528 /* MII Management address register */ +#define TSEC_REG_MIIMCON 0x52c /* MII Management control register */ +#define TSEC_REG_MIIMSTAT 0x530 /* MII Management status register */ +#define TSEC_REG_MIIMIND 0x534 /* MII Management indicator register */ +#define TSEC_REG_IFSTAT 0x53c /* Interface status register */ +#define TSEC_REG_MACSTNADDR1 0x540 /* Station address register, part 1 */ +#define TSEC_REG_MACSTNADDR2 0x544 /* Station address register, part 2 */ + +/* TSEC Transmit and Receive Counters */ +#define TSEC_REG_MON_TR64 0x680 /* Transmit and receive 64-byte + * frame counter register */ +#define TSEC_REG_MON_TR127 0x684 /* Transmit and receive 65-127 byte + * frame counter register */ +#define TSEC_REG_MON_TR255 0x688 /* Transmit and receive 128-255 byte + * frame counter register */ +#define TSEC_REG_MON_TR511 0x68c /* Transmit and receive 256-511 byte + * frame counter register */ +#define TSEC_REG_MON_TR1K 0x690 /* Transmit and receive 512-1023 byte + * frame counter register */ +#define TSEC_REG_MON_TRMAX 0x694 /* Transmit and receive 1024-1518 byte + * frame counter register */ +#define TSEC_REG_MON_TRMGV 0x698 /* Transmit and receive 1519-1522 byte + * good VLAN frame counter register */ + +/* TSEC Receive Counters */ +#define TSEC_REG_MON_RBYT 0x69c /* Receive byte counter register */ +#define TSEC_REG_MON_RPKT 0x6a0 /* Receive packet counter register */ +#define TSEC_REG_MON_RFCS 0x6a4 /* Receive FCS error counter register */ +#define TSEC_REG_MON_RMCA 0x6a8 /* Receive multicast packet counter + * register */ +#define TSEC_REG_MON_RBCA 0x6ac /* Receive broadcast packet counter + * register */ +#define TSEC_REG_MON_RXCF 0x6b0 /* Receive control frame packet counter + * register */ +#define TSEC_REG_MON_RXPF 0x6b4 /* Receive pause frame packet counter + * register */ +#define TSEC_REG_MON_RXUO 0x6b8 /* Receive unknown OP code counter + * register */ +#define TSEC_REG_MON_RALN 0x6bc /* Receive alignment error counter + * register */ +#define TSEC_REG_MON_RFLR 0x6c0 /* Receive frame length error counter + * register */ +#define TSEC_REG_MON_RCDE 0x6c4 /* Receive code error counter register */ +#define TSEC_REG_MON_RCSE 0x6c8 /* Receive carrier sense error counter + * register */ +#define TSEC_REG_MON_RUND 0x6cc /* Receive undersize packet counter + * register */ +#define TSEC_REG_MON_ROVR 0x6d0 /* Receive oversize packet counter + * register */ +#define TSEC_REG_MON_RFRG 0x6d4 /* Receive fragments counter register */ +#define TSEC_REG_MON_RJBR 0x6d8 /* Receive jabber counter register */ +#define TSEC_REG_MON_RDRP 0x6dc /* Receive drop counter register */ + +/* TSEC Transmit Counters */ +#define TSEC_REG_MON_TBYT 0x6e0 /* Transmit byte counter register */ +#define TSEC_REG_MON_TPKT 0x6e4 /* Transmit packet counter register */ +#define TSEC_REG_MON_TMCA 0x6e8 /* Transmit multicast packet counter + * register */ +#define TSEC_REG_MON_TBCA 0x6ec /* Transmit broadcast packet counter + * register */ +#define TSEC_REG_MON_TXPF 0x6f0 /* Transmit PAUSE control frame counter + * register */ +#define TSEC_REG_MON_TDFR 0x6f4 /* Transmit deferral packet counter + * register */ +#define TSEC_REG_MON_TEDF 0x6f8 /* Transmit excessive deferral packet + * counter register */ +#define TSEC_REG_MON_TSCL 0x6fc /* Transmit single collision packet counter + * register */ +#define TSEC_REG_MON_TMCL 0x700 /* Transmit multiple collision packet counter + * register */ +#define TSEC_REG_MON_TLCL 0x704 /* Transmit late collision packet counter + * register */ +#define TSEC_REG_MON_TXCL 0x708 /* Transmit excessive collision packet + * counter register */ +#define TSEC_REG_MON_TNCL 0x70c /* Transmit total collision counter + * register */ +#define TSEC_REG_MON_TDRP 0x714 /* Transmit drop frame counter register */ +#define TSEC_REG_MON_TJBR 0x718 /* Transmit jabber frame counter register */ +#define TSEC_REG_MON_TFCS 0x71c /* Transmit FCS error counter register */ +#define TSEC_REG_MON_TXCF 0x720 /* Transmit control frame counter register */ +#define TSEC_REG_MON_TOVR 0x724 /* Transmit oversize frame counter + * register */ +#define TSEC_REG_MON_TUND 0x728 /* Transmit undersize frame counter + * register */ +#define TSEC_REG_MON_TFRG 0x72c /* Transmit fragments frame counter + * register */ + +/* TSEC General Registers */ +#define TSEC_REG_MON_CAR1 0x730 /* Carry register one register */ +#define TSEC_REG_MON_CAR2 0x734 /* Carry register two register */ +#define TSEC_REG_MON_CAM1 0x738 /* Carry register one mask register */ +#define TSEC_REG_MON_CAM2 0x73c /* Carry register two mask register */ + +/* TSEC Hash Function Registers */ +#define TSEC_REG_IADDR0 0x800 /* Indivdual address register 0 */ +#define TSEC_REG_IADDR1 0x804 /* Indivdual address register 1 */ +#define TSEC_REG_IADDR2 0x808 /* Indivdual address register 2 */ +#define TSEC_REG_IADDR3 0x80c /* Indivdual address register 3 */ +#define TSEC_REG_IADDR4 0x810 /* Indivdual address register 4 */ +#define TSEC_REG_IADDR5 0x814 /* Indivdual address register 5 */ +#define TSEC_REG_IADDR6 0x818 /* Indivdual address register 6 */ +#define TSEC_REG_IADDR7 0x81c /* Indivdual address register 7 */ +#define TSEC_REG_GADDR0 0x880 /* Group address register 0 */ +#define TSEC_REG_GADDR1 0x884 /* Group address register 1 */ +#define TSEC_REG_GADDR2 0x888 /* Group address register 2 */ +#define TSEC_REG_GADDR3 0x88c /* Group address register 3 */ +#define TSEC_REG_GADDR4 0x890 /* Group address register 4 */ +#define TSEC_REG_GADDR5 0x894 /* Group address register 5 */ +#define TSEC_REG_GADDR6 0x898 /* Group address register 6 */ +#define TSEC_REG_GADDR7 0x89c /* Group address register 7 */ + +/* TSEC attribute registers */ +#define TSEC_REG_ATTR 0xbf8 /* Attributes Register */ +#define TSEC_REG_ATTRELI 0xbfc /* Attributes EL & EI register */ + +/* Size of TSEC registers area */ +#define TSEC_IO_SIZE 0x1000 + +/* reg bits */ +#define TSEC_FIFO_PAUSE_CTRL_EN 0x0002 + +#define TSEC_DMACTRL_TDSEN 0x00000080 /* Tx Data snoop enable */ +#define TSEC_DMACTRL_TBDSEN 0x00000040 /* TxBD snoop enable */ +#define TSEC_DMACTRL_GRS 0x00000010 /* Graceful receive stop */ +#define TSEC_DMACTRL_GTS 0x00000008 /* Graceful transmit stop */ +#define DMACTRL_WWR 0x00000002 /* Write with response */ +#define DMACTRL_WOP 0x00000001 /* Wait or poll */ + +#define TSEC_RCTRL_BC_REJ 0x00000010 /* Broadcast frame reject */ +#define TSEC_RCTRL_PROM 0x00000008 /* Promiscuous mode */ +#define TSEC_RCTRL_RSF 0x00000004 /* Receive short frame mode */ + +#define TSEC_TSTAT_THLT 0x80000000 /* Transmit halt */ +#define TSEC_RSTAT_QHLT 0x00800000 /* RxBD queue is halted */ + +#define TSEC_IEVENT_BABR 0x80000000 /* Babbling receive error */ +#define TSEC_IEVENT_RXC 0x40000000 /* Receive control interrupt */ +#define TSEC_IEVENT_BSY 0x20000000 /* Busy condition interrupt */ +#define TSEC_IEVENT_EBERR 0x10000000 /* Ethernet bus error */ +#define TSEC_IEVENT_MSRO 0x04000000 /* MSTAT Register Overflow */ +#define TSEC_IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ +#define TSEC_IEVENT_BABT 0x01000000 /* Babbling transmit error */ +#define TSEC_IEVENT_TXC 0x00800000 /* Transmit control interrupt */ +#define TSEC_IEVENT_TXE 0x00400000 /* Transmit error */ +#define TSEC_IEVENT_TXB 0x00200000 /* Transmit buffer */ +#define TSEC_IEVENT_TXF 0x00100000 /* Transmit frame interrupt */ +#define TSEC_IEVENT_LC 0x00040000 /* Late collision */ +#define TSEC_IEVENT_CRL 0x00020000 /* Collision retry limit/excessive + * defer abort */ +#define TSEC_IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ +#define TSEC_IEVENT_RXB 0x00008000 /* Receive buffer */ +#define TSEC_IEVENT_MMRD 0x00000400 /* MII management read completion */ +#define TSEC_IEVENT_MMWR 0x00000200 /* MII management write completion */ +#define TSEC_IEVENT_GRSC 0x00000100 /* Graceful receive stop complete */ +#define TSEC_IEVENT_RXF 0x00000080 /* Receive frame interrupt */ + +#define TSEC_IMASK_BREN 0x80000000 /* Babbling receiver interrupt */ +#define TSEC_IMASK_RXCEN 0x40000000 /* Receive control interrupt */ +#define TSEC_IMASK_BSYEN 0x20000000 /* Busy interrupt */ +#define TSEC_IMASK_EBERREN 0x10000000 /* Ethernet controller bus error */ +#define TSEC_IMASK_MSROEN 0x04000000 /* MSTAT register overflow interrupt */ +#define TSEC_IMASK_GTSCEN 0x02000000 /* Graceful transmit stop complete interrupt */ +#define TSEC_IMASK_BTEN 0x01000000 /* Babbling transmitter interrupt */ +#define TSEC_IMASK_TXCEN 0x00800000 /* Transmit control interrupt */ +#define TSEC_IMASK_TXEEN 0x00400000 /* Transmit error interrupt */ +#define TSEC_IMASK_TXBEN 0x00200000 /* Transmit buffer interrupt */ +#define TSEC_IMASK_TXFEN 0x00100000 /* Transmit frame interrupt */ +#define TSEC_IMASK_LCEN 0x00040000 /* Late collision */ +#define TSEC_IMASK_CRLEN 0x00020000 /* Collision retry limit/excessive defer */ +#define TSEC_IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun */ +#define TSEC_IMASK_RXBEN 0x00008000 /* Receive buffer interrupt */ +#define TSEC_IMASK_MMRD 0x00000400 /* MII management read completion */ +#define TSEC_IMASK_MMWR 0x00000200 /* MII management write completion */ +#define TSEC_IMASK_GRSCEN 0x00000100 /* Graceful receive stop complete interrupt */ +#define TSEC_IMASK_RXFEN 0x00000080 /* Receive frame interrupt */ + +#define TSEC_ATTR_ELCWT 0x00004000 /* Write extracted data to L2 cache */ +#define TSEC_ATTR_BDLWT 0x00000800 /* Write buffer descriptor to L2 cache */ +#define TSEC_ATTR_RDSEN 0x00000080 /* Rx data snoop enable */ +#define TSEC_ATTR_RBDSEN 0x00000040 /* RxBD snoop enable */ + +#define TSEC_MACCFG1_SOFT_RESET 0x80000000 /* Soft reset */ +#define TSEC_MACCFG1_RESET_RX_MC 0x00080000 /* Reset receive MAC control block */ +#define TSEC_MACCFG1_RESET_TX_MC 0x00040000 /* Reset transmit MAC control block */ +#define TSEC_MACCFG1_RESET_RX_FUN 0x00020000 /* Reset receive function block */ +#define TSEC_MACCFG1_RESET_TX_FUN 0x00010000 /* Reset transmit function block */ +#define TSEC_MACCFG1_LOOPBACK 0x00000100 /* Loopback */ +#define TSEC_MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ +#define TSEC_MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ +#define TSEC_MACCFG1_SYNCD_RX_EN 0x00000008 /* Receive enable synchronized + * to the receive stream (Read-only) */ +#define TSEC_MACCFG1_RX_EN 0x00000004 /* Receive enable */ +#define TSEC_MACCFG1_SYNCD_TX_EN 0x00000002 /* Transmit enable synchronized + * to the transmit stream (Read-only) */ +#define TSEC_MACCFG1_TX_EN 0x00000001 /* Transmit enable */ + +#define TSEC_MACCFG2_PRECNT 0x00007000 /* Preamble Length (0x7) */ +#define TSEC_MACCFG2_IF 0x00000300 /* Determines the type of interface + * to which the MAC is connected */ +#define TSEC_MACCFG2_MII 0x00000100 /* Nibble mode (MII) */ +#define TSEC_MACCFG2_GMII 0x00000200 /* Byte mode (GMII/TBI) */ +#define TSEC_MACCFG2_HUGEFRAME 0x00000020 /* Huge frame enable */ +#define TSEC_MACCFG2_LENGTHCHECK 0x00000010 /* Length check */ +#define TSEC_MACCFG2_PADCRC 0x00000004 /* Pad and append CRC */ +#define TSEC_MACCFG2_CRCEN 0x00000002 /* CRC enable */ +#define TSEC_MACCFG2_FULLDUPLEX 0x00000001 /* Full duplex configure */ + +#define TSEC_ECNTRL_STEN 0x00001000 /* Statistics enabled */ +#define TSEC_ECNTRL_GMIIM 0x00000040 /* GMII I/F mode */ +#define TSEC_ECNTRL_TBIM 0x00000020 /* Ten-bit I/F mode */ +#define TSEC_ECNTRL_R100M 0x00000008 /* RGMII/RMII 100 mode */ +#define TSEC_ECNTRL_RMM 0x00000004 /* Reduced-pin mode */ +#define TSEC_ECNTRL_SGMIIM 0x00000002 /* Serial GMII mode */ + +#define TSEC_MIIMCFG_RESETMGMT 0x80000000 /* Reset management */ +#define TSEC_MIIMCFG_NOPRE 0x00000010 /* Preamble suppress */ +#define TSEC_MIIMCFG_CLKDIV28 0x00000007 /* source clock divided by 28 */ +#define TSEC_MIIMCFG_CLKDIV20 0x00000006 /* source clock divided by 20 */ +#define TSEC_MIIMCFG_CLKDIV14 0x00000005 /* source clock divided by 14 */ +#define TSEC_MIIMCFG_CLKDIV10 0x00000004 /* source clock divided by 10 */ +#define TSEC_MIIMCFG_CLKDIV8 0x00000003 /* source clock divided by 8 */ +#define TSEC_MIIMCFG_CLKDIV6 0x00000002 /* source clock divided by 6 */ +#define TSEC_MIIMCFG_CLKDIV4 0x00000001 /* source clock divided by 4 */ + +#define TSEC_MIIMIND_NOTVALID 0x00000004 /* Not valid */ +#define TSEC_MIIMIND_SCAN 0x00000002 /* Scan in progress */ +#define TSEC_MIIMIND_BUSY 0x00000001 /* Busy */ + +#define TSEC_MIIMCOM_SCANCYCLE 0x00000002 /* Scan cycle */ +#define TSEC_MIIMCOM_READCYCLE 0x00000001 /* Read cycle */ + +/* Transmit Data Buffer Descriptor (TxBD) Field Descriptions */ +#define TSEC_TXBD_R 0x8000 /* Ready */ +#define TSEC_TXBD_PADCRC 0x4000 /* PAD/CRC */ +#define TSEC_TXBD_W 0x2000 /* Wrap */ +#define TSEC_TXBD_I 0x1000 /* Interrupt */ +#define TSEC_TXBD_L 0x0800 /* Last in frame */ +#define TSEC_TXBD_TC 0x0400 /* Tx CRC */ +#define TSEC_TXBD_DEF 0x0200 /* Defer indication */ +#define TSEC_TXBD_TO1 0x0100 /* Transmit software ownership */ +#define TSEC_TXBD_HFE 0x0080 /* Huge frame enable (written by user) */ +#define TSEC_TXBD_LC 0x0080 /* Late collision (written by TSEC) */ +#define TSEC_TXBD_RL 0x0040 /* Retransmission Limit */ +#define TSEC_TXBD_UN 0x0002 /* Underrun */ +#define TSEC_TXBD_TXTRUNC 0x0001 /* TX truncation */ + +/* Receive Data Buffer Descriptor (RxBD) Field Descriptions */ +#define TSEC_RXBD_E 0x8000 /* Empty */ +#define TSEC_RXBD_RO1 0x4000 /* Receive software ownership bit */ +#define TSEC_RXBD_W 0x2000 /* Wrap */ +#define TSEC_RXBD_I 0x1000 /* Interrupt */ +#define TSEC_RXBD_L 0x0800 /* Last in frame */ +#define TSEC_RXBD_F 0x0400 /* First in frame */ +#define TSEC_RXBD_M 0x0100 /* Miss - The frame was received because + * of promiscuous mode. */ +#define TSEC_RXBD_B 0x0080 /* Broadcast */ +#define TSEC_RXBD_MC 0x0040 /* Multicast */ +#define TSEC_RXBD_LG 0x0020 /* Large - Rx frame length violation */ +#define TSEC_RXBD_NO 0x0010 /* Rx non-octet aligned frame */ +#define TSEC_RXBD_SH 0x0008 /* Short frame */ +#define TSEC_RXBD_CR 0x0004 /* Rx CRC error */ +#define TSEC_RXBD_OV 0x0002 /* Overrun */ +#define TSEC_RXBD_TR 0x0001 /* Truncation */ +#define TSEC_RXBD_ZEROONINIT (TSEC_RXBD_TR | TSEC_RXBD_OV | TSEC_RXBD_CR | \ + TSEC_RXBD_SH | TSEC_RXBD_NO | TSEC_RXBD_LG | TSEC_RXBD_MC | \ + TSEC_RXBD_B | TSEC_RXBD_M) + +#define TSEC_TXBUFFER_ALIGNMENT 64 +#define TSEC_RXBUFFER_ALIGNMENT 64 +#define TSEC_DEFAULT_MAX_RX_BUFFER_SIZE 0x0600 +#define TSEC_DEFAULT_MIN_RX_BUFFER_SIZE 0x0040 |
