diff options
Diffstat (limited to 'sys/x86')
| -rw-r--r-- | sys/x86/include/apicvar.h | 6 | ||||
| -rw-r--r-- | sys/x86/include/specialreg.h | 8 | ||||
| -rw-r--r-- | sys/x86/include/x86_smp.h | 5 | ||||
| -rw-r--r-- | sys/x86/include/x86_var.h | 5 | ||||
| -rw-r--r-- | sys/x86/isa/atpic.c | 17 | ||||
| -rw-r--r-- | sys/x86/x86/cpu_machdep.c | 52 | ||||
| -rw-r--r-- | sys/x86/x86/identcpu.c | 11 | ||||
| -rw-r--r-- | sys/x86/x86/local_apic.c | 40 | ||||
| -rw-r--r-- | sys/x86/x86/mp_x86.c | 11 | ||||
| -rw-r--r-- | sys/x86/xen/pv.c | 3 |
10 files changed, 24 insertions, 134 deletions
diff --git a/sys/x86/include/apicvar.h b/sys/x86/include/apicvar.h index cd94ed5..ba3a237 100644 --- a/sys/x86/include/apicvar.h +++ b/sys/x86/include/apicvar.h @@ -179,11 +179,7 @@ inthand_t IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), - IDTVEC(spuriousint), IDTVEC(timerint), - IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti), - IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti), - IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti), - IDTVEC(spuriousint_pti), IDTVEC(timerint_pti); + IDTVEC(spuriousint), IDTVEC(timerint); extern vm_paddr_t lapic_paddr; extern int apic_cpuids[]; diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 9ca3d1a..b897b42 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -578,13 +578,9 @@ #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL #define IA32_MISC_EN_XDD 0x0000000400000000ULL -/* - * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' - * document 336996-001 Speculative Execution Side Channel Mitigations. - */ /* MSR IA32_SPEC_CTRL */ -#define IA32_SPEC_CTRL_IBRS 0x00000001 -#define IA32_SPEC_CTRL_STIBP 0x00000002 +#define IA32_SPEC_CTRL_IBRS 0x0000000000000001ULL +#define IA32_SPEC_CTRL_STIBP 0x0000000000000002ULL /* MSR IA32_PRED_CMD */ #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL diff --git a/sys/x86/include/x86_smp.h b/sys/x86/include/x86_smp.h index 8d5980c..84a0eba 100644 --- a/sys/x86/include/x86_smp.h +++ b/sys/x86/include/x86_smp.h @@ -37,7 +37,6 @@ extern int cpu_logical; extern int cpu_cores; extern volatile uint32_t smp_tlb_generation; extern struct pmap *smp_tlb_pmap; -extern vm_offset_t smp_tlb_addr1, smp_tlb_addr2; extern u_int xhits_gbl[]; extern u_int xhits_pg[]; extern u_int xhits_rng[]; @@ -96,9 +95,9 @@ void ipi_selected(cpuset_t cpus, u_int ipi); u_int mp_bootaddress(u_int); void set_interrupt_apic_ids(void); void smp_cache_flush(void); -void smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, struct pmap *pmap); +void smp_masked_invlpg(cpuset_t mask, vm_offset_t addr); void smp_masked_invlpg_range(cpuset_t mask, vm_offset_t startva, - vm_offset_t endva, struct pmap *pmap); + vm_offset_t endva); void smp_masked_invltlb(cpuset_t mask, struct pmap *pmap); void mem_range_AP_init(void); void topo_probe(void); diff --git a/sys/x86/include/x86_var.h b/sys/x86/include/x86_var.h index a4bb7f3..0f720b3 100644 --- a/sys/x86/include/x86_var.h +++ b/sys/x86/include/x86_var.h @@ -81,7 +81,6 @@ extern int _ufssel; extern int _ugssel; extern int use_xsave; extern uint64_t xsave_mask; -extern int pti; struct pcb; struct thread; @@ -129,15 +128,11 @@ bool fix_cpuid(void); void fillw(int /*u_short*/ pat, void *base, size_t cnt); int is_physical_memory(vm_paddr_t addr); int isa_nmi(int cd); -void handle_ibrs_entry(void); -void handle_ibrs_exit(void); -void hw_ibrs_recalculate(void); void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame); void nmi_call_kdb_smp(u_int type, struct trapframe *frame); void nmi_handle_intr(u_int type, struct trapframe *frame); void pagecopy(void *from, void *to); void printcpuinfo(void); -int pti_get_default(void); int user_dbreg_trap(void); int minidumpsys(struct dumperinfo *); struct pcb *get_pcb_td(struct thread *td); diff --git a/sys/x86/isa/atpic.c b/sys/x86/isa/atpic.c index 0364919..43504e7 100644 --- a/sys/x86/isa/atpic.c +++ b/sys/x86/isa/atpic.c @@ -86,16 +86,6 @@ inthand_t IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11), IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14), IDTVEC(atpic_intr15); -/* XXXKIB i386 uses stubs until pti comes */ -inthand_t - IDTVEC(atpic_intr0_pti), IDTVEC(atpic_intr1_pti), - IDTVEC(atpic_intr2_pti), IDTVEC(atpic_intr3_pti), - IDTVEC(atpic_intr4_pti), IDTVEC(atpic_intr5_pti), - IDTVEC(atpic_intr6_pti), IDTVEC(atpic_intr7_pti), - IDTVEC(atpic_intr8_pti), IDTVEC(atpic_intr9_pti), - IDTVEC(atpic_intr10_pti), IDTVEC(atpic_intr11_pti), - IDTVEC(atpic_intr12_pti), IDTVEC(atpic_intr13_pti), - IDTVEC(atpic_intr14_pti), IDTVEC(atpic_intr15_pti); #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq) @@ -108,7 +98,7 @@ inthand_t #define INTSRC(irq) \ { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \ - IDTVEC(atpic_intr ## irq ## _pti), (irq) % 8 } + (irq) % 8 } struct atpic { struct pic at_pic; @@ -120,7 +110,7 @@ struct atpic { struct atpic_intsrc { struct intsrc at_intsrc; - inthand_t *at_intr, *at_intr_pti; + inthand_t *at_intr; int at_irq; /* Relative to PIC base. */ enum intr_trigger at_trigger; u_long at_count; @@ -445,8 +435,7 @@ atpic_startup(void) ai->at_intsrc.is_count = &ai->at_count; ai->at_intsrc.is_straycount = &ai->at_straycount; setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase + - ai->at_irq, pti ? ai->at_intr_pti : ai->at_intr, SDT_ATPIC, - SEL_KPL, GSEL_ATPIC); + ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC); } #ifdef DEV_MCA diff --git a/sys/x86/x86/cpu_machdep.c b/sys/x86/x86/cpu_machdep.c index 9449d3e..c2d42a9 100644 --- a/sys/x86/x86/cpu_machdep.c +++ b/sys/x86/x86/cpu_machdep.c @@ -139,12 +139,6 @@ acpi_cpu_idle_mwait(uint32_t mwait_hint) int *state; /* - * A comment in Linux patch claims that 'CPUs run faster with - * speculation protection disabled. All CPU threads in a core - * must disable speculation protection for it to be - * disabled. Disable it while we are idle so the other - * hyperthread can run fast.' - * * XXXKIB. Software coordination mode should be supported, * but all Intel CPUs provide hardware coordination. */ @@ -153,11 +147,9 @@ acpi_cpu_idle_mwait(uint32_t mwait_hint) KASSERT(*state == STATE_SLEEPING, ("cpu_mwait_cx: wrong monitorbuf state")); *state = STATE_MWAIT; - handle_ibrs_entry(); cpu_monitor(state, 0, 0); if (*state == STATE_MWAIT) cpu_mwait(MWAIT_INTRBREAK, mwait_hint); - handle_ibrs_exit(); /* * We should exit on any event that interrupts mwait, because @@ -586,47 +578,3 @@ nmi_handle_intr(u_int type, struct trapframe *frame) nmi_call_kdb(PCPU_GET(cpuid), type, frame); #endif } - -int hw_ibrs_active; -int hw_ibrs_disable = 1; - -SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0, - "Indirect Branch Restricted Speculation active"); - -void -hw_ibrs_recalculate(void) -{ - uint64_t v; - - if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) { - if (hw_ibrs_disable) { - v= rdmsr(MSR_IA32_SPEC_CTRL); - v &= ~(uint64_t)IA32_SPEC_CTRL_IBRS; - wrmsr(MSR_IA32_SPEC_CTRL, v); - } else { - v= rdmsr(MSR_IA32_SPEC_CTRL); - v |= IA32_SPEC_CTRL_IBRS; - wrmsr(MSR_IA32_SPEC_CTRL, v); - } - return; - } - hw_ibrs_active = (cpu_stdext_feature3 & CPUID_STDEXT3_IBPB) != 0 && - !hw_ibrs_disable; -} - -static int -hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS) -{ - int error, val; - - val = hw_ibrs_disable; - error = sysctl_handle_int(oidp, &val, 0, req); - if (error != 0 || req->newptr == NULL) - return (error); - hw_ibrs_disable = val != 0; - hw_ibrs_recalculate(); - return (0); -} -SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN | - CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I", - "Disable Indirect Branch Restricted Speculation"); diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c index 2c0af5f..033f873 100644 --- a/sys/x86/x86/identcpu.c +++ b/sys/x86/x86/identcpu.c @@ -1604,17 +1604,6 @@ finishidentcpu(void) #endif } -int -pti_get_default(void) -{ - - if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0) - return (0); - if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) - return (0); - return (1); -} - static u_int find_cpu_vendor_id(void) { diff --git a/sys/x86/x86/local_apic.c b/sys/x86/x86/local_apic.c index 085a28f..11041d4 100644 --- a/sys/x86/x86/local_apic.c +++ b/sys/x86/x86/local_apic.c @@ -166,23 +166,13 @@ static inthand_t *ioint_handlers[] = { IDTVEC(apic_isr7), /* 224 - 255 */ }; -static inthand_t *ioint_pti_handlers[] = { - NULL, /* 0 - 31 */ - IDTVEC(apic_isr1_pti), /* 32 - 63 */ - IDTVEC(apic_isr2_pti), /* 64 - 95 */ - IDTVEC(apic_isr3_pti), /* 96 - 127 */ - IDTVEC(apic_isr4_pti), /* 128 - 159 */ - IDTVEC(apic_isr5_pti), /* 160 - 191 */ - IDTVEC(apic_isr6_pti), /* 192 - 223 */ - IDTVEC(apic_isr7_pti), /* 224 - 255 */ -}; static u_int32_t lapic_timer_divisors[] = { APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 }; -extern inthand_t IDTVEC(rsvd_pti), IDTVEC(rsvd); +extern inthand_t IDTVEC(rsvd); volatile char *lapic_map; vm_paddr_t lapic_paddr; @@ -499,18 +489,15 @@ native_lapic_init(vm_paddr_t addr) PCPU_SET(apic_id, lapic_id()); /* Local APIC timer interrupt. */ - setidt(APIC_TIMER_INT, pti ? IDTVEC(timerint_pti) : IDTVEC(timerint), - SDT_APIC, SEL_KPL, GSEL_APIC); + setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC); /* Local APIC error interrupt. */ - setidt(APIC_ERROR_INT, pti ? IDTVEC(errorint_pti) : IDTVEC(errorint), - SDT_APIC, SEL_KPL, GSEL_APIC); + setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC); /* XXX: Thermal interrupt */ /* Local APIC CMCI. */ - setidt(APIC_CMC_INT, pti ? IDTVEC(cmcint_pti) : IDTVEC(cmcint), - SDT_APICT, SEL_KPL, GSEL_APIC); + setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL, GSEL_APIC); if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) { arat = 0; @@ -1574,8 +1561,8 @@ native_apic_enable_vector(u_int apic_id, u_int vector) KASSERT(vector != IDT_DTRACE_RET, ("Attempt to overwrite DTrace entry")); #endif - setidt(vector, (pti ? ioint_pti_handlers : ioint_handlers)[vector / 32], - SDT_APIC, SEL_KPL, GSEL_APIC); + setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL, + GSEL_APIC); } static void @@ -1594,8 +1581,7 @@ native_apic_disable_vector(u_int apic_id, u_int vector) * We can not currently clear the idt entry because other cpus * may have a valid vector at this offset. */ - setidt(vector, pti ? &IDTVEC(rsvd_pti) : &IDTVEC(rsvd), SDT_APICT, - SEL_KPL, GSEL_APIC); + setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC); #endif } @@ -2098,16 +2084,14 @@ native_lapic_ipi_alloc(inthand_t *ipifunc) long func; int idx, vector; - KASSERT(ipifunc != &IDTVEC(rsvd) && ipifunc != &IDTVEC(rsvd_pti), - ("invalid ipifunc %p", ipifunc)); + KASSERT(ipifunc != &IDTVEC(rsvd), ("invalid ipifunc %p", ipifunc)); vector = -1; mtx_lock_spin(&icu_lock); for (idx = IPI_DYN_FIRST; idx <= IPI_DYN_LAST; idx++) { ip = &idt[idx]; func = (ip->gd_hioffset << 16) | ip->gd_looffset; - if ((!pti && func == (uintptr_t)&IDTVEC(rsvd)) || - (pti && func == (uintptr_t)&IDTVEC(rsvd_pti))) { + if (func == (uintptr_t)&IDTVEC(rsvd)) { vector = idx; setidt(vector, ipifunc, SDT_APIC, SEL_KPL, GSEL_APIC); break; @@ -2129,10 +2113,8 @@ native_lapic_ipi_free(int vector) mtx_lock_spin(&icu_lock); ip = &idt[vector]; func = (ip->gd_hioffset << 16) | ip->gd_looffset; - KASSERT(func != (uintptr_t)&IDTVEC(rsvd) && - func != (uintptr_t)&IDTVEC(rsvd_pti), + KASSERT(func != (uintptr_t)&IDTVEC(rsvd), ("invalid idtfunc %#lx", func)); - setidt(vector, pti ? &IDTVEC(rsvd_pti) : &IDTVEC(rsvd), SDT_APICT, - SEL_KPL, GSEL_APIC); + setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC); mtx_unlock_spin(&icu_lock); } diff --git a/sys/x86/x86/mp_x86.c b/sys/x86/x86/mp_x86.c index cd10782..7cc02d6 100644 --- a/sys/x86/x86/mp_x86.c +++ b/sys/x86/x86/mp_x86.c @@ -1436,7 +1436,7 @@ SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); */ /* Variables needed for SMP tlb shootdown. */ -vm_offset_t smp_tlb_addr1, smp_tlb_addr2; +static vm_offset_t smp_tlb_addr1, smp_tlb_addr2; pmap_t smp_tlb_pmap; volatile uint32_t smp_tlb_generation; @@ -1509,11 +1509,11 @@ smp_masked_invltlb(cpuset_t mask, pmap_t pmap) } void -smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, pmap_t pmap) +smp_masked_invlpg(cpuset_t mask, vm_offset_t addr) { if (smp_started) { - smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0); + smp_targeted_tlb_shootdown(mask, IPI_INVLPG, NULL, addr, 0); #ifdef COUNT_XINVLTLB_HITS ipi_page++; #endif @@ -1521,12 +1521,11 @@ smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, pmap_t pmap) } void -smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2, - pmap_t pmap) +smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2) { if (smp_started) { - smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap, + smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, NULL, addr1, addr2); #ifdef COUNT_XINVLTLB_HITS ipi_range++; diff --git a/sys/x86/xen/pv.c b/sys/x86/xen/pv.c index f4b68f0..9ad9aa9 100644 --- a/sys/x86/xen/pv.c +++ b/sys/x86/xen/pv.c @@ -97,7 +97,6 @@ static int xen_pv_start_all_aps(void); #ifdef SMP /* Variables used by amd64 mp_machdep to start APs */ extern char *doublefault_stack; -extern char *mce_stack; extern char *nmi_stack; #endif @@ -218,8 +217,6 @@ start_xen_ap(int cpu) (void *)kmem_malloc(kernel_arena, stacksize, M_WAITOK | M_ZERO); doublefault_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE, M_WAITOK | M_ZERO); - mce_stack = - (char *)kmem_malloc(kernel_arena, PAGE_SIZE, M_WAITOK | M_ZERO); nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE, M_WAITOK | M_ZERO); dpcpu = |
