diff options
Diffstat (limited to 'sys/pci')
| -rw-r--r-- | sys/pci/pci.c | 39 | ||||
| -rw-r--r-- | sys/pci/pcisupport.c | 16 | ||||
| -rw-r--r-- | sys/pci/pcivar.h | 31 |
3 files changed, 82 insertions, 4 deletions
diff --git a/sys/pci/pci.c b/sys/pci/pci.c index 3583a98..d09665f0 100644 --- a/sys/pci/pci.c +++ b/sys/pci/pci.c @@ -23,7 +23,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pci.c,v 1.102 1999/05/09 20:27:26 peter Exp $ + * $Id: pci.c,v 1.103 1999/05/10 17:56:22 dfr Exp $ * */ @@ -199,6 +199,26 @@ pci_readmaps(pcicfgregs *cfg, int maxmaps) map[j].base = base; map64 = 0; } +#ifdef __alpha__ + /* + * XXX: encode hose number in the base addr, + * This will go away once the bus_space functions + * can deal with multiple hoses + */ + + if(cfg->hose){ + if(map[j].base & 0x80000000){ + printf("base addr = 0x%x\n", map[j].base); + printf("hacked addr = 0x%x\n", + map[j].base | (cfg->hose << 31)); + + panic("hose encoding hack would clobber base addr"); + } + if(cfg->hose > 1 ) + panic("only one hose supported!"); + map[j].base |= (cfg->hose << 31); + } +#endif j++; } } @@ -339,7 +359,8 @@ pci_readcfg(pcicfgregs *probe) bzero(devlist_entry, sizeof *devlist_entry); cfg = &devlist_entry->cfg; - + + cfg->hose = probe->hose; cfg->bus = probe->bus; cfg->slot = probe->slot; cfg->func = probe->func; @@ -447,6 +468,7 @@ pci_freecfg(struct pci_devinfo *dinfo) } #endif + /* * This is the user interface to PCI configuration space. */ @@ -991,7 +1013,14 @@ pci_add_children(device_t dev, int busno) #endif bzero(&probe, sizeof probe); +#ifdef __alpha__ + probe.hose = pcib_get_hose(dev); +#endif +#ifdef __i386__ + probe.hose = 0; +#endif probe.bus = busno; + for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { int pcifunchigh = 0; for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { @@ -1097,6 +1126,12 @@ pci_read_ivar(device_t dev, device_t child, int which, u_long *result) case PCI_IVAR_SUBORDINATEBUS: *result = cfg->subordinatebus; break; + case PCI_IVAR_HOSE: + /* + * Pass up to parent bridge. + */ + *result = pcib_get_hose(dev); + break; default: return ENOENT; } diff --git a/sys/pci/pcisupport.c b/sys/pci/pcisupport.c index 42b788a..dff5600 100644 --- a/sys/pci/pcisupport.c +++ b/sys/pci/pcisupport.c @@ -1,6 +1,6 @@ /************************************************************************** ** -** $Id: pcisupport.c,v 1.110 1999/05/10 17:56:23 dfr Exp $ +** $Id: pcisupport.c,v 1.111 1999/05/11 07:55:31 peter Exp $ ** ** Device driver for DEC/INTEL PCI chipsets. ** @@ -869,6 +869,19 @@ static int pcib_attach(device_t dev) return 0; } +static int +pcib_read_ivar(device_t dev, device_t child, int which, u_long *result) +{ + if (which == PCIB_IVAR_HOSE) { + /* + * Pass up to parent bus. + */ + *result = pci_get_hose(dev); + return(0); + } + return ENOENT; +} + static device_method_t pcib_methods[] = { /* Device interface */ DEVMETHOD(device_probe, pcib_probe), @@ -879,6 +892,7 @@ static device_method_t pcib_methods[] = { /* Bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_read_ivar, pcib_read_ivar), DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), diff --git a/sys/pci/pcivar.h b/sys/pci/pcivar.h index 432551b..29d82a3 100644 --- a/sys/pci/pcivar.h +++ b/sys/pci/pcivar.h @@ -23,7 +23,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pcivar.h,v 1.31 1999/05/11 07:55:32 peter Exp $ + * $Id: pcivar.h,v 1.32 1999/05/18 20:48:38 peter Exp $ * */ @@ -104,6 +104,7 @@ typedef struct pcicfg { u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ u_int8_t nummaps; /* actual number of PCI maps used */ + u_int8_t hose; /* hose which bus is attached to */ u_int8_t bus; /* config space bus address */ u_int8_t slot; /* config space slot address */ u_int8_t func; /* config space function number */ @@ -205,6 +206,7 @@ enum pci_device_ivars { PCI_IVAR_FUNCTION, PCI_IVAR_SECONDARYBUS, PCI_IVAR_SUBORDINATEBUS, + PCI_IVAR_HOSE, }; /* @@ -241,6 +243,7 @@ PCI_ACCESSOR(slot, SLOT, u_int8_t) PCI_ACCESSOR(function, FUNCTION, u_int8_t) PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) +PCI_ACCESSOR(hose, HOSE, u_int32_t) static __inline u_int32_t pci_read_config(device_t dev, int reg, int width) @@ -254,6 +257,32 @@ pci_write_config(device_t dev, int reg, u_int32_t val, int width) PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); } +/* + * Ivars for pci bridges. + */ + +/*typedef enum pci_device_ivars pcib_device_ivars;*/ +enum pcib_device_ivars { + PCIB_IVAR_HOSE, +}; + +#define PCIB_ACCESSOR(A, B, T) \ + \ +static __inline T pcib_get_ ## A(device_t dev) \ +{ \ + uintptr_t v; \ + BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ + return (T) v; \ +} \ + \ +static __inline void pcib_set_ ## A(device_t dev, T t) \ +{ \ + u_long v = (u_long) t; \ + BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ +} + +PCIB_ACCESSOR(hose, HOSE, u_int32_t) + #endif /* for compatibility to FreeBSD-2.2 version of PCI code */ |
