summaryrefslogtreecommitdiffstats
path: root/sys/dev
diff options
context:
space:
mode:
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/drm2/i915/intel_iic.c2
-rw-r--r--sys/dev/drm2/ttm/ttm_bo.c10
-rw-r--r--sys/dev/drm2/ttm/ttm_page_alloc.c10
-rw-r--r--sys/dev/if_ndis/if_ndis_pci.c3
-rw-r--r--sys/dev/ioat/ioat.c9
-rw-r--r--sys/dev/ioat/ioat.h11
-rw-r--r--sys/dev/ioat/ioat_hw.h3
-rw-r--r--sys/dev/mmc/mmc.c2
-rw-r--r--sys/dev/nand/nand_cdev.c4
-rw-r--r--sys/dev/nand/nand_geom.c22
-rw-r--r--sys/dev/ofw/ofw_bus_subr.c17
-rw-r--r--sys/dev/ofw/ofw_bus_subr.h4
12 files changed, 63 insertions, 34 deletions
diff --git a/sys/dev/drm2/i915/intel_iic.c b/sys/dev/drm2/i915/intel_iic.c
index c04b27b..aacc954 100644
--- a/sys/dev/drm2/i915/intel_iic.c
+++ b/sys/dev/drm2/i915/intel_iic.c
@@ -456,7 +456,7 @@ timeout:
/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
sc->force_bit_dev = true;
- error = -IICBUS_TRANSFER(adapter, msgs, num);
+ error = -IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, num);
out:
sx_xunlock(&dev_priv->gmbus_sx);
diff --git a/sys/dev/drm2/ttm/ttm_bo.c b/sys/dev/drm2/ttm/ttm_bo.c
index 70e17c4..010afe6 100644
--- a/sys/dev/drm2/ttm/ttm_bo.c
+++ b/sys/dev/drm2/ttm/ttm_bo.c
@@ -1488,21 +1488,21 @@ int ttm_bo_global_init(struct drm_global_reference *ref)
struct ttm_bo_global_ref *bo_ref =
container_of(ref, struct ttm_bo_global_ref, ref);
struct ttm_bo_global *glob = ref->object;
- int ret;
+ int req, ret;
int tries;
sx_init(&glob->device_list_mutex, "ttmdlm");
mtx_init(&glob->lru_lock, "ttmlru", NULL, MTX_DEF);
glob->mem_glob = bo_ref->mem_glob;
+ req = VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ;
tries = 0;
retry:
- glob->dummy_read_page = vm_page_alloc_contig(NULL, 0,
- VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ,
+ glob->dummy_read_page = vm_page_alloc_contig(NULL, 0, req,
1, 0, VM_MAX_ADDRESS, PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE);
if (unlikely(glob->dummy_read_page == NULL)) {
- if (tries < 1) {
- vm_pageout_grow_cache(tries, 0, VM_MAX_ADDRESS);
+ if (tries < 1 && vm_page_reclaim_contig(req, 1,
+ 0, VM_MAX_ADDRESS, PAGE_SIZE, 0)) {
tries++;
goto retry;
}
diff --git a/sys/dev/drm2/ttm/ttm_page_alloc.c b/sys/dev/drm2/ttm/ttm_page_alloc.c
index 75abd10..2a2e916 100644
--- a/sys/dev/drm2/ttm/ttm_page_alloc.c
+++ b/sys/dev/drm2/ttm/ttm_page_alloc.c
@@ -166,13 +166,9 @@ ttm_vm_page_alloc_dma32(int req, vm_memattr_t memattr)
PAGE_SIZE, 0, memattr);
if (p != NULL || tries > 2)
return (p);
-
- /*
- * Before growing the cache see if this is just a normal
- * memory shortage.
- */
- VM_WAIT;
- vm_pageout_grow_cache(tries, 0, 0xffffffff);
+ if (!vm_page_reclaim_contig(req, 1, 0, 0xffffffff,
+ PAGE_SIZE, 0))
+ VM_WAIT;
}
}
diff --git a/sys/dev/if_ndis/if_ndis_pci.c b/sys/dev/if_ndis/if_ndis_pci.c
index b3085db..bf2f313 100644
--- a/sys/dev/if_ndis/if_ndis_pci.c
+++ b/sys/dev/if_ndis/if_ndis_pci.c
@@ -298,8 +298,7 @@ ndis_attach_pci(dev)
BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
- BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
- NDIS_NSEG_NEW, /* nsegments */
+ DFLTPHYS, NDIS_NSEG_NEW,/* maxsize, nsegments */
BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
BUS_DMA_ALLOCNOW, /* flags */
NULL, NULL, /* lockfunc, lockarg */
diff --git a/sys/dev/ioat/ioat.c b/sys/dev/ioat/ioat.c
index 12a6fe4..4b6d7df 100644
--- a/sys/dev/ioat/ioat.c
+++ b/sys/dev/ioat/ioat.c
@@ -736,6 +736,15 @@ ioat_put_dmaengine(bus_dmaengine_t dmaengine)
}
int
+ioat_get_hwversion(bus_dmaengine_t dmaengine)
+{
+ struct ioat_softc *ioat;
+
+ ioat = to_ioat_softc(dmaengine);
+ return (ioat->version);
+}
+
+int
ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay)
{
struct ioat_softc *ioat;
diff --git a/sys/dev/ioat/ioat.h b/sys/dev/ioat/ioat.h
index 5c64af1..e8f47ae 100644
--- a/sys/dev/ioat/ioat.h
+++ b/sys/dev/ioat/ioat.h
@@ -48,6 +48,14 @@ __FBSDID("$FreeBSD$");
#define DMA_NO_WAIT 0x2
#define DMA_ALL_FLAGS (DMA_INT_EN | DMA_NO_WAIT)
+/*
+ * Hardware revision number. Different hardware revisions support different
+ * features. For example, 3.2 cannot read from MMIO space, while 3.3 can.
+ */
+#define IOAT_VER_3_0 0x30
+#define IOAT_VER_3_2 0x32
+#define IOAT_VER_3_3 0x33
+
typedef void *bus_dmaengine_t;
struct bus_dmadesc;
typedef void (*bus_dmaengine_callback_t)(void *arg, int error);
@@ -60,6 +68,9 @@ bus_dmaengine_t ioat_get_dmaengine(uint32_t channel_index);
/* Release the DMA channel */
void ioat_put_dmaengine(bus_dmaengine_t dmaengine);
+/* Check the DMA engine's HW version */
+int ioat_get_hwversion(bus_dmaengine_t dmaengine);
+
/*
* Set interrupt coalescing on a DMA channel.
*
diff --git a/sys/dev/ioat/ioat_hw.h b/sys/dev/ioat/ioat_hw.h
index 1aeee2d..46ffaeb 100644
--- a/sys/dev/ioat/ioat_hw.h
+++ b/sys/dev/ioat/ioat_hw.h
@@ -46,9 +46,6 @@ __FBSDID("$FreeBSD$");
#define IOAT_CBVER_OFFSET 0x08
-#define IOAT_VER_3_0 0x30
-#define IOAT_VER_3_3 0x33
-
#define IOAT_INTRDELAY_OFFSET 0x0C
#define IOAT_INTRDELAY_SUPPORTED (1 << 15)
/* Reserved. (1 << 14) */
diff --git a/sys/dev/mmc/mmc.c b/sys/dev/mmc/mmc.c
index eb76256..a65ff41 100644
--- a/sys/dev/mmc/mmc.c
+++ b/sys/dev/mmc/mmc.c
@@ -118,7 +118,7 @@ struct mmc_ivars {
static SYSCTL_NODE(_hw, OID_AUTO, mmc, CTLFLAG_RD, NULL, "mmc driver");
static int mmc_debug;
-SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RW, &mmc_debug, 0, "Debug level");
+SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &mmc_debug, 0, "Debug level");
/* bus entry points */
static int mmc_acquire_bus(device_t busdev, device_t dev);
diff --git a/sys/dev/nand/nand_cdev.c b/sys/dev/nand/nand_cdev.c
index b011946..0540955 100644
--- a/sys/dev/nand/nand_cdev.c
+++ b/sys/dev/nand/nand_cdev.c
@@ -236,10 +236,10 @@ nand_strategy(struct bio *bp)
chip = dev->si_drv1;
nand_debug(NDBG_CDEV, "Strategy %s on chip %d [%p]\n",
- (bp->bio_cmd & BIO_READ) == BIO_READ ? "READ" : "WRITE",
+ bp->bio_cmd == BIO_READ ? "READ" : "WRITE",
chip->num, chip);
- if ((bp->bio_cmd & BIO_READ) == BIO_READ) {
+ if (bp->bio_cmd == BIO_READ) {
err = nand_read(chip,
bp->bio_offset & 0xffffffff,
bp->bio_data, bp->bio_bcount);
diff --git a/sys/dev/nand/nand_geom.c b/sys/dev/nand/nand_geom.c
index 8786a0a..593b5f5 100644
--- a/sys/dev/nand/nand_geom.c
+++ b/sys/dev/nand/nand_geom.c
@@ -100,9 +100,9 @@ nand_strategy(struct bio *bp)
bp->bio_driver1 = BIO_NAND_STD;
nand_debug(NDBG_GEOM, "Strategy %s on chip %d [%p]",
- (bp->bio_cmd & BIO_READ) == BIO_READ ? "READ" :
- ((bp->bio_cmd & BIO_WRITE) == BIO_WRITE ? "WRITE" :
- ((bp->bio_cmd & BIO_DELETE) == BIO_DELETE ? "DELETE" : "UNKNOWN")),
+ bp->bio_cmd == BIO_READ ? "READ" :
+ (bp->bio_cmd == BIO_WRITE ? "WRITE" :
+ (bp->bio_cmd == BIO_DELETE ? "DELETE" : "UNKNOWN")),
chip->num, chip);
mtx_lock(&chip->qlock);
@@ -122,9 +122,9 @@ nand_strategy_raw(struct bio *bp)
bp->bio_driver1 = BIO_NAND_RAW;
nand_debug(NDBG_GEOM, "Strategy %s on chip %d [%p]",
- (bp->bio_cmd & BIO_READ) == BIO_READ ? "READ" :
- ((bp->bio_cmd & BIO_WRITE) == BIO_WRITE ? "WRITE" :
- ((bp->bio_cmd & BIO_DELETE) == BIO_DELETE ? "DELETE" : "UNKNOWN")),
+ bp->bio_cmd == BIO_READ ? "READ" :
+ (bp->bio_cmd == BIO_WRITE ? "WRITE" :
+ (bp->bio_cmd == BIO_DELETE ? "DELETE" : "UNKNOWN")),
chip->num, chip);
mtx_lock(&chip->qlock);
@@ -320,21 +320,21 @@ nand_io_proc(void *arg, int pending)
break;
if (bp->bio_driver1 == BIO_NAND_STD) {
- if ((bp->bio_cmd & BIO_READ) == BIO_READ) {
+ if (bp->bio_cmd == BIO_READ) {
err = nand_read(chip,
bp->bio_offset & 0xffffffff,
bp->bio_data, bp->bio_bcount);
- } else if ((bp->bio_cmd & BIO_WRITE) == BIO_WRITE) {
+ } else if (bp->bio_cmd == BIO_WRITE) {
err = nand_write(chip,
bp->bio_offset & 0xffffffff,
bp->bio_data, bp->bio_bcount);
}
} else if (bp->bio_driver1 == BIO_NAND_RAW) {
- if ((bp->bio_cmd & BIO_READ) == BIO_READ) {
+ if (bp->bio_cmd == BIO_READ) {
err = nand_read_raw(chip,
bp->bio_offset & 0xffffffff,
bp->bio_data, bp->bio_bcount);
- } else if ((bp->bio_cmd & BIO_WRITE) == BIO_WRITE) {
+ } else if (bp->bio_cmd == BIO_WRITE) {
err = nand_write_raw(chip,
bp->bio_offset & 0xffffffff,
bp->bio_data, bp->bio_bcount);
@@ -342,7 +342,7 @@ nand_io_proc(void *arg, int pending)
} else
panic("Unknown access type in bio->bio_driver1\n");
- if ((bp->bio_cmd & BIO_DELETE) == BIO_DELETE) {
+ if (bp->bio_cmd == BIO_DELETE) {
nand_debug(NDBG_GEOM, "Delete on chip%d offset %lld "
"length %ld\n", chip->num, bp->bio_offset,
bp->bio_bcount);
diff --git a/sys/dev/ofw/ofw_bus_subr.c b/sys/dev/ofw/ofw_bus_subr.c
index ba2b20e..c286373 100644
--- a/sys/dev/ofw/ofw_bus_subr.c
+++ b/sys/dev/ofw/ofw_bus_subr.c
@@ -341,6 +341,7 @@ ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz,
uint8_t *uiregs = regs;
uint8_t *uiimapmsk = imapmsk;
uint8_t *mptr;
+ pcell_t paddrsz;
pcell_t pintrsz;
int i, rsz, tsz;
@@ -357,19 +358,31 @@ ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz,
mptr = imap;
i = imapsz;
+ paddrsz = 0;
while (i > 0) {
bcopy(mptr + physsz + intrsz, &parent, sizeof(parent));
+#ifdef OFW_EPAPR
+ /*
+ * Find if we need to read the parent address data. Sparc64
+ * uses a different encoding that doesn't include this data.
+ */
+ if (OF_getencprop(OF_node_from_xref(parent),
+ "#address-cells", &paddrsz, sizeof(paddrsz)) == -1)
+ paddrsz = 0; /* default */
+ paddrsz *= sizeof(pcell_t);
+#endif
+
if (OF_searchencprop(OF_node_from_xref(parent),
"#interrupt-cells", &pintrsz, sizeof(pintrsz)) == -1)
pintrsz = 1; /* default */
pintrsz *= sizeof(pcell_t);
/* Compute the map stride size. */
- tsz = physsz + intrsz + sizeof(phandle_t) + pintrsz;
+ tsz = physsz + intrsz + sizeof(phandle_t) + paddrsz + pintrsz;
KASSERT(i >= tsz, ("ofw_bus_search_intrmap: truncated map"));
if (bcmp(ref, mptr, physsz + intrsz) == 0) {
- bcopy(mptr + physsz + intrsz + sizeof(parent),
+ bcopy(mptr + physsz + intrsz + sizeof(parent) + paddrsz,
result, MIN(rintrsz, pintrsz));
if (iparent != NULL)
diff --git a/sys/dev/ofw/ofw_bus_subr.h b/sys/dev/ofw/ofw_bus_subr.h
index 708e984..7c4df33 100644
--- a/sys/dev/ofw/ofw_bus_subr.h
+++ b/sys/dev/ofw/ofw_bus_subr.h
@@ -52,6 +52,10 @@ struct ofw_compat_data {
uintptr_t ocd_data;
};
+#define SIMPLEBUS_PNP_DESCR "Z:compat;P:private;"
+#define SIMPLEBUS_PNP_INFO(t) \
+ MODULE_PNP_INFO(SIMPLEBUS_PNP_DESCR, simplebus, t, t, sizeof(t[0]), sizeof(t) / sizeof(t[0]));
+
/* Generic implementation of ofw_bus_if.m methods and helper routines */
int ofw_bus_gen_setup_devinfo(struct ofw_bus_devinfo *, phandle_t);
void ofw_bus_gen_destroy_devinfo(struct ofw_bus_devinfo *);
OpenPOWER on IntegriCloud