diff options
Diffstat (limited to 'sys/dev/isp/ispreg.h')
| -rw-r--r-- | sys/dev/isp/ispreg.h | 156 |
1 files changed, 130 insertions, 26 deletions
diff --git a/sys/dev/isp/ispreg.h b/sys/dev/isp/ispreg.h index a84ef70..a953bc1 100644 --- a/sys/dev/isp/ispreg.h +++ b/sys/dev/isp/ispreg.h @@ -1,4 +1,4 @@ -/* $Id: ispreg.h,v 1.3 1998/04/14 17:51:32 mjacob Exp $ */ +/* $Id: ispreg.h,v 1.6 1998/09/08 01:09:46 mjacob Exp $ */ /* * Machine Independent (well, as best as possible) register * definitions for Qlogic ISP SCSI adapters. @@ -196,6 +196,12 @@ #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ +/* NVRAM SEMAPHORE REGISTER */ +#define BIU_NVRAM_CLOCK 0x0001 +#define BIU_NVRAM_SELECT 0x0002 +#define BIU_NVRAM_DATAOUT 0x0004 +#define BIU_NVRAM_DATAIN 0x0008 +#define ISP_NVRAM_READ 6 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ @@ -303,31 +309,6 @@ #define NMBOX(isp) \ (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ ((isp)->isp_type & ISP_HA_FC))? 8 : 6) -/* - * Mailbox Command Complete Status Codes - */ -#define MBOX_COMMAND_COMPLETE 0x4000 -#define MBOX_INVALID_COMMAND 0x4001 -#define MBOX_HOST_INTERFACE_ERROR 0x4002 -#define MBOX_TEST_FAILED 0x4003 -#define MBOX_COMMAND_ERROR 0x4005 -#define MBOX_COMMAND_PARAM_ERROR 0x4006 - -/* - * Asynchronous event status codes - */ -#define ASYNC_BUS_RESET 0x8001 -#define ASYNC_SYSTEM_ERROR 0x8002 -#define ASYNC_RQS_XFER_ERR 0x8003 -#define ASYNC_RSP_XFER_ERR 0x8004 -#define ASYNC_QWAKEUP 0x8005 -#define ASYNC_TIMEOUT_RESET 0x8006 - -/* for ISP2100 only */ -#define ASYNC_LIP_OCCURRED 0x8010 -#define ASYNC_LOOP_UP 0x8011 -#define ASYNC_LOOP_DOWN 0x8012 -#define ASYNC_LOOP_RESET 0x8013 /* * SXP Block Register Offsets @@ -550,6 +531,10 @@ #define RISC_PSR_ALU_MSB 0x0400 #define RISC_PSR_ALU_CARRY 0x0200 #define RISC_PSR_ALU_ZERO 0x0100 + +#define RISC_PSR_PCI_ULTRA 0x0080 +#define RISC_PSR_SBUS_ULTRA 0x0020 + #define RISC_PSR_DMA_INT 0x0010 #define RISC_PSR_SXP_INT 0x0008 #define RISC_PSR_HOST_INT 0x0004 @@ -586,4 +571,123 @@ #define HCCR_PAUSE 0x0020 /* R : RISC paused */ #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ + +/* + * Qlogic 1XXX NVRAM is an array of 128 bytes. + * + * Some portion of the front of this is for general host adapter properties + * This is followed by an array of per-target parameters, and is tailed off + * with a checksum xor byte at offset 127. For non-byte entities data is + * stored in Little Endian order. + */ + +#define ISP_NVRAM_SIZE 128 + +#define ISPBSMX(c, byte, shift, mask) \ + (((c)[(byte)] >> (shift)) & (mask)) + +#define ISP_NVRAM_VERSION(c) (c)[4] +#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) +#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) +#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) +#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) +#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] +#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] +#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] +#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) +#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) +#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) +#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) +#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) +#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] +#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) +#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) +#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) +#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) +#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) +#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) +#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) +#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) +#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) +#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) +#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) +#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) +#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) +#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) +#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) +#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) + +#define ISP_NVRAM_TARGOFF 28 +#define ISP_NVARM_TARGSIZE 6 +#define _IxT(tgt, tidx) \ + (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) +#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) +#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) +#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) +#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) +#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) +#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) +#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) +#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) +#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) +#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) +#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) +#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) +#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) + +/* + * Qlogic 2XXX NVRAM is an array of 256 bytes. + * + * Some portion of the front of this is for general RISC engine parameters, + * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. + * + * This is followed by some general host adapter parameters, and ends with + * a checksum xor byte at offset 255. For non-byte entities data is stored + * in Little Endian order. + */ +#define ISP2100_NVRAM_SIZE 256 +/* ISP_NVRAM_VERSION is in same overall place */ +#define ISP2100_NVRAM_RISCVER(c) (c)[6] +#define ISP2100_NVRAM_ENABLE_HARDLOOPID(c) ISPBSMX(c, 8, 0, 0x01) +#define ISP2100_NVRAM_ENABLE_FAIRNESS(c) ISPBSMX(c, 8, 1, 0x01) +#define ISP2100_NVRAM_ENABLE_FULLDUPLEX(c) ISPBSMX(c, 8, 2, 0x01) +#define ISP2100_NVRAM_ENABLE_FAST_POSTING(c) ISPBSMX(c, 8, 3, 0x01) +#define ISP2100_NVRAM_ENABLE_TARGET_MODE(c) ISPBSMX(c, 8, 4, 0x01) +#define ISP2100_NVRAM_ENABLE_INITIATOR_MODE(c) ISPBSMX(c, 8, 5, 0x01) +#define ISP2100_NVRAM_QFRZ(c) ISPBSMX(c, 8, 6, 0x01) +#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) +#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) +#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) +#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] +#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] + +#define ISP2100_NVRAM_NODE_NAME(c) ( \ + (((u_int64_t)(c)[18]) << 56) | \ + (((u_int64_t)(c)[19]) << 48) | \ + (((u_int64_t)(c)[20]) << 40) | \ + (((u_int64_t)(c)[21]) << 32) | \ + (((u_int64_t)(c)[22]) << 24) | \ + (((u_int64_t)(c)[23]) << 16) | \ + (((u_int64_t)(c)[24]) << 8) | \ + (((u_int64_t)(c)[25]) << 0)) +#define ISP2100_NVRAM_HARDLOOPID(c) (c)[24] + +#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) +#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) +#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) +#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) +#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) +#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) + +#define ISP2100_NVRAM_BOOT_NODE_NAME(c) ( \ + (((u_int64_t)(c)[72]) << 56) | \ + (((u_int64_t)(c)[73]) << 48) | \ + (((u_int64_t)(c)[74]) << 40) | \ + (((u_int64_t)(c)[75]) << 32) | \ + (((u_int64_t)(c)[76]) << 24) | \ + (((u_int64_t)(c)[77]) << 16) | \ + (((u_int64_t)(c)[78]) << 8) | \ + (((u_int64_t)(c)[79]) << 0)) +#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] + #endif /* _ISPREG_H */ |
