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-rw-r--r--sys/dev/ic/i8237.h23
1 files changed, 0 insertions, 23 deletions
diff --git a/sys/dev/ic/i8237.h b/sys/dev/ic/i8237.h
index bdda9fa..5d4b3f4 100644
--- a/sys/dev/ic/i8237.h
+++ b/sys/dev/ic/i8237.h
@@ -9,26 +9,3 @@
#define DMA37MD_AUTO 0x50 /* autoinitialise single pass mode */
#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */
#define DMA37MD_READ 0x08 /* write the device, read memory operation */
-
-#ifndef PC98
-/*
-** Register definitions for DMA controller 1 (channels 0..3):
-*/
-#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
-#define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */
-#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
-#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
-#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
-#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
-
-/*
-** Register definitions for DMA controller 2 (channels 4..7):
-*/
-#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
-#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */
-#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
-#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
-#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
-#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
-#endif
-
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