diff options
Diffstat (limited to 'sys/dev/ath/if_athvar.h')
| -rw-r--r-- | sys/dev/ath/if_athvar.h | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/sys/dev/ath/if_athvar.h b/sys/dev/ath/if_athvar.h index 6b074d6..e888ca2 100644 --- a/sys/dev/ath/if_athvar.h +++ b/sys/dev/ath/if_athvar.h @@ -82,6 +82,25 @@ #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ /* + * The following bits can be set during the PCI (and perhaps non-PCI + * later) device probe path. + * + * It controls some of the driver and HAL behaviour. + */ + +#define ATH_PCI_CUS198 0x0001 +#define ATH_PCI_CUS230 0x0002 +#define ATH_PCI_CUS217 0x0004 +#define ATH_PCI_CUS252 0x0008 +#define ATH_PCI_WOW 0x0010 +#define ATH_PCI_BT_ANT_DIV 0x0020 +#define ATH_PCI_D3_L1_WAR 0x0040 +#define ATH_PCI_AR9565_1ANT 0x0080 +#define ATH_PCI_AR9565_2ANT 0x0100 +#define ATH_PCI_NO_PLL_PWRSAVE 0x0200 +#define ATH_PCI_KILLER 0x0400 + +/* * The key cache is used for h/w cipher state and also for * tracking station state such as the current tx antenna. * We also setup a mapping table between key cache slot indices @@ -510,6 +529,7 @@ struct ath_rx_edma { int m_fifo_tail; int m_fifo_depth; struct mbuf *m_rxpending; + struct ath_buf *m_holdbf; }; struct ath_tx_edma_fifo { @@ -565,6 +585,8 @@ struct ath_softc { int sc_tx_statuslen; int sc_tx_nmaps; /* Number of TX maps */ int sc_edma_bufsize; + int sc_rx_stopped; /* XXX only for EDMA */ + int sc_rx_resetted; /* XXX only for EDMA */ void (*sc_node_cleanup)(struct ieee80211_node *); void (*sc_node_free)(struct ieee80211_node *); @@ -621,7 +643,8 @@ struct ath_softc { sc_resetcal : 1,/* reset cal state next trip */ sc_rxslink : 1,/* do self-linked final descriptor */ sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ - sc_isedma : 1;/* supports EDMA */ + sc_isedma : 1,/* supports EDMA */ + sc_do_mybeacon : 1; /* supports mybeacon */ /* * Second set of flags. @@ -864,6 +887,25 @@ struct ath_softc { void (*sc_bar_response)(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, int status); + + /* + * Powersave state tracking. + * + * target/cur powerstate is the chip power state. + * target selfgen state is the self-generated frames + * state. The chip can be awake but transmitted frames + * can have the PWRMGT bit set to 1 so the destination + * thinks the node is asleep. + */ + HAL_POWER_MODE sc_target_powerstate; + HAL_POWER_MODE sc_target_selfgen_state; + + HAL_POWER_MODE sc_cur_powerstate; + + int sc_powersave_refcnt; + + /* ATH_PCI_* flags */ + uint32_t sc_pci_devinfo; }; #define ATH_LOCK_INIT(_sc) \ @@ -1038,6 +1080,8 @@ void ath_intr(void *); ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) #define ath_hal_setpower(_ah, _mode) \ ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) +#define ath_hal_setselfgenpower(_ah, _mode) \ + ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE)) #define ath_hal_keycachesize(_ah) \ ((*(_ah)->ah_getKeyCacheSize)((_ah))) #define ath_hal_keyreset(_ah, _ix) \ @@ -1266,6 +1310,8 @@ void ath_intr(void *); #define ath_hal_setintmit(_ah, _v) \ ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ HAL_CAP_INTMIT_ENABLE, _v, NULL) +#define ath_hal_hasmybeacon(_ah) \ + (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK) #define ath_hal_hasenforcetxop(_ah) \ (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) |
