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-rw-r--r--sys/dev/agp/agpreg.h79
1 files changed, 78 insertions, 1 deletions
diff --git a/sys/dev/agp/agpreg.h b/sys/dev/agp/agpreg.h
index b453cac..dfa93a5 100644
--- a/sys/dev/agp/agpreg.h
+++ b/sys/dev/agp/agpreg.h
@@ -176,10 +176,33 @@
#define AGP_I810_GMADR 0x10
#define AGP_I810_MMADR 0x14
+#define I810_PTE_VALID 0x00000001
+
+/*
+ * Cache control
+ *
+ * Pre-Sandybridge bits
+ */
+#define I810_PTE_MAIN_UNCACHED 0x00000000
+#define I810_PTE_LOCAL 0x00000002 /* Non-snooped main phys memory */
+#define I830_PTE_SYSTEM_CACHED 0x00000006 /* Snooped main phys memory */
+
+/*
+ * Sandybridge
+ * LLC - Last Level Cache
+ * MMC - Mid Level Cache
+ */
+#define GEN6_PTE_RESERVED 0x00000000
+#define GEN6_PTE_UNCACHED 0x00000002 /* Do not cache */
+#define GEN6_PTE_LLC 0x00000004 /* Cache in LLC */
+#define GEN6_PTE_LLC_MLC 0x00000006 /* Cache in LLC and MLC */
+#define GEN6_PTE_GFDT 0x00000008 /* Graphics Data Type */
+
/*
* Memory mapped register offsets for i810 chipset.
*/
#define AGP_I810_PGTBL_CTL 0x2020
+#define AGP_I810_PGTBL_ENABLED 0x00000001
/**
* This field determines the actual size of the global GTT on the 965
* and G33
@@ -187,7 +210,23 @@
#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
#define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
#define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
-#define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
+#define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
+#define AGP_I810_PGTBL_SIZE_1MB (3 << 1)
+#define AGP_I810_PGTBL_SIZE_2MB (4 << 1)
+#define AGP_I810_PGTBL_SIZE_1_5MB (5 << 1)
+#define AGP_G33_GCC1_SIZE_MASK (3 << 8)
+#define AGP_G33_GCC1_SIZE_1M (1 << 8)
+#define AGP_G33_GCC1_SIZE_2M (2 << 8)
+#define AGP_G4x_GCC1_SIZE_MASK (0xf << 8)
+#define AGP_G4x_GCC1_SIZE_1M (0x1 << 8)
+#define AGP_G4x_GCC1_SIZE_2M (0x3 << 8)
+#define AGP_G4x_GCC1_SIZE_VT_EN (0x8 << 8)
+#define AGP_G4x_GCC1_SIZE_VT_1M \
+ (AGP_G4x_GCC1_SIZE_1M | AGP_G4x_GCC1_SIZE_VT_EN)
+#define AGP_G4x_GCC1_SIZE_VT_1_5M ((0x2 << 8) | AGP_G4x_GCC1_SIZE_VT_EN)
+#define AGP_G4x_GCC1_SIZE_VT_2M \
+ (AGP_G4x_GCC1_SIZE_2M | AGP_G4x_GCC1_SIZE_VT_EN)
+
#define AGP_I810_DRT 0x3000
#define AGP_I810_DRT_UNPOPULATED 0x00
#define AGP_I810_DRT_POPULATED 0x01
@@ -207,6 +246,7 @@
#define AGP_I830_GCC1_GMASIZE 0x01
#define AGP_I830_GCC1_GMASIZE_64 0x01
#define AGP_I830_GCC1_GMASIZE_128 0x00
+#define AGP_I830_HIC 0x70
/*
* Config registers for 852GM/855GM/865G device 0
@@ -243,6 +283,9 @@
#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
#define AGP_I915_DEVEN 0x54
+#define AGP_SB_DEVEN_D2EN 0x10 /* SB+ has IGD enabled bit */
+#define AGP_SB_DEVEN_D2EN_ENABLED 0x10 /* in different place */
+#define AGP_SB_DEVEN_D2EN_DISABLED 0x00
#define AGP_I915_DEVEN_D2F0 0x08
#define AGP_I915_DEVEN_D2F0_ENABLED 0x08
#define AGP_I915_DEVEN_D2F0_DISABLED 0x00
@@ -250,6 +293,7 @@
#define AGP_I915_MSAC_GMASIZE 0x02
#define AGP_I915_MSAC_GMASIZE_128 0x02
#define AGP_I915_MSAC_GMASIZE_256 0x00
+#define AGP_I915_IFPADDR 0x60
/*
* G965 registers
@@ -262,6 +306,8 @@
#define AGP_I965_PGTBL_SIZE_1MB (3 << 1)
#define AGP_I965_PGTBL_SIZE_2MB (4 << 1)
#define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1)
+#define AGP_I965_PGTBL_CTL2 0x20c4
+#define AGP_I965_IFPADDR 0x70
/*
* G33 registers
@@ -275,12 +321,43 @@
/*
* G4X registers
*/
+#define AGP_G4X_GMADR 0x20
+#define AGP_G4X_MMADR 0x10
+#define AGP_G4X_GTTADR 0x18
#define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0
#define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0
#define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0
#define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0
/*
+ * SandyBridge/IvyBridge registers
+ */
+#define AGP_SNB_GCC1 0x50
+#define AGP_SNB_GMCH_GMS_STOLEN_MASK 0xF8
+#define AGP_SNB_GMCH_GMS_STOLEN_32M (1 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_64M (2 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_96M (3 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_128M (4 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_160M (5 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_192M (6 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_224M (7 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_256M (8 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_288M (9 << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
+#define AGP_SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
+#define AGP_SNB_GTT_SIZE_0M (0 << 8)
+#define AGP_SNB_GTT_SIZE_1M (1 << 8)
+#define AGP_SNB_GTT_SIZE_2M (2 << 8)
+#define AGP_SNB_GTT_SIZE_MASK (3 << 8)
+
+#define AGP_SNB_GFX_MODE 0x02520
+
+/*
* NVIDIA nForce/nForce2 registers
*/
#define AGP_NVIDIA_0_APBASE 0x10
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