summaryrefslogtreecommitdiffstats
path: root/sys/arm/arm/gic.c
diff options
context:
space:
mode:
Diffstat (limited to 'sys/arm/arm/gic.c')
-rw-r--r--sys/arm/arm/gic.c347
1 files changed, 326 insertions, 21 deletions
diff --git a/sys/arm/arm/gic.c b/sys/arm/arm/gic.c
index 5c0aece..85d1557 100644
--- a/sys/arm/arm/gic.c
+++ b/sys/arm/arm/gic.c
@@ -50,7 +50,7 @@ __FBSDID("$FreeBSD$");
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/smp.h>
-#ifdef ARM_INTRNG
+#ifdef INTRNG
#include <sys/sched.h>
#endif
#include <machine/bus.h>
@@ -62,7 +62,7 @@ __FBSDID("$FreeBSD$");
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
-#ifdef ARM_INTRNG
+#ifdef INTRNG
#include "pic_if.h"
#endif
@@ -116,12 +116,14 @@ __FBSDID("$FreeBSD$");
#define GIC_DEFAULT_ICFGR_INIT 0x00000000
#endif
-#ifdef ARM_INTRNG
+#ifdef INTRNG
struct gic_irqsrc {
struct intr_irqsrc gi_isrc;
uint32_t gi_irq;
enum intr_polarity gi_pol;
enum intr_trigger gi_trig;
+#define GI_FLAG_EARLY_EOI (1 << 0)
+ u_int gi_flags;
};
static u_int gic_irq_cpu;
@@ -134,9 +136,22 @@ u_int sgi_first_unused = GIC_FIRST_SGI;
#endif
#endif
+#ifdef INTRNG
+struct arm_gic_range {
+ uint64_t bus;
+ uint64_t host;
+ uint64_t size;
+};
+
+struct arm_gic_devinfo {
+ struct ofw_bus_devinfo obdinfo;
+ struct resource_list rl;
+};
+#endif
+
struct arm_gic_softc {
device_t gic_dev;
-#ifdef ARM_INTRNG
+#ifdef INTRNG
void * gic_intrhand;
struct gic_irqsrc * gic_irqs;
#endif
@@ -151,16 +166,24 @@ struct arm_gic_softc {
#ifdef GIC_DEBUG_SPURIOUS
uint32_t last_irq[MAXCPU];
#endif
+
+#ifdef INTRNG
+ /* FDT child data */
+ pcell_t addr_cells;
+ pcell_t size_cells;
+ int nranges;
+ struct arm_gic_range * ranges;
+#endif
};
-#ifdef ARM_INTRNG
+#ifdef INTRNG
#define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
#endif
static struct resource_spec arm_gic_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
-#ifdef ARM_INTRNG
+#ifdef INTRNG
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */
#endif
{ -1, 0 }
@@ -181,7 +204,7 @@ static struct arm_gic_softc *gic_sc = NULL;
#define gic_d_write_4(_sc, _reg, _val) \
bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
-#ifndef ARM_INTRNG
+#ifndef INTRNG
static int gic_config_irq(int irq, enum intr_trigger trig,
enum intr_polarity pol);
static void gic_post_filter(void *);
@@ -195,6 +218,7 @@ static struct ofw_compat_data compat_data[] = {
{"arm,cortex-a7-gic", true},
{"arm,arm11mp-gic", true},
{"brcm,brahma-b15-gic", true},
+ {"qcom,msm-qgic2", true},
{NULL, false}
};
@@ -211,7 +235,7 @@ arm_gic_probe(device_t dev)
return (BUS_PROBE_DEFAULT);
}
-#ifdef ARM_INTRNG
+#ifdef INTRNG
static inline void
gic_irq_unmask(struct arm_gic_softc *sc, u_int irq)
{
@@ -251,7 +275,7 @@ gic_cpu_mask(struct arm_gic_softc *sc)
}
#ifdef SMP
-#ifdef ARM_INTRNG
+#ifdef INTRNG
static void
arm_gic_init_secondary(device_t dev)
{
@@ -323,10 +347,10 @@ arm_gic_init_secondary(device_t dev)
gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
}
-#endif /* ARM_INTRNG */
+#endif /* INTRNG */
#endif /* SMP */
-#ifndef ARM_INTRNG
+#ifndef INTRNG
int
gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
int *trig, int *pol)
@@ -387,7 +411,7 @@ gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
}
#endif
-#ifdef ARM_INTRNG
+#ifdef INTRNG
static inline intptr_t
gic_xref(device_t dev)
{
@@ -437,6 +461,107 @@ arm_gic_register_isrcs(struct arm_gic_softc *sc, uint32_t num)
sc->nirqs = num;
return (0);
}
+
+static int
+arm_gic_fill_ranges(phandle_t node, struct arm_gic_softc *sc)
+{
+ pcell_t host_cells;
+ cell_t *base_ranges;
+ ssize_t nbase_ranges;
+ int i, j, k;
+
+ host_cells = 1;
+ OF_getencprop(OF_parent(node), "#address-cells", &host_cells,
+ sizeof(host_cells));
+ sc->addr_cells = 2;
+ OF_getencprop(node, "#address-cells", &sc->addr_cells,
+ sizeof(sc->addr_cells));
+ sc->size_cells = 2;
+ OF_getencprop(node, "#size-cells", &sc->size_cells,
+ sizeof(sc->size_cells));
+
+ nbase_ranges = OF_getproplen(node, "ranges");
+ if (nbase_ranges < 0)
+ return (-1);
+ sc->nranges = nbase_ranges / sizeof(cell_t) /
+ (sc->addr_cells + host_cells + sc->size_cells);
+ if (sc->nranges == 0)
+ return (0);
+
+ sc->ranges = malloc(sc->nranges * sizeof(sc->ranges[0]),
+ M_DEVBUF, M_WAITOK);
+ base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
+ OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
+
+ for (i = 0, j = 0; i < sc->nranges; i++) {
+ sc->ranges[i].bus = 0;
+ for (k = 0; k < sc->addr_cells; k++) {
+ sc->ranges[i].bus <<= 32;
+ sc->ranges[i].bus |= base_ranges[j++];
+ }
+ sc->ranges[i].host = 0;
+ for (k = 0; k < host_cells; k++) {
+ sc->ranges[i].host <<= 32;
+ sc->ranges[i].host |= base_ranges[j++];
+ }
+ sc->ranges[i].size = 0;
+ for (k = 0; k < sc->size_cells; k++) {
+ sc->ranges[i].size <<= 32;
+ sc->ranges[i].size |= base_ranges[j++];
+ }
+ }
+
+ free(base_ranges, M_DEVBUF);
+ return (sc->nranges);
+}
+
+static bool
+arm_gic_add_children(device_t dev)
+{
+ struct arm_gic_softc *sc;
+ struct arm_gic_devinfo *dinfo;
+ phandle_t child, node;
+ device_t cdev;
+
+ sc = device_get_softc(dev);
+ node = ofw_bus_get_node(dev);
+
+ /* If we have no children don't probe for them */
+ child = OF_child(node);
+ if (child == 0)
+ return (false);
+
+ if (arm_gic_fill_ranges(node, sc) < 0) {
+ device_printf(dev, "Have a child, but no ranges\n");
+ return (false);
+ }
+
+ for (; child != 0; child = OF_peer(child)) {
+ dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_WAITOK | M_ZERO);
+
+ if (ofw_bus_gen_setup_devinfo(&dinfo->obdinfo, child) != 0) {
+ free(dinfo, M_DEVBUF);
+ continue;
+ }
+
+ resource_list_init(&dinfo->rl);
+ ofw_bus_reg_to_rl(dev, child, sc->addr_cells,
+ sc->size_cells, &dinfo->rl);
+
+ cdev = device_add_child(dev, NULL, -1);
+ if (cdev == NULL) {
+ device_printf(dev, "<%s>: device_add_child failed\n",
+ dinfo->obdinfo.obd_name);
+ resource_list_free(&dinfo->rl);
+ ofw_bus_gen_destroy_devinfo(&dinfo->obdinfo);
+ free(dinfo, M_DEVBUF);
+ continue;
+ }
+ device_set_ivars(cdev, dinfo);
+ }
+
+ return (true);
+}
#endif
static int
@@ -445,7 +570,7 @@ arm_gic_attach(device_t dev)
struct arm_gic_softc *sc;
int i;
uint32_t icciidr, mask, nirqs;
-#ifdef ARM_INTRNG
+#ifdef INTRNG
phandle_t pxref;
intptr_t xref = gic_xref(dev);
#endif
@@ -481,7 +606,7 @@ arm_gic_attach(device_t dev)
nirqs = gic_d_read_4(sc, GICD_TYPER);
nirqs = 32 * ((nirqs & 0x1f) + 1);
-#ifdef ARM_INTRNG
+#ifdef INTRNG
if (arm_gic_register_isrcs(sc, nirqs)) {
device_printf(dev, "could not register irqs\n");
goto cleanup;
@@ -537,7 +662,7 @@ arm_gic_attach(device_t dev)
/* Enable interrupt distribution */
gic_d_write_4(sc, GICD_CTLR, 0x01);
-#ifndef ARM_INTRNG
+#ifndef INTRNG
return (0);
#else
/*
@@ -578,6 +703,13 @@ arm_gic_attach(device_t dev)
}
OF_device_register_xref(xref, dev);
+
+ /* If we have children probe and attach them */
+ if (arm_gic_add_children(dev)) {
+ bus_generic_probe(dev);
+ return (bus_generic_attach(dev));
+ }
+
return (0);
cleanup:
@@ -591,7 +723,76 @@ cleanup:
#endif
}
-#ifdef ARM_INTRNG
+#ifdef INTRNG
+static struct resource *
+arm_gic_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
+{
+ struct arm_gic_softc *sc;
+ struct arm_gic_devinfo *di;
+ struct resource_list_entry *rle;
+ int j;
+
+ KASSERT(type == SYS_RES_MEMORY, ("Invalid resoure type %x", type));
+
+ sc = device_get_softc(bus);
+
+ /*
+ * Request for the default allocation with a given rid: use resource
+ * list stored in the local device info.
+ */
+ if (RMAN_IS_DEFAULT_RANGE(start, end)) {
+ if ((di = device_get_ivars(child)) == NULL)
+ return (NULL);
+
+ if (type == SYS_RES_IOPORT)
+ type = SYS_RES_MEMORY;
+
+ rle = resource_list_find(&di->rl, type, *rid);
+ if (rle == NULL) {
+ if (bootverbose)
+ device_printf(bus, "no default resources for "
+ "rid = %d, type = %d\n", *rid, type);
+ return (NULL);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+ }
+
+ /* Remap through ranges property */
+ for (j = 0; j < sc->nranges; j++) {
+ if (start >= sc->ranges[j].bus && end <
+ sc->ranges[j].bus + sc->ranges[j].size) {
+ start -= sc->ranges[j].bus;
+ start += sc->ranges[j].host;
+ end -= sc->ranges[j].bus;
+ end += sc->ranges[j].host;
+ break;
+ }
+ }
+ if (j == sc->nranges && sc->nranges != 0) {
+ if (bootverbose)
+ device_printf(bus, "Could not map resource "
+ "%#jx-%#jx\n", (uintmax_t)start, (uintmax_t)end);
+
+ return (NULL);
+ }
+
+ return (bus_generic_alloc_resource(bus, child, type, rid, start, end,
+ count, flags));
+}
+
+static const struct ofw_bus_devinfo *
+arm_gic_ofw_get_devinfo(device_t bus __unused, device_t child)
+{
+ struct arm_gic_devinfo *di;
+
+ di = device_get_ivars(child);
+
+ return (&di->obdinfo);
+}
+
static int
arm_gic_intr(void *arg)
{
@@ -654,12 +855,12 @@ dispatch_irq:
#ifdef GIC_DEBUG_SPURIOUS
sc->last_irq[PCPU_GET(cpuid)] = irq;
#endif
- if (gi->gi_trig == INTR_TRIGGER_EDGE)
+ if ((gi->gi_flags & GI_FLAG_EARLY_EOI) == GI_FLAG_EARLY_EOI)
gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) {
gic_irq_mask(sc, irq);
- if (gi->gi_trig != INTR_TRIGGER_EDGE)
+ if ((gi->gi_flags & GI_FLAG_EARLY_EOI) != GI_FLAG_EARLY_EOI)
gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
device_printf(sc->gic_dev, "Stray irq %u disabled\n", irq);
}
@@ -888,6 +1089,9 @@ arm_gic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
gi->gi_pol = pol;
gi->gi_trig = trig;
+ /* Edge triggered interrupts need an early EOI sent */
+ if (gi->gi_pol == INTR_TRIGGER_EDGE)
+ gi->gi_flags |= GI_FLAG_EARLY_EOI;
/*
* XXX - In case that per CPU interrupt is going to be enabled in time
@@ -961,7 +1165,7 @@ arm_gic_post_filter(device_t dev, struct intr_irqsrc *isrc)
struct gic_irqsrc *gi = (struct gic_irqsrc *)isrc;
/* EOI for edge-triggered done earlier. */
- if (gi->gi_trig == INTR_TRIGGER_EDGE)
+ if ((gi->gi_flags & GI_FLAG_EARLY_EOI) == GI_FLAG_EARLY_EOI)
return;
arm_irq_memory_barrier(0);
@@ -1225,13 +1429,28 @@ pic_ipi_clear(int ipi)
arm_gic_ipi_clear(gic_sc->gic_dev, ipi);
}
#endif
-#endif /* ARM_INTRNG */
+#endif /* INTRNG */
static device_method_t arm_gic_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, arm_gic_probe),
DEVMETHOD(device_attach, arm_gic_attach),
-#ifdef ARM_INTRNG
+
+#ifdef INTRNG
+ /* Bus interface */
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+ DEVMETHOD(bus_alloc_resource, arm_gic_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
+
+ /* ofw_bus interface */
+ DEVMETHOD(ofw_bus_get_devinfo, arm_gic_ofw_get_devinfo),
+ DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
+ DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
+ DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
+ DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
+ DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
+
/* Interrupt controller interface */
DEVMETHOD(pic_disable_intr, arm_gic_disable_intr),
DEVMETHOD(pic_enable_intr, arm_gic_enable_intr),
@@ -1263,3 +1482,89 @@ EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0,
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0,
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
+
+#ifdef INTRNG
+/*
+ * GICv2m support -- the GICv2 MSI/MSI-X controller.
+ */
+
+#define GICV2M_MSI_TYPER 0x008
+#define MSI_TYPER_SPI_BASE(x) (((x) >> 16) & 0x3ff)
+#define MSI_TYPER_SPI_COUNT(x) (((x) >> 0) & 0x3ff)
+#define GICv2M_MSI_SETSPI_NS 0x040
+#define GICV2M_MSI_IIDR 0xFCC
+
+struct arm_gicv2m_softc {
+ struct resource *sc_mem;
+ struct mtx sc_mutex;
+ u_int sc_spi_start;
+ u_int sc_spi_count;
+ u_int sc_spi_offset;
+};
+
+static struct ofw_compat_data gicv2m_compat_data[] = {
+ {"arm,gic-v2m-frame", true},
+ {NULL, false}
+};
+
+static int
+arm_gicv2m_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_search_compatible(dev, gicv2m_compat_data)->ocd_data)
+ return (ENXIO);
+
+ device_set_desc(dev, "ARM Generic Interrupt Controller MSI/MSIX");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+arm_gicv2m_attach(device_t dev)
+{
+ struct arm_gicv2m_softc *sc;
+ uint32_t typer;
+ int rid;
+
+ sc = device_get_softc(dev);
+
+ rid = 0;
+ sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->sc_mem == NULL) {
+ device_printf(dev, "Unable to allocate resources\n");
+ return (ENXIO);
+ }
+
+ typer = bus_read_4(sc->sc_mem, GICV2M_MSI_TYPER);
+ sc->sc_spi_start = MSI_TYPER_SPI_BASE(typer);
+ sc->sc_spi_count = MSI_TYPER_SPI_COUNT(typer);
+
+ mtx_init(&sc->sc_mutex, "GICv2m lock", "", MTX_DEF);
+
+ if (bootverbose)
+ device_printf(dev, "using spi %u to %u\n", sc->sc_spi_start,
+ sc->sc_spi_start + sc->sc_spi_count - 1);
+
+ return (0);
+}
+
+static device_method_t arm_gicv2m_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, arm_gicv2m_probe),
+ DEVMETHOD(device_attach, arm_gicv2m_attach),
+
+ /* End */
+ DEVMETHOD_END
+};
+
+DEFINE_CLASS_0(gicv2m, arm_gicv2m_driver, arm_gicv2m_methods,
+ sizeof(struct arm_gicv2m_softc));
+
+static devclass_t arm_gicv2m_devclass;
+
+EARLY_DRIVER_MODULE(gicv2m, gic, arm_gicv2m_driver,
+ arm_gicv2m_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
+#endif
OpenPOWER on IntegriCloud