diff options
Diffstat (limited to 'sys/amd64/pci/pci_cfgreg.c')
| -rw-r--r-- | sys/amd64/pci/pci_cfgreg.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c index 5120b48..90d9087 100644 --- a/sys/amd64/pci/pci_cfgreg.c +++ b/sys/amd64/pci/pci_cfgreg.c @@ -295,6 +295,13 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) return (1); } +#define PCIE_VADDR(base, reg, bus, slot, func) \ + ((base) + \ + ((((bus) & 0xff) << 20) | \ + (((slot) & 0x1f) << 15) | \ + (((func) & 0x7) << 12) | \ + ((reg) & 0xfff))) + /* * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h * have a requirement that all accesses to the memory mapped PCI configuration @@ -302,12 +309,6 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) * Since other vendors do not currently have any contradicting requirements * the AMD access pattern is applied universally. */ -#define PCIE_VADDR(base, reg, bus, slot, func) \ - ((base) + \ - ((((bus) & 0xff) << 20) | \ - (((slot) & 0x1f) << 15) | \ - (((func) & 0x7) << 12) | \ - ((reg) & 0xfff))) static int pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg, |
