diff options
Diffstat (limited to 'lib/Target/XCore')
21 files changed, 204 insertions, 77 deletions
diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt index 9093de6..a1d73c6 100644 --- a/lib/Target/XCore/CMakeLists.txt +++ b/lib/Target/XCore/CMakeLists.txt @@ -1,14 +1,11 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) -tablegen(XCoreGenRegisterInfo.h.inc -gen-register-desc-header) -tablegen(XCoreGenRegisterNames.inc -gen-register-enums) -tablegen(XCoreGenRegisterInfo.inc -gen-register-desc) -tablegen(XCoreGenInstrNames.inc -gen-instr-enums) -tablegen(XCoreGenInstrInfo.inc -gen-instr-desc) +tablegen(XCoreGenRegisterInfo.inc -gen-register-info) +tablegen(XCoreGenInstrInfo.inc -gen-instr-info) tablegen(XCoreGenAsmWriter.inc -gen-asm-writer) tablegen(XCoreGenDAGISel.inc -gen-dag-isel) tablegen(XCoreGenCallingConv.inc -gen-callingconv) -tablegen(XCoreGenSubtarget.inc -gen-subtarget) +tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget) add_llvm_target(XCoreCodeGen XCoreAsmPrinter.cpp @@ -16,7 +13,6 @@ add_llvm_target(XCoreCodeGen XCoreInstrInfo.cpp XCoreISelDAGToDAG.cpp XCoreISelLowering.cpp - XCoreMCAsmInfo.cpp XCoreRegisterInfo.cpp XCoreSubtarget.cpp XCoreTargetMachine.cpp @@ -25,3 +21,4 @@ add_llvm_target(XCoreCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/lib/Target/XCore/MCTargetDesc/CMakeLists.txt b/lib/Target/XCore/MCTargetDesc/CMakeLists.txt new file mode 100644 index 0000000..c3b3dc9 --- /dev/null +++ b/lib/Target/XCore/MCTargetDesc/CMakeLists.txt @@ -0,0 +1,7 @@ +add_llvm_library(LLVMXCoreDesc + XCoreMCTargetDesc.cpp + XCoreMCAsmInfo.cpp + ) + +# Hack: we need to include 'main' target directory to grab private headers +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..) diff --git a/lib/Target/XCore/MCTargetDesc/Makefile b/lib/Target/XCore/MCTargetDesc/Makefile new file mode 100644 index 0000000..de61543 --- /dev/null +++ b/lib/Target/XCore/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/XCore/TargetDesc/Makefile ----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMXCoreDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/XCore/XCoreMCAsmInfo.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp index 42ab1b3..42ab1b3 100644 --- a/lib/Target/XCore/XCoreMCAsmInfo.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp diff --git a/lib/Target/XCore/XCoreMCAsmInfo.h b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h index 8403922..8403922 100644 --- a/lib/Target/XCore/XCoreMCAsmInfo.h +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp new file mode 100644 index 0000000..939d97c --- /dev/null +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -0,0 +1,56 @@ +//===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides XCore specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "XCoreMCTargetDesc.h" +#include "XCoreMCAsmInfo.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "XCoreGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "XCoreGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "XCoreGenRegisterInfo.inc" + +using namespace llvm; + +static MCInstrInfo *createXCoreMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitXCoreMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeXCoreMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo); +} + +static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitXCoreMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeXCoreMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget, + createXCoreMCSubtargetInfo); +} + +extern "C" void LLVMInitializeXCoreMCAsmInfo() { + RegisterMCAsmInfo<XCoreMCAsmInfo> X(TheXCoreTarget); +} diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h new file mode 100644 index 0000000..3cfc3764 --- /dev/null +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h @@ -0,0 +1,40 @@ +//===-- XCoreMCTargetDesc.h - XCore Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides XCore specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef XCOREMCTARGETDESC_H +#define XCOREMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheXCoreTarget; + +} // End llvm namespace + +// Defines symbolic names for XCore registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "XCoreGenRegisterInfo.inc" + +// Defines symbolic names for the XCore instructions. +// +#define GET_INSTRINFO_ENUM +#include "XCoreGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "XCoreGenSubtargetInfo.inc" + +#endif diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile index 6c1ef88..b823c4e 100644 --- a/lib/Target/XCore/Makefile +++ b/lib/Target/XCore/Makefile @@ -12,13 +12,12 @@ LIBRARYNAME = LLVMXCoreCodeGen TARGET = XCore # Make sure that tblgen is run, first thing. -BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \ - XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ - XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ +BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \ + XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ - XCoreGenSubtarget.inc + XCoreGenSubtargetInfo.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h index 8937fbe..b8fb0ca 100644 --- a/lib/Target/XCore/XCore.h +++ b/lib/Target/XCore/XCore.h @@ -15,6 +15,7 @@ #ifndef TARGET_XCORE_H #define TARGET_XCORE_H +#include "MCTargetDesc/XCoreMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -25,17 +26,6 @@ namespace llvm { FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM); - extern Target TheXCoreTarget; - } // end namespace llvm; -// Defines symbolic names for XCore registers. This defines a mapping from -// register name to register number. -// -#include "XCoreGenRegisterNames.inc" - -// Defines symbolic names for the XCore instructions. -// -#include "XCoreGenInstrNames.inc" - #endif diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index 8f06dd3..1a43714 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -16,7 +16,6 @@ #include "XCore.h" #include "XCoreInstrInfo.h" #include "XCoreSubtarget.h" -#include "XCoreMCAsmInfo.h" #include "XCoreTargetMachine.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" @@ -27,6 +26,7 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" @@ -114,7 +114,7 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { MCSymbol *GVSym = Mang->getSymbol(GV); - Constant *C = GV->getInitializer(); + const Constant *C = GV->getInitializer(); unsigned Align = (unsigned)TD->getPreferredTypeAlignmentShift(C->getType()); // Mark the start of the global diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 8cabbbf..6d040e0 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1591,21 +1591,18 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, // XCore Inline Assembly Support //===----------------------------------------------------------------------===// -std::vector<unsigned> XCoreTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const -{ - if (Constraint.size() != 1) - return std::vector<unsigned>(); - - switch (Constraint[0]) { +std::pair<unsigned, const TargetRegisterClass*> +XCoreTargetLowering:: +getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { default : break; case 'r': - return make_vector<unsigned>(XCore::R0, XCore::R1, XCore::R2, - XCore::R3, XCore::R4, XCore::R5, - XCore::R6, XCore::R7, XCore::R8, - XCore::R9, XCore::R10, XCore::R11, 0); - break; + return std::make_pair(0U, XCore::GRRegsRegisterClass); + } } - return std::vector<unsigned>(); + // Use the default implementation in TargetLowering to convert the register + // constraint into a member of a register class. + return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index a8d67d4..9c803be 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -148,9 +148,9 @@ namespace llvm { SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; // Inline asm support - std::vector<unsigned> - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; + std::pair<unsigned, const TargetRegisterClass*> + getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const; // Expand specifics SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const; diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 9cb6a7d..f90481f 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -18,11 +18,14 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "XCoreGenInstrInfo.inc" +#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_CTOR +#include "XCoreGenInstrInfo.inc" + namespace llvm { namespace XCore { @@ -38,7 +41,7 @@ namespace XCore { using namespace llvm; XCoreInstrInfo::XCoreInstrInfo() - : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)), + : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), RI(*this) { } diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index 977fe8d..840b1e1 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -17,9 +17,12 @@ #include "llvm/Target/TargetInstrInfo.h" #include "XCoreRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "XCoreGenInstrInfo.inc" + namespace llvm { -class XCoreInstrInfo : public TargetInstrInfoImpl { +class XCoreInstrInfo : public XCoreGenInstrInfo { const XCoreRegisterInfo RI; public: XCoreInstrInfo(); diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 46c9e57..357a4a0 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -33,11 +33,13 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#define GET_REGINFO_TARGET_DESC +#include "XCoreGenRegisterInfo.inc" + using namespace llvm; XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) - : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), - TII(tii) { + : XCoreGenRegisterInfo(), TII(tii) { } // helper functions @@ -193,7 +195,16 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, #endif Offset += StackSize; - + + unsigned FrameReg = getFrameRegister(MF); + + // Special handling of DBG_VALUE instructions. + if (MI.isDebugValue()) { + MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/); + MI.getOperand(i+1).ChangeToImmediate(Offset); + return; + } + // fold constant into offset. Offset += MI.getOperand(i + 1).getImm(); MI.getOperand(i + 1).ChangeToImmediate(0); @@ -205,7 +216,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Offset/=4; bool FP = TFI->hasFP(MF); - + unsigned Reg = MI.getOperand(0).getReg(); bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill(); @@ -216,7 +227,6 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (FP) { bool isUs = isImmUs(Offset); - unsigned FramePtr = XCore::R10; if (!isUs) { if (!RS) @@ -228,18 +238,18 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, switch (MI.getOpcode()) { case XCore::LDWFI: BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) - .addReg(FramePtr) + .addReg(FrameReg) .addReg(ScratchReg, RegState::Kill); break; case XCore::STWFI: BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) .addReg(Reg, getKillRegState(isKill)) - .addReg(FramePtr) + .addReg(FrameReg) .addReg(ScratchReg, RegState::Kill); break; case XCore::LDAWFI: BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) - .addReg(FramePtr) + .addReg(FrameReg) .addReg(ScratchReg, RegState::Kill); break; default: @@ -249,18 +259,18 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, switch (MI.getOpcode()) { case XCore::LDWFI: BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) - .addReg(FramePtr) + .addReg(FrameReg) .addImm(Offset); break; case XCore::STWFI: BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) .addReg(Reg, getKillRegState(isKill)) - .addReg(FramePtr) + .addReg(FrameReg) .addImm(Offset); break; case XCore::LDAWFI: BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) - .addReg(FramePtr) + .addReg(FrameReg) .addImm(Offset); break; default: @@ -328,6 +338,3 @@ unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { unsigned XCoreRegisterInfo::getRARegister() const { return XCore::LR; } - -#include "XCoreGenRegisterInfo.inc" - diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h index 7a9bc9f..801d9eb 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.h +++ b/lib/Target/XCore/XCoreRegisterInfo.h @@ -15,7 +15,9 @@ #define XCOREREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "XCoreGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "XCoreGenRegisterInfo.inc" namespace llvm { diff --git a/lib/Target/XCore/XCoreRegisterInfo.td b/lib/Target/XCore/XCoreRegisterInfo.td index 0951097..c354230 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.td +++ b/lib/Target/XCore/XCoreRegisterInfo.td @@ -44,13 +44,13 @@ def LR : Ri<15, "lr">, DwarfRegNum<[15]>; // def GRRegs : RegisterClass<"XCore", [i32], 32, // Return values and arguments - [R0, R1, R2, R3, + (add R0, R1, R2, R3, // Not preserved across procedure calls R11, // Callee save - R4, R5, R6, R7, R8, R9, R10]>; + R4, R5, R6, R7, R8, R9, R10)>; // Reserved -def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> { +def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> { let isAllocatable = 0; } diff --git a/lib/Target/XCore/XCoreSubtarget.cpp b/lib/Target/XCore/XCoreSubtarget.cpp index 78a6fa5..ad069bf 100644 --- a/lib/Target/XCore/XCoreSubtarget.cpp +++ b/lib/Target/XCore/XCoreSubtarget.cpp @@ -7,14 +7,22 @@ // //===----------------------------------------------------------------------===// // -// This file implements the XCore specific subclass of TargetSubtarget. +// This file implements the XCore specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// #include "XCoreSubtarget.h" #include "XCore.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR +#include "XCoreGenSubtargetInfo.inc" + using namespace llvm; -XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &FS) +XCoreSubtarget::XCoreSubtarget(const std::string &TT, + const std::string &CPU, const std::string &FS) + : XCoreGenSubtargetInfo(TT, CPU, FS) { } diff --git a/lib/Target/XCore/XCoreSubtarget.h b/lib/Target/XCore/XCoreSubtarget.h index f8be3ec..7b29fa2 100644 --- a/lib/Target/XCore/XCoreSubtarget.h +++ b/lib/Target/XCore/XCoreSubtarget.h @@ -7,32 +7,35 @@ // //===----------------------------------------------------------------------===// // -// This file declares the XCore specific subclass of TargetSubtarget. +// This file declares the XCore specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// #ifndef XCORESUBTARGET_H #define XCORESUBTARGET_H -#include "llvm/Target/TargetSubtarget.h" +#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Target/TargetMachine.h" - #include <string> +#define GET_SUBTARGETINFO_HEADER +#include "XCoreGenSubtargetInfo.inc" + namespace llvm { +class StringRef; -class XCoreSubtarget : public TargetSubtarget { +class XCoreSubtarget : public XCoreGenSubtargetInfo { public: /// This constructor initializes the data members to match that /// of the specified triple. /// - XCoreSubtarget(const std::string &TT, const std::string &FS); + XCoreSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); }; } // End llvm namespace diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index 30da2c8..342966a 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -10,7 +10,6 @@ // //===----------------------------------------------------------------------===// -#include "XCoreMCAsmInfo.h" #include "XCoreTargetMachine.h" #include "XCore.h" #include "llvm/Module.h" @@ -21,9 +20,10 @@ using namespace llvm; /// XCoreTargetMachine ctor - Create an ILP32 architecture model /// XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : LLVMTargetMachine(T, TT), - Subtarget(TT, FS), + : LLVMTargetMachine(T, TT, CPU, FS), + Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), InstrInfo(), @@ -41,5 +41,4 @@ bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, // Force static initialization. extern "C" void LLVMInitializeXCoreTarget() { RegisterTargetMachine<XCoreTargetMachine> X(TheXCoreTarget); - RegisterAsmInfo<XCoreMCAsmInfo> Y(TheXCoreTarget); } diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index 24daadc..6235ac3 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -33,7 +33,7 @@ class XCoreTargetMachine : public LLVMTargetMachine { XCoreSelectionDAGInfo TSInfo; public: XCoreTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreFrameLowering *getFrameLowering() const { |
