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Diffstat (limited to 'docs/ReleaseNotes.html')
| -rw-r--r-- | docs/ReleaseNotes.html | 101 |
1 files changed, 94 insertions, 7 deletions
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html index 85448a5..a4b1d58 100644 --- a/docs/ReleaseNotes.html +++ b/docs/ReleaseNotes.html @@ -466,7 +466,45 @@ Release Notes</a>.</h1> <p>In addition to many minor performance tweaks and bug fixes, this release includes a few major enhancements and additions to the optimizers:</p> +<p> Loop Vectorizer - We've added a loop vectorizer and we are now able to + vectorize small loops. The loop vectorizer is disabled by default and + can be enabled using the <b>-mllvm -vectorize-loops</b> flag. + The SIMD vector width can be specified using the flag + <b>-mllvm -force-vector-width=4</b>. + The default value is <b>0</b> which means auto-select. + <br/> + We can now vectorize this function: + + <pre class="doc_code"> + unsigned sum_arrays(int *A, int *B, int start, int end) { + unsigned sum = 0; + for (int i = start; i < end; ++i) + sum += A[i] + B[i] + i; + + return sum; + } + </pre> + + We vectorize under the following loops: + <ul> + <li>The inner most loops must have a single basic block.</li> + <li>The number of iterations are known before the loop starts to execute.</li> + <li>The loop counter needs to be incrimented by one.</li> + <li>The loop trip count <b>can</b> be a variable.</li> + <li>Loops do <b>not</b> need to start at zero.</li> + <li>The induction variable can be used inside the loop.</li> + <li>Loop reductions are supported.</li> + <li>Arrays with affine access pattern do <b>not</b> need to be marked as 'noalias' and are checked at runtime.</li> + <li>...</li> + </ul> + +</p> + +<p>SROA - We've re-written SROA to be significantly more powerful. +<!-- FIXME: Add more text here... --></p> + <ul> + <li>Branch weight metadata is preseved through more of the optimizer.</li> <li>...</li> </ul> @@ -499,13 +537,14 @@ Release Notes</a>.</h1> <div> -<p>We have changed the way that the Type Legalizer legalizes vectors. The type - legalizer now attempts to promote integer elements. This enabled the - implementation of vector-select. Additionally, we see a performance boost on - workloads which use vectors of chars and shorts, since they are now promoted - to 32-bit types, which are better supported by the SIMD instruction set. - Floating point types are still widened as before.</p> +<p>Stack Coloring - We have implemented a new optimization pass + to merge stack objects which are used in disjoin areas of the code. + This optimization reduces the required stack space significantly, in cases + where it is clear to the optimizer that the stack slot is not shared. + We use the lifetime markers to tell the codegen that a certain alloca + is used within a region.</p> +<p> We now merge consecutive loads and stores. </p> <p>We have put a significant amount of work into the code generator infrastructure, which allows us to implement more aggressive algorithms and @@ -608,6 +647,46 @@ Release Notes</a>.</h1> <!--=========================================================================--> <h3> +<a name="PowerPC">PowerPC Target Improvements</a> +</h3> + +<div> + +<ul> +<p>Many fixes and changes across LLVM (and Clang) for better compliance with + the 64-bit PowerPC ELF Application Binary Interface, interoperability with + GCC, and overall 64-bit PowerPC support. Some highlights include:</p> +<ul> + <li> MCJIT support added.</li> + <li> PPC64 relocation support and (small code model) TOC handling + added.</li> + <li> Parameter passing and return value fixes (alignment issues, + padding, varargs support, proper register usage, odd-sized + structure support, float support, extension of return values + for i32 return values).</li> + <li> Fixes in spill and reload code for vector registers.</li> + <li> C++ exception handling enabled.</li> + <li> Changes to remediate double-rounding compatibility issues with + respect to GCC behavior.</li> + <li> Refactoring to disentangle ppc64-elf-linux ABI from Darwin + ppc64 ABI support.</li> + <li> Assorted new test cases and test case fixes (endian and word + size issues).</li> + <li> Fixes for big-endian codegen bugs, instruction encodings, and + instruction constraints.</li> + <li> Implemented -integrated-as support.</li> + <li> Additional support for Altivec compare operations.</li> + <li> IBM long double support.</li> +</ul> +<p>There have also been code generation improvements for both 32- and 64-bit + code. Instruction scheduling support for the Freescale e500mc and e5500 + cores has been added.</p> +</ul> + +</div> + +<!--=========================================================================--> +<h3> <a name="OtherTS">Other Target Specific Improvements</a> </h3> @@ -646,6 +725,14 @@ Release Notes</a>.</h1> <p>In addition, many APIs have changed in this release. Some of the major LLVM API changes are:</p> +<p> We've added a new interface for allowing IR-level passes to access + target-specific information. A new IR-level pass, called + "TargetTransformInfo" provides a number of low-level interfaces. + LSR and LowerInvoke already use the new interface. </p> + +<p> The TargetData structure has been renamed to DataLayout and moved to VMCore +to remove a dependency on Target. </p> + <ul> <li>...</li> </ul> @@ -749,7 +836,7 @@ Release Notes</a>.</h1> src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a> <a href="http://llvm.org/">LLVM Compiler Infrastructure</a><br> - Last modified: $Date: 2012-07-13 14:44:23 +0200 (Fri, 13 Jul 2012) $ + Last modified: $Date: 2012-11-20 05:22:44 +0100 (Tue, 20 Nov 2012) $ </address> </body> |
