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-rw-r--r--contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp267
1 files changed, 145 insertions, 122 deletions
diff --git a/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp b/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp
index ca937d0..4736c4e 100644
--- a/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -23,96 +23,100 @@
using namespace llvm;
#define MRM_MAPPING \
- MAP(C0, 32) \
- MAP(C1, 33) \
- MAP(C2, 34) \
- MAP(C3, 35) \
- MAP(C4, 36) \
- MAP(C5, 37) \
- MAP(C6, 38) \
- MAP(C7, 39) \
- MAP(C8, 40) \
- MAP(C9, 41) \
- MAP(CA, 42) \
- MAP(CB, 43) \
- MAP(CC, 44) \
- MAP(CD, 45) \
- MAP(CE, 46) \
- MAP(CF, 47) \
- MAP(D0, 48) \
- MAP(D1, 49) \
- MAP(D2, 50) \
- MAP(D3, 51) \
- MAP(D4, 52) \
- MAP(D5, 53) \
- MAP(D6, 54) \
- MAP(D7, 55) \
- MAP(D8, 56) \
- MAP(D9, 57) \
- MAP(DA, 58) \
- MAP(DB, 59) \
- MAP(DC, 60) \
- MAP(DD, 61) \
- MAP(DE, 62) \
- MAP(DF, 63) \
- MAP(E0, 64) \
- MAP(E1, 65) \
- MAP(E2, 66) \
- MAP(E3, 67) \
- MAP(E4, 68) \
- MAP(E5, 69) \
- MAP(E6, 70) \
- MAP(E7, 71) \
- MAP(E8, 72) \
- MAP(E9, 73) \
- MAP(EA, 74) \
- MAP(EB, 75) \
- MAP(EC, 76) \
- MAP(ED, 77) \
- MAP(EE, 78) \
- MAP(EF, 79) \
- MAP(F0, 80) \
- MAP(F1, 81) \
- MAP(F2, 82) \
- MAP(F3, 83) \
- MAP(F4, 84) \
- MAP(F5, 85) \
- MAP(F6, 86) \
- MAP(F7, 87) \
- MAP(F8, 88) \
- MAP(F9, 89) \
- MAP(FA, 90) \
- MAP(FB, 91) \
- MAP(FC, 92) \
- MAP(FD, 93) \
- MAP(FE, 94) \
- MAP(FF, 95)
+ MAP(C0, 64) \
+ MAP(C1, 65) \
+ MAP(C2, 66) \
+ MAP(C3, 67) \
+ MAP(C4, 68) \
+ MAP(C5, 69) \
+ MAP(C6, 70) \
+ MAP(C7, 71) \
+ MAP(C8, 72) \
+ MAP(C9, 73) \
+ MAP(CA, 74) \
+ MAP(CB, 75) \
+ MAP(CC, 76) \
+ MAP(CD, 77) \
+ MAP(CE, 78) \
+ MAP(CF, 79) \
+ MAP(D0, 80) \
+ MAP(D1, 81) \
+ MAP(D2, 82) \
+ MAP(D3, 83) \
+ MAP(D4, 84) \
+ MAP(D5, 85) \
+ MAP(D6, 86) \
+ MAP(D7, 87) \
+ MAP(D8, 88) \
+ MAP(D9, 89) \
+ MAP(DA, 90) \
+ MAP(DB, 91) \
+ MAP(DC, 92) \
+ MAP(DD, 93) \
+ MAP(DE, 94) \
+ MAP(DF, 95) \
+ MAP(E0, 96) \
+ MAP(E1, 97) \
+ MAP(E2, 98) \
+ MAP(E3, 99) \
+ MAP(E4, 100) \
+ MAP(E5, 101) \
+ MAP(E6, 102) \
+ MAP(E7, 103) \
+ MAP(E8, 104) \
+ MAP(E9, 105) \
+ MAP(EA, 106) \
+ MAP(EB, 107) \
+ MAP(EC, 108) \
+ MAP(ED, 109) \
+ MAP(EE, 110) \
+ MAP(EF, 111) \
+ MAP(F0, 112) \
+ MAP(F1, 113) \
+ MAP(F2, 114) \
+ MAP(F3, 115) \
+ MAP(F4, 116) \
+ MAP(F5, 117) \
+ MAP(F6, 118) \
+ MAP(F7, 119) \
+ MAP(F8, 120) \
+ MAP(F9, 121) \
+ MAP(FA, 122) \
+ MAP(FB, 123) \
+ MAP(FC, 124) \
+ MAP(FD, 125) \
+ MAP(FE, 126) \
+ MAP(FF, 127)
// A clone of X86 since we can't depend on something that is generated.
namespace X86Local {
enum {
- Pseudo = 0,
- RawFrm = 1,
- AddRegFrm = 2,
- MRMDestReg = 3,
- MRMDestMem = 4,
- MRMSrcReg = 5,
- MRMSrcMem = 6,
- RawFrmMemOffs = 7,
- RawFrmSrc = 8,
- RawFrmDst = 9,
- RawFrmDstSrc = 10,
- RawFrmImm8 = 11,
- RawFrmImm16 = 12,
- MRMXr = 14, MRMXm = 15,
- MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
- MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
- MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
- MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
+ Pseudo = 0,
+ RawFrm = 1,
+ AddRegFrm = 2,
+ RawFrmMemOffs = 3,
+ RawFrmSrc = 4,
+ RawFrmDst = 5,
+ RawFrmDstSrc = 6,
+ RawFrmImm8 = 7,
+ RawFrmImm16 = 8,
+ MRMDestMem = 32,
+ MRMSrcMem = 33,
+ MRMSrcMem4VOp3 = 34,
+ MRMSrcMemOp4 = 35,
+ MRMXm = 39,
+ MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43,
+ MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47,
+ MRMDestReg = 48,
+ MRMSrcReg = 49,
+ MRMSrcReg4VOp3 = 50,
+ MRMSrcRegOp4 = 51,
+ MRMXr = 55,
+ MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59,
+ MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63,
#define MAP(from, to) MRM_##from = to,
MRM_MAPPING
#undef MAP
- lastMRM
};
enum {
@@ -138,19 +142,6 @@ namespace X86Local {
using namespace X86Disassembler;
-/// isRegFormat - Indicates whether a particular form requires the Mod field of
-/// the ModR/M byte to be 0b11.
-///
-/// @param form - The form of the instruction.
-/// @return - true if the form implies that Mod must be 0b11, false
-/// otherwise.
-static bool isRegFormat(uint8_t form) {
- return (form == X86Local::MRMDestReg ||
- form == X86Local::MRMSrcReg ||
- form == X86Local::MRMXr ||
- (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
-}
-
/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
/// Useful for switch statements and the like.
///
@@ -212,9 +203,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
AdSize = byteFromRec(Rec, "AdSizeBits");
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
- HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
- HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
@@ -565,7 +554,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
// Given the set of prefix bits, how many additional operands does the
// instruction have?
unsigned additionalOperands = 0;
- if (HasVEX_4V || HasVEX_4VOp3)
+ if (HasVEX_4V)
++additionalOperands;
if (HasEVEX_K)
++additionalOperands;
@@ -666,19 +655,27 @@ void RecognizableInstr::emitInstructionSpecifier() {
// in ModRMVEX and the one above the one in the VEX.VVVV field
HANDLE_OPERAND(vvvvRegister)
- if (HasMemOp4Prefix)
- HANDLE_OPERAND(immediate)
-
HANDLE_OPERAND(rmRegister)
-
- if (HasVEX_4VOp3)
- HANDLE_OPERAND(vvvvRegister)
-
- if (!HasMemOp4Prefix)
- HANDLE_OPTIONAL(immediate)
+ HANDLE_OPTIONAL(immediate)
HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
HANDLE_OPTIONAL(immediate)
break;
+ case X86Local::MRMSrcReg4VOp3:
+ assert(numPhysicalOperands == 3 &&
+ "Unexpected number of operands for MRMSrcRegFrm");
+ HANDLE_OPERAND(roRegister)
+ HANDLE_OPERAND(rmRegister)
+ HANDLE_OPERAND(vvvvRegister)
+ break;
+ case X86Local::MRMSrcRegOp4:
+ assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
+ "Unexpected number of operands for MRMSrcRegOp4Frm");
+ HANDLE_OPERAND(roRegister)
+ HANDLE_OPERAND(vvvvRegister)
+ HANDLE_OPERAND(immediate) // Register in imm[7:4]
+ HANDLE_OPERAND(rmRegister)
+ HANDLE_OPTIONAL(immediate)
+ break;
case X86Local::MRMSrcMem:
// Operand 1 is a register operand in the Reg/Opcode field.
// Operand 2 is a memory operand (possibly SIB-extended)
@@ -699,18 +696,26 @@ void RecognizableInstr::emitInstructionSpecifier() {
// in ModRMVEX and the one above the one in the VEX.VVVV field
HANDLE_OPERAND(vvvvRegister)
- if (HasMemOp4Prefix)
- HANDLE_OPERAND(immediate)
-
HANDLE_OPERAND(memory)
-
- if (HasVEX_4VOp3)
- HANDLE_OPERAND(vvvvRegister)
-
- if (!HasMemOp4Prefix)
- HANDLE_OPTIONAL(immediate)
+ HANDLE_OPTIONAL(immediate)
HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
break;
+ case X86Local::MRMSrcMem4VOp3:
+ assert(numPhysicalOperands == 3 &&
+ "Unexpected number of operands for MRMSrcMemFrm");
+ HANDLE_OPERAND(roRegister)
+ HANDLE_OPERAND(memory)
+ HANDLE_OPERAND(vvvvRegister)
+ break;
+ case X86Local::MRMSrcMemOp4:
+ assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
+ "Unexpected number of operands for MRMSrcMemOp4Frm");
+ HANDLE_OPERAND(roRegister)
+ HANDLE_OPERAND(vvvvRegister)
+ HANDLE_OPERAND(immediate) // Register in imm[7:4]
+ HANDLE_OPERAND(memory)
+ HANDLE_OPTIONAL(immediate)
+ break;
case X86Local::MRMXr:
case X86Local::MRM0r:
case X86Local::MRM1r:
@@ -841,13 +846,31 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
}
switch (Form) {
- default:
+ default: llvm_unreachable("Invalid form!");
+ case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
+ case X86Local::RawFrm:
+ case X86Local::AddRegFrm:
+ case X86Local::RawFrmMemOffs:
+ case X86Local::RawFrmSrc:
+ case X86Local::RawFrmDst:
+ case X86Local::RawFrmDstSrc:
+ case X86Local::RawFrmImm8:
+ case X86Local::RawFrmImm16:
filter = new DumbFilter();
break;
- case X86Local::MRMDestReg: case X86Local::MRMDestMem:
- case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
- case X86Local::MRMXr: case X86Local::MRMXm:
- filter = new ModFilter(isRegFormat(Form));
+ case X86Local::MRMDestReg:
+ case X86Local::MRMSrcReg:
+ case X86Local::MRMSrcReg4VOp3:
+ case X86Local::MRMSrcRegOp4:
+ case X86Local::MRMXr:
+ filter = new ModFilter(true);
+ break;
+ case X86Local::MRMDestMem:
+ case X86Local::MRMSrcMem:
+ case X86Local::MRMSrcMem4VOp3:
+ case X86Local::MRMSrcMemOp4:
+ case X86Local::MRMXm:
+ filter = new ModFilter(false);
break;
case X86Local::MRM0r: case X86Local::MRM1r:
case X86Local::MRM2r: case X86Local::MRM3r:
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