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-rw-r--r--contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp95
1 files changed, 51 insertions, 44 deletions
diff --git a/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp b/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp
index fc2138f..a7c6104 100644
--- a/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -13,32 +13,53 @@
//===----------------------------------------------------------------------===//
#include "AsmWriterInst.h"
+#include "CodeGenInstruction.h"
+#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "SequenceToOffsetTable.h"
+#include "Types.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <algorithm>
#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <deque>
+#include <iterator>
#include <map>
+#include <set>
+#include <string>
+#include <tuple>
#include <utility>
#include <vector>
+
using namespace llvm;
#define DEBUG_TYPE "asm-writer-emitter"
namespace {
+
class AsmWriterEmitter {
RecordKeeper &Records;
CodeGenTarget Target;
ArrayRef<const CodeGenInstruction *> NumberedInstructions;
std::vector<AsmWriterInst> Instructions;
+
public:
AsmWriterEmitter(RecordKeeper &R);
@@ -54,10 +75,11 @@ private:
std::vector<unsigned> &InstOpsUsed,
bool PassSubtarget) const;
};
+
} // end anonymous namespace
static void PrintCases(std::vector<std::pair<std::string,
- AsmWriterOperand> > &OpsToPrint, raw_ostream &O,
+ AsmWriterOperand>> &OpsToPrint, raw_ostream &O,
bool PassSubtarget) {
O << " case " << OpsToPrint.back().first << ":";
AsmWriterOperand TheOp = OpsToPrint.back().second;
@@ -76,7 +98,6 @@ static void PrintCases(std::vector<std::pair<std::string,
O << "\n break;\n";
}
-
/// EmitInstructions - Emit the last instruction in the vector and any other
/// instructions that are suitably similar to it.
static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
@@ -115,14 +136,14 @@ static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
// emit a switch for just this operand now.
O << " switch (MI->getOpcode()) {\n";
O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
- std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
+ std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
- FirstInst.CGI->TheDef->getName(),
+ FirstInst.CGI->TheDef->getName().str(),
FirstInst.Operands[i]));
for (const AsmWriterInst &AWI : SimilarInsts) {
- OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
- AWI.CGI->TheDef->getName(),
+ OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::" +
+ AWI.CGI->TheDef->getName().str(),
AWI.Operands[i]));
}
std::reverse(OpsToPrint.begin(), OpsToPrint.end());
@@ -140,7 +161,6 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
std::vector<std::vector<unsigned>> &InstIdxs,
std::vector<unsigned> &InstOpsUsed,
bool PassSubtarget) const {
-
// This vector parallels UniqueOperandCommands, keeping track of which
// instructions each case are used for. It is a comma separated string of
// enums.
@@ -157,8 +177,7 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
// Check to see if we already have 'Command' in UniqueOperandCommands.
// If not, add it.
- auto I = std::find(UniqueOperandCommands.begin(),
- UniqueOperandCommands.end(), Command);
+ auto I = llvm::find(UniqueOperandCommands, Command);
if (I != UniqueOperandCommands.end()) {
size_t idx = I - UniqueOperandCommands.begin();
InstrsForCase[idx] += ", ";
@@ -225,7 +244,6 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
}
}
-
static void UnescapeString(std::string &Str) {
for (unsigned i = 0; i != Str.size(); ++i) {
if (Str[i] == '\\' && i != Str.size()-1) {
@@ -317,7 +335,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
- while (1) {
+ while (true) {
std::vector<std::string> UniqueOperandCommands;
std::vector<std::vector<unsigned>> InstIdxs;
std::vector<unsigned> NumInstOpsHandled;
@@ -451,10 +469,8 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
}
// Okay, delete instructions with no operand info left.
- auto I = std::remove_if(Instructions.begin(), Instructions.end(),
- [](AsmWriterInst &Inst) {
- return Inst.Operands.empty();
- });
+ auto I = llvm::remove_if(Instructions,
+ [](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
Instructions.erase(I, Instructions.end());
@@ -480,15 +496,6 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
O << "}\n";
}
-static const char *getMinimalTypeForRange(uint64_t Range) {
- assert(Range < 0xFFFFFFFFULL && "Enum too large");
- if (Range > 0xFFFF)
- return "uint32_t";
- if (Range > 0xFF)
- return "uint16_t";
- return "uint8_t";
-}
-
static void
emitRegisterNameString(raw_ostream &O, StringRef AltName,
const std::deque<CodeGenRegister> &Registers) {
@@ -533,7 +540,7 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
StringTable.emit(O, printChar);
O << " };\n\n";
- O << " static const " << getMinimalTypeForRange(StringTable.size()-1)
+ O << " static const " << getMinimalTypeForRange(StringTable.size() - 1, 32)
<< " RegAsmOffset" << AltName << "[] = {";
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
if ((i % 14) == 0)
@@ -595,6 +602,7 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
}
namespace {
+
// IAPrinter - Holds information about an InstAlias. Two InstAliases match if
// they both have the same conditionals. In which case, we cannot print out the
// alias for that pattern.
@@ -604,6 +612,7 @@ class IAPrinter {
std::string Result;
std::string AsmString;
+
public:
IAPrinter(std::string R, std::string AS)
: Result(std::move(R)), AsmString(std::move(AS)) {}
@@ -725,9 +734,10 @@ static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
}
namespace {
+
struct AliasPriorityComparator {
typedef std::pair<CodeGenInstAlias, int> ValueType;
- bool operator()(const ValueType &LHS, const ValueType &RHS) {
+ bool operator()(const ValueType &LHS, const ValueType &RHS) const {
if (LHS.second == RHS.second) {
// We don't actually care about the order, but for consistency it
// shouldn't depend on pointer comparisons.
@@ -738,8 +748,8 @@ struct AliasPriorityComparator {
return LHS.second > RHS.second;
}
};
-}
+} // end anonymous namespace
void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
@@ -814,14 +824,14 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
NumMIOps += Operand.getMINumOperands();
std::string Cond;
- Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
+ Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps);
IAP.addCond(Cond);
bool CantHandle = false;
unsigned MIOpNum = 0;
for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
- std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
+ std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")";
const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
@@ -838,9 +848,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
Rec->isSubClassOf("Operand")) {
std::string PrintMethod = Rec->getValueAsString("PrintMethod");
if (PrintMethod != "" && PrintMethod != "printOperand") {
- PrintMethodIdx = std::find(PrintMethods.begin(),
- PrintMethods.end(), PrintMethod) -
- PrintMethods.begin();
+ PrintMethodIdx =
+ llvm::find(PrintMethods, PrintMethod) - PrintMethods.begin();
if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
PrintMethods.push_back(PrintMethod);
}
@@ -856,12 +865,12 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
Record *R = CGA.ResultOperands[i].getRecord();
if (R->isSubClassOf("RegisterOperand"))
R = R->getValueAsDef("RegClass");
- Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
- R->getName() + "RegClassID)"
- ".contains(" + Op + ".getReg())";
+ Cond = std::string("MRI.getRegClass(") + Target.getName().str() +
+ "::" + R->getName().str() + "RegClassID).contains(" + Op +
+ ".getReg())";
} else {
Cond = Op + ".getReg() == MI->getOperand(" +
- llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()";
+ utostr(IAP.getOpIndex(ROName)) + ").getReg()";
}
} else {
// Assume all printable operands are desired for now. This can be
@@ -878,8 +887,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
} else
break; // No conditions on this operand at all
}
- Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
- Op + ", STI, " + llvm::utostr(Entry) + ")";
+ Cond = Target.getName().str() + ClassName + "ValidateMCOperand(" +
+ Op + ", STI, " + utostr(Entry) + ")";
}
// for all subcases of ResultOperand::K_Record:
IAP.addCond(Cond);
@@ -890,8 +899,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
// MCInst will. An MCExpr could be present, for example.
IAP.addCond(Op + ".isImm()");
- Cond = Op + ".getImm() == " +
- llvm::utostr(CGA.ResultOperands[i].getImm());
+ Cond = Op + ".getImm() == " + itostr(CGA.ResultOperands[i].getImm());
IAP.addCond(Cond);
break;
}
@@ -903,8 +911,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
break;
}
- Cond = Op + ".getReg() == " + Target.getName() + "::" +
- CGA.ResultOperands[i].getRegister()->getName();
+ Cond = Op + ".getReg() == " + Target.getName().str() + "::" +
+ CGA.ResultOperands[i].getRegister()->getName().str();
IAP.addCond(Cond);
break;
}
@@ -1112,7 +1120,6 @@ void AsmWriterEmitter::run(raw_ostream &O) {
EmitPrintAliasInstruction(O);
}
-
namespace llvm {
void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
@@ -1120,4 +1127,4 @@ void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
AsmWriterEmitter(RK).run(OS);
}
-} // End llvm namespace
+} // end namespace llvm
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