diff options
Diffstat (limited to 'contrib/llvm/projects/libunwind/include/libunwind.h')
| -rw-r--r-- | contrib/llvm/projects/libunwind/include/libunwind.h | 150 |
1 files changed, 75 insertions, 75 deletions
diff --git a/contrib/llvm/projects/libunwind/include/libunwind.h b/contrib/llvm/projects/libunwind/include/libunwind.h index 4f08381..64534b1 100644 --- a/contrib/llvm/projects/libunwind/include/libunwind.h +++ b/contrib/llvm/projects/libunwind/include/libunwind.h @@ -46,12 +46,12 @@ enum { }; struct unw_context_t { - uint64_t data[128]; + uint64_t data[_LIBUNWIND_CONTEXT_SIZE]; }; typedef struct unw_context_t unw_context_t; struct unw_cursor_t { - uint64_t data[140]; + uint64_t data[_LIBUNWIND_CURSOR_SIZE]; }; typedef struct unw_cursor_t unw_cursor_t; @@ -151,8 +151,8 @@ enum { UNW_X86_ECX = 1, UNW_X86_EDX = 2, UNW_X86_EBX = 3, - UNW_X86_EBP = 4, - UNW_X86_ESP = 5, + UNW_X86_ESP = 4, + UNW_X86_EBP = 5, UNW_X86_ESI = 6, UNW_X86_EDI = 7 }; @@ -295,77 +295,6 @@ enum { UNW_PPC_SPEFSCR = 112 }; -// 64-bit RISC-V registers -enum { - UNW_RISCV_X0 = 0, - UNW_RISCV_X1 = 1, - UNW_RISCV_RA = 1, - UNW_RISCV_X2 = 2, - UNW_RISCV_SP = 2, - UNW_RISCV_X3 = 3, - UNW_RISCV_X4 = 4, - UNW_RISCV_X5 = 5, - UNW_RISCV_X6 = 6, - UNW_RISCV_X7 = 7, - UNW_RISCV_X8 = 8, - UNW_RISCV_X9 = 9, - UNW_RISCV_X10 = 10, - UNW_RISCV_X11 = 11, - UNW_RISCV_X12 = 12, - UNW_RISCV_X13 = 13, - UNW_RISCV_X14 = 14, - UNW_RISCV_X15 = 15, - UNW_RISCV_X16 = 16, - UNW_RISCV_X17 = 17, - UNW_RISCV_X18 = 18, - UNW_RISCV_X19 = 19, - UNW_RISCV_X20 = 20, - UNW_RISCV_X21 = 21, - UNW_RISCV_X22 = 22, - UNW_RISCV_X23 = 23, - UNW_RISCV_X24 = 24, - UNW_RISCV_X25 = 25, - UNW_RISCV_X26 = 26, - UNW_RISCV_X27 = 27, - UNW_RISCV_X28 = 28, - UNW_RISCV_X29 = 29, - UNW_RISCV_X30 = 30, - UNW_RISCV_X31 = 31, - // reserved block - UNW_RISCV_D0 = 64, - UNW_RISCV_D1 = 65, - UNW_RISCV_D2 = 66, - UNW_RISCV_D3 = 67, - UNW_RISCV_D4 = 68, - UNW_RISCV_D5 = 69, - UNW_RISCV_D6 = 70, - UNW_RISCV_D7 = 71, - UNW_RISCV_D8 = 72, - UNW_RISCV_D9 = 73, - UNW_RISCV_D10 = 74, - UNW_RISCV_D11 = 75, - UNW_RISCV_D12 = 76, - UNW_RISCV_D13 = 77, - UNW_RISCV_D14 = 78, - UNW_RISCV_D15 = 79, - UNW_RISCV_D16 = 80, - UNW_RISCV_D17 = 81, - UNW_RISCV_D18 = 82, - UNW_RISCV_D19 = 83, - UNW_RISCV_D20 = 84, - UNW_RISCV_D21 = 85, - UNW_RISCV_D22 = 86, - UNW_RISCV_D23 = 87, - UNW_RISCV_D24 = 88, - UNW_RISCV_D25 = 89, - UNW_RISCV_D26 = 90, - UNW_RISCV_D27 = 91, - UNW_RISCV_D28 = 92, - UNW_RISCV_D29 = 93, - UNW_RISCV_D30 = 94, - UNW_RISCV_D31 = 95, -}; - // 64-bit ARM64 registers enum { UNW_ARM64_X0 = 0, @@ -604,4 +533,75 @@ enum { UNW_OR1K_R31 = 31, }; +// 64-bit RISC-V registers +enum { + UNW_RISCV_X0 = 0, + UNW_RISCV_X1 = 1, + UNW_RISCV_RA = 1, + UNW_RISCV_X2 = 2, + UNW_RISCV_SP = 2, + UNW_RISCV_X3 = 3, + UNW_RISCV_X4 = 4, + UNW_RISCV_X5 = 5, + UNW_RISCV_X6 = 6, + UNW_RISCV_X7 = 7, + UNW_RISCV_X8 = 8, + UNW_RISCV_X9 = 9, + UNW_RISCV_X10 = 10, + UNW_RISCV_X11 = 11, + UNW_RISCV_X12 = 12, + UNW_RISCV_X13 = 13, + UNW_RISCV_X14 = 14, + UNW_RISCV_X15 = 15, + UNW_RISCV_X16 = 16, + UNW_RISCV_X17 = 17, + UNW_RISCV_X18 = 18, + UNW_RISCV_X19 = 19, + UNW_RISCV_X20 = 20, + UNW_RISCV_X21 = 21, + UNW_RISCV_X22 = 22, + UNW_RISCV_X23 = 23, + UNW_RISCV_X24 = 24, + UNW_RISCV_X25 = 25, + UNW_RISCV_X26 = 26, + UNW_RISCV_X27 = 27, + UNW_RISCV_X28 = 28, + UNW_RISCV_X29 = 29, + UNW_RISCV_X30 = 30, + UNW_RISCV_X31 = 31, + // reserved block + UNW_RISCV_D0 = 64, + UNW_RISCV_D1 = 65, + UNW_RISCV_D2 = 66, + UNW_RISCV_D3 = 67, + UNW_RISCV_D4 = 68, + UNW_RISCV_D5 = 69, + UNW_RISCV_D6 = 70, + UNW_RISCV_D7 = 71, + UNW_RISCV_D8 = 72, + UNW_RISCV_D9 = 73, + UNW_RISCV_D10 = 74, + UNW_RISCV_D11 = 75, + UNW_RISCV_D12 = 76, + UNW_RISCV_D13 = 77, + UNW_RISCV_D14 = 78, + UNW_RISCV_D15 = 79, + UNW_RISCV_D16 = 80, + UNW_RISCV_D17 = 81, + UNW_RISCV_D18 = 82, + UNW_RISCV_D19 = 83, + UNW_RISCV_D20 = 84, + UNW_RISCV_D21 = 85, + UNW_RISCV_D22 = 86, + UNW_RISCV_D23 = 87, + UNW_RISCV_D24 = 88, + UNW_RISCV_D25 = 89, + UNW_RISCV_D26 = 90, + UNW_RISCV_D27 = 91, + UNW_RISCV_D28 = 92, + UNW_RISCV_D29 = 93, + UNW_RISCV_D30 = 94, + UNW_RISCV_D31 = 95, +}; + #endif |
