diff options
Diffstat (limited to 'contrib/llvm/lib/Target/XCore')
29 files changed, 189 insertions, 185 deletions
diff --git a/contrib/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/contrib/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 7fef796..640e6b0 100644 --- a/contrib/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/contrib/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -19,7 +19,6 @@ #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/MemoryObject.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -36,47 +35,35 @@ public: XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) {} - /// \brief See MCDisassembler. - virtual DecodeStatus getInstruction(MCInst &instr, - uint64_t &size, - const MemoryObject ®ion, - uint64_t address, - raw_ostream &vStream, - raw_ostream &cStream) const override; - + DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const override; }; } -static bool readInstruction16(const MemoryObject ®ion, - uint64_t address, - uint64_t &size, - uint16_t &insn) { - uint8_t Bytes[4]; - +static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, + uint64_t &Size, uint16_t &Insn) { // We want to read exactly 2 Bytes of data. - if (region.readBytes(address, 2, Bytes) == -1) { - size = 0; + if (Bytes.size() < 2) { + Size = 0; return false; } // Encoded as a little-endian 16-bit word in the stream. - insn = (Bytes[0] << 0) | (Bytes[1] << 8); + Insn = (Bytes[0] << 0) | (Bytes[1] << 8); return true; } -static bool readInstruction32(const MemoryObject ®ion, - uint64_t address, - uint64_t &size, - uint32_t &insn) { - uint8_t Bytes[4]; - +static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, + uint64_t &Size, uint32_t &Insn) { // We want to read exactly 4 Bytes of data. - if (region.readBytes(address, 4, Bytes) == -1) { - size = 0; + if (Bytes.size() < 4) { + Size = 0; return false; } // Encoded as a little-endian 32-bit word in the stream. - insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | - (Bytes[3] << 24); + Insn = + (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24); return true; } @@ -748,16 +735,12 @@ DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } -MCDisassembler::DecodeStatus -XCoreDisassembler::getInstruction(MCInst &instr, - uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &vStream, - raw_ostream &cStream) const { +MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction( + MCInst &instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream &vStream, raw_ostream &cStream) const { uint16_t insn16; - if (!readInstruction16(Region, Address, Size, insn16)) { + if (!readInstruction16(Bytes, Address, Size, insn16)) { return Fail; } @@ -771,7 +754,7 @@ XCoreDisassembler::getInstruction(MCInst &instr, uint32_t insn32; - if (!readInstruction32(Region, Address, Size, insn32)) { + if (!readInstruction32(Bytes, Address, Size, insn32)) { return Fail; } diff --git a/contrib/llvm/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h b/contrib/llvm/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h index 98e7c98..78521fd 100644 --- a/contrib/llvm/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h +++ b/contrib/llvm/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h @@ -13,8 +13,8 @@ /// //===----------------------------------------------------------------------===// -#ifndef XCOREINSTPRINTER_H -#define XCOREINSTPRINTER_H +#ifndef LLVM_LIB_TARGET_XCORE_INSTPRINTER_XCOREINSTPRINTER_H +#define LLVM_LIB_TARGET_XCORE_INSTPRINTER_XCOREINSTPRINTER_H #include "llvm/MC/MCInstPrinter.h" namespace llvm { diff --git a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp index 5665911..f2d2b37 100644 --- a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp +++ b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp @@ -28,7 +28,6 @@ XCoreMCAsmInfo::XCoreMCAsmInfo(StringRef TT) { ProtectedVisibilityAttr = MCSA_Invalid; // Debug - HasLEB128 = true; ExceptionsType = ExceptionHandling::DwarfCFI; DwarfRegNumForCFI = true; } diff --git a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h index da2689a..26df211 100644 --- a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h +++ b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCORETARGETASMINFO_H -#define XCORETARGETASMINFO_H +#ifndef LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H +#define LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCASMINFO_H #include "llvm/MC/MCAsmInfoELF.h" diff --git a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index d54e94f..4073549 100644 --- a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -99,10 +99,10 @@ class XCoreTargetAsmStreamer : public XCoreTargetStreamer { formatted_raw_ostream &OS; public: XCoreTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS); - virtual void emitCCTopData(StringRef Name) override; - virtual void emitCCTopFunction(StringRef Name) override; - virtual void emitCCBottomData(StringRef Name) override; - virtual void emitCCBottomFunction(StringRef Name) override; + void emitCCTopData(StringRef Name) override; + void emitCCTopFunction(StringRef Name) override; + void emitCCBottomData(StringRef Name) override; + void emitCCBottomFunction(StringRef Name) override; }; XCoreTargetAsmStreamer::XCoreTargetAsmStreamer(MCStreamer &S, diff --git a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h index a255adb..0ff5961 100644 --- a/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h +++ b/contrib/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCOREMCTARGETDESC_H -#define XCOREMCTARGETDESC_H +#ifndef LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCTARGETDESC_H +#define LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCTARGETDESC_H namespace llvm { class Target; diff --git a/contrib/llvm/lib/Target/XCore/XCore.h b/contrib/llvm/lib/Target/XCore/XCore.h index d707edc..140ba2a 100644 --- a/contrib/llvm/lib/Target/XCore/XCore.h +++ b/contrib/llvm/lib/Target/XCore/XCore.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef TARGET_XCORE_H -#define TARGET_XCORE_H +#ifndef LLVM_LIB_TARGET_XCORE_XCORE_H +#define LLVM_LIB_TARGET_XCORE_XCORE_H #include "MCTargetDesc/XCoreMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" diff --git a/contrib/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp b/contrib/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp index e98d4f9..82e4e36 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -117,7 +117,7 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { EmitSpecialLLVMGlobal(GV)) return; - const DataLayout *TD = TM.getDataLayout(); + const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout(); OutStreamer.SwitchSection( getObjFileLowering().SectionForGlobal(GV, *Mang, TM)); @@ -210,7 +210,7 @@ printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { - const DataLayout *DL = TM.getDataLayout(); + const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout(); const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: diff --git a/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index e694736..7c74340 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -16,6 +16,7 @@ #include "XCore.h" #include "XCoreInstrInfo.h" #include "XCoreMachineFunctionInfo.h" +#include "XCoreSubtarget.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -226,7 +227,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { MachineModuleInfo *MMI = &MF.getMMI(); const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); // Debug location must be unknown since the first debug location is used // to determine the end of the prologue. @@ -262,7 +263,8 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { MBB.addLiveIn(XCore::LR); MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)); MIB.addImm(Adjusted); - MIB->addRegisterKilled(XCore::LR, MF.getTarget().getRegisterInfo(), true); + MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(), + true); if (emitFrameMoves) { EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4); unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true); @@ -310,11 +312,10 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { if (emitFrameMoves) { // Frame moves for callee saved. - auto SpillLabels = XFI->getSpillLabels(); - for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) { - MachineBasicBlock::iterator Pos = SpillLabels[I].first; + for (const auto &SpillLabel : XFI->getSpillLabels()) { + MachineBasicBlock::iterator Pos = SpillLabel.first; ++Pos; - CalleeSavedInfo &CSI = SpillLabels[I].second; + const CalleeSavedInfo &CSI = SpillLabel.second; int Offset = MFI->getObjectOffset(CSI.getFrameIdx()); unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true); EmitCfiOffset(MBB, Pos, dl, TII, MMI, DRegNum, Offset); @@ -323,7 +324,8 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { // The unwinder requires stack slot & CFI offsets for the exception info. // We do not save/spill these registers. SmallVector<StackSlotInfo,2> SpillList; - GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering()); + GetEHSpillList(SpillList, MFI, XFI, + MF.getSubtarget().getTargetLowering()); assert(SpillList.size()==2 && "Unexpected SpillList size"); EmitCfiOffset(MBB, MBBI, dl, TII, MMI, MRI->getDwarfRegNum(SpillList[0].Reg, true), @@ -340,7 +342,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); DebugLoc dl = MBBI->getDebugLoc(); unsigned RetOpcode = MBBI->getOpcode(); @@ -355,7 +357,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, // 'Restore' the exception info the unwinder has placed into the stack // slots. SmallVector<StackSlotInfo,2> SpillList; - GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering()); + GetEHSpillList(SpillList, MFI, XFI, MF.getSubtarget().getTargetLowering()); RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList); // Return to the landing pad. @@ -413,7 +415,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, return true; MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>(); bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); @@ -446,7 +448,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const{ MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); bool AtStart = MI == MBB.begin(); MachineBasicBlock::iterator BeforeI = MI; if (!AtStart) @@ -479,7 +481,7 @@ void XCoreFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (!hasReservedCallFrame(MF)) { // Turn the adjcallstackdown instruction into 'extsp <amt>' and the // adjcallstackup instruction into 'ldaw sp, sp[<amt>]' diff --git a/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.h b/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.h index e4f806a..7b169c2 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.h +++ b/contrib/llvm/lib/Target/XCore/XCoreFrameLowering.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCOREFRAMEINFO_H -#define XCOREFRAMEINFO_H +#ifndef LLVM_LIB_TARGET_XCORE_XCOREFRAMELOWERING_H +#define LLVM_LIB_TARGET_XCORE_XCOREFRAMELOWERING_H #include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" @@ -59,4 +59,4 @@ namespace llvm { }; } -#endif // XCOREFRAMEINFO_H +#endif diff --git a/contrib/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp b/contrib/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp index 30c7b59..77292c4 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp @@ -13,6 +13,7 @@ #include "XCore.h" #include "XCoreInstrInfo.h" +#include "XCoreSubtarget.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -43,7 +44,7 @@ FunctionPass *llvm::createXCoreFrameToArgsOffsetEliminationPass() { bool XCoreFTAOElim::runOnMachineFunction(MachineFunction &MF) { const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); unsigned StackSize = MF.getFrameInfo()->getStackSize(); for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { diff --git a/contrib/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/contrib/llvm/lib/Target/XCore/XCoreISelLowering.cpp index be7ef64..51e4d03 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -69,7 +69,7 @@ getTargetNodeName(unsigned Opcode) const } XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM) - : TargetLowering(TM, new XCoreTargetObjectFile()), TM(TM), + : TargetLowering(TM), TM(TM), Subtarget(TM.getSubtarget<XCoreSubtarget>()) { // Set up the register classes. @@ -127,12 +127,14 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM) setOperationAction(ISD::ConstantPool, MVT::i32, Custom); // Loads - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); + } // Custom expand misaligned loads / stores. setOperationAction(ISD::LOAD, MVT::i32, Custom); @@ -426,7 +428,9 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const { assert(LD->getExtensionType() == ISD::NON_EXTLOAD && "Unexpected extension type"); assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); - if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) + if (allowsMisalignedMemoryAccesses(LD->getMemoryVT(), + LD->getAddressSpace(), + LD->getAlignment())) return SDValue(); unsigned ABIAlignment = getDataLayout()-> @@ -461,14 +465,15 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const { if (LD->getAlignment() == 2) { SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr, LD->getPointerInfo(), MVT::i16, - LD->isVolatile(), LD->isNonTemporal(), 2); + LD->isVolatile(), LD->isNonTemporal(), + LD->isInvariant(), 2); SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, DAG.getConstant(2, MVT::i32)); SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr, LD->getPointerInfo().getWithOffset(2), MVT::i16, LD->isVolatile(), - LD->isNonTemporal(), 2); + LD->isNonTemporal(), LD->isInvariant(), 2); SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, DAG.getConstant(16, MVT::i32)); SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); @@ -504,7 +509,9 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) const StoreSDNode *ST = cast<StoreSDNode>(Op); assert(!ST->isTruncatingStore() && "Unexpected store type"); assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); - if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { + if (allowsMisalignedMemoryAccesses(ST->getMemoryVT(), + ST->getAddressSpace(), + ST->getAlignment())) { return SDValue(); } unsigned ABIAlignment = getDataLayout()-> @@ -800,7 +807,8 @@ SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, return SDValue(); MachineFunction &MF = DAG.getMachineFunction(); - const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); + const TargetRegisterInfo *RegInfo = + getTargetMachine().getSubtargetImpl()->getRegisterInfo(); return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), RegInfo->getFrameRegister(MF), MVT::i32); } @@ -846,7 +854,8 @@ LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); // Absolute SP = (FP + FrameToArgs) + Offset - const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); + const TargetRegisterInfo *RegInfo = + getTargetMachine().getSubtargetImpl()->getRegisterInfo(); SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RegInfo->getFrameRegister(MF), MVT::i32); SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl, @@ -969,7 +978,7 @@ LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const { N->getBasePtr(), N->getPointerInfo(), N->isVolatile(), N->isNonTemporal(), N->isInvariant(), N->getAlignment(), - N->getTBAAInfo(), N->getRanges()); + N->getAAInfo(), N->getRanges()); } if (N->getMemoryVT() == MVT::i16) { if (N->getAlignment() < 2) @@ -977,13 +986,13 @@ LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const { return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), N->getBasePtr(), N->getPointerInfo(), MVT::i16, N->isVolatile(), N->isNonTemporal(), - N->getAlignment(), N->getTBAAInfo()); + N->isInvariant(), N->getAlignment(), N->getAAInfo()); } if (N->getMemoryVT() == MVT::i8) return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), N->getBasePtr(), N->getPointerInfo(), MVT::i8, N->isVolatile(), N->isNonTemporal(), - N->getAlignment(), N->getTBAAInfo()); + N->isInvariant(), N->getAlignment(), N->getAAInfo()); return SDValue(); } @@ -999,7 +1008,7 @@ LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const { return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(), N->getPointerInfo(), N->isVolatile(), N->isNonTemporal(), - N->getAlignment(), N->getTBAAInfo()); + N->getAlignment(), N->getAAInfo()); } if (N->getMemoryVT() == MVT::i16) { if (N->getAlignment() < 2) @@ -1007,13 +1016,13 @@ LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const { return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(), N->getPointerInfo(), MVT::i16, N->isVolatile(), N->isNonTemporal(), - N->getAlignment(), N->getTBAAInfo()); + N->getAlignment(), N->getAAInfo()); } if (N->getMemoryVT() == MVT::i8) return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(), N->getPointerInfo(), MVT::i8, N->isVolatile(), N->isNonTemporal(), - N->getAlignment(), N->getTBAAInfo()); + N->getAlignment(), N->getAAInfo()); return SDValue(); } @@ -1118,8 +1127,8 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, // Analyze operands of the call, assigning locations to each operand. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); // The ABI dictates there should be one stack slot available to the callee // on function entry (for saving lr). @@ -1129,8 +1138,8 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, SmallVector<CCValAssign, 16> RVLocs; // Analyze return values to determine the number of bytes of stack required. - CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), RVLocs, *DAG.getContext()); + CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4); RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore); @@ -1284,8 +1293,8 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, // Assign locations to all of the incoming arguments. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); @@ -1443,7 +1452,7 @@ CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { SmallVector<CCValAssign, 16> RVLocs; - CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); + CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); if (!CCInfo.CheckReturn(Outs, RetCC_XCore)) return false; if (CCInfo.getNextStackOffset() != 0 && isVarArg) @@ -1467,8 +1476,8 @@ XCoreTargetLowering::LowerReturn(SDValue Chain, SmallVector<CCValAssign, 16> RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); // Analyze return values. if (!isVarArg) @@ -1541,7 +1550,8 @@ XCoreTargetLowering::LowerReturn(SDValue Chain, MachineBasicBlock * XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { - const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); + const TargetInstrInfo &TII = + *getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); assert((MI->getOpcode() == XCore::SELECT_CC) && "Unexpected instr type to insert"); @@ -1803,7 +1813,9 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, // Replace unaligned store of unaligned load with memmove. StoreSDNode *ST = cast<StoreSDNode>(N); if (!DCI.isBeforeLegalize() || - allowsUnalignedMemoryAccesses(ST->getMemoryVT()) || + allowsMisalignedMemoryAccesses(ST->getMemoryVT(), + ST->getAddressSpace(), + ST->getAlignment()) || ST->isVolatile() || ST->isIndexed()) { break; } @@ -1912,7 +1924,7 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, if (Ty->getTypeID() == Type::VoidTyID) return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); - const DataLayout *TD = TM.getDataLayout(); + const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout(); unsigned Size = TD->getTypeAllocSize(Ty); if (AM.BaseGV) { return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && diff --git a/contrib/llvm/lib/Target/XCore/XCoreISelLowering.h b/contrib/llvm/lib/Target/XCore/XCoreISelLowering.h index 62b89c3..13154c6 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreISelLowering.h +++ b/contrib/llvm/lib/Target/XCore/XCoreISelLowering.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCOREISELLOWERING_H -#define XCOREISELLOWERING_H +#ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H +#define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H #include "XCore.h" #include "llvm/CodeGen/SelectionDAG.h" @@ -215,4 +215,4 @@ namespace llvm { }; } -#endif // XCOREISELLOWERING_H +#endif diff --git a/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index 36ea9a0..c310aa3 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -446,16 +446,19 @@ MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate( dl = MI->getDebugLoc(); if (isImmMskBitp(Value)) { int N = Log2_32(Value) + 1; - return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N); + return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg) + .addImm(N) + .getInstr(); } if (isImmU16(Value)) { int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; - return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value); + return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); } MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool(); const Constant *C = ConstantInt::get( Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value); unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg) - .addConstantPoolIndex(Idx); + .addConstantPoolIndex(Idx) + .getInstr(); } diff --git a/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.h b/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.h index e0be96b..60bb3f8 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCOREINSTRUCTIONINFO_H -#define XCOREINSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H +#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H #include "XCoreRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" diff --git a/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.td b/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.td index 00cb705..8e9bb45 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/contrib/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -381,7 +381,7 @@ def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER", // Three operand short defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; def LSS_3r : F3R_np<0b11000, "lss">; def LSU_3r : F3R_np<0b11001, "lsu">; @@ -412,7 +412,7 @@ def STW_l3r : _FL3R<0b000001100, (outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), "stw $val, $addr[$offset]", []>; -def STW_2rus : _F2RUS<0b0000, (outs), +def STW_2rus : _F2RUS<0b00000, (outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), "stw $val, $addr[$offset]", []>; } @@ -432,7 +432,7 @@ def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), "ldaw $dst, $addr[$offset]", []>; @@ -443,7 +443,7 @@ def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), "ldaw $dst, $addr[-$offset]", []>; @@ -538,7 +538,7 @@ def LMUL_l6r : _FL6R< // Register - U6 //let Uses = [DP] in ... -let neverHasSideEffects = 1, isReMaterializable = 1 in +let hasSideEffects = 0, isReMaterializable = 1 in def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), "ldaw $a, dp[$b]", []>; @@ -564,7 +564,7 @@ def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; //let Uses = [CP] in .. -let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in { +let mayLoad = 1, isReMaterializable = 1, hasSideEffects = 0 in { def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), "ldw $a, cp[$b]", []>; def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), @@ -593,7 +593,7 @@ def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>; } -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), "ldaw $a, sp[$b]", []>; @@ -628,7 +628,7 @@ defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; // U6 let Defs = [SP], Uses = [SP] in { -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; let mayStore = 1 in @@ -639,7 +639,7 @@ defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; } } -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; let Uses = [R11], isCall=1 in @@ -656,7 +656,7 @@ def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; } //let Uses = [CP] in ... -let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in +let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", []>; @@ -690,17 +690,17 @@ defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; // U10 let Defs = [R11], isReMaterializable = 1 in { -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>; def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", [(set R11, (pcrelwrapper tglobaladdr:$a))]>; -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a", []>; -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a", [(set R11, (pcrelwrapper tglobaladdr:$a))]>; @@ -729,7 +729,7 @@ def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; } let Defs = [R11], mayLoad = 1, isReMaterializable = 1, - neverHasSideEffects = 1 in { + hasSideEffects = 0 in { def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", @@ -772,7 +772,7 @@ def ANDNOT_2r : [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; } -let isReMaterializable = 1, neverHasSideEffects = 1 in +let isReMaterializable = 1, hasSideEffects = 0 in def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), "mkmsk $dst, $size", []>; @@ -902,7 +902,7 @@ def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), "byterev $dst, $src", [(set GRRegs:$dst, (bswap GRRegs:$src))]>; -def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), +def CLZ_l2r : _FL2R<0b0000111000, (outs GRRegs:$dst), (ins GRRegs:$src), "clz $dst, $src", [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; @@ -972,13 +972,13 @@ def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; -let Defs=[SP], neverHasSideEffects=1 in +let Defs=[SP], hasSideEffects=0 in def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; -let neverHasSideEffects=1 in +let hasSideEffects=0 in def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; -let neverHasSideEffects=1 in +let hasSideEffects=0 in def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; let hasCtrlDep = 1 in diff --git a/contrib/llvm/lib/Target/XCore/XCoreMCInstLower.h b/contrib/llvm/lib/Target/XCore/XCoreMCInstLower.h index 28e702b..5691478 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreMCInstLower.h +++ b/contrib/llvm/lib/Target/XCore/XCoreMCInstLower.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCOREMCINSTLOWER_H -#define XCOREMCINSTLOWER_H +#ifndef LLVM_LIB_TARGET_XCORE_XCOREMCINSTLOWER_H +#define LLVM_LIB_TARGET_XCORE_XCOREMCINSTLOWER_H #include "llvm/CodeGen/MachineOperand.h" #include "llvm/Support/Compiler.h" diff --git a/contrib/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h b/contrib/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h index 212a5cf..078ffde 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h +++ b/contrib/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCOREMACHINEFUNCTIONINFO_H -#define XCOREMACHINEFUNCTIONINFO_H +#ifndef LLVM_LIB_TARGET_XCORE_XCOREMACHINEFUNCTIONINFO_H +#define LLVM_LIB_TARGET_XCORE_XCOREMACHINEFUNCTIONINFO_H #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -103,4 +103,4 @@ public: }; } // End llvm namespace -#endif // XCOREMACHINEFUNCTIONINFO_H +#endif diff --git a/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp b/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp index 316c82c..5c666ae 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -15,6 +15,7 @@ #include "XCore.h" #include "XCoreInstrInfo.h" #include "XCoreMachineFunctionInfo.h" +#include "XCoreSubtarget.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -98,7 +99,7 @@ static void InsertFPConstInst(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); DebugLoc dl = MI.getDebugLoc(); unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); - RS->setUsed(ScratchOffset); + RS->setRegUsed(ScratchOffset); TII.loadImmediate(MBB, II, ScratchOffset, Offset); switch (MI.getOpcode()) { @@ -170,12 +171,12 @@ static void InsertSPConstInst(MachineBasicBlock::iterator II, unsigned ScratchBase; if (OpCode==XCore::STWFI) { ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); - RS->setUsed(ScratchBase); + RS->setRegUsed(ScratchBase); } else ScratchBase = Reg; BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0); unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); - RS->setUsed(ScratchOffset); + RS->setRegUsed(ScratchOffset); TII.loadImmediate(MBB, II, ScratchOffset, Offset); switch (OpCode) { @@ -221,7 +222,7 @@ const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF XCore::R8, XCore::R9, 0 }; - const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering(); + const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); if (TFI->hasFP(*MF)) return CalleeSavedRegsFP; return CalleeSavedRegs; @@ -229,7 +230,7 @@ const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); Reserved.set(XCore::CP); Reserved.set(XCore::DP); @@ -267,9 +268,9 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineFunction &MF = *MI.getParent()->getParent(); const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); - const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); int StackSize = MF.getFrameInfo()->getStackSize(); @@ -323,7 +324,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; } diff --git a/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.h b/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.h index aa617a0..5d7721c 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.h +++ b/contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCOREREGISTERINFO_H -#define XCOREREGISTERINFO_H +#ifndef LLVM_LIB_TARGET_XCORE_XCOREREGISTERINFO_H +#define LLVM_LIB_TARGET_XCORE_XCOREREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" diff --git a/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp b/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp index 91b33fd..a348844 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp @@ -33,7 +33,7 @@ EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, // Call __memcpy_4 if the src, dst and size are all 4 byte aligned. if (!AlwaysInline && (Align & 3) == 0 && DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { - const TargetLowering &TLI = *DAG.getTarget().getTargetLowering(); + const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering(); TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; Entry.Ty = TLI.getDataLayout()->getIntPtrType(*DAG.getContext()); diff --git a/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h b/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h index 0079de1..cfd80b3 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h +++ b/contrib/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCORESELECTIONDAGINFO_H -#define XCORESELECTIONDAGINFO_H +#ifndef LLVM_LIB_TARGET_XCORE_XCORESELECTIONDAGINFO_H +#define LLVM_LIB_TARGET_XCORE_XCORESELECTIONDAGINFO_H #include "llvm/Target/TargetSelectionDAGInfo.h" diff --git a/contrib/llvm/lib/Target/XCore/XCoreSubtarget.h b/contrib/llvm/lib/Target/XCore/XCoreSubtarget.h index 1e9810b..695578d 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreSubtarget.h +++ b/contrib/llvm/lib/Target/XCore/XCoreSubtarget.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCORESUBTARGET_H -#define XCORESUBTARGET_H +#ifndef LLVM_LIB_TARGET_XCORE_XCORESUBTARGET_H +#define LLVM_LIB_TARGET_XCORE_XCORESUBTARGET_H #include "XCoreFrameLowering.h" #include "XCoreISelLowering.h" @@ -48,14 +48,20 @@ public: /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); - const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } - const XCoreFrameLowering *getFrameLowering() const { return &FrameLowering; } - const XCoreTargetLowering *getTargetLowering() const { return &TLInfo; } - const XCoreSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } - const TargetRegisterInfo *getRegisterInfo() const { + const XCoreInstrInfo *getInstrInfo() const override { return &InstrInfo; } + const XCoreFrameLowering *getFrameLowering() const override { + return &FrameLowering; + } + const XCoreTargetLowering *getTargetLowering() const override { + return &TLInfo; + } + const XCoreSelectionDAGInfo *getSelectionDAGInfo() const override { + return &TSInfo; + } + const TargetRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); } - const DataLayout *getDataLayout() const { return &DL; } + const DataLayout *getDataLayout() const override { return &DL; } }; } // End llvm namespace diff --git a/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index 8d8bb38..21ebf45 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "XCoreTargetMachine.h" +#include "XCoreTargetObjectFile.h" #include "XCore.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Module.h" @@ -26,10 +27,13 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique<XCoreTargetObjectFile>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } +XCoreTargetMachine::~XCoreTargetMachine() {} + namespace { /// XCore Code Generator Pass Configuration Options. class XCorePassConfig : public TargetPassConfig { @@ -41,9 +45,10 @@ public: return getTM<XCoreTargetMachine>(); } + void addIRPasses() override; bool addPreISel() override; bool addInstSelector() override; - bool addPreEmitPass() override; + void addPreEmitPass() override; }; } // namespace @@ -51,6 +56,12 @@ TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) { return new XCorePassConfig(this, PM); } +void XCorePassConfig::addIRPasses() { + addPass(createAtomicExpandPass(&getXCoreTargetMachine())); + + TargetPassConfig::addIRPasses(); +} + bool XCorePassConfig::addPreISel() { addPass(createXCoreLowerThreadLocalPass()); return false; @@ -61,9 +72,8 @@ bool XCorePassConfig::addInstSelector() { return false; } -bool XCorePassConfig::addPreEmitPass() { - addPass(createXCoreFrameToArgsOffsetEliminationPass()); - return false; +void XCorePassConfig::addPreEmitPass() { + addPass(createXCoreFrameToArgsOffsetEliminationPass(), false); } // Force static initialization. diff --git a/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.h b/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.h index 14c43bf..8ff9269 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.h +++ b/contrib/llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCORETARGETMACHINE_H -#define XCORETARGETMACHINE_H +#ifndef LLVM_LIB_TARGET_XCORE_XCORETARGETMACHINE_H +#define LLVM_LIB_TARGET_XCORE_XCORETARGETMACHINE_H #include "XCoreSubtarget.h" #include "llvm/Target/TargetMachine.h" @@ -20,37 +20,24 @@ namespace llvm { class XCoreTargetMachine : public LLVMTargetMachine { + std::unique_ptr<TargetLoweringObjectFile> TLOF; XCoreSubtarget Subtarget; public: XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + ~XCoreTargetMachine() override; - const XCoreInstrInfo *getInstrInfo() const override { - return getSubtargetImpl()->getInstrInfo(); - } - const XCoreFrameLowering *getFrameLowering() const override { - return getSubtargetImpl()->getFrameLowering(); - } const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; } - const XCoreTargetLowering *getTargetLowering() const override { - return getSubtargetImpl()->getTargetLowering(); - } - const XCoreSelectionDAGInfo* getSelectionDAGInfo() const override { - return getSubtargetImpl()->getSelectionDAGInfo(); - } - const TargetRegisterInfo *getRegisterInfo() const override { - return getSubtargetImpl()->getRegisterInfo(); - } - const DataLayout *getDataLayout() const override { - return getSubtargetImpl()->getDataLayout(); - } // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; void addAnalysisPasses(PassManagerBase &PM) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; } // end namespace llvm diff --git a/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp b/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp index cfd3302..86d0de6 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp @@ -145,9 +145,9 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler &Mang, if (Kind.isMergeableConst16()) return MergeableConst16Section; } Type *ObjType = GV->getType()->getPointerElementType(); - if (TM.getCodeModel() == CodeModel::Small || - !ObjType->isSized() || - TM.getDataLayout()->getTypeAllocSize(ObjType) < CodeModelLargeSize) { + if (TM.getCodeModel() == CodeModel::Small || !ObjType->isSized() || + TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(ObjType) < + CodeModelLargeSize) { if (Kind.isReadOnly()) return UseCPRel? ReadOnlySection : DataRelROSection; if (Kind.isBSS() || Kind.isCommon())return BSSSection; diff --git a/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.h b/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.h index d389e55..7d3f49d 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.h +++ b/contrib/llvm/lib/Target/XCore/XCoreTargetObjectFile.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_XCORE_TARGETOBJECTFILE_H -#define LLVM_TARGET_XCORE_TARGETOBJECTFILE_H +#ifndef LLVM_LIB_TARGET_XCORE_XCORETARGETOBJECTFILE_H +#define LLVM_LIB_TARGET_XCORE_XCORETARGETOBJECTFILE_H #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" diff --git a/contrib/llvm/lib/Target/XCore/XCoreTargetStreamer.h b/contrib/llvm/lib/Target/XCore/XCoreTargetStreamer.h index 0a394da..48bf0fa 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreTargetStreamer.h +++ b/contrib/llvm/lib/Target/XCore/XCoreTargetStreamer.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef XCORETARGETSTREAMER_H -#define XCORETARGETSTREAMER_H +#ifndef LLVM_LIB_TARGET_XCORE_XCORETARGETSTREAMER_H +#define LLVM_LIB_TARGET_XCORE_XCORETARGETSTREAMER_H #include "llvm/MC/MCStreamer.h" diff --git a/contrib/llvm/lib/Target/XCore/XCoreTargetTransformInfo.cpp b/contrib/llvm/lib/Target/XCore/XCoreTargetTransformInfo.cpp index 80d193d..da232da 100644 --- a/contrib/llvm/lib/Target/XCore/XCoreTargetTransformInfo.cpp +++ b/contrib/llvm/lib/Target/XCore/XCoreTargetTransformInfo.cpp @@ -43,17 +43,17 @@ public: initializeXCoreTTIPass(*PassRegistry::getPassRegistry()); } - virtual void initializePass() override { + void initializePass() override { pushTTIStack(this); } - virtual void getAnalysisUsage(AnalysisUsage &AU) const override { + void getAnalysisUsage(AnalysisUsage &AU) const override { TargetTransformInfo::getAnalysisUsage(AU); } static char ID; - virtual void *getAdjustedAnalysisPointer(const void *ID) override { + void *getAdjustedAnalysisPointer(const void *ID) override { if (ID == &TargetTransformInfo::ID) return (TargetTransformInfo*)this; return this; |
