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-rw-r--r--contrib/llvm/lib/Target/Hexagon/HexagonIICScalar.td32
1 files changed, 32 insertions, 0 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonIICScalar.td b/contrib/llvm/lib/Target/Hexagon/HexagonIICScalar.td
new file mode 100644
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--- /dev/null
+++ b/contrib/llvm/lib/Target/Hexagon/HexagonIICScalar.td
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+//===--- HexagonIICScalar.td ----------------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+// These itinerary class descriptions are based on the instruction timing
+// classes as per V62. Curretnly, they are just extracted from
+// HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
+
+class PseudoItin {
+ list<InstrItinData> PseudoItin_list = [
+ InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
+ [1, 1, 1]>,
+ InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
+ InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
+ InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
+ ];
+}
+
+class ScalarItin {
+ list<InstrItinData> ScalarItin_list = [
+ InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
+ [3, 1], [Hex_FWD, Hex_FWD]>,
+ InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
+ [1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
+ ];
+}
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