diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/Hexagon.td')
| -rw-r--r-- | contrib/llvm/lib/Target/Hexagon/Hexagon.td | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/Hexagon.td b/contrib/llvm/lib/Target/Hexagon/Hexagon.td index 0b2b463..4767165 100644 --- a/contrib/llvm/lib/Target/Hexagon/Hexagon.td +++ b/contrib/llvm/lib/Target/Hexagon/Hexagon.td @@ -22,14 +22,12 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // Hexagon Architectures -def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">; -def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">; -def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">; -def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">; +include "HexagonDepArch.td" -def FeatureHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", +// Hexagon ISA Extensions +def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", "Hexagon HVX instructions">; -def FeatureHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", +def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", "Hexagon HVX Double instructions">; def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", "Use constant-extended calls">; @@ -37,19 +35,14 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", //===----------------------------------------------------------------------===// // Hexagon Instruction Predicate Definitions. //===----------------------------------------------------------------------===// -def HasV5T : Predicate<"HST->hasV5TOps()">; -def NoV5T : Predicate<"!HST->hasV5TOps()">; -def HasV55T : Predicate<"HST->hasV55TOps()">, - AssemblerPredicate<"ArchV55">; -def HasV60T : Predicate<"HST->hasV60TOps()">, - AssemblerPredicate<"ArchV60">; + def UseMEMOP : Predicate<"HST->useMemOps()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, - AssemblerPredicate<"FeatureHVXDbl">; + AssemblerPredicate<"ExtensionHVXDbl">; def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, - AssemblerPredicate<"FeatureHVX">; + AssemblerPredicate<"ExtensionHVX">; //===----------------------------------------------------------------------===// // Classes used for relation maps. @@ -81,7 +74,7 @@ class IntrinsicsRel; def getPredOpcode : InstrMapping { let FilterClass = "PredRel"; // Instructions with the same BaseOpcode and isNVStore values form a row. - let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"]; + let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"]; // Instructions with the same predicate sense form a column. let ColFields = ["PredSense"]; // The key column is the unpredicated instructions. @@ -132,7 +125,7 @@ def getPredNewOpcode : InstrMapping { // def getPredOldOpcode : InstrMapping { let FilterClass = "PredNewRel"; - let RowFields = ["BaseOpcode", "PredSense", "isNVStore"]; + let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; let ColFields = ["PNewValue"]; let KeyCol = ["new"]; let ValueCols = [[""]]; @@ -248,11 +241,18 @@ def getRealHWInstr : InstrMapping { //===----------------------------------------------------------------------===// include "HexagonSchedule.td" include "HexagonRegisterInfo.td" -include "HexagonCallingConv.td" -include "HexagonInstrInfo.td" +include "HexagonOperands.td" +include "HexagonDepOperands.td" +include "HexagonDepITypes.td" +include "HexagonInstrFormats.td" +include "HexagonDepInstrFormats.td" +include "HexagonDepInstrInfo.td" +include "HexagonPseudo.td" include "HexagonPatterns.td" +include "HexagonDepMappings.td" include "HexagonIntrinsics.td" include "HexagonIntrinsicsDerived.td" +include "HexagonMapAsm2IntrinV62.gen.td" def HexagonInstrInfo : InstrInfo; @@ -271,7 +271,9 @@ def : Proc<"hexagonv5", HexagonModelV4, def : Proc<"hexagonv55", HexagonModelV55, [ArchV4, ArchV5, ArchV55]>; def : Proc<"hexagonv60", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60, FeatureHVX]>; + [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>; +def : Proc<"hexagonv62", HexagonModelV62, + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing |
