diff options
Diffstat (limited to 'contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h')
| -rw-r--r-- | contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 47 |
1 files changed, 21 insertions, 26 deletions
diff --git a/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 9a2faf8..507e897 100644 --- a/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -20,6 +20,9 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" +#define GET_INSTRINFO_HEADER +#include "ARMGenInstrInfo.inc" + namespace llvm { class ARMSubtarget; class ARMBaseRegisterInfo; @@ -36,24 +39,16 @@ namespace ARMII { // This four-bit field describes the addressing mode used. AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h - // Size* - Flags to keep track of the size of an instruction. - SizeShift = 5, - SizeMask = 7 << SizeShift, - SizeSpecial = 1, // 0 byte pseudo or special case. - Size8Bytes = 2, - Size4Bytes = 3, - Size2Bytes = 4, - // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load // and store ops only. Generic "updating" flag is used for ld/st multiple. // The index mode enums are declared in ARMBaseInfo.h - IndexModeShift = 8, + IndexModeShift = 5, IndexModeMask = 3 << IndexModeShift, //===------------------------------------------------------------------===// // Instruction encoding formats. // - FormShift = 10, + FormShift = 7, FormMask = 0x3f << FormShift, // Pseudo instructions @@ -126,15 +121,15 @@ namespace ARMII { // UnaryDP - Indicates this is a unary data processing instruction, i.e. // it doesn't have a Rn operand. - UnaryDP = 1 << 16, + UnaryDP = 1 << 13, // Xform16Bit - Indicates this Thumb2 instruction may be transformed into // a 16-bit Thumb instruction if certain conditions are met. - Xform16Bit = 1 << 17, + Xform16Bit = 1 << 14, //===------------------------------------------------------------------===// // Code domain. - DomainShift = 18, + DomainShift = 15, DomainMask = 7 << DomainShift, DomainGeneral = 0 << DomainShift, DomainVFP = 1 << DomainShift, @@ -172,7 +167,7 @@ namespace ARMII { }; } -class ARMBaseInstrInfo : public TargetInstrInfoImpl { +class ARMBaseInstrInfo : public ARMGenInstrInfo { const ARMSubtarget &Subtarget; protected: @@ -291,8 +286,8 @@ public: int64_t &Offset1, int64_t &Offset2)const; /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to - /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should - /// be scheduled togther. On some targets if two loads are loading from + /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads + /// should be scheduled togther. On some targets if two loads are loading from /// addresses in the same cache line, it's better if they are scheduled /// together. This function takes two integers that represent the load offsets /// from the common base address. It returns true if it decides it's desirable @@ -308,18 +303,18 @@ public: virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, - float Prob, float Confidence) const; + const BranchProbability &Probability) const; virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, - float Probability, float Confidence) const; + const BranchProbability &Probability) const; virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, - float Probability, - float Confidence) const { + const BranchProbability + &Probability) const { return NumCycles == 1; } @@ -353,25 +348,25 @@ public: SDNode *UseNode, unsigned UseIdx) const; private: int getVLDMDefCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const; int getLDMDefCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const; int getVSTMUseCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const; int getSTMUseCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const; int getOperandLatency(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const; int getInstrLatency(const InstrItineraryData *ItinData, |
