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-rw-r--r--contrib/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h65
1 files changed, 64 insertions, 1 deletions
diff --git a/contrib/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/contrib/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 9a1ca61..ce970b0 100644
--- a/contrib/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/contrib/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -289,6 +289,7 @@ namespace A64SE {
enum ShiftExtSpecifiers {
Invalid = -1,
LSL,
+ MSL,
LSR,
ASR,
ROR,
@@ -305,6 +306,65 @@ namespace A64SE {
};
}
+namespace A64Layout {
+ enum VectorLayout {
+ Invalid = -1,
+ VL_8B,
+ VL_4H,
+ VL_2S,
+ VL_1D,
+
+ VL_16B,
+ VL_8H,
+ VL_4S,
+ VL_2D,
+
+ // Bare layout for the 128-bit vector
+ // (only show ".b", ".h", ".s", ".d" without vector number)
+ VL_B,
+ VL_H,
+ VL_S,
+ VL_D
+ };
+}
+
+inline static const char *
+A64VectorLayoutToString(A64Layout::VectorLayout Layout) {
+ switch (Layout) {
+ case A64Layout::VL_8B: return ".8b";
+ case A64Layout::VL_4H: return ".4h";
+ case A64Layout::VL_2S: return ".2s";
+ case A64Layout::VL_1D: return ".1d";
+ case A64Layout::VL_16B: return ".16b";
+ case A64Layout::VL_8H: return ".8h";
+ case A64Layout::VL_4S: return ".4s";
+ case A64Layout::VL_2D: return ".2d";
+ case A64Layout::VL_B: return ".b";
+ case A64Layout::VL_H: return ".h";
+ case A64Layout::VL_S: return ".s";
+ case A64Layout::VL_D: return ".d";
+ default: llvm_unreachable("Unknown Vector Layout");
+ }
+}
+
+inline static A64Layout::VectorLayout
+A64StringToVectorLayout(StringRef LayoutStr) {
+ return StringSwitch<A64Layout::VectorLayout>(LayoutStr)
+ .Case(".8b", A64Layout::VL_8B)
+ .Case(".4h", A64Layout::VL_4H)
+ .Case(".2s", A64Layout::VL_2S)
+ .Case(".1d", A64Layout::VL_1D)
+ .Case(".16b", A64Layout::VL_16B)
+ .Case(".8h", A64Layout::VL_8H)
+ .Case(".4s", A64Layout::VL_4S)
+ .Case(".2d", A64Layout::VL_2D)
+ .Case(".b", A64Layout::VL_B)
+ .Case(".h", A64Layout::VL_H)
+ .Case(".s", A64Layout::VL_S)
+ .Case(".d", A64Layout::VL_D)
+ .Default(A64Layout::Invalid);
+}
+
namespace A64SysReg {
enum SysRegROValues {
MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
@@ -1068,7 +1128,10 @@ namespace A64Imms {
// MOVN but *not* with a MOVZ (because that would take priority).
bool isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
-}
+ uint64_t decodeNeonModImm(unsigned Val, unsigned OpCmode, unsigned &EltBits);
+ bool decodeNeonModShiftImm(unsigned OpCmode, unsigned &ShiftImm,
+ unsigned &ShiftOnesIn);
+ }
} // end namespace llvm;
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