diff options
Diffstat (limited to 'contrib/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 67 |
1 files changed, 22 insertions, 45 deletions
diff --git a/contrib/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/contrib/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 6de27d6..878e29c 100644 --- a/contrib/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/contrib/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -15,12 +15,11 @@ #include "AArch64Subtarget.h" #include "MCTargetDesc/AArch64AddressingModes.h" #include "Utils/AArch64BaseInfo.h" -#include "llvm/MC/MCInst.h" #include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" #include "llvm/Support/Debug.h" -#include "llvm/Support/MemoryObject.h" -#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -200,26 +199,24 @@ static MCDisassembler *createAArch64Disassembler(const Target &T, } DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &os, - raw_ostream &cs) const { - CommentStream = &cs; - - uint8_t bytes[4]; + ArrayRef<uint8_t> Bytes, + uint64_t Address, + raw_ostream &OS, + raw_ostream &CS) const { + CommentStream = &CS; Size = 0; // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1) + if (Bytes.size() < 4) return Fail; Size = 4; // Encoded as a small-endian 32-bit word in the stream. - uint32_t insn = - (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0); + uint32_t Insn = + (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); // Calling the auto-generated decoder function. - return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); + return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); } static MCSymbolizer * @@ -243,13 +240,9 @@ extern "C" void LLVMInitializeAArch64Disassembler() { TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget, createAArch64ExternalSymbolizer); - TargetRegistry::RegisterMCDisassembler(TheARM64leTarget, - createAArch64Disassembler); - TargetRegistry::RegisterMCDisassembler(TheARM64beTarget, + TargetRegistry::RegisterMCDisassembler(TheARM64Target, createAArch64Disassembler); - TargetRegistry::RegisterMCSymbolizer(TheARM64leTarget, - createAArch64ExternalSymbolizer); - TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget, + TargetRegistry::RegisterMCSymbolizer(TheARM64Target, createAArch64ExternalSymbolizer); } @@ -592,7 +585,7 @@ static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { // scale{5} is asserted as 1 in tblgen. - Imm |= 0x20; + Imm |= 0x20; Inst.addOperand(MCOperand::CreateImm(64 - Imm)); return Success; } @@ -614,7 +607,7 @@ static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, if (ImmVal & (1 << (19 - 1))) ImmVal |= ~((1LL << 19) - 1); - if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal << 2, Addr, + if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 4)) Inst.addOperand(MCOperand::CreateImm(ImmVal)); return Success; @@ -630,35 +623,19 @@ static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) { - const AArch64Disassembler *Dis = - static_cast<const AArch64Disassembler *>(Decoder); - const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); - - Imm |= 0x8000; Inst.addOperand(MCOperand::CreateImm(Imm)); - bool ValidNamed; - (void)AArch64SysReg::MRSMapper(STI.getFeatureBits()) - .toString(Imm, ValidNamed); - - return ValidNamed ? Success : Fail; + // Every system register in the encoding space is valid with the syntax + // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. + return Success; } static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) { - const AArch64Disassembler *Dis = - static_cast<const AArch64Disassembler *>(Decoder); - const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); - - Imm |= 0x8000; Inst.addOperand(MCOperand::CreateImm(Imm)); - bool ValidNamed; - (void)AArch64SysReg::MSRMapper(STI.getFeatureBits()) - .toString(Imm, ValidNamed); - - return ValidNamed ? Success : Fail; + return Success; } static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, @@ -1510,7 +1487,7 @@ static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, if (imm & (1 << (26 - 1))) imm |= ~((1LL << 26) - 1); - if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4)) + if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) Inst.addOperand(MCOperand::CreateImm(imm)); return Success; @@ -1530,7 +1507,7 @@ static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, bool ValidNamed; (void)AArch64PState::PStateMapper().toString(pstate_field, ValidNamed); - + return ValidNamed ? Success : Fail; } @@ -1552,7 +1529,7 @@ static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, else DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); Inst.addOperand(MCOperand::CreateImm(bit)); - if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) + if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) Inst.addOperand(MCOperand::CreateImm(dst)); return Success; |
