diff options
Diffstat (limited to 'contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 178 |
1 files changed, 99 insertions, 79 deletions
diff --git a/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index e7722b3..fbf6512 100644 --- a/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -102,7 +102,8 @@ TargetLowering::makeLibCall(SelectionDAG &DAG, } if (LC == RTLIB::UNKNOWN_LIBCALL) report_fatal_error("Unsupported library call operation!"); - SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy()); + SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), + getPointerTy(DAG.getDataLayout())); Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); TargetLowering::CallLoweringInfo CLI(DAG); @@ -206,14 +207,16 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, NewRHS = DAG.getConstant(0, dl, RetVT); CCCode = getCmpLibcallCC(LC1); if (LC2 != RTLIB::UNKNOWN_LIBCALL) { - SDValue Tmp = DAG.getNode(ISD::SETCC, dl, - getSetCCResultType(*DAG.getContext(), RetVT), - NewLHS, NewRHS, DAG.getCondCode(CCCode)); + SDValue Tmp = DAG.getNode( + ISD::SETCC, dl, + getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), + NewLHS, NewRHS, DAG.getCondCode(CCCode)); NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/, dl).first; - NewLHS = DAG.getNode(ISD::SETCC, dl, - getSetCCResultType(*DAG.getContext(), RetVT), NewLHS, - NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); + NewLHS = DAG.getNode( + ISD::SETCC, dl, + getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), + NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); NewRHS = SDValue(); } @@ -242,7 +245,7 @@ SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) - return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0)); + return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout())); return Table; } @@ -265,9 +268,7 @@ TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { // In dynamic-no-pic mode, assume that known defined values are safe. if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && - GA && - !GA->getGlobal()->isDeclaration() && - !GA->getGlobal()->isWeakForLinker()) + GA && GA->getGlobal()->isStrongDefinitionForLinker()) return true; // Otherwise assume nothing is safe. @@ -383,6 +384,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, "Mask size mismatches value type size!"); APInt NewMask = DemandedMask; SDLoc dl(Op); + auto &DL = TLO.DAG.getDataLayout(); // Don't know anything. KnownZero = KnownOne = APInt(BitWidth, 0); @@ -645,7 +647,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, unsigned InnerBits = InnerVT.getSizeInBits(); if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && isTypeDesirableForOp(ISD::SHL, InnerVT)) { - EVT ShTy = getShiftAmountTy(InnerVT); + EVT ShTy = getShiftAmountTy(InnerVT, DL); if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) ShTy = InnerVT; SDValue NarrowShl = @@ -824,7 +826,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, // for scalar types after legalization. EVT ShiftAmtTy = Op.getValueType(); if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) - ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); + ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL); SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl, ShiftAmtTy); @@ -1009,8 +1011,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, SDValue Shift = In.getOperand(1); if (TLO.LegalTypes()) { uint64_t ShVal = ShAmt->getZExtValue(); - Shift = - TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(Op.getValueType())); + Shift = TLO.DAG.getConstant(ShVal, dl, + getShiftAmountTy(Op.getValueType(), DL)); } APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, @@ -1400,7 +1402,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, APInt newMask = APInt::getLowBitsSet(maskWidth, width); for (unsigned offset=0; offset<origWidth/width; offset++) { if ((newMask & Mask) == Mask) { - if (!getDataLayout()->isLittleEndian()) + if (!DAG.getDataLayout().isLittleEndian()) bestOffset = (origWidth/width - offset - 1) * (width/8); else bestOffset = (uint64_t)offset * (width/8); @@ -1473,7 +1475,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, if (DCI.isBeforeLegalizeOps() || (isOperationLegal(ISD::SETCC, newVT) && getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) { - EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT); + EVT NewSetCCVT = + getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT); SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT); SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), @@ -1692,11 +1695,13 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && (VT == N0.getValueType() || (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && - N0.getOpcode() == ISD::AND) + N0.getOpcode() == ISD::AND) { + auto &DL = DAG.getDataLayout(); if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { - EVT ShiftTy = DCI.isBeforeLegalize() ? - getPointerTy() : getShiftAmountTy(N0.getValueType()); + EVT ShiftTy = DCI.isBeforeLegalize() + ? getPointerTy(DL) + : getShiftAmountTy(N0.getValueType(), DL); if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 // Perform the xform if the AND RHS is a single bit. if (AndRHS->getAPIntValue().isPowerOf2()) { @@ -1716,6 +1721,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, } } } + } if (C1.getMinSignedBits() <= 64 && !isLegalICmpImmediate(C1.getSExtValue())) { @@ -1727,8 +1733,10 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, const APInt &AndRHSC = AndRHS->getAPIntValue(); if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { unsigned ShiftBits = AndRHSC.countTrailingZeros(); - EVT ShiftTy = DCI.isBeforeLegalize() ? - getPointerTy() : getShiftAmountTy(N0.getValueType()); + auto &DL = DAG.getDataLayout(); + EVT ShiftTy = DCI.isBeforeLegalize() + ? getPointerTy(DL) + : getShiftAmountTy(N0.getValueType(), DL); EVT CmpTy = N0.getValueType(); SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), DAG.getConstant(ShiftBits, dl, @@ -1757,8 +1765,10 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, NewC = NewC.lshr(ShiftBits); if (ShiftBits && NewC.getMinSignedBits() <= 64 && isLegalICmpImmediate(NewC.getSExtValue())) { - EVT ShiftTy = DCI.isBeforeLegalize() ? - getPointerTy() : getShiftAmountTy(N0.getValueType()); + auto &DL = DAG.getDataLayout(); + EVT ShiftTy = DCI.isBeforeLegalize() + ? getPointerTy(DL) + : getShiftAmountTy(N0.getValueType(), DL); EVT CmpTy = N0.getValueType(); SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, DAG.getConstant(ShiftBits, dl, ShiftTy)); @@ -1945,10 +1955,12 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, Cond); if (N0.getNode()->hasOneUse()) { assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); + auto &DL = DAG.getDataLayout(); // (Z-X) == X --> Z == X<<1 - SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, - DAG.getConstant(1, dl, - getShiftAmountTy(N1.getValueType()))); + SDValue SH = DAG.getNode( + ISD::SHL, dl, N1.getValueType(), N1, + DAG.getConstant(1, dl, + getShiftAmountTy(N1.getValueType(), DL))); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(SH.getNode()); return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); @@ -1969,10 +1981,11 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, DAG.getConstant(0, dl, N1.getValueType()), Cond); if (N1.getNode()->hasOneUse()) { assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); + auto &DL = DAG.getDataLayout(); // X == (Z-X) --> X<<1 == Z - SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, - DAG.getConstant(1, dl, - getShiftAmountTy(N0.getValueType()))); + SDValue SH = DAG.getNode( + ISD::SHL, dl, N1.getValueType(), N0, + DAG.getConstant(1, dl, getShiftAmountTy(N0.getValueType(), DL))); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(SH.getNode()); return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); @@ -2105,9 +2118,8 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { // Inline Assembler Implementation Methods //===----------------------------------------------------------------------===// - TargetLowering::ConstraintType -TargetLowering::getConstraintType(const std::string &Constraint) const { +TargetLowering::getConstraintType(StringRef Constraint) const { unsigned S = Constraint.size(); if (S == 1) { @@ -2140,7 +2152,7 @@ TargetLowering::getConstraintType(const std::string &Constraint) const { } if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { - if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}" + if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}" return C_Memory; return C_Register; } @@ -2206,8 +2218,8 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), C ? SDLoc(C) : SDLoc(), Op.getValueType(), Offs)); - return; } + return; } if (C) { // just C, no GV. // Simple constants are not allowed for 's'. @@ -2217,8 +2229,8 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, // ScheduleDAGSDNodes::EmitNode, which is very generic. Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), SDLoc(C), MVT::i64)); - return; } + return; } break; } @@ -2227,7 +2239,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::pair<unsigned, const TargetRegisterClass *> TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI, - const std::string &Constraint, + StringRef Constraint, MVT VT) const { if (Constraint.empty() || Constraint[0] != '{') return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr)); @@ -2293,7 +2305,8 @@ unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { /// If this returns an empty vector, and if the constraint string itself /// isn't empty, there was an error parsing. TargetLowering::AsmOperandInfoVector -TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI, +TargetLowering::ParseConstraints(const DataLayout &DL, + const TargetRegisterInfo *TRI, ImmutableCallSite CS) const { /// ConstraintOperands - Information about all of the constraints. AsmOperandInfoVector ConstraintOperands; @@ -2329,10 +2342,11 @@ TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI, assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); if (StructType *STy = dyn_cast<StructType>(CS.getType())) { - OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo)); + OpInfo.ConstraintVT = + getSimpleValueType(DL, STy->getElementType(ResNo)); } else { assert(ResNo == 0 && "Asm only has one result!"); - OpInfo.ConstraintVT = getSimpleValueType(CS.getType()); + OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType()); } ++ResNo; break; @@ -2361,7 +2375,7 @@ TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI, // If OpTy is not a single value, it may be a struct/union that we // can tile with integers. if (!OpTy->isSingleValueType() && OpTy->isSized()) { - unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy); + unsigned BitSize = DL.getTypeSizeInBits(OpTy); switch (BitSize) { default: break; case 1: @@ -2375,8 +2389,7 @@ TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI, break; } } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { - unsigned PtrSize - = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace()); + unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace()); OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); } else { OpInfo.ConstraintVT = MVT::getVT(OpTy, true); @@ -2684,7 +2697,8 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d, if (ShAmt) { // TODO: For UDIV use SRL instead of SRA. SDValue Amt = - DAG.getConstant(ShAmt, dl, TLI.getShiftAmountTy(Op1.getValueType())); + DAG.getConstant(ShAmt, dl, TLI.getShiftAmountTy(Op1.getValueType(), + DAG.getDataLayout())); SDNodeFlags Flags; Flags.setExact(true); Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags); @@ -2750,17 +2764,19 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor, Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); Created->push_back(Q.getNode()); } + auto &DL = DAG.getDataLayout(); // Shift right algebraic if shift value is nonzero if (magics.s > 0) { - Q = DAG.getNode(ISD::SRA, dl, VT, Q, - DAG.getConstant(magics.s, dl, - getShiftAmountTy(Q.getValueType()))); + Q = DAG.getNode( + ISD::SRA, dl, VT, Q, + DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL))); Created->push_back(Q.getNode()); } // Extract the sign bit and add it to the quotient - SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, - DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, - getShiftAmountTy(Q.getValueType()))); + SDValue T = + DAG.getNode(ISD::SRL, dl, VT, Q, + DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, + getShiftAmountTy(Q.getValueType(), DL))); Created->push_back(T.getNode()); return DAG.getNode(ISD::ADD, dl, VT, Q, T); } @@ -2776,6 +2792,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor, EVT VT = N->getValueType(0); SDLoc dl(N); + auto &DL = DAG.getDataLayout(); // Check to see if we can do this. // FIXME: We should be more aggressive here. @@ -2792,9 +2809,9 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor, // the divided value upfront. if (magics.a != 0 && !Divisor[0]) { unsigned Shift = Divisor.countTrailingZeros(); - Q = DAG.getNode(ISD::SRL, dl, VT, Q, - DAG.getConstant(Shift, dl, - getShiftAmountTy(Q.getValueType()))); + Q = DAG.getNode( + ISD::SRL, dl, VT, Q, + DAG.getConstant(Shift, dl, getShiftAmountTy(Q.getValueType(), DL))); Created->push_back(Q.getNode()); // Get magic number for the shifted divisor. @@ -2819,21 +2836,22 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor, if (magics.a == 0) { assert(magics.s < Divisor.getBitWidth() && "We shouldn't generate an undefined shift!"); - return DAG.getNode(ISD::SRL, dl, VT, Q, - DAG.getConstant(magics.s, dl, - getShiftAmountTy(Q.getValueType()))); + return DAG.getNode( + ISD::SRL, dl, VT, Q, + DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL))); } else { SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); Created->push_back(NPQ.getNode()); - NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, - DAG.getConstant(1, dl, - getShiftAmountTy(NPQ.getValueType()))); + NPQ = DAG.getNode( + ISD::SRL, dl, VT, NPQ, + DAG.getConstant(1, dl, getShiftAmountTy(NPQ.getValueType(), DL))); Created->push_back(NPQ.getNode()); NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); Created->push_back(NPQ.getNode()); - return DAG.getNode(ISD::SRL, dl, VT, NPQ, - DAG.getConstant(magics.s - 1, dl, - getShiftAmountTy(NPQ.getValueType()))); + return DAG.getNode( + ISD::SRL, dl, VT, NPQ, + DAG.getConstant(magics.s - 1, dl, + getShiftAmountTy(NPQ.getValueType(), DL))); } } @@ -2919,8 +2937,9 @@ bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, if (!LH.getNode() && !RH.getNode() && isOperationLegalOrCustom(ISD::SRL, VT) && isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) { + auto &DL = DAG.getDataLayout(); unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); - SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT)); + SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT, DL)); LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift); LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); @@ -2980,14 +2999,15 @@ bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result, SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); - SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT, - DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), - DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT))); + auto &DL = DAG.getDataLayout(); + SDValue ExponentBits = DAG.getNode( + ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), + DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL))); SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias); - SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT, - DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask), - DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT))); + SDValue Sign = DAG.getNode( + ISD::SRA, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask), + DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT, DL))); Sign = DAG.getSExtOrTrunc(Sign, dl, NVT); SDValue R = DAG.getNode(ISD::OR, dl, IntVT, @@ -2996,17 +3016,17 @@ bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result, R = DAG.getZExtOrTrunc(R, dl, NVT); - - R = DAG.getSelectCC(dl, Exponent, ExponentLoBit, - DAG.getNode(ISD::SHL, dl, NVT, R, - DAG.getZExtOrTrunc( - DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit), - dl, getShiftAmountTy(IntVT))), - DAG.getNode(ISD::SRL, dl, NVT, R, - DAG.getZExtOrTrunc( - DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent), - dl, getShiftAmountTy(IntVT))), - ISD::SETGT); + R = DAG.getSelectCC( + dl, Exponent, ExponentLoBit, + DAG.getNode(ISD::SHL, dl, NVT, R, + DAG.getZExtOrTrunc( + DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit), + dl, getShiftAmountTy(IntVT, DL))), + DAG.getNode(ISD::SRL, dl, NVT, R, + DAG.getZExtOrTrunc( + DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent), + dl, getShiftAmountTy(IntVT, DL))), + ISD::SETGT); SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT, DAG.getNode(ISD::XOR, dl, NVT, R, Sign), |
