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Diffstat (limited to 'contrib/gcc/md.texi')
| -rw-r--r-- | contrib/gcc/md.texi | 329 |
1 files changed, 263 insertions, 66 deletions
diff --git a/contrib/gcc/md.texi b/contrib/gcc/md.texi index 6fcf419..e9d810c 100644 --- a/contrib/gcc/md.texi +++ b/contrib/gcc/md.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988, 1989, 1992, 1993, 1994 Free Software Foundation, Inc. +@c Copyright (C) 1988, 89, 92, 93, 94, 96, 1998 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -174,7 +174,9 @@ Operand numbers must be chosen consecutively counting from zero in each instruction pattern. There may be only one @code{match_operand} expression in the pattern for each operand number. Usually operands are numbered in the order of appearance in @code{match_operand} -expressions. +expressions. In the case of a @code{define_expand}, any operand numbers +used only in @code{match_dup} expressions have higher values than all +other operand numbers. @var{predicate} is a string that is the name of a C function that accepts two arguments, an expression and a machine mode. During matching, the @@ -399,6 +401,25 @@ An insn that matches this pattern might look like: Like @code{match_op_dup}, but for @code{match_parallel} instead of @code{match_operator}. +@findex match_insn +@item (match_insn @var{predicate}) +Match a complete insn. Unlike the other @code{match_*} recognizers, +@code{match_insn} does not take an operand number. + +The machine mode @var{m} of @code{match_insn} works like that of +@code{match_operand}: it is passed as the second argument to the +predicate function, and that function is solely responsible for +deciding whether the expression to be matched ``has'' that mode. + +@findex match_insn2 +@item (match_insn2 @var{n} @var{predicate}) +Match a complete insn. + +The machine mode @var{m} of @code{match_insn2} works like that of +@code{match_operand}: it is passed as the second argument to the +predicate function, and that function is solely responsible for +deciding whether the expression to be matched ``has'' that mode. + @findex address @item (address (match_operand:@var{m} @var{n} "address_operand" "")) This complex of expressions is a placeholder for an operand number @@ -507,8 +528,8 @@ already defined, then you can simply use @code{#} as the output template instead of writing an output template that emits the multiple assembler instructions. -If @code{ASSEMBLER_DIALECT} is defined, you can use -@samp{@{option0|option1|option2@}} constructs in the templates. These +If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct +of the form @samp{@{option0|option1|option2@}} in the templates. These describe multiple variants of assembler language syntax. @xref{Instruction Output}. @@ -621,7 +642,7 @@ as follows, having the output control string start with a @samp{@@}: @cindex constraints Each @code{match_operand} in an instruction pattern can specify a -constraint for the type of operands allowed. +constraint for the type of operands allowed. @end ifset @ifclear INTERNALS @node Constraints @@ -794,7 +815,7 @@ registers that are not general registers. @ifset INTERNALS Any operand whatsoever is allowed, even if it does not satisfy @code{general_operand}. This is normally used in the constraint of -a @code{match_scratch} when certain alternatives will not actually +a @code{match_scratch} when certain alternatives will not actually require a scratch register. @end ifset @ifclear INTERNALS @@ -818,7 +839,7 @@ input operands and one output operand in the RTL, but on most CISC @end ifset @ifclear INTERNALS which @code{asm} distinguishes. For example, an add instruction uses -two input operands and an output operand, but on most CISC +two input operands and an output operand, but on most CISC @end ifclear machines an add instruction really has only two operands, one of them an input-output operand: @@ -992,6 +1013,15 @@ If the operand's predicate can recognize registers, but the constraint does not permit them, it can make the compiler crash. When this operand happens to be a register, the reload pass will be stymied, because it does not know how to copy a register temporarily into memory. + +If the predicate accepts a unary operator, the constraint applies to the +operand. For example, the MIPS processor at ISA level 3 supports an +instruction which adds two registers in @code{SImode} to produce a +@code{DImode} result, but only if the registers are correctly sign +extended. This predicate for the input operands accepts a +@code{sign_extend} of an @code{SImode} register. Write the constraint +to indicate the type of register that is required for the operand of the +@code{sign_extend}. @end ifset @node Multi-Alternative @@ -1108,17 +1138,25 @@ identifies an operand that is both input and output; all other operands are assumed to be input only. @cindex @samp{&} in constraint +@cindex earlyclobber operand @item & -Means (in a particular alternative) that this operand is written -before the instruction is finished using the input operands. -Therefore, this operand may not lie in a register that is used as an -input operand or as part of any memory address. +Means (in a particular alternative) that this operand is an +@dfn{earlyclobber} operand, which is modified before the instruction is +finished using the input operands. Therefore, this operand may not lie +in a register that is used as an input operand or as part of any memory +address. @samp{&} applies only to the alternative in which it is written. In constraints with multiple alternatives, sometimes one alternative requires @samp{&} while others do not. See, for example, the @samp{movdf} insn of the 68000. +An input operand can be tied to an earlyclobber operand if its only +use as an input occurs before the early result is written. Adding +alternatives of this form often allows GCC to produce better code +when only some of the inputs can be affected by the earlyclobber. +See, for example, the @samp{mulsi3} insn of the ARM. + @samp{&} does not obviate the need to write @samp{=}. @cindex @samp{%} in constraint @@ -1249,7 +1287,7 @@ Integer that satisfies constraint @samp{I} when negated (twos complement) Integer in the range 0 to 32 @item Q -A memory reference where the exact address is in a single register +A memory reference where the exact address is in a single register (`@samp{m}' is preferable for @code{asm} statements) @item R @@ -1370,6 +1408,18 @@ instruction per word @item Q Memory operand that is an offset from a register (@samp{m} is preferable for @code{asm} statements) + +@item R +AIX TOC entry + +@item S +Windows NT SYMBOL_REF + +@item T +Windows NT LABEL_REF + +@item U +System V Release 4 small data area reference @end table @item Intel 386---@file{i386.h} @@ -1552,6 +1602,9 @@ Signed number whose magnitude is greater than 0x80 @item L Integer in the range -8 to -1 +@item M +Signed number whose magnitude is greater than 0x100 + @item G Floating point constant that is not a 68881 constant @@ -1563,7 +1616,10 @@ Floating point constant that can be used by Sun FPA @item SPARC---@file{sparc.h} @table @code @item f -Floating-point register +Floating-point register that can hold 32 or 64 bit values. + +@item e +Floating-point register that can hold 64 or 128 bit values. @item I Signed 13 bit constant @@ -1591,7 +1647,7 @@ Constant, or memory address @item T Memory address aligned to an 8-byte boundary -@item U +@item U Even register @end table @end table @@ -1632,7 +1688,7 @@ now in existence use constraints. Here is a table of the instruction names that are meaningful in the RTL generation pass of the compiler. Giving one of these names to an instruction pattern tells the RTL generation pass that it can use the -pattern in to accomplish a certain task. +pattern to accomplish a certain task. @table @asis @cindex @code{mov@var{m}} instruction pattern @@ -1698,23 +1754,23 @@ scratch registers after reload, you must define patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle them. @xref{Register Classes}. -The constraints on a @samp{move@var{m}} must permit moving any hard +The constraints on a @samp{mov@var{m}} must permit moving any hard register to any other hard register provided that @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2. -It is obligatory to support floating point @samp{move@var{m}} +It is obligatory to support floating point @samp{mov@var{m}} instructions into and out of any registers that can hold fixed point values, because unions and structures (which have modes @code{SImode} or @code{DImode}) can be in those registers and they may have floating point members. -There may also be a need to support fixed point @samp{move@var{m}} +There may also be a need to support fixed point @samp{mov@var{m}} instructions in and out of floating point registers. Unfortunately, I have forgotten why this was so, and I don't know whether it is still true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in floating point registers, then the constraints of the fixed point -@samp{move@var{m}} instructions must be designed to avoid ever trying to +@samp{mov@var{m}} instructions must be designed to avoid ever trying to reload into a floating point register. @cindex @code{reload_in} instruction pattern @@ -1776,8 +1832,8 @@ means of constraints requiring operands 1 and 0 to be the same location. @cindex @code{udiv@var{m}3} instruction pattern @cindex @code{mod@var{m}3} instruction pattern @cindex @code{umod@var{m}3} instruction pattern -@cindex @code{min@var{m}3} instruction pattern -@cindex @code{max@var{m}3} instruction pattern +@cindex @code{smin@var{m}3} instruction pattern +@cindex @code{smax@var{m}3} instruction pattern @cindex @code{umin@var{m}3} instruction pattern @cindex @code{umax@var{m}3} instruction pattern @cindex @code{and@var{m}3} instruction pattern @@ -1912,16 +1968,43 @@ The @samp{cmp@var{m}} patterns should be used instead. @item @samp{movstr@var{m}} Block move instruction. The addresses of the destination and source strings are the first two operands, and both are in mode @code{Pmode}. + The number of bytes to move is the third operand, in mode @var{m}. +Usually, you specify @code{word_mode} for @var{m}. However, if you can +generate better code knowing the range of valid lengths is smaller than +those representable in a full word, you should provide a pattern with a +mode corresponding to the range of values you can handle efficiently +(e.g., @code{QImode} for values in the range 0--127; note we avoid numbers +that appear negative) and also a pattern with @code{word_mode}. The fourth operand is the known shared alignment of the source and destination, in the form of a @code{const_int} rtx. Thus, if the compiler knows that both source and destination are word-aligned, it may provide the value 4 for this operand. +Descriptions of multiple @code{movstr@var{m}} patterns can only be +beneficial if the patterns for smaller modes have fewer restrictions +on their first, second and fourth operands. Note that the mode @var{m} +in @code{movstr@var{m}} does not impose any restriction on the mode of +individually moved data units in the block. + These patterns need not give special consideration to the possibility that the source and destination strings might overlap. +@cindex @code{clrstr@var{m}} instruction pattern +@item @samp{clrstr@var{m}} +Block clear instruction. The addresses of the destination string is the +first operand, in mode @code{Pmode}. The number of bytes to clear is +the second operand, in mode @var{m}. See @samp{movstr@var{m}} for +a discussion of the choice of mode. + +The third operand is the known alignment of the destination, in the form +of a @code{const_int} rtx. Thus, if the compiler knows that the +destination is word-aligned, it may provide the value 4 for this +operand. + +The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}. + @cindex @code{cmpstr@var{m}} instruction pattern @item @samp{cmpstr@var{m}} Block compare instruction, with five operands. Operand 0 is the output; @@ -1932,6 +2015,7 @@ to store a value in operand 0 whose sign indicates the result of the comparison. @cindex @code{strlen@var{m}} instruction pattern +@item @samp{strlen@var{m}} Compute the length of a string, with three operands. Operand 0 is the result (of mode @var{m}), operand 1 is a @code{mem} referring to the first character of the string, @@ -1981,20 +2065,20 @@ of mode @var{m} by converting the value to an integer. Like @samp{fixuns@var{m}@var{n}2} but works for any floating point value of mode @var{m} by converting the value to an integer. -@cindex @code{trunc@var{mn}} instruction pattern -@item @samp{trunc@var{m}@var{n}} +@cindex @code{trunc@var{mn}2} instruction pattern +@item @samp{trunc@var{m}@var{n}2} Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and store in operand 0 (which has mode @var{n}). Both modes must be fixed point or both floating point. -@cindex @code{extend@var{mn}} instruction pattern -@item @samp{extend@var{m}@var{n}} +@cindex @code{extend@var{mn}2} instruction pattern +@item @samp{extend@var{m}@var{n}2} Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and store in operand 0 (which has mode @var{n}). Both modes must be fixed point or both floating point. -@cindex @code{zero_extend@var{mn}} instruction pattern -@item @samp{zero_extend@var{m}@var{n}} +@cindex @code{zero_extend@var{mn}2} instruction pattern +@item @samp{zero_extend@var{m}@var{n}2} Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and store in operand 0 (which has mode @var{n}). Both modes must be fixed point. @@ -2091,7 +2175,7 @@ pattern or a @samp{tst@var{m}} pattern. Machines that use a pseudo register for the condition code value, or where the mode used for the comparison depends on the condition being -tested, should also use the above mechanism. @xref{Jump Patterns} +tested, should also use the above mechanism. @xref{Jump Patterns}. The above discussion also applies to the @samp{mov@var{mode}cc} and @samp{s@var{cond}} patterns. @@ -2100,8 +2184,8 @@ The above discussion also applies to the @samp{mov@var{mode}cc} and @item @samp{call} Subroutine call instruction returning no value. Operand 0 is the function to call; operand 1 is the number of bytes of arguments pushed -(in mode @code{SImode}, except it is normally a @code{const_int}); -operand 2 is the number of registers used as operands. +as a @code{const_int}; operand 2 is the number of registers used as +operands. On most machines, operand 2 is not actually stored into the RTL pattern. It is supplied for the sake of some RISC machines which need @@ -2254,9 +2338,9 @@ is no @samp{casesi} pattern. This pattern requires two operands: the address or offset, and a label which should immediately precede the jump table. If the macro -@code{CASE_VECTOR_PC_RELATIVE} is defined then the first operand is an -offset which counts from the address of the table; otherwise, it is an -absolute address to jump to. In either case, the first operand has +@code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first +operand is an offset which counts from the address of the table; otherwise, +it is an absolute address to jump to. In either case, the first operand has mode @code{Pmode}. The @samp{tablejump} insn is always the last insn before the jump @@ -2264,6 +2348,23 @@ table it uses. Its assembler code normally has no need to use the second operand, but you should incorporate it in the RTL pattern so that the jump optimizer will not delete the table as unreachable code. +@cindex @code{canonicalize_funcptr_for_compare} instruction pattern +@item @samp{canonicalize_funcptr_for_compare} +Canonicalize the function pointer in operand 1 and store the result +into operand 0. + +Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 +may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc +and also has mode @code{Pmode}. + +Canonicalization of a function pointer usually involves computing +the address of the function which would be called if the function +pointer were used in an indirect call. + +Only define this pattern if function pointers on the target machine +can have different values but still call the same function when +used in an indirect call. + @cindex @code{save_stack_block} instruction pattern @cindex @code{save_stack_function} instruction pattern @cindex @code{save_stack_nonlocal} instruction pattern @@ -2311,14 +2412,15 @@ such required data. @end enumerate When saving the stack pointer, operand 0 is the save area and operand 1 -is the stack pointer. The mode used to allocate the save area is the -mode of operand 0. You must specify an integral mode, or -@code{VOIDmode} if no save area is needed for a particular type of save -(either because no save is needed or because a machine-specific save -area can be used). Operand 0 is the stack pointer and operand 1 is the -save area for restore operations. If @samp{save_stack_block} is -defined, operand 0 must not be @code{VOIDmode} since these saves can be -arbitrarily nested. +is the stack pointer. The mode used to allocate the save area defaults +to @code{Pmode} but you can override that choice by defining the +@code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must +specify an integral mode, or @code{VOIDmode} if no save area is needed +for a particular type of save (either because no save is needed or +because a machine-specific save area can be used). Operand 0 is the +stack pointer and operand 1 is the save area for restore operations. If +@samp{save_stack_block} is defined, operand 0 must not be +@code{VOIDmode} since these saves can be arbitrarily nested. A save area is a @code{mem} that is at a constant offset from @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by @@ -2326,13 +2428,109 @@ nonlocal gotos and a @code{reg} in the other two cases. @cindex @code{allocate_stack} instruction pattern @item @samp{allocate_stack} -Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 0 from +Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from the stack pointer to create space for dynamically allocated data. +Store the resultant pointer to this space into operand 0. If you +are allocating space from the main stack, do this by emitting a +move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. +If you are allocating the space elsewhere, generate code to copy the +location of the space to operand 0. In the latter case, you must +ensure this space gets freed when the corresponding space on the main +stack is free. + Do not define this pattern if all that must be done is the subtraction. Some machines require other operations such as stack probes or maintaining the back chain. Define this pattern to emit those operations in addition to updating the stack pointer. + +@cindex @code{probe} instruction pattern +@item @samp{probe} +Some machines require instructions to be executed after space is +allocated from the stack, for example to generate a reference at +the bottom of the stack. + +If you need to emit instructions before the stack has been adjusted, +put them into the @samp{allocate_stack} pattern. Otherwise, define +this pattern to emit the required instructions. + +No operands are provided. + +@cindex @code{check_stack} instruction pattern +@item @samp{check_stack} +If stack checking cannot be done on your system by probing the stack with +a load or store instruction (@pxref{Stack Checking}), define this pattern +to perform the needed check and signaling an error if the stack +has overflowed. The single operand is the location in the stack furthest +from the current stack pointer that you need to validate. Normally, +on machines where this pattern is needed, you would obtain the stack +limit from a global or thread-specific variable or register. + +@cindex @code{nonlocal_goto} instruction pattern +@item @samp{nonlocal_goto} +Emit code to generate a non-local goto, e.g., a jump from one function +to a label in an outer function. This pattern has four arguments, +each representing a value to be used in the jump. The first +argument is to be loaded into the frame pointer, the second is +the address to branch to (code to dispatch to the actual label), +the third is the address of a location where the stack is saved, +and the last is the address of the label, to be placed in the +location for the incoming static chain. + +On most machines you need not define this pattern, since GNU CC will +already generate the correct code, which is to load the frame pointer +and static chain, restore the stack (using the +@samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly +to the dispatcher. You need only define this pattern if this code will +not work on your machine. + +@cindex @code{nonlocal_goto_receiver} instruction pattern +@item @samp{nonlocal_goto_receiver} +This pattern, if defined, contains code needed at the target of a +nonlocal goto after the code already generated by GNU CC. You will not +normally need to define this pattern. A typical reason why you might +need this pattern is if some value, such as a pointer to a global table, +must be restored when the frame pointer is restored. Note that a nonlocal +goto only ocurrs within a unit-of-translation, so a global table pointer +that is shared by all functions of a given module need not be restored. +There are no arguments. + +@cindex @code{exception_receiver} instruction pattern +@item @samp{exception_receiver} +This pattern, if defined, contains code needed at the site of an +exception handler that isn't needed at the site of a nonlocal goto. You +will not normally need to define this pattern. A typical reason why you +might need this pattern is if some value, such as a pointer to a global +table, must be restored after control flow is branched to the handler of +an exception. There are no arguments. + +@cindex @code{builtin_setjmp_setup} instruction pattern +@item @samp{builtin_setjmp_setup} +This pattern, if defined, contains additional code needed to initialize +the @code{jmp_buf}. You will not normally need to define this pattern. +A typical reason why you might need this pattern is if some value, such +as a pointer to a global table, must be restored. Though it is +preferred that the pointer value be recalculated if possible (given the +address of a label for instance). The single argument is a pointer to +the @code{jmp_buf}. Note that the buffer is five words long and that +the first three are normally used by the generic mechanism. + +@cindex @code{builtin_setjmp_receiver} instruction pattern +@item @samp{builtin_setjmp_receiver} +This pattern, if defined, contains code needed at the site of an +builtin setjmp that isn't needed at the site of a nonlocal goto. You +will not normally need to define this pattern. A typical reason why you +might need this pattern is if some value, such as a pointer to a global +table, must be restored. It takes one argument, which is the label +to which builtin_longjmp transfered control; this pattern may be emitted +at a small offset from that label. + +@cindex @code{builtin_longjmp} instruction pattern +@item @samp{builtin_longjmp} +This pattern, if defined, performs the entire action of the longjmp. +You will not normally need to define this pattern unless you also define +@code{builtin_setjmp_setup}. The single argument is a pointer to the +@code{jmp_buf}. @end table @node Pattern Ordering @@ -2608,6 +2806,7 @@ converted into the appropriate multiplication by a power of two. @cindex @code{ior}, canonicalization of @cindex @code{and}, canonicalization of @cindex De Morgan's law +@item De`Morgan's Law is used to move bitwise negation inside a bitwise logical-and or logical-or operation. If this results in only one operand being a @code{not} expression, it will be the first one. @@ -3051,8 +3250,7 @@ on this machine. So it must be copied into a register with (match_dup 2)))] "" "operands[2] - = force_reg (SImode, gen_rtx (CONST_INT, - VOIDmode, 65535)); ") + = force_reg (SImode, GEN_INT (65535)); ") @end smallexample @strong{Note:} If the @code{define_expand} is used to serve a @@ -3183,8 +3381,8 @@ Here is an example of this use of @code{define_split}, taken from if (low & 0x8000) high++, low |= 0xffff0000; - operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); - operands[4] = gen_rtx (CONST_INT, VOIDmode, low); + operands[3] = GEN_INT (high << 16); + operands[4] = GEN_INT (low); @}") @end smallexample @@ -3209,16 +3407,16 @@ an equality comparison of a register and a large constant: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] " @{ - /* Get the constant we are comparing against, C, and see what it - looks like sign-extended to 16 bits. Then see what constant + /* Get the constant we are comparing against, C, and see what it + looks like sign-extended to 16 bits. Then see what constant could be XOR'ed with C to get the sign-extended value. */ int c = INTVAL (operands[2]); int sextc = (c << 16) >> 16; int xorv = c ^ sextc; - operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); - operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); + operands[4] = GEN_INT (xorv); + operands[5] = GEN_INT (sextc); @}") @end smallexample @@ -3320,7 +3518,7 @@ defined and the function to obtain the attribute's value will return @cindex attribute expressions RTL expressions used to define attributes use the codes described above -plus a few specific to attribute definitions, to be discussed below. +plus a few specific to attribute definitions, to be discussed below. Attribute value expressions must have one of the following forms: @table @code @@ -3485,21 +3683,21 @@ scheduled. @var{name} is a string specifying one of a fixed set of flags to test. Test the flags @code{forward} and @code{backward} to determine the -direction of a conditional branch. Test the flags @code{very_likely}, -@code{likely}, @code{very_unlikely}, and @code{unlikely} to determine +direction of a conditional branch. Test the flags @code{very_likely}, +@code{likely}, @code{very_unlikely}, and @code{unlikely} to determine if a conditional branch is expected to be taken. -If the @code{very_likely} flag is true, then the @code{likely} flag is also +If the @code{very_likely} flag is true, then the @code{likely} flag is also true. Likewise for the @code{very_unlikely} and @code{unlikely} flags. This example describes a conditional branch delay slot which -can be nullified for forward branches that are taken (annul-true) or -for backward branches which are not taken (annul-false). +can be nullified for forward branches that are taken (annul-true) or +for backward branches which are not taken (annul-false). @smallexample (define_delay (eq_attr "type" "cbranch") - [(eq_attr "in_branch_delay" "true") - (and (eq_attr "in_branch_delay" "true") + [(eq_attr "in_branch_delay" "true") + (and (eq_attr "in_branch_delay" "true") (attr_flag "forward")) (and (eq_attr "in_branch_delay" "true") (attr_flag "backward"))]) @@ -3508,12 +3706,12 @@ for backward branches which are not taken (annul-false). The @code{forward} and @code{backward} flags are false if the current @code{insn} being scheduled is not a conditional branch. -The @code{very_likely} and @code{likely} flags are true if the -@code{insn} being scheduled is not a conditional branch. The +The @code{very_likely} and @code{likely} flags are true if the +@code{insn} being scheduled is not a conditional branch. The @code{very_unlikely} and @code{unlikely} flags are false if the @code{insn} being scheduled is not a conditional branch. -@code{attr_flag} is only used during delay slot scheduling and has no +@code{attr_flag} is only used during delay slot scheduling and has no meaning to other passes of the compiler. @end table @@ -3702,7 +3900,7 @@ must be a @code{label_ref}. @item (pc) This refers to the address of the @emph{current} insn. It might have been more consistent with other usage to make this the address of the -@emph{next} insn but this would be confusing because the length of the +@emph{next} insn but this would be confusing because the length of the current insn is to be computed. @end table @@ -3713,7 +3911,7 @@ For normal insns, the length will be determined by value of the @code{addr_diff_vec} insn patterns, the length is computed as the number of vectors multiplied by the size of each vector. -Lengths are measured in addressable storage units (bytes). +Lengths are measured in addressable storage units (bytes). The following macros can be used to refine the length computation: @@ -3729,8 +3927,7 @@ not specified, 0 is used. If defined, modifies the length assigned to instruction @var{insn} as a function of the context in which it is used. @var{length} is an lvalue that contains the initially computed length of the insn and should be -updated with the correct length of the insn. If updating is required, -@var{insn} must not be a varying-length insn. +updated with the correct length of the insn. This macro will normally not be required. A case in which it is required is the ROMP. On this machine, the size of an @code{addr_vec} @@ -3813,7 +4010,7 @@ On some machines, conditional branch instructions can optionally instruction will not be executed for certain branch outcomes. Both instructions that annul if the branch is true and instructions that annul if the branch is false are supported. - + Delay slot scheduling differs from instruction scheduling in that determining whether an instruction needs a delay slot is dependent only on the type of instruction being generated, not on data flow between the |
