diff options
Diffstat (limited to 'contrib/gcc/config/sparc/sparc.md')
| -rw-r--r-- | contrib/gcc/config/sparc/sparc.md | 41 |
1 files changed, 33 insertions, 8 deletions
diff --git a/contrib/gcc/config/sparc/sparc.md b/contrib/gcc/config/sparc/sparc.md index ebe9d2b..b53013e 100644 --- a/contrib/gcc/config/sparc/sparc.md +++ b/contrib/gcc/config/sparc/sparc.md @@ -148,8 +148,12 @@ (eq_attr "branch_type" "fcc") (if_then_else (match_operand 0 "fcc0_reg_operand" "") (if_then_else (eq_attr "empty_delay_slot" "true") - (const_int 2) - (const_int 1)) + (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0)) + (const_int 3) + (const_int 2)) + (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0)) + (const_int 2) + (const_int 1))) (if_then_else (lt (pc) (match_dup 2)) (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 260000)) (if_then_else (eq_attr "empty_delay_slot" "true") @@ -6881,6 +6885,8 @@ { if (operands[2] == const1_rtx) return "add\t%1, %1, %0"; + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); return "sll\t%1, %2, %0"; } [(set (attr "type") @@ -6910,6 +6916,8 @@ { if (operands[2] == const1_rtx) return "add\t%1, %1, %0"; + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); return "sllx\t%1, %2, %0"; } [(set (attr "type") @@ -6969,7 +6977,11 @@ (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "sra\t%1, %2, %0" + { + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "sra\t%1, %2, %0"; + } [(set_attr "type" "shift")]) (define_insn "*ashrsi3_extend" @@ -7016,12 +7028,17 @@ } }) -(define_insn "" +(define_insn "*ashrdi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "srax\t%1, %2, %0" + + { + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + return "srax\t%1, %2, %0"; + } [(set_attr "type" "shift")]) ;; XXX @@ -7040,7 +7057,11 @@ (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "srl\t%1, %2, %0" + { + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "srl\t%1, %2, %0"; + } [(set_attr "type" "shift")]) ;; This handles the case where @@ -7097,12 +7118,16 @@ } }) -(define_insn "" +(define_insn "*lshrdi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "srlx\t%1, %2, %0" + { + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + return "srlx\t%1, %2, %0"; + } [(set_attr "type" "shift")]) ;; XXX |
