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-rw-r--r--sys/amd64/include/param.h4
-rw-r--r--sys/arm/include/param.h4
-rw-r--r--sys/i386/include/param.h4
-rw-r--r--sys/ia64/include/param.h4
-rw-r--r--sys/mips/include/param.h4
-rw-r--r--sys/powerpc/include/param.h4
-rw-r--r--sys/sparc64/include/param.h4
-rw-r--r--sys/sun4v/include/param.h4
8 files changed, 32 insertions, 0 deletions
diff --git a/sys/amd64/include/param.h b/sys/amd64/include/param.h
index 7cf1286..16c30ad 100644
--- a/sys/amd64/include/param.h
+++ b/sys/amd64/include/param.h
@@ -89,6 +89,10 @@
#define ALIGN(p) _ALIGN(p)
#define ALIGNED_POINTER(p,t) _ALIGNED_POINTER(p,t)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 6
#endif
diff --git a/sys/arm/include/param.h b/sys/arm/include/param.h
index 6e3ee59..4a83e27 100644
--- a/sys/arm/include/param.h
+++ b/sys/arm/include/param.h
@@ -81,6 +81,10 @@
#define ALIGNBYTES _ALIGNBYTES
#define ALIGN(p) _ALIGN(p)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 6
#endif
diff --git a/sys/i386/include/param.h b/sys/i386/include/param.h
index d9a3cda..abf855d 100644
--- a/sys/i386/include/param.h
+++ b/sys/i386/include/param.h
@@ -74,6 +74,10 @@
#define ALIGNBYTES _ALIGNBYTES
#define ALIGN(p) _ALIGN(p)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 6
#endif
diff --git a/sys/ia64/include/param.h b/sys/ia64/include/param.h
index f9a9c4a..4130ec4 100644
--- a/sys/ia64/include/param.h
+++ b/sys/ia64/include/param.h
@@ -99,6 +99,10 @@
#define ALIGN(p) _ALIGN(p)
#define ALIGNED_POINTER(p,t) _ALIGNED_POINTER(p,t)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 6
#endif
diff --git a/sys/mips/include/param.h b/sys/mips/include/param.h
index 55f877f..af1e06f 100644
--- a/sys/mips/include/param.h
+++ b/sys/mips/include/param.h
@@ -89,6 +89,10 @@
#define ALIGNBYTES _ALIGNBYTES
#define ALIGN(p) _ALIGN(p)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 6
#endif
diff --git a/sys/powerpc/include/param.h b/sys/powerpc/include/param.h
index 7dddb30..cab873e 100644
--- a/sys/powerpc/include/param.h
+++ b/sys/powerpc/include/param.h
@@ -79,6 +79,10 @@
#define ALIGNBYTES _ALIGNBYTES
#define ALIGN(p) _ALIGN(p)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 7
#endif
diff --git a/sys/sparc64/include/param.h b/sys/sparc64/include/param.h
index e8f783f..b909971 100644
--- a/sys/sparc64/include/param.h
+++ b/sys/sparc64/include/param.h
@@ -71,6 +71,10 @@
#define ALIGNBYTES _ALIGNBYTES
#define ALIGN(p) _ALIGN(p)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 6
#endif
diff --git a/sys/sun4v/include/param.h b/sys/sun4v/include/param.h
index 4d7b42e..aca3c37 100644
--- a/sys/sun4v/include/param.h
+++ b/sys/sun4v/include/param.h
@@ -71,6 +71,10 @@
#define ALIGNBYTES _ALIGNBYTES
#define ALIGN(p) _ALIGN(p)
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
#ifndef CACHE_LINE_SHIFT
#define CACHE_LINE_SHIFT 6
#endif
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