diff options
| -rw-r--r-- | sys/dev/ntb/ntb_hw/ntb_hw.c | 39 |
1 files changed, 10 insertions, 29 deletions
diff --git a/sys/dev/ntb/ntb_hw/ntb_hw.c b/sys/dev/ntb/ntb_hw/ntb_hw.c index 96e64a8..0ff9c8c 100644 --- a/sys/dev/ntb/ntb_hw/ntb_hw.c +++ b/sys/dev/ntb/ntb_hw/ntb_hw.c @@ -1817,42 +1817,23 @@ xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { - size_t size, xlatoffset; + uint32_t xlat_reg, lmt_reg; enum ntb_bar bar_num; - bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx); - switch (bar_num) { - case NTB_B2B_BAR_1: - size = 8; - xlatoffset = XEON_SBAR2XLAT_OFFSET; - break; - case NTB_B2B_BAR_2: - xlatoffset = XEON_SBAR4XLAT_OFFSET; - if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) - size = 4; - else - size = 8; - break; - case NTB_B2B_BAR_3: - xlatoffset = XEON_SBAR5XLAT_OFFSET; - size = 4; - break; - default: - KASSERT(false, ("Bogus msix mw idx: %u", - ntb->msix_mw_idx)); - return (EINVAL); - } - /* * We point the chosen MSIX MW BAR xlat to remote LAPIC for * workaround */ - if (size == 4) { - ntb_reg_write(4, xlatoffset, MSI_INTEL_ADDR_BASE); - ntb->msix_xlat = ntb_reg_read(4, xlatoffset); + bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx); + bar_get_xlat_params(ntb, bar_num, NULL, &xlat_reg, &lmt_reg); + if (bar_is_64bit(ntb, bar_num)) { + ntb_reg_write(8, xlat_reg, MSI_INTEL_ADDR_BASE); + ntb->msix_xlat = ntb_reg_read(8, xlat_reg); + ntb_reg_write(8, lmt_reg, 0); } else { - ntb_reg_write(8, xlatoffset, MSI_INTEL_ADDR_BASE); - ntb->msix_xlat = ntb_reg_read(8, xlatoffset); + ntb_reg_write(4, xlat_reg, MSI_INTEL_ADDR_BASE); + ntb->msix_xlat = ntb_reg_read(4, xlat_reg); + ntb_reg_write(8, lmt_reg, 0); } ntb->peer_lapic_bar = &ntb->bar_info[bar_num]; |
