diff options
| -rw-r--r-- | sys/dev/ti/if_ti.c | 2 | ||||
| -rw-r--r-- | sys/dev/ti/if_tireg.h | 7 | ||||
| -rw-r--r-- | sys/pci/if_ti.c | 2 | ||||
| -rw-r--r-- | sys/pci/if_tireg.h | 7 |
4 files changed, 14 insertions, 4 deletions
diff --git a/sys/dev/ti/if_ti.c b/sys/dev/ti/if_ti.c index a25c2f2..4db8b7d 100644 --- a/sys/dev/ti/if_ti.c +++ b/sys/dev/ti/if_ti.c @@ -1173,7 +1173,7 @@ static int ti_chipinit(sc) /* Do special setup for Tigon 2. */ if (sc->ti_hwrev == TI_HWREV_TIGON_II) { TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); - TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); + TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); } diff --git a/sys/dev/ti/if_tireg.h b/sys/dev/ti/if_tireg.h index df399be..e244e90 100644 --- a/sys/dev/ti/if_tireg.h +++ b/sys/dev/ti/if_tireg.h @@ -143,7 +143,6 @@ * Miscelaneous Local Control register. */ #define TI_MLC_EE_WRITE_ENB 0x00000010 -#define TI_MLC_SRAM_BANK_256K 0x00000200 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ #define TI_MLC_LOCALADDR_21 0x00004000 #define TI_MLC_LOCALADDR_22 0x00008000 @@ -153,6 +152,12 @@ #define TI_MLC_EE_DOUT 0x00400000 #define TI_MLC_EE_DIN 0x00800000 +/* Possible memory sizes. */ +#define TI_MLC_SRAM_BANK_DISA 0x00000000 +#define TI_MLC_SRAM_BANK_1024K 0x00000100 +#define TI_MLC_SRAM_BANK_512K 0x00000200 +#define TI_MLC_SRAM_BANK_256K 0x00000300 + /* * Offset of MAC address inside EEPROM. */ diff --git a/sys/pci/if_ti.c b/sys/pci/if_ti.c index a25c2f2..4db8b7d 100644 --- a/sys/pci/if_ti.c +++ b/sys/pci/if_ti.c @@ -1173,7 +1173,7 @@ static int ti_chipinit(sc) /* Do special setup for Tigon 2. */ if (sc->ti_hwrev == TI_HWREV_TIGON_II) { TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); - TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); + TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); } diff --git a/sys/pci/if_tireg.h b/sys/pci/if_tireg.h index df399be..e244e90 100644 --- a/sys/pci/if_tireg.h +++ b/sys/pci/if_tireg.h @@ -143,7 +143,6 @@ * Miscelaneous Local Control register. */ #define TI_MLC_EE_WRITE_ENB 0x00000010 -#define TI_MLC_SRAM_BANK_256K 0x00000200 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ #define TI_MLC_LOCALADDR_21 0x00004000 #define TI_MLC_LOCALADDR_22 0x00008000 @@ -153,6 +152,12 @@ #define TI_MLC_EE_DOUT 0x00400000 #define TI_MLC_EE_DIN 0x00800000 +/* Possible memory sizes. */ +#define TI_MLC_SRAM_BANK_DISA 0x00000000 +#define TI_MLC_SRAM_BANK_1024K 0x00000100 +#define TI_MLC_SRAM_BANK_512K 0x00000200 +#define TI_MLC_SRAM_BANK_256K 0x00000300 + /* * Offset of MAC address inside EEPROM. */ |
