diff options
283 files changed, 18025 insertions, 7939 deletions
diff --git a/Makefile.inc1 b/Makefile.inc1 index e4e3a83..617366c 100644 --- a/Makefile.inc1 +++ b/Makefile.inc1 @@ -220,7 +220,7 @@ INSTALLTMP!= /usr/bin/mktemp -d -u -t install # This stage is responsible for creating the object # tree and building any tools that are needed during # the build process. Some programs are listed during -# this phase because they build binaires to generate +# this phase because they build binaries to generate # files needed to build these programs. This stage also # builds the 'build-tools' target rather than 'all'. # 3. cross-tools stage [XMAKE] @@ -1494,7 +1494,7 @@ _btxld= usr.sbin/btxld .if ${MK_BINUTILS_BOOTSTRAP} != "no" _binutils= gnu/usr.bin/binutils .endif -.if ${MK_ELFTOOLCHAIN_TOOLS} != "no" +.if ${MK_ELFTOOLCHAIN_BOOTSTRAP} != "no" _elftctools= lib/libelftc \ usr.bin/elfcopy \ usr.bin/nm \ @@ -1504,7 +1504,7 @@ _elftctools= lib/libelftc \ # cross-build on a FreeBSD 10 host: _elftctools+= usr.bin/addr2line .endif -.elif ${TARGET_ARCH} != ${MACHINE_ARCH} && ${MK_ELFTOOLCHAIN_TOOLS} != "no" +.elif ${TARGET_ARCH} != ${MACHINE_ARCH} && ${MK_ELFTOOLCHAIN_BOOTSTRAP} != "no" # If cross-building with an external binutils we still need to build strip for # the target (for at least crunchide). _elftctools= lib/libelftc \ @@ -36,6 +36,26 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: 20141231 entry below for information about prerequisites and upgrading, if you are not already using 3.5.0 or higher. +20150817: + Kernel-loadable modules for the random(4) device are back. To use + them, the kernel must have + + device random + options RANDOM_LOADABLE + + kldload(8) can then be used to load random_fortuna.ko + or random_yarrow.ko. Please note that due to the indirect + function calls that the loadable modules need to provide, + the build-in variants will be slightly more efficient. + + The random(4) kernel option RANDOM_DUMMY has been retired due to + unpopularity. It was not all that useful anyway. + +20150813: + The WITHOUT_ELFTOOLCHAIN_TOOLS src.conf(5) knob has been retired. + Control over building the ELF Tool Chain tools is now provided by + the WITHOUT_TOOLCHAIN knob. + 20150810: The polarity of Pulse Per Second (PPS) capture events with the uart(4) driver has been corrected. Prior to this change the PPS diff --git a/bin/sh/miscbltin.c b/bin/sh/miscbltin.c index 715e324..4575e96 100644 --- a/bin/sh/miscbltin.c +++ b/bin/sh/miscbltin.c @@ -191,9 +191,10 @@ readcmd(int argc __unused, char **argv __unused) CHECKSTRSPACE(1, p); if (backslash) { backslash = 0; - startword = 0; - if (c != '\n') + if (c != '\n') { + startword = 0; USTPUTC(c, p); + } continue; } if (!rflag && c == '\\') { diff --git a/bin/sh/options.c b/bin/sh/options.c index 2d0ddce..1568937 100644 --- a/bin/sh/options.c +++ b/bin/sh/options.c @@ -73,6 +73,7 @@ char *minusc; /* argument to -c option */ static void options(int); static void minus_o(char *, int); static void setoption(int, int); +static void setoptionbyindex(int, int); static int getopts(char *, char *, char **, char ***, char **); @@ -269,7 +270,7 @@ minus_o(char *name, int val) } else { for (i = 0; i < NOPTS; i++) if (equal(name, optlist[i].name)) { - setoption(optlist[i].letter, val); + setoptionbyindex(i, val); return; } error("Illegal option -o %s", name); @@ -278,26 +279,32 @@ minus_o(char *name, int val) static void -setoption(int flag, int val) +setoptionbyindex(int idx, int val) { - int i; - - if (flag == 'p' && !val && privileged) { + if (optlist[idx].letter == 'p' && !val && privileged) { if (setgid(getgid()) == -1) error("setgid"); if (setuid(getuid()) == -1) error("setuid"); } + optlist[idx].val = val; + if (val) { + /* #%$ hack for ksh semantics */ + if (optlist[idx].letter == 'V') + Eflag = 0; + else if (optlist[idx].letter == 'E') + Vflag = 0; + } +} + +static void +setoption(int flag, int val) +{ + int i; + for (i = 0; i < NOPTS; i++) if (optlist[i].letter == flag) { - optlist[i].val = val; - if (val) { - /* #%$ hack for ksh semantics */ - if (flag == 'V') - Eflag = 0; - else if (flag == 'E') - Vflag = 0; - } + setoptionbyindex(i, val); return; } error("Illegal option -%c", flag); diff --git a/bin/sh/tests/builtins/Makefile b/bin/sh/tests/builtins/Makefile index ad39aac..f3c1dc7 100644 --- a/bin/sh/tests/builtins/Makefile +++ b/bin/sh/tests/builtins/Makefile @@ -121,6 +121,7 @@ FILES+= read4.0 read4.0.stdout FILES+= read5.0 FILES+= read6.0 FILES+= read7.0 +FILES+= read8.0 FILES+= return1.0 FILES+= return2.1 FILES+= return3.1 diff --git a/bin/sh/tests/builtins/read8.0 b/bin/sh/tests/builtins/read8.0 new file mode 100644 index 0000000..fb786ff --- /dev/null +++ b/bin/sh/tests/builtins/read8.0 @@ -0,0 +1,17 @@ +# $FreeBSD$ + +read a b c <<\EOF +\ +A\ + \ + \ + \ +B\ + \ + \ +C\ + \ + \ + \ +EOF +[ "$a.$b.$c" = "A.B.C" ] diff --git a/cddl/contrib/opensolaris/cmd/zdb/zdb.c b/cddl/contrib/opensolaris/cmd/zdb/zdb.c index 7c5df0b..4f5c372 100644 --- a/cddl/contrib/opensolaris/cmd/zdb/zdb.c +++ b/cddl/contrib/opensolaris/cmd/zdb/zdb.c @@ -21,7 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2011, 2014 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. */ #include <stdio.h> @@ -2221,7 +2221,7 @@ dump_label(const char *dev) (void) close(fd); } -static uint64_t num_large_blocks; +static uint64_t dataset_feature_count[SPA_FEATURES]; /*ARGSUSED*/ static int @@ -2235,8 +2235,15 @@ dump_one_dir(const char *dsname, void *arg) (void) printf("Could not open %s, error %d\n", dsname, error); return (0); } - if (dmu_objset_ds(os)->ds_large_blocks) - num_large_blocks++; + + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (!dmu_objset_ds(os)->ds_feature_inuse[f]) + continue; + ASSERT(spa_feature_table[f].fi_flags & + ZFEATURE_FLAG_PER_DATASET); + dataset_feature_count[f]++; + } + dump_dir(os); dmu_objset_disown(os, FTAG); fuid_table_destroy(); @@ -2428,6 +2435,9 @@ zdb_blkptr_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, dmu_object_type_t type; boolean_t is_metadata; + if (bp == NULL) + return (0); + if (dump_opt['b'] >= 5 && bp->blk_birth > 0) { char blkbuf[BP_SPRINTF_LEN]; snprintf_blkptr(blkbuf, sizeof (blkbuf), bp); @@ -2917,7 +2927,7 @@ zdb_ddt_add_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, avl_index_t where; zdb_ddt_entry_t *zdde, zdde_search; - if (BP_IS_HOLE(bp) || BP_IS_EMBEDDED(bp)) + if (bp == NULL || BP_IS_HOLE(bp) || BP_IS_EMBEDDED(bp)) return (0); if (dump_opt['S'] > 1 && zb->zb_level == ZB_ROOT_LEVEL) { @@ -3032,7 +3042,6 @@ dump_zpool(spa_t *spa) dump_metaslab_groups(spa); if (dump_opt['d'] || dump_opt['i']) { - uint64_t refcount; dump_dir(dp->dp_meta_objset); if (dump_opt['d'] >= 3) { dump_full_bpobj(&spa->spa_deferred_bpobj, @@ -3054,17 +3063,29 @@ dump_zpool(spa_t *spa) (void) dmu_objset_find(spa_name(spa), dump_one_dir, NULL, DS_FIND_SNAPSHOTS | DS_FIND_CHILDREN); - (void) feature_get_refcount(spa, - &spa_feature_table[SPA_FEATURE_LARGE_BLOCKS], &refcount); - if (num_large_blocks != refcount) { - (void) printf("large_blocks feature refcount mismatch: " - "expected %lld != actual %lld\n", - (longlong_t)num_large_blocks, - (longlong_t)refcount); - rc = 2; - } else { - (void) printf("Verified large_blocks feature refcount " - "is correct (%llu)\n", (longlong_t)refcount); + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + uint64_t refcount; + + if (!(spa_feature_table[f].fi_flags & + ZFEATURE_FLAG_PER_DATASET)) { + ASSERT0(dataset_feature_count[f]); + continue; + } + (void) feature_get_refcount(spa, + &spa_feature_table[f], &refcount); + if (dataset_feature_count[f] != refcount) { + (void) printf("%s feature refcount mismatch: " + "%lld datasets != %lld refcount\n", + spa_feature_table[f].fi_uname, + (longlong_t)dataset_feature_count[f], + (longlong_t)refcount); + rc = 2; + } else { + (void) printf("Verified %s feature refcount " + "of %llu is correct\n", + spa_feature_table[f].fi_uname, + (longlong_t)refcount); + } } } if (rc == 0 && (dump_opt['b'] || dump_opt['c'])) diff --git a/cddl/contrib/opensolaris/cmd/zfs/zfs.8 b/cddl/contrib/opensolaris/cmd/zfs/zfs.8 index 2254de1..4da6d0b 100644 --- a/cddl/contrib/opensolaris/cmd/zfs/zfs.8 +++ b/cddl/contrib/opensolaris/cmd/zfs/zfs.8 @@ -191,11 +191,13 @@ .Nm .Cm receive Ns | Ns Cm recv .Op Fl vnFu +.Op Fl o Sy origin Ns = Ns Ar snapshot .Ar filesystem Ns | Ns Ar volume Ns | Ns Ar snapshot .Nm .Cm receive Ns | Ns Cm recv .Op Fl vnFu .Op Fl d | e +.Op Fl o Sy origin Ns = Ns Ar snapshot .Ar filesystem .Nm .Cm allow @@ -2705,6 +2707,7 @@ feature. .Nm .Cm receive Ns | Ns Cm recv .Op Fl vnFu +.Op Fl o Sy origin Ns = Ns Ar snapshot .Ar filesystem Ns | Ns Ar volume Ns | Ns Ar snapshot .Xc .It Xo @@ -2712,6 +2715,7 @@ feature. .Cm receive Ns | Ns Cm recv .Op Fl vnFu .Op Fl d | e +.Op Fl o Sy origin Ns = Ns Ar snapshot .Ar filesystem .Xc .Pp @@ -2796,6 +2800,10 @@ receive operation. Do not actually receive the stream. This can be useful in conjunction with the .Fl v option to verify the name the receive operation would use. +.It Fl o Sy origin Ns = Ns Ar snapshot +Forces the stream to be received as a clone of the given snapshot. +This is only valid if the stream is an incremental stream whose source +is the same as the provided origin. .It Fl F Force a rollback of the file system to the most recent snapshot before performing the receive operation. If receiving an incremental replication diff --git a/cddl/contrib/opensolaris/cmd/zfs/zfs_main.c b/cddl/contrib/opensolaris/cmd/zfs/zfs_main.c index 389b248..9d80b9b 100644 --- a/cddl/contrib/opensolaris/cmd/zfs/zfs_main.c +++ b/cddl/contrib/opensolaris/cmd/zfs/zfs_main.c @@ -264,8 +264,9 @@ get_usage(zfs_help_t idx) return (gettext("\tpromote <clone-filesystem>\n")); case HELP_RECEIVE: return (gettext("\treceive|recv [-vnFu] <filesystem|volume|" - "snapshot>\n" - "\treceive|recv [-vnFu] [-d | -e] <filesystem>\n")); + "snapshot>\n" + "\treceive|recv [-vnFu] [-o origin=<snapshot>] [-d | -e] " + "<filesystem>\n")); case HELP_RENAME: return (gettext("\trename [-f] <filesystem|volume|snapshot> " "<filesystem|volume|snapshot>\n" @@ -791,7 +792,7 @@ zfs_do_create(int argc, char **argv) nomem(); break; case 'o': - if (parseprop(props, optarg)) + if (parseprop(props, optarg) != 0) goto error; break; case 's': @@ -3659,7 +3660,7 @@ zfs_do_snapshot(int argc, char **argv) while ((c = getopt(argc, argv, "ro:")) != -1) { switch (c) { case 'o': - if (parseprop(props, optarg)) + if (parseprop(props, optarg) != 0) return (1); break; case 'r': @@ -3918,10 +3919,19 @@ zfs_do_receive(int argc, char **argv) { int c, err; recvflags_t flags = { 0 }; + nvlist_t *props; + nvpair_t *nvp = NULL; + + if (nvlist_alloc(&props, NV_UNIQUE_NAME, 0) != 0) + nomem(); /* check options */ - while ((c = getopt(argc, argv, ":denuvF")) != -1) { + while ((c = getopt(argc, argv, ":o:denuvF")) != -1) { switch (c) { + case 'o': + if (parseprop(props, optarg) != 0) + return (1); + break; case 'd': flags.isprefix = B_TRUE; break; @@ -3966,6 +3976,13 @@ zfs_do_receive(int argc, char **argv) usage(B_FALSE); } + while ((nvp = nvlist_next_nvpair(props, nvp))) { + if (strcmp(nvpair_name(nvp), "origin") != 0) { + (void) fprintf(stderr, gettext("invalid option")); + usage(B_FALSE); + } + } + if (isatty(STDIN_FILENO)) { (void) fprintf(stderr, gettext("Error: Backup stream can not be read " @@ -3974,7 +3991,7 @@ zfs_do_receive(int argc, char **argv) return (1); } - err = zfs_receive(g_zfs, argv[0], &flags, STDIN_FILENO, NULL); + err = zfs_receive(g_zfs, argv[0], props, &flags, STDIN_FILENO, NULL); return (err != 0); } diff --git a/cddl/contrib/opensolaris/cmd/zhack/zhack.c b/cddl/contrib/opensolaris/cmd/zhack/zhack.c index 6e3f029..f4434a1 100644 --- a/cddl/contrib/opensolaris/cmd/zhack/zhack.c +++ b/cddl/contrib/opensolaris/cmd/zhack/zhack.c @@ -20,7 +20,7 @@ */ /* - * Copyright (c) 2011, 2014 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2013 Steven Hartland. All rights reserved. */ @@ -294,8 +294,8 @@ zhack_feature_enable_sync(void *arg, dmu_tx_t *tx) feature_enable_sync(spa, feature, tx); spa_history_log_internal(spa, "zhack enable feature", tx, - "name=%s can_readonly=%u", - feature->fi_guid, feature->fi_can_readonly); + "guid=%s flags=%x", + feature->fi_guid, feature->fi_flags); } static void @@ -314,9 +314,7 @@ zhack_do_feature_enable(int argc, char **argv) */ desc = NULL; feature.fi_uname = "zhack"; - feature.fi_mos = B_FALSE; - feature.fi_can_readonly = B_FALSE; - feature.fi_activate_on_enable = B_FALSE; + feature.fi_flags = 0; feature.fi_depends = nodeps; feature.fi_feature = SPA_FEATURE_NONE; @@ -324,7 +322,7 @@ zhack_do_feature_enable(int argc, char **argv) while ((c = getopt(argc, argv, "rmd:")) != -1) { switch (c) { case 'r': - feature.fi_can_readonly = B_TRUE; + feature.fi_flags |= ZFEATURE_FLAG_READONLY_COMPAT; break; case 'd': desc = strdup(optarg); @@ -413,7 +411,7 @@ zhack_do_feature_ref(int argc, char **argv) * disk later. */ feature.fi_uname = "zhack"; - feature.fi_mos = B_FALSE; + feature.fi_flags = 0; feature.fi_desc = NULL; feature.fi_depends = nodeps; feature.fi_feature = SPA_FEATURE_NONE; @@ -422,7 +420,7 @@ zhack_do_feature_ref(int argc, char **argv) while ((c = getopt(argc, argv, "md")) != -1) { switch (c) { case 'm': - feature.fi_mos = B_TRUE; + feature.fi_flags |= ZFEATURE_FLAG_MOS; break; case 'd': decr = B_TRUE; @@ -455,10 +453,10 @@ zhack_do_feature_ref(int argc, char **argv) if (0 == zap_contains(mos, spa->spa_feat_for_read_obj, feature.fi_guid)) { - feature.fi_can_readonly = B_FALSE; + feature.fi_flags &= ~ZFEATURE_FLAG_READONLY_COMPAT; } else if (0 == zap_contains(mos, spa->spa_feat_for_write_obj, feature.fi_guid)) { - feature.fi_can_readonly = B_TRUE; + feature.fi_flags |= ZFEATURE_FLAG_READONLY_COMPAT; } else { fatal(spa, FTAG, "feature is not enabled: %s", feature.fi_guid); } diff --git a/cddl/contrib/opensolaris/cmd/zpool/zpool_main.c b/cddl/contrib/opensolaris/cmd/zpool/zpool_main.c index d8243f3..a3eabd1 100644 --- a/cddl/contrib/opensolaris/cmd/zpool/zpool_main.c +++ b/cddl/contrib/opensolaris/cmd/zpool/zpool_main.c @@ -22,7 +22,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright 2011 Nexenta Systems, Inc. All rights reserved. - * Copyright (c) 2011, 2014 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2012 by Frederik Wessels. All rights reserved. * Copyright (c) 2012 Martin Matuska <mm@FreeBSD.org>. All rights reserved. * Copyright (c) 2013 by Prasad Joshi (sTec). All rights reserved. @@ -4986,7 +4986,8 @@ zpool_do_upgrade(int argc, char **argv) "---------------\n"); for (i = 0; i < SPA_FEATURES; i++) { zfeature_info_t *fi = &spa_feature_table[i]; - const char *ro = fi->fi_can_readonly ? + const char *ro = + (fi->fi_flags & ZFEATURE_FLAG_READONLY_COMPAT) ? " (read-only compatible)" : ""; (void) printf("%-37s%s\n", fi->fi_uname, ro); diff --git a/cddl/contrib/opensolaris/cmd/ztest/ztest.c b/cddl/contrib/opensolaris/cmd/ztest/ztest.c index 0695834..7cc8d5f 100644 --- a/cddl/contrib/opensolaris/cmd/ztest/ztest.c +++ b/cddl/contrib/opensolaris/cmd/ztest/ztest.c @@ -3586,7 +3586,8 @@ ztest_dmu_read_write(ztest_ds_t *zd, uint64_t id) */ n = ztest_random(regions) * stride + ztest_random(width); s = 1 + ztest_random(2 * width - 1); - dmu_prefetch(os, bigobj, n * chunksize, s * chunksize); + dmu_prefetch(os, bigobj, 0, n * chunksize, s * chunksize, + ZIO_PRIORITY_SYNC_READ); /* * Pick a random index and compute the offsets into packobj and bigobj. @@ -5705,8 +5706,10 @@ ztest_run(ztest_shared_t *zs) * Right before closing the pool, kick off a bunch of async I/O; * spa_close() should wait for it to complete. */ - for (uint64_t object = 1; object < 50; object++) - dmu_prefetch(spa->spa_meta_objset, object, 0, 1ULL << 20); + for (uint64_t object = 1; object < 50; object++) { + dmu_prefetch(spa->spa_meta_objset, object, 0, 0, 1ULL << 20, + ZIO_PRIORITY_SYNC_READ); + } spa_close(spa, FTAG); @@ -5905,6 +5908,7 @@ ztest_init(ztest_shared_t *zs) } VERIFY3U(0, ==, spa_create(ztest_opts.zo_pool, nvroot, props, NULL)); nvlist_free(nvroot); + nvlist_free(props); VERIFY3U(0, ==, spa_open(ztest_opts.zo_pool, &spa, FTAG)); zs->zs_metaslab_sz = diff --git a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h index fbfaab1..968732e 100644 --- a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h +++ b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h @@ -668,8 +668,8 @@ typedef struct recvflags { boolean_t nomount; } recvflags_t; -extern int zfs_receive(libzfs_handle_t *, const char *, recvflags_t *, - int, avl_tree_t *); +extern int zfs_receive(libzfs_handle_t *, const char *, nvlist_t *, + recvflags_t *, int, avl_tree_t *); typedef enum diff_flags { ZFS_DIFF_PARSEABLE = 0x1, diff --git a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c index b9db421..5c78e81 100644 --- a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c +++ b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c @@ -3535,7 +3535,7 @@ zpool_vdev_name(libzfs_handle_t *hdl, zpool_handle_t *zhp, nvlist_t *nv, } static int -zbookmark_compare(const void *a, const void *b) +zbookmark_mem_compare(const void *a, const void *b) { return (memcmp(a, b, sizeof (zbookmark_phys_t))); } @@ -3598,7 +3598,7 @@ zpool_get_errlog(zpool_handle_t *zhp, nvlist_t **nverrlistp) zc.zc_nvlist_dst_size; count -= zc.zc_nvlist_dst_size; - qsort(zb, count, sizeof (zbookmark_phys_t), zbookmark_compare); + qsort(zb, count, sizeof (zbookmark_phys_t), zbookmark_mem_compare); verify(nvlist_alloc(nverrlistp, 0, KM_SLEEP) == 0); diff --git a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c index bd3832e..f6efa97 100644 --- a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c +++ b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c @@ -64,8 +64,9 @@ extern void zfs_setprop_error(libzfs_handle_t *, zfs_prop_t, int, char *); /* We need to use something for ENODATA. */ #define ENODATA EIDRM -static int zfs_receive_impl(libzfs_handle_t *, const char *, recvflags_t *, - int, const char *, nvlist_t *, avl_tree_t *, char **, int, uint64_t *); +static int zfs_receive_impl(libzfs_handle_t *, const char *, const char *, + recvflags_t *, int, const char *, nvlist_t *, avl_tree_t *, char **, int, + uint64_t *); static const zio_cksum_t zero_cksum = { 0 }; @@ -2498,7 +2499,7 @@ zfs_receive_package(libzfs_handle_t *hdl, int fd, const char *destname, * zfs_receive_one() will take care of it (ie, * recv_skip() and return 0). */ - error = zfs_receive_impl(hdl, destname, flags, fd, + error = zfs_receive_impl(hdl, destname, NULL, flags, fd, sendfs, stream_nv, stream_avl, top_zfs, cleanup_fd, action_handlep); if (error == ENODATA) { @@ -2631,9 +2632,9 @@ recv_skip(libzfs_handle_t *hdl, int fd, boolean_t byteswap) */ static int zfs_receive_one(libzfs_handle_t *hdl, int infd, const char *tosnap, - recvflags_t *flags, dmu_replay_record_t *drr, - dmu_replay_record_t *drr_noswap, const char *sendfs, - nvlist_t *stream_nv, avl_tree_t *stream_avl, char **top_zfs, int cleanup_fd, + const char *originsnap, recvflags_t *flags, dmu_replay_record_t *drr, + dmu_replay_record_t *drr_noswap, const char *sendfs, nvlist_t *stream_nv, + avl_tree_t *stream_avl, char **top_zfs, int cleanup_fd, uint64_t *action_handlep) { zfs_cmd_t zc = { 0 }; @@ -2798,10 +2799,15 @@ zfs_receive_one(libzfs_handle_t *hdl, int infd, const char *tosnap, } if (flags->verbose) (void) printf("found clone origin %s\n", zc.zc_string); + } else if (originsnap) { + (void) strncpy(zc.zc_string, originsnap, ZFS_MAXNAMELEN); + if (flags->verbose) + (void) printf("using provided clone origin %s\n", + zc.zc_string); } stream_wantsnewfs = (drrb->drr_fromguid == 0 || - (drrb->drr_flags & DRR_FLAG_CLONE)); + (drrb->drr_flags & DRR_FLAG_CLONE) || originsnap); if (stream_wantsnewfs) { /* @@ -3179,9 +3185,10 @@ zfs_receive_one(libzfs_handle_t *hdl, int infd, const char *tosnap, } static int -zfs_receive_impl(libzfs_handle_t *hdl, const char *tosnap, recvflags_t *flags, - int infd, const char *sendfs, nvlist_t *stream_nv, avl_tree_t *stream_avl, - char **top_zfs, int cleanup_fd, uint64_t *action_handlep) +zfs_receive_impl(libzfs_handle_t *hdl, const char *tosnap, + const char *originsnap, recvflags_t *flags, int infd, const char *sendfs, + nvlist_t *stream_nv, avl_tree_t *stream_avl, char **top_zfs, int cleanup_fd, + uint64_t *action_handlep) { int err; dmu_replay_record_t drr, drr_noswap; @@ -3200,6 +3207,12 @@ zfs_receive_impl(libzfs_handle_t *hdl, const char *tosnap, recvflags_t *flags, "(%s) does not exist"), tosnap); return (zfs_error(hdl, EZFS_NOENT, errbuf)); } + if (originsnap && + !zfs_dataset_exists(hdl, originsnap, ZFS_TYPE_DATASET)) { + zfs_error_aux(hdl, dgettext(TEXT_DOMAIN, "specified origin fs " + "(%s) does not exist"), originsnap); + return (zfs_error(hdl, EZFS_NOENT, errbuf)); + } /* read in the BEGIN record */ if (0 != (err = recv_read(hdl, infd, &drr, sizeof (drr), B_FALSE, @@ -3272,14 +3285,14 @@ zfs_receive_impl(libzfs_handle_t *hdl, const char *tosnap, recvflags_t *flags, *cp = '\0'; sendfs = nonpackage_sendfs; } - return (zfs_receive_one(hdl, infd, tosnap, flags, - &drr, &drr_noswap, sendfs, stream_nv, stream_avl, - top_zfs, cleanup_fd, action_handlep)); + return (zfs_receive_one(hdl, infd, tosnap, originsnap, flags, + &drr, &drr_noswap, sendfs, stream_nv, stream_avl, top_zfs, + cleanup_fd, action_handlep)); } else { assert(DMU_GET_STREAM_HDRTYPE(drrb->drr_versioninfo) == DMU_COMPOUNDSTREAM); - return (zfs_receive_package(hdl, infd, tosnap, flags, - &drr, &zcksum, top_zfs, cleanup_fd, action_handlep)); + return (zfs_receive_package(hdl, infd, tosnap, flags, &drr, + &zcksum, top_zfs, cleanup_fd, action_handlep)); } } @@ -3290,18 +3303,24 @@ zfs_receive_impl(libzfs_handle_t *hdl, const char *tosnap, recvflags_t *flags, * (-1 will override -2). */ int -zfs_receive(libzfs_handle_t *hdl, const char *tosnap, recvflags_t *flags, - int infd, avl_tree_t *stream_avl) +zfs_receive(libzfs_handle_t *hdl, const char *tosnap, nvlist_t *props, + recvflags_t *flags, int infd, avl_tree_t *stream_avl) { char *top_zfs = NULL; int err; int cleanup_fd; uint64_t action_handle = 0; + char *originsnap = NULL; + if (props) { + err = nvlist_lookup_string(props, "origin", &originsnap); + if (err && err != ENOENT) + return (err); + } cleanup_fd = open(ZFS_DEV, O_RDWR|O_EXCL); VERIFY(cleanup_fd >= 0); - err = zfs_receive_impl(hdl, tosnap, flags, infd, NULL, NULL, + err = zfs_receive_impl(hdl, tosnap, originsnap, flags, infd, NULL, NULL, stream_avl, &top_zfs, cleanup_fd, &action_handle); VERIFY(0 == close(cleanup_fd)); diff --git a/cddl/contrib/opensolaris/lib/libzpool/common/sys/zfs_context.h b/cddl/contrib/opensolaris/lib/libzpool/common/sys/zfs_context.h index 493be33..15ad5ed 100644 --- a/cddl/contrib/opensolaris/lib/libzpool/common/sys/zfs_context.h +++ b/cddl/contrib/opensolaris/lib/libzpool/common/sys/zfs_context.h @@ -135,8 +135,18 @@ extern int aok; /* * DTrace SDT probes have different signatures in userland than they do in - * kernel. If they're being used in kernel code, re-define them out of + * the kernel. If they're being used in kernel code, re-define them out of * existence for their counterparts in libzpool. + * + * Here's an example of how to use the set-error probes in userland: + * zfs$target:::set-error /arg0 == EBUSY/ {stack();} + * + * Here's an example of how to use DTRACE_PROBE probes in userland: + * If there is a probe declared as follows: + * DTRACE_PROBE2(zfs__probe_name, uint64_t, blkid, dnode_t *, dn); + * Then you can use it as follows: + * zfs$target:::probe2 /copyinstr(arg0) == "zfs__probe_name"/ + * {printf("%u %p\n", arg1, arg2);} */ #ifdef DTRACE_PROBE diff --git a/contrib/compiler-rt/lib/builtins/floatditf.c b/contrib/compiler-rt/lib/builtins/floatditf.c index 01261c6..1a5f8e5 100644 --- a/contrib/compiler-rt/lib/builtins/floatditf.c +++ b/contrib/compiler-rt/lib/builtins/floatditf.c @@ -34,7 +34,7 @@ COMPILER_RT_ABI fp_t __floatditf(di_int a) { } // Exponent of (fp_t)a is the width of abs(a). - const int exponent = (aWidth - 1) - __builtin_clz(a); + const int exponent = (aWidth - 1) - __builtin_clzll(a); rep_t result; // Shift a into the significand field and clear the implicit bit. Extra diff --git a/contrib/compiler-rt/lib/builtins/floatunditf.c b/contrib/compiler-rt/lib/builtins/floatunditf.c index 7533f81..8098e95 100644 --- a/contrib/compiler-rt/lib/builtins/floatunditf.c +++ b/contrib/compiler-rt/lib/builtins/floatunditf.c @@ -25,7 +25,7 @@ COMPILER_RT_ABI fp_t __floatunditf(du_int a) { if (a == 0) return fromRep(0); // Exponent of (fp_t)a is the width of abs(a). - const int exponent = (aWidth - 1) - __builtin_clz(a); + const int exponent = (aWidth - 1) - __builtin_clzll(a); rep_t result; // Shift a into the significand field and clear the implicit bit. diff --git a/contrib/gcclibs/libcpp/files.c b/contrib/gcclibs/libcpp/files.c index 366d30a..95cda0e 100644 --- a/contrib/gcclibs/libcpp/files.c +++ b/contrib/gcclibs/libcpp/files.c @@ -567,7 +567,7 @@ read_file_guts (cpp_reader *pfile, _cpp_file *file) SSIZE_MAX to be much smaller than the actual range of the type. Use INTTYPE_MAXIMUM unconditionally to ensure this does not bite us. */ - if (file->st.st_size > INTTYPE_MAXIMUM (ssize_t)) + if (file->st.st_size > SSIZE_MAX) { cpp_error (pfile, CPP_DL_ERROR, "%s is too large", file->path); return false; @@ -581,7 +581,7 @@ read_file_guts (cpp_reader *pfile, _cpp_file *file) file->path); return false; } - else if (offset > INTTYPE_MAXIMUM (ssize_t) || (ssize_t)offset > size) + else if (offset > SSIZE_MAX || (ssize_t)offset > size) { cpp_error (pfile, CPP_DL_ERROR, "current position of %s is too large", file->path); diff --git a/contrib/tzdata/africa b/contrib/tzdata/africa index 5ad47e3..f20d216 100644 --- a/contrib/tzdata/africa +++ b/contrib/tzdata/africa @@ -538,7 +538,7 @@ Zone Africa/Tripoli 0:52:44 - LMT 1920 # From Alex Krivenyshev (2008-07-11): # Seems that English language article "The revival of daylight saving -# time: Energy conservation?"-# No. 16578 (07/11/2008) was originally +# time: Energy conservation?"- No. 16578 (07/11/2008) was originally # published on Monday, June 30, 2008... # # I guess that article in French "Le gouvernement avance l'introduction @@ -670,7 +670,7 @@ Zone Indian/Mauritius 3:50:00 - LMT 1907 # Port Louis # Here is a link to official document from Royaume du Maroc Premier Ministre, # Ministère de la Modernisation des Secteurs Publics # -# Under Article 1 of Royal Decree No. 455-67 of Act 23 safar 1387 (2 june 1967) +# Under Article 1 of Royal Decree No. 455-67 of Act 23 safar 1387 (2 June 1967) # concerning the amendment of the legal time, the Ministry of Modernization of # Public Sectors announced that the official time in the Kingdom will be # advanced 60 minutes from Sunday 31 May 2009 at midnight. diff --git a/contrib/tzdata/asia b/contrib/tzdata/asia index 756e3d0..4f8756b 100644 --- a/contrib/tzdata/asia +++ b/contrib/tzdata/asia @@ -6,7 +6,7 @@ # tz@iana.org for general use in the future). For more, please see # the file CONTRIBUTING in the tz distribution. -# From Paul Eggert (2014-10-31): +# From Paul Eggert (2015-08-08): # # Unless otherwise specified, the source for data through 1990 is: # Thomas G. Shanks and Rique Pottenger, The International Atlas (6th edition), @@ -43,7 +43,7 @@ # 2:00 EET EEST Eastern European Time # 2:00 IST IDT Israel # 3:00 AST ADT Arabia* -# 3:30 IRST IRDT Iran +# 3:30 IRST IRDT Iran* # 4:00 GST Gulf* # 5:30 IST India # 7:00 ICT Indochina, most times and locations* @@ -52,10 +52,11 @@ # 8:00 CST China # 8:00 IDT Indochina, 1943-45, 1947-55, 1960-75 (some locations)* # 8:00 JWST Western Standard Time (Japan, 1896/1937)* +# 8:30 KST KDT Korea when at +0830* # 9:00 JCST Central Standard Time (Japan, 1896/1937) # 9:00 WIT east Indonesia (Waktu Indonesia Timur) # 9:00 JST JDT Japan -# 9:00 KST KDT Korea +# 9:00 KST KDT Korea when at +09 # 9:30 ACST Australian Central Standard Time # # See the 'europe' file for Russia and Turkey in Asia. @@ -1027,7 +1028,7 @@ Zone Asia/Jayapura 9:22:48 - LMT 1932 Nov # # From Roozbeh Pournader (2007-11-05): # This is quoted from Official Gazette of the Islamic Republic of -# Iran, Volume 63, Number 18242, dated Tuesday 1386/6/24 +# Iran, Volume 63, No. 18242, dated Tuesday 1386/6/24 # [2007-10-16]. I am doing the best translation I can:... # The official time of the country will be moved forward for one hour # on the 24 hours of the first day of the month of Farvardin and will @@ -1557,7 +1558,7 @@ Zone Asia/Amman 2:23:44 - LMT 1931 # - Qyzylorda switched from +5:00 to +6:00 on 1992-01-19 02:00. # - Oral switched from +5:00 to +4:00 in spring 1989. -# From Kazakhstan Embassy's News Bulletin #11 +# From Kazakhstan Embassy's News Bulletin No. 11 # <http://www.kazsociety.org.uk/news/2005/03/30.htm> (2005-03-21): # The Government of Kazakhstan passed a resolution March 15 abolishing # daylight saving time citing lack of economic benefits and health @@ -1711,6 +1712,17 @@ Rule ROK 1987 1988 - Oct Sun>=8 3:00 0 S # # For Pyongyang we have no information; guess no changes since World War II. +# From Steffen Thorsen (2015-08-07): +# According to many news sources, North Korea is going to change to +# the 8:30 time zone on August 15, one example: +# http://www.bbc.com/news/world-asia-33815049 +# +# From Paul Eggert (2015-08-07): +# No transition time is specified; assume 00:00. +# There is no common English-language abbreviation for this time zone. +# Use %z rather than invent one. We can't assume %z works everywhere yet, +# so for now substitute its output manually. + # Zone NAME GMTOFF RULES FORMAT [UNTIL] Zone Asia/Seoul 8:27:52 - LMT 1908 Apr 1 8:30 - KST 1912 Jan 1 @@ -1723,7 +1735,8 @@ Zone Asia/Pyongyang 8:23:00 - LMT 1908 Apr 1 8:30 - KST 1912 Jan 1 9:00 - JCST 1937 Oct 1 9:00 - JST 1945 Aug 24 - 9:00 - KST + 9:00 - KST 2015 Aug 15 + 8:30 - KST ############################################################################### diff --git a/contrib/tzdata/europe b/contrib/tzdata/europe index c64c41b..6b89b6e 100644 --- a/contrib/tzdata/europe +++ b/contrib/tzdata/europe @@ -193,11 +193,14 @@ # republished in Finest Hour (Spring 2002) 1(114):26 # http://www.winstonchurchill.org/images/finesthour/Vol.01%20No.114.pdf -# From Paul Eggert (1996-09-03): +# From Paul Eggert (2015-08-08): # The OED Supplement says that the English originally said "Daylight Saving" # when they were debating the adoption of DST in 1908; but by 1916 this # term appears only in quotes taken from DST's opponents, whereas the # proponents (who eventually won the argument) are quoted as using "Summer". +# The term "Summer Time" was introduced by Herbert Samuel, Home Secretary; see: +# Viscount Samuel. Leisure in a Democracy. Cambridge University Press +# ISBN 978-1-107-49471-8 (1949, reissued 2015), p 8. # From Arthur David Olson (1989-01-19): # A source at the British Information Office in New York avers that it's @@ -343,7 +346,7 @@ # From an anonymous contributor (1996-06-02): # The law governing time in Ireland is under Statutory Instrument SI 395/94, -# which gives force to European Union 7th Council Directive # 94/21/EC. +# which gives force to European Union 7th Council Directive No. 94/21/EC. # Under this directive, the Minister for Justice in Ireland makes appropriate # regulations. I spoke this morning with the Secretary of the Department of # Justice (tel +353 1 678 9711) who confirmed to me that the correct name is @@ -592,11 +595,11 @@ Rule Russia 1921 only - Feb 14 23:00 1:00 MSD Rule Russia 1921 only - Mar 20 23:00 2:00 MSM # Midsummer Rule Russia 1921 only - Sep 1 0:00 1:00 MSD Rule Russia 1921 only - Oct 1 0:00 0 - -# Act No.925 of the Council of Ministers of the USSR (1980-10-24): +# Act No. 925 of the Council of Ministers of the USSR (1980-10-24): Rule Russia 1981 1984 - Apr 1 0:00 1:00 S Rule Russia 1981 1983 - Oct 1 0:00 0 - -# Act No.967 of the Council of Ministers of the USSR (1984-09-13), repeated in -# Act No.227 of the Council of Ministers of the USSR (1989-03-14): +# Act No. 967 of the Council of Ministers of the USSR (1984-09-13), repeated in +# Act No. 227 of the Council of Ministers of the USSR (1989-03-14): Rule Russia 1984 1991 - Sep lastSun 2:00s 0 - Rule Russia 1985 1991 - Mar lastSun 2:00s 1:00 S # @@ -828,7 +831,7 @@ Zone Europe/Brussels 0:17:30 - LMT 1880 # Bulgaria # # From Plamen Simenov via Steffen Thorsen (1999-09-09): -# A document of Government of Bulgaria (No.94/1997) says: +# A document of Government of Bulgaria (No. 94/1997) says: # EET -> EETDST is in 03:00 Local time in last Sunday of March ... # EETDST -> EET is in 04:00 Local time in last Sunday of October # @@ -845,7 +848,7 @@ Zone Europe/Sofia 1:33:16 - LMT 1880 1:00 C-Eur CE%sT 1945 1:00 - CET 1945 Apr 2 3:00 2:00 - EET 1979 Mar 31 23:00 - 2:00 Bulg EE%sT 1982 Sep 26 2:00 + 2:00 Bulg EE%sT 1982 Sep 26 3:00 2:00 C-Eur EE%sT 1991 2:00 E-Eur EE%sT 1997 2:00 EU EE%sT @@ -1062,8 +1065,8 @@ Zone America/Thule -4:35:08 - LMT 1916 Jul 28 # Pituffik air base # after that. # From Mart Oruaas (2000-01-29): -# Regulation no. 301 (1999-10-12) obsoletes previous regulation -# no. 206 (1998-09-22) and thus sticks Estonia to +02:00 GMT for all +# Regulation No. 301 (1999-10-12) obsoletes previous regulation +# No. 206 (1998-09-22) and thus sticks Estonia to +02:00 GMT for all # the year round. The regulation is effective 1999-11-01. # From Toomas Soome (2002-02-21): @@ -1084,7 +1087,7 @@ Zone Europe/Tallinn 1:39:00 - LMT 1880 3:00 Russia MSK/MSD 1989 Mar 26 2:00s 2:00 1:00 EEST 1989 Sep 24 2:00s 2:00 C-Eur EE%sT 1998 Sep 22 - 2:00 EU EE%sT 1999 Nov 1 + 2:00 EU EE%sT 1999 Oct 31 4:00 2:00 - EET 2002 Feb 21 2:00 EU EE%sT @@ -1527,21 +1530,21 @@ Link Europe/Rome Europe/San_Marino # correct data in juridical acts and I found some juridical documents about # changes in the counting of time in Latvia from 1981.... # -# Act No.35 of the Council of Ministers of Latvian SSR of 1981-01-22 ... -# according to the Act No.925 of the Council of Ministers of USSR of 1980-10-24 +# Act No. 35 of the Council of Ministers of Latvian SSR of 1981-01-22 ... +# according to the Act No. 925 of the Council of Ministers of USSR of 1980-10-24 # ...: all year round the time of 2nd time zone + 1 hour, in addition turning # the hands of the clock 1 hour forward on 1 April at 00:00 (GMT 31 March 21:00) # and 1 hour backward on the 1 October at 00:00 (GMT 30 September 20:00). # -# Act No.592 of the Council of Ministers of Latvian SSR of 1984-09-24 ... -# according to the Act No.967 of the Council of Ministers of USSR of 1984-09-13 +# Act No. 592 of the Council of Ministers of Latvian SSR of 1984-09-24 ... +# according to the Act No. 967 of the Council of Ministers of USSR of 1984-09-13 # ...: all year round the time of 2nd time zone + 1 hour, in addition turning # the hands of the clock 1 hour forward on the last Sunday of March at 02:00 # (GMT 23:00 on the previous day) and 1 hour backward on the last Sunday of # September at 03:00 (GMT 23:00 on the previous day). # -# Act No.81 of the Council of Ministers of Latvian SSR of 1989-03-22 ... -# according to the Act No.227 of the Council of Ministers of USSR of 1989-03-14 +# Act No. 81 of the Council of Ministers of Latvian SSR of 1989-03-22 ... +# according to the Act No. 227 of the Council of Ministers of USSR of 1989-03-14 # ...: since the last Sunday of March 1989 in Lithuanian SSR, Latvian SSR, # Estonian SSR and Kaliningrad region of Russian Federation all year round the # time of 2nd time zone (Moscow time minus one hour). On the territory of Latvia @@ -1558,7 +1561,7 @@ Link Europe/Rome Europe/San_Marino # From Andrei Ivanov (2000-03-06): # This year Latvia will not switch to Daylight Savings Time (as specified in # The Regulations of the Cabinet of Ministers of the Rep. of Latvia of -# 29-Feb-2000 (#79) <http://www.lv-laiks.lv/wwwraksti/2000/071072/vd4.htm>, +# 29-Feb-2000 (No. 79) <http://www.lv-laiks.lv/wwwraksti/2000/071072/vd4.htm>, # in Latvian for subscribers only). # From RFE/RL Newsline @@ -1763,6 +1766,18 @@ Zone Europe/Malta 0:58:04 - LMT 1893 Nov 2 0:00s # Valletta # News from Moldova (in russian): # http://ru.publika.md/link_317061.html +# From Roman Tudos (2015-07-02): +# http://lex.justice.md/index.php?action=view&view=doc&lang=1&id=355077 +# From Paul Eggert (2015-07-01): +# The abovementioned official link to IGO1445-868/2014 states that +# 2014-10-26's fallback transition occurred at 03:00 local time. Also, +# http://www.trm.md/en/social/la-30-martie-vom-trece-la-ora-de-vara +# says the 2014-03-30 spring-forward transition was at 02:00 local time. +# Guess that since 1997 Moldova has switched one hour before the EU. + +# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S +Rule Moldova 1997 max - Mar lastSun 2:00 1:00 S +Rule Moldova 1997 max - Oct lastSun 3:00 0 - # Zone NAME GMTOFF RULES FORMAT [UNTIL] Zone Europe/Chisinau 1:55:20 - LMT 1880 @@ -1777,7 +1792,7 @@ Zone Europe/Chisinau 1:55:20 - LMT 1880 2:00 Russia EE%sT 1992 2:00 E-Eur EE%sT 1997 # See Romania commentary for the guessed 1997 transition to EU rules. - 2:00 EU EE%sT + 2:00 Moldova EE%sT # Monaco # Shanks & Pottenger give 0:09:20 for Paris Mean Time; go with Howse's @@ -2123,7 +2138,7 @@ Zone Europe/Bucharest 1:44:24 - LMT 1891 Oct # Russia # From Alexander Krivenyshev (2011-09-15): -# Based on last Russian Government Decree # 725 on August 31, 2011 +# Based on last Russian Government Decree No. 725 on August 31, 2011 # (Government document # http://www.government.ru/gov/results/16355/print/ # in Russian) @@ -2133,7 +2148,7 @@ Zone Europe/Bucharest 1:44:24 - LMT 1891 Oct # http://www.worldtimezone.com/dst_news/dst_news_russia36.htm # From Sanjeev Gupta (2011-09-27): -# Scans of [Decree #23 of January 8, 1992] are available at: +# Scans of [Decree No. 23 of January 8, 1992] are available at: # http://government.consultant.ru/page.aspx?1223966 # They are in Cyrillic letters (presumably Russian). @@ -2144,19 +2159,19 @@ Zone Europe/Bucharest 1:44:24 - LMT 1891 Oct # One source is # http://government.ru/gov/results/16355/ # which, according to translate.google.com, begins "Decree of August 31, -# 2011 No 725" and contains no other dates or "effective date" information. +# 2011 No. 725" and contains no other dates or "effective date" information. # # Another source is # http://www.rg.ru/2011/09/06/chas-zona-dok.html # which, according to translate.google.com, begins "Resolution of the # Government of the Russian Federation on August 31, 2011 N 725" and also # contains "Date first official publication: September 6, 2011 Posted on: -# in the 'RG' - Federal Issue number 5573 September 6, 2011" but which +# in the 'RG' - Federal Issue No. 5573 September 6, 2011" but which # does not contain any "effective date" information. # # Another source is # http://en.wikipedia.org/wiki/Oymyakonsky_District#cite_note-RuTime-7 -# which, in note 8, contains "Resolution #725 of August 31, 2011... +# which, in note 8, contains "Resolution No. 725 of August 31, 2011... # Effective as of after 7 days following the day of the official publication" # but which does not contain any reference to September 6, 2011. # @@ -2364,7 +2379,7 @@ Zone Europe/Simferopol 2:16:24 - LMT 1880 # changed in May. 2:00 E-Eur EE%sT 1994 May # From IATA SSIM (1994/1997), which also says that Kerch is still like Kiev. - 3:00 E-Eur MSK/MSD 1996 Mar 31 3:00s + 3:00 E-Eur MSK/MSD 1996 Mar 31 0:00s 3:00 1:00 MSD 1996 Oct 27 3:00s # IATA SSIM (1997-09) says Crimea switched to EET/EEST. # Assume it happened in March by not changing the clocks. @@ -2499,7 +2514,7 @@ Zone Asia/Novosibirsk 5:31:40 - LMT 1919 Dec 14 6:00 # from current Russia Zone 6 - Krasnoyarsk Time Zone (KRA) UTC +0700 # to Russia Zone 5 - Novosibirsk Time Zone (NOV) UTC +0600 # -# This is according to Government of Russia decree # 740, on September +# This is according to Government of Russia decree No. 740, on September # 14, 2009 "Application in the territory of the Kemerovo region the Fifth # time zone." ("Russia Zone 5" or old "USSR Zone 5" is GMT +0600) # @@ -2922,7 +2937,7 @@ Zone Africa/Ceuta -0:21:16 - LMT 1901 Zone Atlantic/Canary -1:01:36 - LMT 1922 Mar # Las Palmas de Gran C. -1:00 - CANT 1946 Sep 30 1:00 # Canaries T 0:00 - WET 1980 Apr 6 0:00s - 0:00 1:00 WEST 1980 Sep 28 0:00s + 0:00 1:00 WEST 1980 Sep 28 1:00u 0:00 EU WE%sT # IATA SSIM (1996-09) says the Canaries switch at 2:00u, not 1:00u. # Ignore this for now, as the Canaries are part of the EU. @@ -3212,7 +3227,7 @@ Link Europe/Istanbul Asia/Istanbul # Istanbul is in both continents. # From Igor Karpov, who works for the Ukrainian Ministry of Justice, # via Garrett Wollman (2003-01-27): # BTW, I've found the official document on this matter. It's government -# regulations number 509, May 13, 1996. In my poor translation it says: +# regulations No. 509, May 13, 1996. In my poor translation it says: # "Time in Ukraine is set to second timezone (Kiev time). Each last Sunday # of March at 3am the time is changing to 4am and each last Sunday of # October the time at 4am is changing to 3am" @@ -3221,7 +3236,7 @@ Link Europe/Istanbul Asia/Istanbul # Istanbul is in both continents. # On September 20, 2011 the deputies of the Verkhovna Rada agreed to # abolish the transfer clock to winter time. # -# Bill number 8330 of MP from the Party of Regions Oleg Nadoshi got +# Bill No. 8330 of MP from the Party of Regions Oleg Nadoshi got # approval from 266 deputies. # # Ukraine abolishes transfer back to the winter time (in Russian) diff --git a/contrib/tzdata/leap-seconds.list b/contrib/tzdata/leap-seconds.list index 5bac01ba..0a0bacb 100644 --- a/contrib/tzdata/leap-seconds.list +++ b/contrib/tzdata/leap-seconds.list @@ -199,10 +199,10 @@ # current -- the update time stamp, the data and the name of the file # will not change. # -# Updated through IERS Bulletin C49 -# File expires on: 28 December 2015 +# Updated through IERS Bulletin C50 +# File expires on: 28 June 2016 # -#@ 3660249600 +#@ 3676060800 # 2272060800 10 # 1 Jan 1972 2287785600 11 # 1 Jul 1972 @@ -246,4 +246,4 @@ # the hash line is also ignored in the # computation. # -#h 45e70fa7 a9df2033 f4a49ab0 ec648273 7b6c22c +#h 3d037453 3acade76 570bd8f8 be2b8bc9 55ec6fe8 diff --git a/contrib/tzdata/northamerica b/contrib/tzdata/northamerica index 88423e6..660a920 100644 --- a/contrib/tzdata/northamerica +++ b/contrib/tzdata/northamerica @@ -1235,10 +1235,19 @@ Zone America/Goose_Bay -4:01:40 - LMT 1884 # Happy Valley-Goose Bay # west Labrador, Nova Scotia, Prince Edward I -# From Paul Eggert (2006-03-22): +# From Brian Inglis (2015-07-20): +# From the historical weather station records available at: +# https://weatherspark.com/history/28351/1971/Sydney-Nova-Scotia-Canada +# Sydney shares the same time history as Glace Bay, so was +# likely to be the same across the island.... +# Sydney, as the capital and most populous location, or Cape Breton, would +# have been better names for the zone had we known this in 1996. + +# From Paul Eggert (2015-07-20): # Shanks & Pottenger write that since 1970 most of this region has been like # Halifax. Many locales did not observe peacetime DST until 1972; -# Glace Bay, NS is the largest that we know of. +# the Cape Breton area, represented by Glace Bay, is the largest we know of +# (Glace Bay was perhaps not the best name choice but no point changing now). # Shanks & Pottenger also write that Liverpool, NS was the only town # in Canada to observe DST in 1971 but not 1970; for now we'll assume # this is a typo. @@ -1796,13 +1805,13 @@ Zone America/Edmonton -7:33:52 - LMT 1906 Sep # Exact date in October unknown; Sunday October 1 is a reasonable guess. # 3. June 1918: switch to Pacific Daylight Time (GMT-7) # Exact date in June unknown; Sunday June 2 is a reasonable guess. -# note#1: +# note 1: # On Oct 27/1918 when daylight saving ended in the rest of Canada, # Creston did not change its clocks. -# note#2: +# note 2: # During WWII when the Federal Government legislated a mandatory clock change, # Creston did not oblige. -# note#3: +# note 3: # There is no guarantee that Creston will remain on Mountain Standard Time # (UTC-7) forever. # The subject was debated at least once this year by the town Council. diff --git a/contrib/tzdata/southamerica b/contrib/tzdata/southamerica index 6bbc2c8..50d118e 100644 --- a/contrib/tzdata/southamerica +++ b/contrib/tzdata/southamerica @@ -131,7 +131,7 @@ Rule Arg 2000 only - Mar 3 0:00 0 - # Timezone Law (which never was effectively applied) will (would?) be # in effect.... The article is at # http://ar.clarin.com/diario/2001-06-06/e-01701.htm -# ... The Law itself is "Ley No 25155", sanctioned on 1999-08-25, enacted +# ... The Law itself is "Ley No. 25155", sanctioned on 1999-08-25, enacted # 1999-09-17, and published 1999-09-21. The official publication is at: # http://www.boletin.jus.gov.ar/BON/Primera/1999/09-Septiembre/21/PDF/BO21-09-99LEG.PDF # Regretfully, you have to subscribe (and pay) for the on-line version.... @@ -175,15 +175,11 @@ Rule Arg 2000 only - Mar 3 0:00 0 - # http://www.worldtimezone.com/dst_news/dst_news_argentina03.html # http://www.impulsobaires.com.ar/nota.php?id=57832 (in spanish) -# From Rodrigo Severo (2008-10-06): -# Here is some info available at a Gentoo bug related to TZ on Argentina's DST: -# ... -# ------- Comment #1 from [jmdocile] 2008-10-06 16:28 0000 ------- -# Hi, there is a problem with timezone-data-2008e and maybe with -# timezone-data-2008f -# Argentinian law [Number] 25.155 is no longer valid. +# From Juan Manuel Docile in https://bugs.gentoo.org/240339 (2008-10-07) +# via Rodrigo Severo: +# Argentinian law No. 25.155 is no longer valid. # http://www.infoleg.gov.ar/infolegInternet/anexos/60000-64999/60036/norma.htm -# The new one is law [Number] 26.350 +# The new one is law No. 26.350 # http://www.infoleg.gov.ar/infolegInternet/anexos/135000-139999/136191/norma.htm # So there is no summer time in Argentina for now. @@ -771,7 +767,7 @@ Zone America/La_Paz -4:32:36 - LMT 1890 # [ and in a second message (same day): ] # I found the decree. # -# DECRETO No- 7.584, DE 13 DE OUTUBRO DE 2011 +# DECRETO No. 7.584, DE 13 DE OUTUBRO DE 2011 # Link : # http://www.in.gov.br/visualiza/index.jsp?data=13/10/2011&jornal=1000&pagina=6&totalArquivos=6 @@ -1125,7 +1121,7 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 # Conflicts between [1] and [2] were resolved as follows: # # - [1] says the 1910 transition was Jan 1, [2] says Jan 10 and cites -# Boletín Nº 1, Aviso Nº 1 (1910). Go with [2]. +# Boletín No. 1, Aviso No. 1 (1910). Go with [2]. # # - [1] says SMT was -4:42:45, [2] says Chile's official time from # 1916 to 1919 was -4:42:46.3, the meridian of Chile's National @@ -1133,7 +1129,7 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 # Quinta Normal in Santiago. Go with [2], rounding it to -4:42:46. # # - [1] says the 1918 transition was Sep 1, [2] says Sep 10 and cites -# Boletín Nº 22, Aviso Nº 129/1918 (1918-08-23). Go with [2]. +# Boletín No. 22, Aviso No. 129/1918 (1918-08-23). Go with [2]. # # - [1] does not give times for transitions; assume they occur # at midnight mainland time, the current common practice. However, @@ -1533,7 +1529,7 @@ Rule Para 1997 only - Feb lastSun 0:00 0 - # (1999-09) reports no date; go with above sources and Gerd Knops (2001-02-27). Rule Para 1998 2001 - Mar Sun>=1 0:00 0 - # From Rives McDow (2002-02-28): -# A decree was issued in Paraguay (no. 16350) on 2002-02-26 that changed the +# A decree was issued in Paraguay (No. 16350) on 2002-02-26 that changed the # dst method to be from the first Sunday in September to the first Sunday in # April. Rule Para 2002 2004 - Apr Sun>=1 0:00 0 - @@ -1713,8 +1709,19 @@ Rule Uruguay 2005 only - Oct 9 2:00 1:00 S Rule Uruguay 2006 only - Mar 12 2:00 0 - # From Jesper Nørgaard Welen (2006-09-06): # http://www.presidencia.gub.uy/_web/decretos/2006/09/CM%20210_08%2006%202006_00001.PDF -Rule Uruguay 2006 max - Oct Sun>=1 2:00 1:00 S -Rule Uruguay 2007 max - Mar Sun>=8 2:00 0 - +# +# From Steffen Thorsen (2015-06-30): +# ... it looks like they will not be using DST the coming summer: +# http://www.elobservador.com.uy/gobierno-resolvio-que-no-habra-cambio-horario-verano-n656787 +# http://www.republica.com.uy/este-ano-no-se-modificara-el-huso-horario-en-uruguay/523760/ +# From Paul Eggert (2015-06-30): +# Apparently restaurateurs complained that DST caused people to go to the beach +# instead of out to dinner. +# From Pablo Camargo (2015-07-13): +# http://archivo.presidencia.gub.uy/sci/decretos/2015/06/cons_min_201.pdf +# [dated 2015-06-29; repeals Decree 311/006 dated 2006-09-04] +Rule Uruguay 2006 2014 - Oct Sun>=1 2:00 1:00 S +Rule Uruguay 2007 2015 - Mar Sun>=8 2:00 0 - # Zone NAME GMTOFF RULES FORMAT [UNTIL] Zone America/Montevideo -3:44:44 - LMT 1898 Jun 28 -3:44:44 - MMT 1920 May 1 # Montevideo MT @@ -1723,6 +1730,10 @@ Zone America/Montevideo -3:44:44 - LMT 1898 Jun 28 # Venezuela # +# From Paul Eggert (2015-07-28): +# For the 1965 transition see Gaceta Oficial No. 27.619 (1964-12-15), p 205.533 +# http://www.pgr.gob.ve/dmdocuments/1964/27619.pdf +# # From John Stainforth (2007-11-28): # ... the change for Venezuela originally expected for 2007-12-31 has # been brought forward to 2007-12-09. The official announcement was @@ -1734,6 +1745,6 @@ Zone America/Montevideo -3:44:44 - LMT 1898 Jun 28 # Zone NAME GMTOFF RULES FORMAT [UNTIL] Zone America/Caracas -4:27:44 - LMT 1890 -4:27:40 - CMT 1912 Feb 12 # Caracas Mean Time? - -4:30 - VET 1965 # Venezuela Time + -4:30 - VET 1965 Jan 1 0:00 # Venezuela T. -4:00 - VET 2007 Dec 9 3:00 -4:30 - VET diff --git a/contrib/tzdata/zone.tab b/contrib/tzdata/zone.tab index f418e7f..381f245 100644 --- a/contrib/tzdata/zone.tab +++ b/contrib/tzdata/zone.tab @@ -106,8 +106,8 @@ BW -2439+02555 Africa/Gaborone BY +5354+02734 Europe/Minsk BZ +1730-08812 America/Belize CA +4734-05243 America/St_Johns Newfoundland Time, including SE Labrador -CA +4439-06336 America/Halifax Atlantic Time - Nova Scotia (most places), PEI -CA +4612-05957 America/Glace_Bay Atlantic Time - Nova Scotia - places that did not observe DST 1966-1971 +CA +4439-06336 America/Halifax Atlantic Time - Nova Scotia (peninsula), PEI +CA +4612-05957 America/Glace_Bay Atlantic Time - Nova Scotia (Cape Breton) CA +4606-06447 America/Moncton Atlantic Time - New Brunswick CA +5320-06025 America/Goose_Bay Atlantic Time - Labrador - most locations CA +5125-05707 America/Blanc-Sablon Atlantic Standard Time - Quebec - Lower North Shore diff --git a/contrib/tzdata/zone1970.tab b/contrib/tzdata/zone1970.tab index 52d6165..5e81d73 100644 --- a/contrib/tzdata/zone1970.tab +++ b/contrib/tzdata/zone1970.tab @@ -104,8 +104,8 @@ BT +2728+08939 Asia/Thimphu BY +5354+02734 Europe/Minsk BZ +1730-08812 America/Belize CA +4734-05243 America/St_Johns Newfoundland Time, including SE Labrador -CA +4439-06336 America/Halifax Atlantic Time - Nova Scotia (most places), PEI -CA +4612-05957 America/Glace_Bay Atlantic Time - Nova Scotia - places that did not observe DST 1966-1971 +CA +4439-06336 America/Halifax Atlantic Time - Nova Scotia (peninsula), PEI +CA +4612-05957 America/Glace_Bay Atlantic Time - Nova Scotia (Cape Breton) CA +4606-06447 America/Moncton Atlantic Time - New Brunswick CA +5320-06025 America/Goose_Bay Atlantic Time - Labrador - most locations CA +5125-05707 America/Blanc-Sablon Atlantic Standard Time - Quebec - Lower North Shore diff --git a/gnu/usr.bin/binutils/Makefile b/gnu/usr.bin/binutils/Makefile index d8ebdb1..cf5086a 100644 --- a/gnu/usr.bin/binutils/Makefile +++ b/gnu/usr.bin/binutils/Makefile @@ -12,7 +12,7 @@ SUBDIR= doc\ ${_objcopy} \ objdump \ -.if ${MK_ELFTOOLCHAIN_TOOLS} == "no" || ${MK_ELFCOPY_AS_OBJCOPY} == "no" +.if ${MK_ELFCOPY_AS_OBJCOPY} == "no" _objcopy= objcopy .endif diff --git a/lib/Makefile b/lib/Makefile index d17cb5d..031c1b4 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -182,7 +182,7 @@ _clang= clang _cuse= libcuse .endif -.if ${MK_ELFTOOLCHAIN_TOOLS} != "no" +.if ${MK_TOOLCHAIN} != "no" _libelftc= libelftc .endif diff --git a/lib/libc/Makefile b/lib/libc/Makefile index b6d3f9f..2f8865c 100644 --- a/lib/libc/Makefile +++ b/lib/libc/Makefile @@ -95,6 +95,7 @@ NOASM= .include "${LIBC_SRCTOP}/stdtime/Makefile.inc" .include "${LIBC_SRCTOP}/string/Makefile.inc" .include "${LIBC_SRCTOP}/sys/Makefile.inc" +.include "${LIBC_SRCTOP}/secure/Makefile.inc" .include "${LIBC_SRCTOP}/rpc/Makefile.inc" .include "${LIBC_SRCTOP}/uuid/Makefile.inc" .include "${LIBC_SRCTOP}/xdr/Makefile.inc" diff --git a/lib/libc/gen/wordexp.c b/lib/libc/gen/wordexp.c index c7f4b1d..d0ddcf0 100644 --- a/lib/libc/gen/wordexp.c +++ b/lib/libc/gen/wordexp.c @@ -138,8 +138,7 @@ we_askshell(const char *words, wordexp_t *we, int flags) } else if (pid == 0) { /* - * We are the child; just get /bin/sh to run the wordexp - * builtin on `words'. + * We are the child; make /bin/sh expand `words'. */ (void)_sigprocmask(SIG_SETMASK, &oldsigblock, NULL); if ((pdes[1] != STDOUT_FILENO ? @@ -147,7 +146,9 @@ we_askshell(const char *words, wordexp_t *we, int flags) _fcntl(pdes[1], F_SETFD, 0)) < 0) _exit(1); execl(_PATH_BSHELL, "sh", flags & WRDE_UNDEF ? "-u" : "+u", - "-c", "IFS=$1;eval \"$2\";eval \"wordexp $3\"", "", + "-c", "IFS=$1;eval \"$2\";eval \"set -- $3\";IFS=;a=\"$*\";" + "printf '%08x' \"$#\" \"${#a}\";printf '%s\\0' \"$@\"", + "", ifs != NULL ? ifs : " \t\n", flags & WRDE_SHOWERR ? "" : "exec 2>/dev/null", words, (char *)NULL); diff --git a/lib/libc/secure/Makefile.inc b/lib/libc/secure/Makefile.inc new file mode 100644 index 0000000..6f18bde --- /dev/null +++ b/lib/libc/secure/Makefile.inc @@ -0,0 +1,12 @@ +# $FreeBSD$ +# +# libc sources related to security + +.PATH: ${LIBC_SRCTOP}/secure + +# Sources common to both syscall interfaces: +SRCS+= \ + stack_protector.c \ + stack_protector_compat.c + +SYM_MAPS+= ${LIBC_SRCTOP}/secure/Symbol.map diff --git a/lib/libc/secure/Symbol.map b/lib/libc/secure/Symbol.map new file mode 100644 index 0000000..aaa76c1 --- /dev/null +++ b/lib/libc/secure/Symbol.map @@ -0,0 +1,9 @@ +/* + * $FreeBSD$ + */ + +FBSD_1.0 { + __chk_fail; + __stack_chk_fail; + __stack_chk_guard; +}; diff --git a/lib/libc/sys/stack_protector.c b/lib/libc/secure/stack_protector.c index cd5f166..cd5f166 100644 --- a/lib/libc/sys/stack_protector.c +++ b/lib/libc/secure/stack_protector.c diff --git a/lib/libc/sys/stack_protector_compat.c b/lib/libc/secure/stack_protector_compat.c index cacb863..cacb863 100644 --- a/lib/libc/sys/stack_protector_compat.c +++ b/lib/libc/secure/stack_protector_compat.c diff --git a/lib/libc/string/bcopy.3 b/lib/libc/string/bcopy.3 index ede910b..c1bb807 100644 --- a/lib/libc/string/bcopy.3 +++ b/lib/libc/string/bcopy.3 @@ -31,7 +31,7 @@ .\" @(#)bcopy.3 8.1 (Berkeley) 6/4/93 .\" $FreeBSD$ .\" -.Dd August 11, 2015 +.Dd August 14, 2015 .Dt BCOPY 3 .Os .Sh NAME @@ -57,20 +57,6 @@ The two strings may overlap. If .Fa len is zero, no bytes are copied. -.Pp -This function is deprecated (marked as LEGACY in -POSIX.1-2001): use -.Xr memcpy 3 -or -.Xr memmove 3 -in new programs. -Note that the first two arguments are -interchanged for -.Xr memcpy 3 -and -.Xr memmove 3 . -POSIX.1-2008 removes the specification of -.Fn bcopy . .Sh SEE ALSO .Xr memccpy 3 , .Xr memcpy 3 , @@ -89,3 +75,25 @@ before it was moved to for .St -p1003.1-2001 compliance. +.Pp +The +.St -p1003.1-2008 +removes the specification of +.Fn bcopy +and it is marked as LEGACY in +.St -p1003.1-2004 . +New programs should use +.Xr memmove 3 . +If the input and output buffer do not overlap, then +.Xr memcpy 3 +is more efficient. +Note that +.Fn bcopy +takes +.Ar src +and +.Ar dst +in the opposite order from +.Fn memmove +and +.Fn memcpy . diff --git a/lib/libc/sys/Makefile.inc b/lib/libc/sys/Makefile.inc index e672b69..fad970c 100644 --- a/lib/libc/sys/Makefile.inc +++ b/lib/libc/sys/Makefile.inc @@ -21,8 +21,6 @@ PSEUDO+= _clock_gettime.o _gettimeofday.o # Sources common to both syscall interfaces: SRCS+= \ - stack_protector.c \ - stack_protector_compat.c \ __error.c \ interposing_table.c diff --git a/lib/libc/sys/Symbol.map b/lib/libc/sys/Symbol.map index a3a613e..7b3257c 100644 --- a/lib/libc/sys/Symbol.map +++ b/lib/libc/sys/Symbol.map @@ -3,8 +3,8 @@ */ /* - * It'd be nice to have this automatically generated, but we don't - * know to what version they will eventually belong, so for now + * It'd be nice to automatically generate the syscall symbols, but we + * don't know to what version they will eventually belong to, so for now * it has to be manual. */ FBSD_1.0 { @@ -56,7 +56,6 @@ FBSD_1.0 { bind; chdir; chflags; - __chk_fail; chmod; chown; chroot; @@ -281,8 +280,6 @@ FBSD_1.0 { sigwaitinfo; socket; socketpair; - __stack_chk_fail; - __stack_chk_guard; stat; statfs; swapoff; diff --git a/lib/libgeom/geom_xml2tree.c b/lib/libgeom/geom_xml2tree.c index 2c23361..54a31ca 100644 --- a/lib/libgeom/geom_xml2tree.c +++ b/lib/libgeom/geom_xml2tree.c @@ -286,7 +286,7 @@ EndElement(void *userData, const char *name) "element", name); return; } - gc->lg_val = p ? p : strdup("1"); + gc->lg_val = p; LIST_INSERT_HEAD(c, gc, lg_config); return; } diff --git a/lib/libnv/tests/Makefile b/lib/libnv/tests/Makefile index 7fc8d91..38e7f13 100644 --- a/lib/libnv/tests/Makefile +++ b/lib/libnv/tests/Makefile @@ -4,6 +4,7 @@ TESTSDIR= ${TESTSBASE}/lib/libnv ATF_TESTS_CXX= \ dnv_tests \ + nv_array_tests \ nv_tests \ TAP_TESTS_C+= nvlist_add_test diff --git a/lib/libnv/tests/nv_array_tests.cc b/lib/libnv/tests/nv_array_tests.cc new file mode 100644 index 0000000..3de0ee8 --- /dev/null +++ b/lib/libnv/tests/nv_array_tests.cc @@ -0,0 +1,1191 @@ +/*- + * Copyright (c) 2015 Mariusz Zaborski <oshogbo@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/nv.h> +#include <sys/types.h> +#include <sys/socket.h> + +#include <atf-c++.hpp> + +#include <cstdio> +#include <errno.h> +#include <fcntl.h> +#include <limits> +#include <set> +#include <sstream> +#include <string> + +#define fd_is_valid(fd) (fcntl((fd), F_GETFL) != -1 || errno != EBADF) + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_bool_array__basic); +ATF_TEST_CASE_BODY(nvlist_bool_array__basic) +{ + bool testbool[16]; + const bool *const_result; + bool *result; + nvlist_t *nvl; + size_t nitems; + unsigned int i; + const char *key; + + key = "nvl/bool"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + for (i = 0; i < 16; i++) + testbool[i] = (i % 2 == 0); + + nvlist_add_bool_array(nvl, key, testbool, 16); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_bool_array(nvl, key)); + ATF_REQUIRE(nvlist_exists_bool_array(nvl, "nvl/bool")); + + const_result = nvlist_get_bool_array(nvl, key, &nitems); + ATF_REQUIRE_EQ(nitems, 16); + ATF_REQUIRE(const_result != NULL); + for (i = 0; i < nitems; i++) + ATF_REQUIRE_EQ(const_result[i], testbool[i]); + + result = nvlist_take_bool_array(nvl, key, &nitems); + ATF_REQUIRE_EQ(nitems, 16); + ATF_REQUIRE(const_result != NULL); + for (i = 0; i < nitems; i++) + ATF_REQUIRE_EQ(result[i], testbool[i]); + + ATF_REQUIRE(!nvlist_exists_bool_array(nvl, key)); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + + free(result); + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_string_array__basic); +ATF_TEST_CASE_BODY(nvlist_string_array__basic) +{ + const char * const *const_result; + char **result; + nvlist_t *nvl; + size_t nitems; + unsigned int i; + const char *key; + const char *string[8] = { "a", "b", "kot", "foo", + "tests", "nice test", "", "abcdef" }; + + key = "nvl/string"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + nvlist_add_string_array(nvl, key, string, 8); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_string_array(nvl, key)); + ATF_REQUIRE(nvlist_exists_string_array(nvl, "nvl/string")); + + const_result = nvlist_get_string_array(nvl, key, &nitems); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE(nitems == 8); + for (i = 0; i < nitems; i++) { + if (string[i] != NULL) { + ATF_REQUIRE(strcmp(const_result[i], string[i]) == 0); + } else { + ATF_REQUIRE(const_result[i] == string[i]); + } + } + + result = nvlist_take_string_array(nvl, key, &nitems); + ATF_REQUIRE(result != NULL); + ATF_REQUIRE_EQ(nitems, 8); + for (i = 0; i < nitems; i++) { + if (string[i] != NULL) { + ATF_REQUIRE_EQ(strcmp(result[i], string[i]), 0); + } else { + ATF_REQUIRE_EQ(result[i], string[i]); + } + } + + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + + for (i = 0; i < 8; i++) + free(result[i]); + free(result); + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_descriptor_array__basic); +ATF_TEST_CASE_BODY(nvlist_descriptor_array__basic) +{ + int fd[32], *result; + const int *const_result; + nvlist_t *nvl; + size_t nitems; + unsigned int i; + const char *key; + + for (i = 0; i < 32; i++) { + fd[i] = dup(STDERR_FILENO); + ATF_REQUIRE(fd_is_valid(fd[i])); + } + + key = "nvl/descriptor"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_descriptor_array(nvl, key)); + + nvlist_add_descriptor_array(nvl, key, fd, 32); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_descriptor_array(nvl, key)); + ATF_REQUIRE(nvlist_exists_descriptor_array(nvl, "nvl/descriptor")); + + const_result = nvlist_get_descriptor_array(nvl, key, &nitems); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE(nitems == 32); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE(fd_is_valid(const_result[i])); + if (i > 0) + ATF_REQUIRE(const_result[i] != const_result[i - 1]); + } + + result = nvlist_take_descriptor_array(nvl, key, &nitems); + ATF_REQUIRE(result != NULL); + ATF_REQUIRE_EQ(nitems, 32); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE(fd_is_valid(result[i])); + if (i > 0) + ATF_REQUIRE(const_result[i] != const_result[i - 1]); + } + + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + + for (i = 0; i < nitems; i++) { + close(result[i]); + close(fd[i]); + } + free(result); + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_number_array__basic); +ATF_TEST_CASE_BODY(nvlist_number_array__basic) +{ + const uint64_t *const_result; + uint64_t *result; + nvlist_t *nvl; + size_t nitems; + unsigned int i; + const char *key; + const uint64_t number[8] = { 0, UINT_MAX, 7, 123, 90, + 100000, 8, 1 }; + + key = "nvl/number"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + nvlist_add_number_array(nvl, key, number, 8); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_number_array(nvl, key)); + ATF_REQUIRE(nvlist_exists_number_array(nvl, "nvl/number")); + + const_result = nvlist_get_number_array(nvl, key, &nitems); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE(nitems == 8); + for (i = 0; i < nitems; i++) + ATF_REQUIRE_EQ(const_result[i], number[i]); + + result = nvlist_take_number_array(nvl, key, &nitems); + ATF_REQUIRE(result != NULL); + ATF_REQUIRE_EQ(nitems, 8); + for (i = 0; i < nitems; i++) + ATF_REQUIRE_EQ(result[i], number[i]); + + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + + free(result); + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_nvlist_array__basic); +ATF_TEST_CASE_BODY(nvlist_nvlist_array__basic) +{ + nvlist_t *testnvl[8]; + const nvlist_t * const *const_result; + nvlist_t **result; + nvlist_t *nvl; + size_t nitems; + unsigned int i; + const char *somestr[8] = { "a", "b", "c", "d", "e", "f", "g", "h" }; + const char *key; + + for (i = 0; i < 8; i++) { + testnvl[i] = nvlist_create(0); + ATF_REQUIRE(testnvl[i] != NULL); + ATF_REQUIRE_EQ(nvlist_error(testnvl[i]), 0); + nvlist_add_string(testnvl[i], "nvl/string", somestr[i]); + ATF_REQUIRE_EQ(nvlist_error(testnvl[i]), 0); + ATF_REQUIRE(nvlist_exists_string(testnvl[i], "nvl/string")); + } + + key = "nvl/nvlist"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + nvlist_add_nvlist_array(nvl, key, (const nvlist_t * const *)testnvl, 8); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_nvlist_array(nvl, key)); + ATF_REQUIRE(nvlist_exists_nvlist_array(nvl, "nvl/nvlist")); + + const_result = nvlist_get_nvlist_array(nvl, key, &nitems); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE(nitems == 8); + + for (i = 0; i < nitems; i++) { + ATF_REQUIRE_EQ(nvlist_error(const_result[i]), 0); + if (i < nitems - 1) { + ATF_REQUIRE(nvlist_get_array_next(const_result[i]) == + const_result[i + 1]); + } else { + ATF_REQUIRE(nvlist_get_array_next(const_result[i]) == + NULL); + } + ATF_REQUIRE(nvlist_get_parent(const_result[i], NULL) == nvl); + ATF_REQUIRE(nvlist_in_array(const_result[i])); + ATF_REQUIRE(nvlist_exists_string(const_result[i], + "nvl/string")); + ATF_REQUIRE(strcmp(nvlist_get_string(const_result[i], + "nvl/string"), somestr[i]) == 0); + } + + result = nvlist_take_nvlist_array(nvl, key, &nitems); + ATF_REQUIRE(result != NULL); + ATF_REQUIRE_EQ(nitems, 8); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE_EQ(nvlist_error(result[i]), 0); + ATF_REQUIRE(nvlist_get_array_next(result[i]) == NULL); + ATF_REQUIRE(nvlist_get_array_next(const_result[i]) == NULL); + ATF_REQUIRE(!nvlist_in_array(const_result[i])); + } + + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + + for (i = 0; i < 8; i++) { + nvlist_destroy(result[i]); + nvlist_destroy(testnvl[i]); + } + + free(result); + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_clone_array); +ATF_TEST_CASE_BODY(nvlist_clone_array) +{ + nvlist_t *testnvl[8]; + nvlist_t *src, *dst; + const nvlist_t *nvl; + bool testbool[16]; + int testfd[16]; + size_t i, nitems; + const char *string[8] = { "a", "b", "kot", "foo", + "tests", "nice test", "", "abcdef" }; + const char *somestr[8] = { "a", "b", "c", "d", "e", "f", "g", "h" }; + const uint64_t number[8] = { 0, UINT_MAX, 7, 123, 90, + 100000, 8, 1 }; + + for (i = 0; i < 16; i++) { + testbool[i] = (i % 2 == 0); + testfd[i] = dup(STDERR_FILENO); + ATF_REQUIRE(fd_is_valid(testfd[i])); + } + for (i = 0; i < 8; i++) { + testnvl[i] = nvlist_create(0); + ATF_REQUIRE(nvlist_error(testnvl[i]) == 0); + nvlist_add_string(testnvl[i], "nvl/nvl/teststr", somestr[i]); + ATF_REQUIRE(nvlist_error(testnvl[i]) == 0); + } + + src = nvlist_create(0); + ATF_REQUIRE(nvlist_error(src) == 0); + + ATF_REQUIRE(!nvlist_exists_bool_array(src, "nvl/bool")); + nvlist_add_bool_array(src, "nvl/bool", testbool, 16); + ATF_REQUIRE_EQ(nvlist_error(src), 0); + ATF_REQUIRE(nvlist_exists_bool_array(src, "nvl/bool")); + + ATF_REQUIRE(!nvlist_exists_string_array(src, "nvl/string")); + nvlist_add_string_array(src, "nvl/string", string, 8); + ATF_REQUIRE_EQ(nvlist_error(src), 0); + ATF_REQUIRE(nvlist_exists_string_array(src, "nvl/string")); + + ATF_REQUIRE(!nvlist_exists_descriptor_array(src, "nvl/fd")); + nvlist_add_descriptor_array(src, "nvl/fd", testfd, 16); + ATF_REQUIRE_EQ(nvlist_error(src), 0); + ATF_REQUIRE(nvlist_exists_descriptor_array(src, "nvl/fd")); + + ATF_REQUIRE(!nvlist_exists_number_array(src, "nvl/number")); + nvlist_add_number_array(src, "nvl/number", number, 8); + ATF_REQUIRE_EQ(nvlist_error(src), 0); + ATF_REQUIRE(nvlist_exists_number_array(src, "nvl/number")); + + ATF_REQUIRE(!nvlist_exists_nvlist_array(src, "nvl/array")); + nvlist_add_nvlist_array(src, "nvl/array", + (const nvlist_t * const *)testnvl, 8); + ATF_REQUIRE_EQ(nvlist_error(src), 0); + ATF_REQUIRE(nvlist_exists_nvlist_array(src, "nvl/array")); + + dst = nvlist_clone(src); + ATF_REQUIRE(dst != NULL); + + ATF_REQUIRE(nvlist_exists_bool_array(dst, "nvl/bool")); + (void) nvlist_get_bool_array(dst, "nvl/bool", &nitems); + ATF_REQUIRE_EQ(nitems, 16); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE( + nvlist_get_bool_array(dst, "nvl/bool", &nitems)[i] == + nvlist_get_bool_array(src, "nvl/bool", &nitems)[i]); + } + + ATF_REQUIRE(nvlist_exists_string_array(dst, "nvl/string")); + (void) nvlist_get_string_array(dst, "nvl/string", &nitems); + ATF_REQUIRE_EQ(nitems, 8); + for (i = 0; i < nitems; i++) { + if (nvlist_get_string_array(dst, "nvl/string", + &nitems)[i] == NULL) { + ATF_REQUIRE(nvlist_get_string_array(dst, "nvl/string", + &nitems)[i] == nvlist_get_string_array(src, + "nvl/string", &nitems)[i]); + } else { + ATF_REQUIRE(strcmp(nvlist_get_string_array(dst, + "nvl/string", &nitems)[i], nvlist_get_string_array( + src, "nvl/string", &nitems)[i]) == 0); + } + } + + ATF_REQUIRE(nvlist_exists_descriptor_array(dst, "nvl/fd")); + (void) nvlist_get_descriptor_array(dst, "nvl/fd", &nitems); + ATF_REQUIRE_EQ(nitems, 16); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE(fd_is_valid( + nvlist_get_descriptor_array(dst, "nvl/fd", &nitems)[i])); + } + ATF_REQUIRE(nvlist_exists_number_array(dst, "nvl/number")); + (void) nvlist_get_number_array(dst, "nvl/number", &nitems); + ATF_REQUIRE_EQ(nitems, 8); + + for (i = 0; i < nitems; i++) { + ATF_REQUIRE( + nvlist_get_number_array(dst, "nvl/number", &nitems)[i] == + nvlist_get_number_array(src, "nvl/number", &nitems)[i]); + } + + ATF_REQUIRE(nvlist_exists_nvlist_array(dst, "nvl/array")); + (void) nvlist_get_nvlist_array(dst, "nvl/array", &nitems); + ATF_REQUIRE_EQ(nitems, 8); + for (i = 0; i < nitems; i++) { + nvl = nvlist_get_nvlist_array(dst, "nvl/array", &nitems)[i]; + ATF_REQUIRE(nvlist_exists_string(nvl, "nvl/nvl/teststr")); + ATF_REQUIRE(strcmp(nvlist_get_string(nvl, "nvl/nvl/teststr"), + somestr[i]) == 0); + } + + for (i = 0; i < 16; i++) { + close(testfd[i]); + if (i < 8) { + nvlist_destroy(testnvl[i]); + } + } + nvlist_destroy(src); + nvlist_destroy(dst); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_bool_array__move); +ATF_TEST_CASE_BODY(nvlist_bool_array__move) +{ + bool *testbool; + const bool *const_result; + nvlist_t *nvl; + size_t nitems, count; + unsigned int i; + const char *key; + + key = "nvl/bool"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + count = 16; + testbool = (bool*)malloc(sizeof(*testbool) * count); + ATF_REQUIRE(testbool != NULL); + for (i = 0; i < count; i++) + testbool[i] = (i % 2 == 0); + + nvlist_move_bool_array(nvl, key, testbool, count); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_bool_array(nvl, key)); + + const_result = nvlist_get_bool_array(nvl, key, &nitems); + ATF_REQUIRE_EQ(nitems, count); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE(const_result == testbool); + for (i = 0; i < nitems; i++) + ATF_REQUIRE_EQ(const_result[i], (i % 2 == 0)); + + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_string_array__move); +ATF_TEST_CASE_BODY(nvlist_string_array__move) +{ + char **teststr; + const char * const *const_result; + nvlist_t *nvl; + size_t nitems, count; + unsigned int i; + const char *key; + + key = "nvl/string"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + count = 26; + teststr = (char**)malloc(sizeof(*teststr) * count); + ATF_REQUIRE(teststr != NULL); + for (i = 0; i < count; i++) { + teststr[i] = (char*)malloc(sizeof(**teststr) * 2); + ATF_REQUIRE(teststr[i] != NULL); + teststr[i][0] = 'a' + i; + teststr[i][1] = '\0'; + } + + nvlist_move_string_array(nvl, key, teststr, count); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_string_array(nvl, key)); + + const_result = nvlist_get_string_array(nvl, key, &nitems); + ATF_REQUIRE_EQ(nitems, count); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE((intptr_t)const_result == (intptr_t)teststr); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE_EQ(const_result[i][0], (char)('a' + i)); + ATF_REQUIRE_EQ(const_result[i][1], '\0'); + } + + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_nvlist_array__move); +ATF_TEST_CASE_BODY(nvlist_nvlist_array__move) +{ + nvlist **testnv; + const nvlist * const *const_result; + nvlist_t *nvl; + size_t nitems, count; + unsigned int i; + const char *key; + + key = "nvl/nvlist"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_nvlist_array(nvl, key)); + + count = 26; + testnv = (nvlist**)malloc(sizeof(*testnv) * count); + ATF_REQUIRE(testnv != NULL); + for (i = 0; i < count; i++) { + testnv[i] = nvlist_create(0); + ATF_REQUIRE(testnv[i] != NULL); + } + + nvlist_move_nvlist_array(nvl, key, testnv, count); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_nvlist_array(nvl, key)); + + const_result = nvlist_get_nvlist_array(nvl, key, &nitems); + ATF_REQUIRE_EQ(nitems, count); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE((intptr_t)const_result == (intptr_t)testnv); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE_EQ(nvlist_error(const_result[i]), 0); + ATF_REQUIRE(nvlist_empty(const_result[i])); + if (i < nitems - 1) { + ATF_REQUIRE(nvlist_get_array_next(const_result[i]) == + const_result[i + 1]); + } else { + ATF_REQUIRE(nvlist_get_array_next(const_result[i]) == + NULL); + } + ATF_REQUIRE(nvlist_get_parent(const_result[i], NULL) == nvl); + ATF_REQUIRE(nvlist_in_array(const_result[i])); + } + + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_number_array__move); +ATF_TEST_CASE_BODY(nvlist_number_array__move) +{ + uint64_t *testnumber; + const uint64_t *const_result; + nvlist_t *nvl; + size_t nitems, count; + unsigned int i; + const char *key; + + key = "nvl/number"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + count = 1000; + testnumber = (uint64_t*)malloc(sizeof(*testnumber) * count); + ATF_REQUIRE(testnumber != NULL); + for (i = 0; i < count; i++) + testnumber[i] = i; + + nvlist_move_number_array(nvl, key, testnumber, count); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_number_array(nvl, key)); + + const_result = nvlist_get_number_array(nvl, key, &nitems); + ATF_REQUIRE_EQ(nitems, count); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE(const_result == testnumber); + for (i = 0; i < nitems; i++) + ATF_REQUIRE_EQ(const_result[i], i); + + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_descriptor_array__move); +ATF_TEST_CASE_BODY(nvlist_descriptor_array__move) +{ + int *testfd; + const int *const_result; + nvlist_t *nvl; + size_t nitems, count; + unsigned int i; + const char *key; + + key = "nvl/fd"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + count = 50; + testfd = (int*)malloc(sizeof(*testfd) * count); + ATF_REQUIRE(testfd != NULL); + for (i = 0; i < count; i++) { + testfd[i] = dup(STDERR_FILENO); + ATF_REQUIRE(fd_is_valid(testfd[i])); + } + + nvlist_move_descriptor_array(nvl, key, testfd, count); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_descriptor_array(nvl, key)); + + const_result = nvlist_get_descriptor_array(nvl, key, &nitems); + ATF_REQUIRE_EQ(nitems, count); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE(const_result == testfd); + for (i = 0; i < nitems; i++) + ATF_REQUIRE(fd_is_valid(const_result[i])); + + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_arrays__error_null); +ATF_TEST_CASE_BODY(nvlist_arrays__error_null) +{ + nvlist_t *nvl; + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_number_array(nvl, "nvl/number", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_move_number_array(nvl, "nvl/number", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_descriptor_array(nvl, "nvl/fd", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_move_descriptor_array(nvl, "nvl/fd", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_string_array(nvl, "nvl/string", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_move_string_array(nvl, "nvl/string", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_nvlist_array(nvl, "nvl/nvlist", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_move_nvlist_array(nvl, "nvl/nvlist", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_bool_array(nvl, "nvl/bool", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_move_bool_array(nvl, "nvl/bool", NULL, 0); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_arrays__bad_value); +ATF_TEST_CASE_BODY(nvlist_arrays__bad_value) +{ + nvlist_t *nvl, *nvladd[1], **nvlmove; + int fdadd[1], *fdmove; + + nvladd[0] = NULL; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_nvlist_array(nvl, "nvl/nvlist", nvladd, 1); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + nvlmove = (nvlist_t**)malloc(sizeof(*nvlmove)); + ATF_REQUIRE(nvlmove != NULL); + nvlmove[0] = NULL; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_move_nvlist_array(nvl, "nvl/nvlist", nvlmove, 1); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + fdadd[0] = -2; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_descriptor_array(nvl, "nvl/fd", fdadd, 1); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); + + fdmove = (int*)malloc(sizeof(*fdmove)); + ATF_REQUIRE(fdmove != NULL); + fdmove[0] = -2; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_move_descriptor_array(nvl, "nvl/fd", fdmove, 1); + ATF_REQUIRE(nvlist_error(nvl) != 0); + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_nvlist_array__travel); +ATF_TEST_CASE_BODY(nvlist_nvlist_array__travel) +{ + nvlist_t *nvl, *test[5], *nasted; + const nvlist_t *travel; + void *cookie; + int index, i, type; + const char *name; + + for (i = 0; i < 5; i++) { + test[i] = nvlist_create(0); + ATF_REQUIRE(test[i] != NULL); + nvlist_add_number(test[i], "nvl/number", i); + ATF_REQUIRE(nvlist_error(test[i]) == 0); + } + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_nvlist_array(nvl, "nvl/nvlist_array", test, 5); + ATF_REQUIRE(nvlist_error(nvl) == 0); + nasted = nvlist_create(0); + ATF_REQUIRE(nasted != NULL); + nvlist_add_nvlist_array(nasted, "nvl/nvl/nvlist_array", test, 5); + ATF_REQUIRE(nvlist_error(nasted) == 0); + nvlist_move_nvlist(nvl, "nvl/nvl", nasted); + ATF_REQUIRE(nvlist_error(nvl) == 0); + nvlist_add_string(nvl, "nvl/string", "END"); + ATF_REQUIRE(nvlist_error(nvl) == 0); + + cookie = NULL; + index = 0; + travel = nvl; + do { + while ((name = nvlist_next(travel, &type, &cookie)) != NULL) { + if (index == 0) { + ATF_REQUIRE(type == NV_TYPE_NVLIST_ARRAY); + } else if (index >= 1 && index <= 5) { + ATF_REQUIRE(type == NV_TYPE_NUMBER); + } else if (index == 6) { + ATF_REQUIRE(type == NV_TYPE_NVLIST); + } else if (index == 7) { + ATF_REQUIRE(type == NV_TYPE_NVLIST_ARRAY); + } else if (index >= 8 && index <= 12) { + ATF_REQUIRE(type == NV_TYPE_NUMBER); + } else if (index == 13) { + ATF_REQUIRE(type == NV_TYPE_STRING); + } + + if (type == NV_TYPE_NVLIST) { + travel = nvlist_get_nvlist(travel, name); + cookie = NULL; + } else if (type == NV_TYPE_NVLIST_ARRAY) { + travel = nvlist_get_nvlist_array(travel, name, + NULL)[0]; + cookie = NULL; + } + index ++; + } + } while ((travel = nvlist_get_pararr(travel, &cookie)) != NULL); + + for (i = 0; i < 5; i++) + nvlist_destroy(test[i]); + + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_nvlist_array__travel_alternative); +ATF_TEST_CASE_BODY(nvlist_nvlist_array__travel_alternative) +{ + nvlist_t *nvl, *test[5], *nasted; + const nvlist_t *travel, *tmp; + void *cookie; + int index, i, type; + const char *name; + + for (i = 0; i < 5; i++) { + test[i] = nvlist_create(0); + ATF_REQUIRE(test[i] != NULL); + nvlist_add_number(test[i], "nvl/number", i); + ATF_REQUIRE(nvlist_error(test[i]) == 0); + } + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + nvlist_add_nvlist_array(nvl, "nvl/nvlist_array", test, 5); + ATF_REQUIRE(nvlist_error(nvl) == 0); + nasted = nvlist_create(0); + ATF_REQUIRE(nasted != NULL); + nvlist_add_nvlist_array(nasted, "nvl/nvl/nvlist_array", test, 5); + ATF_REQUIRE(nvlist_error(nasted) == 0); + nvlist_move_nvlist(nvl, "nvl/nvl", nasted); + ATF_REQUIRE(nvlist_error(nvl) == 0); + nvlist_add_string(nvl, "nvl/string", "END"); + ATF_REQUIRE(nvlist_error(nvl) == 0); + + cookie = NULL; + index = 0; + tmp = travel = nvl; + do { + do { + travel = tmp; + while ((name = nvlist_next(travel, &type, &cookie)) != + NULL) { + if (index == 0) { + ATF_REQUIRE(type == + NV_TYPE_NVLIST_ARRAY); + } else if (index >= 1 && index <= 5) { + ATF_REQUIRE(type == NV_TYPE_NUMBER); + } else if (index == 6) { + ATF_REQUIRE(type == NV_TYPE_NVLIST); + } else if (index == 7) { + ATF_REQUIRE(type == + NV_TYPE_NVLIST_ARRAY); + } else if (index >= 8 && index <= 12) { + ATF_REQUIRE(type == NV_TYPE_NUMBER); + } else if (index == 13) { + ATF_REQUIRE(type == NV_TYPE_STRING); + } + + if (type == NV_TYPE_NVLIST) { + travel = nvlist_get_nvlist(travel, + name); + cookie = NULL; + } else if (type == NV_TYPE_NVLIST_ARRAY) { + travel = nvlist_get_nvlist_array(travel, + name, NULL)[0]; + cookie = NULL; + } + index ++; + } + cookie = NULL; + } while ((tmp = nvlist_get_array_next(travel)) != NULL); + } while ((tmp = nvlist_get_parent(travel, &cookie)) != NULL); + + for (i = 0; i < 5; i++) + nvlist_destroy(test[i]); + + nvlist_destroy(nvl); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_bool_array__pack); +ATF_TEST_CASE_BODY(nvlist_bool_array__pack) +{ + nvlist_t *nvl, *unpacked; + const char *key; + size_t packed_size, count; + void *packed; + unsigned int i; + const bool *const_result; + bool testbool[16]; + + for (i = 0; i < 16; i++) + testbool[i] = (i % 2 == 0); + + key = "nvl/bool"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + nvlist_add_bool_array(nvl, key, testbool, 16); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_bool_array(nvl, key)); + + packed = nvlist_pack(nvl, &packed_size); + ATF_REQUIRE(packed != NULL); + + unpacked = nvlist_unpack(packed, packed_size, 0); + ATF_REQUIRE(unpacked != NULL); + ATF_REQUIRE_EQ(nvlist_error(unpacked), 0); + ATF_REQUIRE(nvlist_exists_bool_array(unpacked, key)); + + const_result = nvlist_get_bool_array(unpacked, key, &count); + ATF_REQUIRE_EQ(count, 16); + for (i = 0; i < count; i++) { + ATF_REQUIRE_EQ(testbool[i], const_result[i]); + } + + nvlist_destroy(nvl); + nvlist_destroy(unpacked); + free(packed); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_number_array__pack); +ATF_TEST_CASE_BODY(nvlist_number_array__pack) +{ + nvlist_t *nvl, *unpacked; + const char *key; + size_t packed_size, count; + void *packed; + unsigned int i; + const uint64_t *const_result; + const uint64_t number[8] = { 0, UINT_MAX, 7, 123, 90, + 100000, 8, 1 }; + + key = "nvl/number"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + nvlist_add_number_array(nvl, key, number, 8); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_number_array(nvl, key)); + + packed = nvlist_pack(nvl, &packed_size); + ATF_REQUIRE(packed != NULL); + + unpacked = nvlist_unpack(packed, packed_size, 0); + ATF_REQUIRE(unpacked != NULL); + ATF_REQUIRE_EQ(nvlist_error(unpacked), 0); + ATF_REQUIRE(nvlist_exists_number_array(unpacked, key)); + + const_result = nvlist_get_number_array(unpacked, key, &count); + ATF_REQUIRE_EQ(count, 8); + for (i = 0; i < count; i++) { + ATF_REQUIRE_EQ(number[i], const_result[i]); + } + + nvlist_destroy(nvl); + nvlist_destroy(unpacked); + free(packed); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_descriptor_array__pack); +ATF_TEST_CASE_BODY(nvlist_descriptor_array__pack) +{ + nvlist_t *nvl; + const char *key; + size_t nitems; + unsigned int i; + const int *const_result; + int desc[32], fd, socks[2]; + pid_t pid; + + key = "nvl/descriptor"; + + ATF_REQUIRE_EQ(socketpair(PF_UNIX, SOCK_STREAM, 0, socks), 0); + + pid = atf::utils::fork(); + ATF_REQUIRE(pid >= 0); + if (pid == 0) { + /* Child. */ + fd = socks[0]; + close(socks[1]); + for (i = 0; i < 32; i++) { + desc[i] = dup(STDERR_FILENO); + ATF_REQUIRE(fd_is_valid(desc[i])); + } + + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_descriptor_array(nvl, key)); + + nvlist_add_descriptor_array(nvl, key, desc, 32); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_descriptor_array(nvl, key)); + + ATF_REQUIRE(nvlist_send(fd, nvl) >= 0); + + for (i = 0; i < nitems; i++) + close(desc[i]); + } else { + /* Parent */ + fd = socks[1]; + close(socks[0]); + + errno = 0; + nvl = nvlist_recv(fd, 0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(nvlist_exists_descriptor_array(nvl, key)); + + const_result = nvlist_get_descriptor_array(nvl, key, &nitems); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE_EQ(nitems, 32); + for (i = 0; i < nitems; i++) + ATF_REQUIRE(fd_is_valid(const_result[i])); + + atf::utils::wait(pid, 0, "", ""); + } + + nvlist_destroy(nvl); + close(fd); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_string_array__pack); +ATF_TEST_CASE_BODY(nvlist_string_array__pack) +{ + nvlist_t *nvl, *unpacked; + const char *key; + size_t packed_size, count; + void *packed; + unsigned int i; + const char * const *const_result; + const char *string[8] = { "a", "b", "kot", "foo", + "tests", "nice test", "", "abcdef" }; + + key = "nvl/string"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + nvlist_add_string_array(nvl, key, string, 8); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_string_array(nvl, key)); + + packed = nvlist_pack(nvl, &packed_size); + ATF_REQUIRE(packed != NULL); + + unpacked = nvlist_unpack(packed, packed_size, 0); + ATF_REQUIRE(unpacked != NULL); + ATF_REQUIRE_EQ(nvlist_error(unpacked), 0); + ATF_REQUIRE(nvlist_exists_string_array(unpacked, key)); + + const_result = nvlist_get_string_array(unpacked, key, &count); + ATF_REQUIRE_EQ(count, 8); + for (i = 0; i < count; i++) { + ATF_REQUIRE_EQ(strcmp(string[i], const_result[i]), 0); + } + + nvlist_destroy(nvl); + nvlist_destroy(unpacked); + free(packed); +} + +ATF_TEST_CASE_WITHOUT_HEAD(nvlist_nvlist_array__pack); +ATF_TEST_CASE_BODY(nvlist_nvlist_array__pack) +{ + nvlist_t *testnvl[8], *unpacked; + const nvlist_t * const *const_result; + nvlist_t **result; + nvlist_t *nvl; + size_t nitems, packed_size; + unsigned int i; + void *packed; + const char *somestr[8] = { "a", "b", "c", "d", "e", "f", "g", "h" }; + const char *key; + + for (i = 0; i < 8; i++) { + testnvl[i] = nvlist_create(0); + ATF_REQUIRE(testnvl[i] != NULL); + ATF_REQUIRE_EQ(nvlist_error(testnvl[i]), 0); + nvlist_add_string(testnvl[i], "nvl/string", somestr[i]); + ATF_REQUIRE_EQ(nvlist_error(testnvl[i]), 0); + ATF_REQUIRE(nvlist_exists_string(testnvl[i], "nvl/string")); + } + + key = "nvl/nvlist"; + nvl = nvlist_create(0); + ATF_REQUIRE(nvl != NULL); + ATF_REQUIRE(nvlist_empty(nvl)); + ATF_REQUIRE(!nvlist_exists_string_array(nvl, key)); + + nvlist_add_nvlist_array(nvl, key, (const nvlist_t * const *)testnvl, 8); + ATF_REQUIRE_EQ(nvlist_error(nvl), 0); + ATF_REQUIRE(!nvlist_empty(nvl)); + ATF_REQUIRE(nvlist_exists_nvlist_array(nvl, key)); + ATF_REQUIRE(nvlist_exists_nvlist_array(nvl, "nvl/nvlist")); + packed = nvlist_pack(nvl, &packed_size); + ATF_REQUIRE(packed != NULL); + + unpacked = nvlist_unpack(packed, packed_size, 0); + ATF_REQUIRE(unpacked != NULL); + ATF_REQUIRE_EQ(nvlist_error(unpacked), 0); + ATF_REQUIRE(nvlist_exists_nvlist_array(unpacked, key)); + + const_result = nvlist_get_nvlist_array(unpacked, key, &nitems); + ATF_REQUIRE(const_result != NULL); + ATF_REQUIRE_EQ(nitems, 8); + for (i = 0; i < nitems; i++) { + ATF_REQUIRE_EQ(nvlist_error(const_result[i]), 0); + if (i < nitems - 1) { + ATF_REQUIRE(nvlist_get_array_next(const_result[i]) == + const_result[i + 1]); + } else { + ATF_REQUIRE(nvlist_get_array_next(const_result[i]) == + NULL); + } + ATF_REQUIRE(nvlist_get_parent(const_result[i], NULL) == unpacked); + ATF_REQUIRE(nvlist_in_array(const_result[i])); + ATF_REQUIRE(nvlist_exists_string(const_result[i], + "nvl/string")); + ATF_REQUIRE(strcmp(nvlist_get_string(const_result[i], + "nvl/string"), somestr[i]) == 0); + } + + for (i = 0; i < 8; i++) + nvlist_destroy(testnvl[i]); + free(result); + nvlist_destroy(nvl); + nvlist_destroy(unpacked); + free(packed); +} + +ATF_INIT_TEST_CASES(tp) +{ + + ATF_ADD_TEST_CASE(tp, nvlist_bool_array__basic); + ATF_ADD_TEST_CASE(tp, nvlist_string_array__basic); + ATF_ADD_TEST_CASE(tp, nvlist_descriptor_array__basic); + ATF_ADD_TEST_CASE(tp, nvlist_number_array__basic); + ATF_ADD_TEST_CASE(tp, nvlist_nvlist_array__basic) + + ATF_ADD_TEST_CASE(tp, nvlist_clone_array) + + ATF_ADD_TEST_CASE(tp, nvlist_bool_array__move); + ATF_ADD_TEST_CASE(tp, nvlist_string_array__move); + ATF_ADD_TEST_CASE(tp, nvlist_nvlist_array__move); + ATF_ADD_TEST_CASE(tp, nvlist_number_array__move); + ATF_ADD_TEST_CASE(tp, nvlist_descriptor_array__move); + + ATF_ADD_TEST_CASE(tp, nvlist_arrays__error_null); + + ATF_ADD_TEST_CASE(tp, nvlist_arrays__bad_value) + + ATF_ADD_TEST_CASE(tp, nvlist_nvlist_array__travel) + ATF_ADD_TEST_CASE(tp, nvlist_nvlist_array__travel_alternative) + + ATF_ADD_TEST_CASE(tp, nvlist_bool_array__pack) + ATF_ADD_TEST_CASE(tp, nvlist_number_array__pack) + ATF_ADD_TEST_CASE(tp, nvlist_descriptor_array__pack) + ATF_ADD_TEST_CASE(tp, nvlist_string_array__pack) + ATF_ADD_TEST_CASE(tp, nvlist_nvlist_array__pack) +} + diff --git a/lib/libusb/Makefile b/lib/libusb/Makefile index 24d97fd..6560f8f 100644 --- a/lib/libusb/Makefile +++ b/lib/libusb/Makefile @@ -70,8 +70,6 @@ CFLAGS+= -DUSB_GLOBAL_INCLUDE_FILE=\"${LIBUSB_GLOBAL_INCLUDE_FILE}\" CFLAGS+= -I ../../sys .endif -.include <bsd.lib.mk> - # LibUSB v1.0 MLINKS += libusb.3 libusb_init.3 MLINKS += libusb.3 libusb_exit.3 @@ -259,3 +257,5 @@ MLINKS += libusb20.3 libusb20_me_decode.3 MLINKS += libusb20.3 libusb20_desc_foreach.3 MLINKS += libusb20.3 libusb20_strerror.3 MLINKS += libusb20.3 libusb20_error_name.3 + +.include <bsd.lib.mk> diff --git a/sbin/ifconfig/ifconfig.8 b/sbin/ifconfig/ifconfig.8 index 56b5c14..9e31e5b 100644 --- a/sbin/ifconfig/ifconfig.8 +++ b/sbin/ifconfig/ifconfig.8 @@ -28,7 +28,7 @@ .\" From: @(#)ifconfig.8 8.3 (Berkeley) 1/5/94 .\" $FreeBSD$ .\" -.Dd May 15, 2015 +.Dd Aug 12, 2015 .Dt IFCONFIG 8 .Os .Sh NAME @@ -2396,6 +2396,10 @@ Disable local hash computation for RSS hash on the interface. Set a shift parameter for RSS local hash computation. Hash is calculated by using flowid bits in a packet header mbuf which are shifted by the number of this parameter. +.It Cm lacp_fast_timeout +Enable lacp fast-timeout on the interface. +.It Cm -lacp_fast_timeout +Disable lacp fast-timeout on the interface. .El .Pp The following parameters are specific to IP tunnel interfaces, diff --git a/sbin/ifconfig/iflagg.c b/sbin/ifconfig/iflagg.c index 51a6faa..c595dc9 100644 --- a/sbin/ifconfig/iflagg.c +++ b/sbin/ifconfig/iflagg.c @@ -115,6 +115,8 @@ setlaggsetopt(const char *val, int d, int s, const struct afswtch *afp) case -LAGG_OPT_LACP_TXTEST: case LAGG_OPT_LACP_RXTEST: case -LAGG_OPT_LACP_RXTEST: + case LAGG_OPT_LACP_TIMEOUT: + case -LAGG_OPT_LACP_TIMEOUT: break; default: err(1, "Invalid lagg option"); @@ -293,6 +295,8 @@ static struct cmd lagg_cmds[] = { DEF_CMD("-lacp_txtest", -LAGG_OPT_LACP_TXTEST, setlaggsetopt), DEF_CMD("lacp_rxtest", LAGG_OPT_LACP_RXTEST, setlaggsetopt), DEF_CMD("-lacp_rxtest", -LAGG_OPT_LACP_RXTEST, setlaggsetopt), + DEF_CMD("lacp_fast_timeout", LAGG_OPT_LACP_TIMEOUT, setlaggsetopt), + DEF_CMD("-lacp_fast_timeout", -LAGG_OPT_LACP_TIMEOUT, setlaggsetopt), DEF_CMD_ARG("flowid_shift", setlaggflowidshift), }; static struct afswtch af_lagg = { diff --git a/sbin/ipfw/ipfw2.c b/sbin/ipfw/ipfw2.c index 5dea974..9669dc6 100644 --- a/sbin/ipfw/ipfw2.c +++ b/sbin/ipfw/ipfw2.c @@ -2869,14 +2869,14 @@ fill_ip(ipfw_insn_ip *cmd, char *av, int cblen, struct tidx *tstate) case '/': masklen = atoi(p); if (masklen == 0) - d[1] = htonl(0); /* mask */ + d[1] = htonl(0U); /* mask */ else if (masklen > 32) errx(EX_DATAERR, "bad width ``%s''", p); else - d[1] = htonl(~0 << (32 - masklen)); + d[1] = htonl(~0U << (32 - masklen)); break; case '{': /* no mask, assume /24 and put back the '{' */ - d[1] = htonl(~0 << (32 - 24)); + d[1] = htonl(~0U << (32 - 24)); *(--p) = md; break; @@ -2885,7 +2885,7 @@ fill_ip(ipfw_insn_ip *cmd, char *av, int cblen, struct tidx *tstate) /* FALLTHROUGH */ case 0: /* initialization value */ default: - d[1] = htonl(~0); /* force /32 */ + d[1] = htonl(~0U); /* force /32 */ break; } d[0] &= d[1]; /* mask base address with mask */ diff --git a/sbin/ping6/Makefile b/sbin/ping6/Makefile index 35a76e4..707bff4 100644 --- a/sbin/ping6/Makefile +++ b/sbin/ping6/Makefile @@ -3,8 +3,7 @@ PROG= ping6 MAN= ping6.8 -CFLAGS+=-DIPSEC -DKAME_SCOPEID -DUSE_RFC2292BIS \ - -DHAVE_ARC4RANDOM +CFLAGS+=-DIPSEC -DKAME_SCOPEID -DUSE_RFC2292BIS WARNS?= 3 BINOWN= root diff --git a/sbin/ping6/ping6.c b/sbin/ping6/ping6.c index d71c021..03381e0 100644 --- a/sbin/ping6/ping6.c +++ b/sbin/ping6/ping6.c @@ -288,9 +288,6 @@ main(int argc, char *argv[]) { struct timeval last, intvl; struct sockaddr_in6 from, *sin6; -#ifndef HAVE_ARC4RANDOM - struct timeval seed; -#endif struct addrinfo hints, *res; struct sigaction si_sa; int cc, i; @@ -751,17 +748,7 @@ main(int argc, char *argv[]) *datap++ = i; ident = getpid() & 0xFFFF; -#ifndef HAVE_ARC4RANDOM - gettimeofday(&seed, NULL); - srand((unsigned int)(seed.tv_sec ^ seed.tv_usec ^ (long)ident)); - memset(nonce, 0, sizeof(nonce)); - for (i = 0; i < sizeof(nonce); i += sizeof(int)) - *((int *)&nonce[i]) = rand(); -#else - memset(nonce, 0, sizeof(nonce)); - for (i = 0; i < (int)sizeof(nonce); i += sizeof(u_int32_t)) - *((u_int32_t *)&nonce[i]) = arc4random(); -#endif + arc4random_buf(nonce, sizeof(nonce)); optval = 1; if (options & F_DONTFRAG) if (setsockopt(s, IPPROTO_IPV6, IPV6_DONTFRAG, diff --git a/share/man/man4/em.4 b/share/man/man4/em.4 index a9fd11f..ac7319d 100644 --- a/share/man/man4/em.4 +++ b/share/man/man4/em.4 @@ -31,7 +31,7 @@ .\" .\" $FreeBSD$ .\" -.Dd October 11, 2011 +.Dd August 16, 2015 .Dt EM 4 .Os .Sh NAME @@ -205,6 +205,11 @@ Tunables can be set at the prompt before booting the kernel or stored in .Xr loader.conf 5 . .Bl -tag -width indent +.It Va hw.em.disable_crc_stripping +Disable or enable hardware stripping of CRC field. +This is mostly useful on BMC/IPMI shared interfaces where stripping the CRC +causes remote access over IPMI to fail. +Default 0 (enabled). .It Va hw.em.eee_setting Disable or enable Energy Efficient Ethernet. Default 1 (disabled). diff --git a/share/man/man4/man4.arm/am335x_dmtpps.4 b/share/man/man4/man4.arm/am335x_dmtpps.4 new file mode 100644 index 0000000..fadd702 --- /dev/null +++ b/share/man/man4/man4.arm/am335x_dmtpps.4 @@ -0,0 +1,163 @@ +.\" +.\" Copyright (c) 2015 Ian Lepore <ian@freebsd.org> +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd August 12, 2015 +.Dt AM335X_DMTPPS 4 +.Os +.Sh NAME +.Nm am335x_dmtpps +.Nd RFC 2783 Pulse Per Second API driver for AM335x systems +.Sh SYNOPSIS +.Cd "device am335x_dmtpps" +.Pp +Optional in +.Pa /boot/loader.conf : +.Cd hw.am335x_dmtpps.input="pin name" +.\" +.Sh DESCRIPTION +The +.Nm +device driver provides a system time counter that includes precise +capture of Pulse Per Second (PPS) signals emitted by GPS receivers +and other timing devices. +The +.Nm +driver may be compiled into the kernel or loaded as a module. +.Pp +The AM335x timer hardware captures the value of the system time counter +on the leading edge of the PPS pulse. +Because the capture is done by the hardware there is no interrupt +latency in the measurement. +The time counter runs at 24Mhz, providing a measurement resolution +of 42 nanoseconds. +.Pp +To use the PPS timing information provided by this driver with +.Xr ntpd 8 , +symlink the +.Pa /dev/dmtpps +device to +.Pa /dev/pps0 +and configure server +.Va 127.127.22.0 +in +.Xr ntp.conf 5 +to configure a type 22 (ATOM) refclock. +.\" +.Sh DRIVER CONFIGURATION +The AM335x hardware provides four timer devices with a capture input +pin, DMTimer4 through DMTimer7. +Because it also provides the active system time counter, +only one instance of the +.Nm +driver can be active at a time. +The driver uses system pin configuration to determine which hardware +timer device to use. +Configure the timer input pin in the system's FDT data, or by +supplying the pin name using a tunable variable in +.Xr loader.conf 5 . +.Pp +To use a standard kernel and FDT data, use +.Xr loader.conf 5 +to load the +.Nm +module and set the +.Va hw.am335x_dmtpps.input +tunable variable to the name of the input pin, one of the following: +.Pp +.Bl -tag -width "GPMC_ADVn_ALE MMMM" -offset MMMM -compact +.It Em Name +.Em Hardware +.It P8-7 +DMTimer4; Beaglebone P8 header pin 7. +.It P8-8 +DMTimer7; Beaglebone P8 header pin 8. +.It P8-9 +DMTimer5; Beaglebone P8 header pin 9. +.It P8-10 +DMTimer6; Beaglebone P8 header pin 10. +.It GPMC_ADVn_ALE +DMTimer4. +.It GPMC_BEn0_CLE +DMTimer5. +.It GPMC_WEn +DMTimer6. +.It GPMC_OEn_REn +DMTimer7. +.El +.Pp +To configure the +.Nm +driver using FDT data, create a new pinctrl node by referencing the standard +.Va am33xx_pinmux +driver node (which is defined in am33xx.dtsi) in your dts file. +For example: +.Bd -literal + &am33xx_pinmux { + timer4_pins: timer4_pins { + pinctrl-single,pins = <0x90 (PIN_INPUT | MUX_MODE2)>; + }; + }; +.Ed +.Pp +Add pinctrl properties referencing +.Va timer4_pins +to the standard +.Va timer4 +device node (also defined in am33xx.dtsi) by referencing it in +your dts file as follows: +.Bd -literal + &timer4 { + pinctrl-names = "default"; + pinctrl-0 = <&timer4_pins>; + }; +.Ed +.\" +.Sh FILES +.Bl -tag -width ".Pa /dev/dmtpps" -compact +.It Pa /dev/dmtpps +The device providing +.Xr ioctl 2 +access to the RFC 2783 API. +.El +.\" +.Sh SEE ALSO +.Xr timecounters 4 , +.Xr loader.conf 5 , +.Xr ntp.conf 5 , +.Xr ntpd 8 +.\" +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 11.0 . +.\" +.Sh AUTHORS +The +.Nm +device driver and this manual page were written by +.An Ian Lepore Aq Mt ian@FreeBSD.org . diff --git a/share/man/man4/random.4 b/share/man/man4/random.4 index 133fb3b..75a7274 100644 --- a/share/man/man4/random.4 +++ b/share/man/man4/random.4 @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd June 30, 2015 +.Dd August 17, 2015 .Dt RANDOM 4 .Os .Sh NAME @@ -31,6 +31,7 @@ .Nd the entropy device .Sh SYNOPSIS .Cd "device random" +.Cd "options RANDOM_LOADABLE" .Sh DESCRIPTION The .Nm @@ -133,15 +134,49 @@ The .Va kern.random.harvest.mask_bin and .Va kern.random.harvest.mask_symbolic -sysctl -can be used confirm -that your choices are correct. +sysctls +can be used to confirm +that the choices are correct. Note that disabled items in the latter item are listed in square brackets. See .Xr random_harvest 9 for more on the harvesting of entropy. +.Pp +When +.Cd "options RANDOM_LOADABLE" +is used, +the +.Pa /dev/random +device is not created +until an "algorithm module" +is loaded. +Two of these modules +are built by default, +.Em random_fortuna +and +.Em random_yarrow . +The +.Em random_yarrow +module is deprecated, +and will be removed in +.Fx 12. +Use of the Yarrow algorithm +is not encouraged, +but while still present +in the kernel source, +it can be selected with the +.Cd "options RANDOM_YARROW" +kernel option. +Note that these loadable modules +are slightly less efficient +than their compiled-in equivalents. +This is because some functions +must be locked against +load and unload events, +and also must be indirect calls +to allow for removal. .Sh RANDOMNESS The use of randomness in the field of computing is a rather subtle issue because randomness means @@ -294,7 +329,7 @@ It replaces the previous implementation, introduced in .Fx 5.0 . -The older -.Em Yarrow -algorithm remains available -as a compile-time fallback. +The Yarrow algorithm +is no longer supported +by its authors, +and is therefore deprecated. diff --git a/share/man/man4/timecounters.4 b/share/man/man4/timecounters.4 index 9abb522..52c68d7 100644 --- a/share/man/man4/timecounters.4 +++ b/share/man/man4/timecounters.4 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd April 12, 2014 +.Dd August 12, 2015 .Dt TIMECOUNTERS 4 .Os .Sh NAME @@ -96,10 +96,16 @@ compared to others. A negative value means this time counter is broken and should not be used. .El .Pp -The time management code of the kernel chooses one time counter from that list. -The current choice can be read and affected via the +The time management code of the kernel automatically switches to a +higher-quality time counter when it registers, unless the .Va kern.timecounter.hardware -tunable/sysctl. +sysctl has been used to choose a specific device. +.Pp +There is no way to unregister a time counter once it has registered +with the kernel. +If a dynamically loaded module contains a time counter you will not +be able to unload that module, even if the time counter it contains +is not the one currently in use. .Sh SEE ALSO .Xr attimer 4 , .Xr eventtimers 4 , diff --git a/share/man/man5/src.conf.5 b/share/man/man5/src.conf.5 index b1ac394..ee339cf 100644 --- a/share/man/man5/src.conf.5 +++ b/share/man/man5/src.conf.5 @@ -1,7 +1,7 @@ .\" DO NOT EDIT-- this file is automatically generated. .\" from FreeBSD: head/tools/build/options/makeman 284708 2015-06-22 20:21:57Z sjg .\" $FreeBSD$ -.Dd August 1, 2015 +.Dd August 16, 2015 .Dt SRC.CONF 5 .Os .Sh NAME @@ -137,9 +137,8 @@ associated utilities, and examples. .Pp This option only affects amd64/amd64. .It Va WITHOUT_BINUTILS -.\" from FreeBSD: head/tools/build/options/WITHOUT_BINUTILS 286036 2015-07-29 20:02:20Z emaste -Set to not build or install binutils (as, c++-filt, -ld, nm, objcopy, objdump, readelf, size and strip) as part +.\" from FreeBSD: head/tools/build/options/WITHOUT_BINUTILS 286332 2015-08-05 18:30:00Z emaste +Set to not build or install binutils (as, ld, objcopy, and objdump ) as part of the normal system build. The resulting system cannot build programs from source. .Pp @@ -457,18 +456,6 @@ instead of the one from GNU Binutils. .Pp It is a default setting on arm64/aarch64. -.It Va WITHOUT_ELFTOOLCHAIN_TOOLS -.\" from FreeBSD: head/tools/build/options/WITHOUT_ELFTOOLCHAIN_TOOLS 286016 2015-07-29 15:42:22Z emaste -Set to use -.Xr addr2line 1 , -.Xr c++filt 1 , -.Xr nm 1 , -.Xr readelf 1 , -.Xr size 1 , -.Xr strings 1 , -and -.Xr strip 1 -from GNU binutils instead of the ELF Tool Chain project. .It Va WITHOUT_EXAMPLES .\" from FreeBSD: head/tools/build/options/WITHOUT_EXAMPLES 156938 2006-03-21 09:06:24Z ru Set to avoid installing examples to @@ -1228,11 +1215,6 @@ Set to disable symbol versioning when building shared libraries. Set to not build .Xr syscons 4 support files such as keyboard maps, fonts, and screen output maps. -.It Va WITHOUT_SYSINSTALL -.\" from FreeBSD: head/tools/build/options/WITHOUT_SYSINSTALL 183242 2008-09-21 22:02:26Z sam -Set to not build -.Xr sysinstall 8 -and related programs. .It Va WITH_SYSROOT .\" from FreeBSD: head/tools/build/options/WITH_SYSROOT 284708 2015-06-22 20:21:57Z sjg Enable use of sysroot during build. diff --git a/share/man/man9/atomic.9 b/share/man/man9/atomic.9 index 819233b..cee30e6 100644 --- a/share/man/man9/atomic.9 +++ b/share/man/man9/atomic.9 @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd August 9, 2015 +.Dd August 14, 2015 .Dt ATOMIC 9 .Os .Sh NAME @@ -68,7 +68,7 @@ .Fn atomic_testandset_<type> "volatile <type> *p" "u_int v" .Sh DESCRIPTION Each of the atomic operations is guaranteed to be atomic across multiple -processors and in the presence of interrupts. +threads and in the presence of interrupts. They can be used to implement reference counts or as building blocks for more advanced synchronization primitives such as mutexes. .Ss Types @@ -108,59 +108,78 @@ unsigned 16-bit integer .El .Pp These must not be used in MI code because the instructions to implement them -efficiently may not be available. -.Ss Memory Barriers -Memory barriers are used to guarantee the order of data accesses in -two ways. -First, they specify hints to the compiler to not re-order or optimize the -operations. -Second, on architectures that do not guarantee ordered data accesses, -special instructions or special variants of instructions are used to indicate -to the processor that data accesses need to occur in a certain order. -As a result, most of the atomic operations have three variants in order to -include optional memory barriers. -The first form just performs the operation without any explicit barriers. -The second form uses a read memory barrier, and the third variant uses a write -memory barrier. -.Pp -The second variant of each operation includes an +efficiently might not be available. +.Ss Acquire and Release Operations +By default, a thread's accesses to different memory locations might not be +performed in +.Em program order , +that is, the order in which the accesses appear in the source code. +To optimize the program's execution, both the compiler and processor might +reorder the thread's accesses. +However, both ensure that their reordering of the accesses is not visible to +the thread. +Otherwise, the traditional memory model that is expected by single-threaded +programs would be violated. +Nonetheless, other threads in a multithreaded program, such as the +.Fx +kernel, might observe the reordering. +Moreover, in some cases, such as the implementation of synchronization between +threads, arbitrary reordering might result in the incorrect execution of the +program. +To constrain the reordering that both the compiler and processor might perform +on a thread's accesses, the thread should use atomic operations with .Em acquire -memory barrier. -This barrier ensures that the effects of this operation are completed before the -effects of any later data accesses. -As a result, the operation is said to have acquire semantics as it acquires a -pseudo-lock requiring further operations to wait until it has completed. -To denote this, the suffix +and +.Em release +semantics. +.Pp +Most of the atomic operations on memory have three variants. +The first variant performs the operation without imposing any ordering +constraints on memory accesses to other locations. +The second variant has acquire semantics, and the third variant has release +semantics. +In effect, operations with acquire and release semantics establish one-way +barriers to reordering. +.Pp +When an atomic operation has acquire semantics, the effects of the operation +must have completed before any subsequent load or store (by program order) is +performed. +Conversely, acquire semantics do not require that prior loads or stores have +completed before the atomic operation is performed. +To denote acquire semantics, the suffix .Dq Li _acq is inserted into the function name immediately prior to the .Dq Li _ Ns Aq Fa type suffix. -For example, to subtract two integers ensuring that any later writes will -happen after the subtraction is performed, use +For example, to subtract two integers ensuring that subsequent loads and +stores happen after the subtraction is performed, use .Fn atomic_subtract_acq_int . .Pp -The third variant of each operation includes a -.Em release -memory barrier. -This ensures that all effects of all previous data accesses are completed -before this operation takes place. -As a result, the operation is said to have release semantics as it releases -any pending data accesses to be completed before its operation is performed. -To denote this, the suffix +When an atomic operation has release semantics, the effects of all prior +loads or stores (by program order) must have completed before the operation +is performed. +Conversely, release semantics do not require that the effects of the +atomic operation must have completed before any subsequent load or store is +performed. +To denote release semantics, the suffix .Dq Li _rel is inserted into the function name immediately prior to the .Dq Li _ Ns Aq Fa type suffix. -For example, to add two long integers ensuring that all previous -writes will happen first, use +For example, to add two long integers ensuring that all prior loads and +stores happen before the addition, use .Fn atomic_add_rel_long . .Pp -A practical example of using memory barriers is to ensure that data accesses -that are protected by a lock are all performed while the lock is held. -To achieve this, one would use a read barrier when acquiring the lock to -guarantee that the lock is held before any protected operations are performed. -Finally, one would use a write barrier when releasing the lock to ensure that -all of the protected operations are completed before the lock is released. +The one-way barriers provided by acquire and release operations allow the +implementations of common synchronization primitives to express their +ordering requirements without also imposing unnecessary ordering. +For example, for a critical section guarded by a mutex, an acquire operation +when the mutex is locked and a release operation when the mutex is unlocked +will prevent any loads or stores from moving outside of the critical +section. +However, they will not prevent the compiler or processor from moving loads +or stores into the critical section, which does not violate the semantics of +a mutex. .Ss Multiple Processors In multiprocessor systems, the atomicity of the atomic operations on memory depends on support for cache coherence in the underlying architecture. @@ -173,7 +192,7 @@ For example, cache coherence is guaranteed on write-back memory by the and .Tn i386 architectures. -However, on some architectures, cache coherence may not be enabled on all +However, on some architectures, cache coherence might not be enabled on all memory types. To determine if cache coherence is enabled for a non-default memory type, consult the architecture's documentation. diff --git a/share/man/man9/nv.9 b/share/man/man9/nv.9 index e3d7080..b5d755f 100644 --- a/share/man/man9/nv.9 +++ b/share/man/man9/nv.9 @@ -1,5 +1,6 @@ .\" .\" Copyright (c) 2013 The FreeBSD Foundation +.\" Copyright (c) 2013-2015 Mariusz Zaborski <oshogbo@FreeBSD.org> .\" All rights reserved. .\" .\" This documentation was written by Pawel Jakub Dawidek under sponsorship @@ -28,7 +29,7 @@ .\" .\" $FreeBSD$ .\" -.Dd Aug 11, 2015 +.Dd August 15, 2015 .Dt NV 9 .Os .Sh NAME @@ -49,6 +50,7 @@ .Nm nvlist_send , .Nm nvlist_recv , .Nm nvlist_xfer , +.Nm nvlist_in_array , .Nm nvlist_next , .Nm nvlist_add , .Nm nvlist_move , @@ -71,6 +73,8 @@ .Fn nvlist_empty "const nvlist_t *nvl" .Ft int .Fn nvlist_flags "const nvlist_t *nvl" +.Ft bool +.Fn nvlist_in_array "const nvlist_t *nvl" .\" .Ft "nvlist_t *" .Fn nvlist_clone "const nvlist_t *nvl" @@ -115,6 +119,16 @@ .Fn nvlist_exists_descriptor "const nvlist_t *nvl" "const char *name" .Ft bool .Fn nvlist_exists_binary "const nvlist_t *nvl" "const char *name" +.Ft bool +.Fn nvlist_exists_bool_array "const nvlist_t *nvl" "const char *name" +.Ft bool +.Fn nvlist_exists_number_array "const nvlist_t *nvl" "const char *name" +.Ft bool +.Fn nvlist_exists_string_array "const nvlist_t *nvl" "const char *name" +.Ft bool +.Fn nvlist_exists_nvlist_array "const nvlist_t *nvl" "const char *name" +.Ft bool +.Fn nvlist_exists_descriptor_array "const nvlist_t *nvl" "const char *name" .\" .Ft void .Fn nvlist_add_null "nvlist_t *nvl" "const char *name" @@ -134,6 +148,20 @@ .Fn nvlist_add_descriptor "nvlist_t *nvl" "const char *name" "int value" .Ft void .Fn nvlist_add_binary "nvlist_t *nvl" "const char *name" "const void *value" "size_t size" +.Ft void +.Fn nvlist_add_bool_array "nvlist_t *nvl" "const char *name" "const bool *value" "size_t nitems" +. +.Ft void +.Fn nvlist_add_number_array "nvlist_t *nvl" "const char *name" "const uint64_t *value" "size_t nitems" +. +.Ft void +.Fn nvlist_add_string_array "nvlist_t *nvl" "const char *name" "const char * const * value" "size_t nitems" +. +.Ft void +.Fn nvlist_add_nvlist_array "nvlist_t *nvl" "const char *name" "const nvlist_t * const * value" "size_t nitems" +. +.Ft void +.Fn nvlist_add_descriptor_array "nvlist_t *nvl" "const char *name" "const int *value" "size_t nitems" .\" .Ft void .Fn nvlist_move_string "nvlist_t *nvl" "const char *name" "char *value" @@ -143,6 +171,20 @@ .Fn nvlist_move_descriptor "nvlist_t *nvl" "const char *name" "int value" .Ft void .Fn nvlist_move_binary "nvlist_t *nvl" "const char *name" "void *value" "size_t size" +.Ft void +.Fn nvlist_move_bool_array "nvlist_t *nvl" "const char *name" "bool *value" "size_t nitems" +. +.Ft void +.Fn nvlist_move_number_array "nvlist_t *nvl" "const char *name" "uint64_t *value" "size_t nitems" +. +.Ft void +.Fn nvlist_move_string_array "nvlist_t *nvl" "const char *name" "char **value" "size_t nitems" +. +.Ft void +.Fn nvlist_move_nvlist_array "nvlist_t *nvl" "const char *name" "nvlist_t **value" "size_t nitems" +. +.Ft void +.Fn nvlist_move_descriptor_array "nvlist_t *nvl" "const char *name" "int *value" "size_t nitems" .\" .Ft bool .Fn nvlist_get_bool "const nvlist_t *nvl" "const char *name" @@ -156,8 +198,22 @@ .Fn nvlist_get_descriptor "const nvlist_t *nvl" "const char *name" .Ft "const void *" .Fn nvlist_get_binary "const nvlist_t *nvl" "const char *name" "size_t *sizep" +.Ft "const bool *" +.Fn nvlist_get_bool_array "const nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "const uint64_t *" +.Fn nvlist_get_number "const nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "const char * const *" +.Fn nvlist_get_string "const nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "const nvlist_t * const *" +.Fn nvlist_get_nvlist "const nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "const int *" +.Fn nvlist_get_descriptor_array "const nvlist_t *nvl" "const char *name" "size_t *nitems" .Ft "const nvlist_t *" .Fn nvlist_get_parent "const nvlist_t *nvl" "void **cookiep" +.Ft "const nvlist_t *" +.Fn nvlist_get_array_next "const nvlist_t *nvl" +.Ft "const nvlist_t *" +.Fn nvlist_get_pararr "const nvlist_t *nvl" "void **cookiep" .\" .Ft bool .Fn nvlist_take_bool "nvlist_t *nvl" "const char *name" @@ -171,6 +227,16 @@ .Fn nvlist_take_descriptor "nvlist_t *nvl" "const char *name" .Ft "void *" .Fn nvlist_take_binary "nvlist_t *nvl" "const char *name" "size_t *sizep" +.Ft "bool *" +.Fn nvlist_take_bool_array "nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "uint64_t **" +.Fn nvlist_take_number "nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "char **" +.Fn nvlist_take_string "nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "nvlist_t **" +.Fn nvlist_take_nvlist "nvlist_t *nvl" "const char *name" "size_t *nitems" +.Ft "int *" +.Fn nvlist_take_descriptor "nvlist_t *nvl" "const char *name" "size_t *nitems" .\" .Ft void .Fn nvlist_free "nvlist_t *nvl" "const char *name" @@ -191,6 +257,16 @@ .Fn nvlist_free_descriptor "nvlist_t *nvl" "const char *name" .Ft void .Fn nvlist_free_binary "nvlist_t *nvl" "const char *name" +.Ft void +.Fn nvlist_free_bool_array "nvlist_t *nvl" "const char *name" +.Ft void +.Fn nvlist_free_number_array "nvlist_t *nvl" "const char *name" +.Ft void +.Fn nvlist_free_string_array "nvlist_t *nvl" "const char *name" +.Ft void +.Fn nvlist_free_nvlist_array "nvlist_t *nvl" "const char *name" +.Ft void +.Fn nvlist_free_descriptor_array "nvlist_t *nvl" "const char *name" .Sh DESCRIPTION The .Nm libnv @@ -221,6 +297,23 @@ Note that file descriptors can be sent only over domain sockets. .It Sy binary ( NV_TYPE_BINARY ) The value is a binary buffer. +.It Sy bool array ( NV_TYPE_BOOL_ARRAY ) +The value is an array of boolean values. +.It Sy number array ( NV_TYPE_NUMBER_ARRAY ) +The value is an array of numbers, each stored as +.Vt uint64_t . +.It Sy string array ( NV_TYPE_STRING_ARRAY ) +The value is an array of C strings. +.It Sy nvlist array ( NV_TYPE_NVLIST_ARRAY ) +The value is an array of nvlists. +When an nvlist is added to an array, it becomes part of the primary nvlist. +Traversing these arrays can be done using the +.Fn nvlist_get_array_next +and +.Fn nvlist_get_pararr +functions. +.It Sy descriptor array ( NV_TYPE_DESCRIPTOR_ARRAY ) +The value is an array of files descriptors. .El .Pp The @@ -280,6 +373,14 @@ function returns flags used to create the nvlist with the function. .Pp The +.Fn nvlist_in_array +function returns +.Dv true +if +.Fa nvl +is part of an array that is a member of another nvlist. +.Pp +The .Fn nvlist_clone functions clones the given nvlist. The clone shares no resources with its origin. @@ -446,7 +547,12 @@ The .Fn nvlist_exists_string , .Fn nvlist_exists_nvlist , .Fn nvlist_exists_descriptor , -.Fn nvlist_exists_binary +.Fn nvlist_exists_binary , +.Fn nvlist_exists_bool_array , +.Fn nvlist_exists_number_array , +.Fn nvlist_exists_string_array , +.Fn nvlist_exists_nvlist_array , +.Fn nvlist_exists_descriptor_array functions return .Dv true if element of the given name and the given type determined by the function name @@ -464,7 +570,12 @@ The .Fn nvlist_add_stringv , .Fn nvlist_add_nvlist , .Fn nvlist_add_descriptor , -.Fn nvlist_add_binary +.Fn nvlist_add_binary , +.Fn nvlist_add_bool_array , +.Fn nvlist_add_number_array , +.Fn nvlist_add_string_array , +.Fn nvlist_add_nvlist_array , +.Fn nvlist_add_descriptor_array functions add element to the given nvlist. When adding string or binary buffor the functions will allocate memory and copy the data over. @@ -472,6 +583,10 @@ When adding nvlist, the nvlist will be cloned and clone will be added. When adding descriptor, the descriptor will be duplicated using the .Xr dup 2 system call and the new descriptor will be added. +The array functions will fail if there are any +.Dv NULL +elements in the array, or if the array pointer is +.Dv NULL . If an error occurs while adding new element, internal error is set which can be examined using the .Fn nvlist_error @@ -481,10 +596,21 @@ The .Fn nvlist_move_string , .Fn nvlist_move_nvlist , .Fn nvlist_move_descriptor , -.Fn nvlist_move_binary +.Fn nvlist_move_binary , +.Fn nvlist_move_bool_array , +.Fn nvlist_move_number_array , +.Fn nvlist_move_string_array , +.Fn nvlist_move_nvlist_array , +.Fn nvlist_move_descriptor_array functions add new element to the given nvlist, but unlike .Fn nvlist_add_<type> functions they will consume the given resource. +In the case of strings, descriptors, or nvlists every elements must be +unique, or it could cause a double free. +The array functions will fail if there are any +.Dv NULL +elements, or if the array pointer is +.Dv NULL . If an error occurs while adding new element, the resource is destroyed and internal error is set which can be examined using the .Fn nvlist_error @@ -496,20 +622,43 @@ The .Fn nvlist_get_string , .Fn nvlist_get_nvlist , .Fn nvlist_get_descriptor , -.Fn nvlist_get_binary -functions allow to obtain value of the given name. -In case of string, nvlist, descriptor or binary, returned resource should -not be modified - it still belongs to the nvlist. -If element of the given name does not exist, the program will be aborted. -To avoid that the caller should check for existence before trying to obtain -the value or use +.Fn nvlist_get_binary , +.Fn nvlist_get_bool_array , +.Fn nvlist_get_number_array , +.Fn nvlist_get_string_array , +.Fn nvlist_get_nvlist_array , +.Fn nvlist_get_descriptor_array +functions return the value that corresponds to the given key name. +In the case of strings, nvlists, descriptors, binary, or arrays, the returned +resource should not be modified - they still belong to the nvlist. +If an element of the given name does not exist, the program will be aborted. +To avoid this, the caller should check for the existence of the name before +trying to obtain the value, or use the .Xr dnvlist 3 -extension, which allows to provide default value for a missing element. +extension, which can provide a default value in the case of a missing element. The nvlist must not be in error state. .Pp The .Fn nvlist_get_parent -function allows to obtain the parent nvlist from the nested nvlist. +function returns the parent nvlist of the nested nvlist. +.Pp +The +.Fn nvlist_get_array_next +function returns the next element from the array or +.Dv NULL +if the nvlist is not in array or it is the last element. +Note that +.Fn nvlist_get_array_next +only works if you added the nvlist array using the +.Fn nvlist_move_nvlist_array +or +.Fn nvlist_add_nvlist_array +functions. +.Pp +The +.Fn nvlist_get_pararr +function returns the next element in the array, or if not available +the parent of the nested nvlist. .Pp The .Fn nvlist_take_bool , @@ -517,7 +666,12 @@ The .Fn nvlist_take_string , .Fn nvlist_take_nvlist , .Fn nvlist_take_descriptor , -.Fn nvlist_take_binary +.Fn nvlist_take_binary , +.Fn nvlist_take_bool_array , +.Fn nvlist_take_number_array , +.Fn nvlist_take_string_array , +.Fn nvlist_take_nvlist_array , +.Fn nvlist_take_descriptor_array functions return value associated with the given name and remove the element from the nvlist. In case of string and binary values, the caller is responsible for free returned @@ -532,11 +686,27 @@ In case of descriptor, the caller is responsible for closing returned descriptor using the .Fn close 2 system call. -If element of the given name does not exist, the program will be aborted. -To avoid that the caller should check for existence before trying to obtain -the value or use +If an element of the given name does not exist, the program will be aborted. +To avoid that the caller should check for the existence of the given name +before trying to obtain the value, or use the .Xr dnvlist 3 -extension, which allows to provide default value for a missing element. +extension, which can provide a default value in the case of a missing element. +In the case of an array of strings or binary values, the caller is responsible +for freeing every element of the array using the +.Xr free 3 +function. +In the case of an array of nvlists, the caller is responsible for destroying +every element of array using the +.Fn nvlist_destroy +function. +In the case of descriptors, the caller is responsible for closing every +element of array using the +.Fn close 2 +system call. +In every case involving an array, the caller must also free the pointer to +the array using the +.Xr free 3 +function. The nvlist must not be in error state. .Pp The @@ -561,7 +731,12 @@ The .Fn nvlist_free_string , .Fn nvlist_free_nvlist , .Fn nvlist_free_descriptor , -.Fn nvlist_free_binary +.Fn nvlist_free_binary , +.Fn nvlist_free_bool_array , +.Fn nvlist_free_number_array , +.Fn nvlist_free_string_array , +.Fn nvlist_free_nvlist_array , +.Fn nvlist_free_descriptor_array functions remove element of the given name and the given type determined by the function name from the nvlist and free all resources associated with it. If element of the given name and the given type does not exist, the program @@ -679,6 +854,65 @@ do { } } while ((nvl = nvlist_get_parent(nvl, &cookie)) != NULL); .Ed +.Pp +Iterating over every nested nvlist and every nvlist element: +.Bd -literal +nvlist_t *nvl; +const nvlist_t * const *array; +const char *name; +void *cookie; +int type; + +nvl = nvlist_recv(sock, 0); +if (nvl == null) + err(1, "nvlist_recv() failed"); + +cookie = null; +do { + while ((name = nvlist_next(nvl, &type, &cookie)) != NULL) { + if (type == NV_TYPE_NVLIST) { + nvl = nvlist_get_nvlist(nvl, name); + cookie = NULL; + } else if (type == NV_TYPE_NVLIST_ARRAY) { + nvl = nvlist_get_nvlist_array(nvl, name, NULL)[0]; + cookie = NULL; + } + } +} while ((nvl = nvlist_get_pararr(nvl, &cookie)) != NULL); +.Ed +.Pp +Or alternatively: +.Bd -literal +nvlist_t *nvl, *tmp; +const nvlist_t * const *array; +const char *name; +void *cookie; +int type; + +nvl = nvlist_recv(sock, 0); +if (nvl == null) + err(1, "nvlist_recv() failed"); + +cooke = NULL; +tmp = nvl; +do { + do { + nvl = tmp; + while ((name = nvlist_next(nvl, &type, &cookie)) != NULL) { + if (type == NV_TYPE_NVLIST) { + nvl = nvlist_get_nvlist(nvl, + name); + cookie = NULL; + } else if (type == NV_TYPE_NVLIST_ARRAY) { + nvl = nvlist_get_nvlist_array(nvl, name, + NULL)[0]; + cookie = NULL; + } + } + cookie = NULL; + } while ((tmp = nvlist_get_array_next(nvl)) != NULL); +} while ((tmp = nvlist_get_parent(nvl, &cookie)) != NULL); +.Ed .Sh SEE ALSO .Xr close 2 , .Xr dup 2 , diff --git a/share/misc/pci_vendors b/share/misc/pci_vendors index ca35435..a4a8b76 100644 --- a/share/misc/pci_vendors +++ b/share/misc/pci_vendors @@ -3,8 +3,8 @@ # # List of PCI ID's # -# Version: 2012.10.24 -# Date: 2012-10-24 03:15:01 +# Version: 2015.07.31 +# Date: 2015-07-31 03:15:02 # # Maintained by Martin Mares <mj@ucw.cz> and other volunteers from the # PCI ID Project at http://pci-ids.ucw.cz/. @@ -23,44 +23,23 @@ # device device_name <-- single tab # subvendor subdevice subsystem_name <-- two tabs -0000 Gammagraphx, Inc. (or missing ID) -0010 Allied Telesis, Inc +0010 Allied Telesis, Inc (Wrong ID) # This is a relabelled RTL-8139 8139 AT-2500TX V3 Ethernet -001a Ascend Communications, Inc. 001c PEAK-System Technik GmbH 0001 PCAN-PCI CAN-Bus controller 001c 0004 2 Channel CAN Bus SJC1000 001c 0005 2 Channel CAN Bus SJC1000 (Optically Isolated) -0033 Paradyne corp. 003d Lockheed Martin-Marietta Corp # Real TJN ID is e159, but they got it wrong several times --mj 0059 Tiger Jet Network Inc. (Wrong ID) 0070 Hauppauge computer works Inc. - 0003 WinTV PVR-250 - 0009 WinTV PVR-150 - 0801 WinTV PVR-150 - 0807 WinTV PVR-150 - 4000 WinTV PVR-350 - 4001 WinTV PVR-250 (v1) - 4009 WinTV PVR-250 - 4800 WinTV PVR-350 - 4801 WinTV PVR-250 MCE - 4803 WinTV PVR-250 - 7444 WinTV HVR-1600 7801 WinTV HVR-1800 MCE - 8003 WinTV PVR-150 - 8801 WinTV PVR-150 - c108 WinTV-HVR-4400-HD model 1278 - c801 WinTV PVR-150 - e807 WinTV PVR-500 MCE (1st tuner) - e817 WinTV PVR-500 MCE (2nd tuner) 0071 Nebula Electronics Ltd. 0095 Silicon Image, Inc. (Wrong ID) 0680 Ultra ATA/133 IDE RAID CONTROLLER CARD # Wrong ID used in subsystem ID of the TELES.S0/PCI 2.x ISDN adapter 00a7 Teles AG (Wrong ID) -00f5 BFG Technologies, Inc. 0100 Ncipher Corp Ltd 0123 General Dynamics # 018a is not LevelOne but there is a board misprogrammed @@ -70,72 +49,28 @@ 021b Compaq Computer Corporation 8139 HNE-300 (RealTek RTL8139c) [iPaq Networking] 0270 Hauppauge computer works Inc. (Wrong ID) -0291 Davicom Semiconductor, Inc. - 8212 DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40) # SpeedStream is Efficient Networks, Inc, a Siemens Company 02ac SpeedStream 1012 1012 PCMCIA 10/100 Ethernet Card [RTL81xx] -02e0 XFX Pine Group Inc 0303 Hewlett-Packard Company (Wrong ID) -0308 ZyXEL Communications Corporation +0308 ZyXEL Communications Corporation (Wrong ID) 0315 SK-Electronics Co., Ltd. -0357 TTTech AG +0357 TTTech Computertechnik AG (Wrong ID) 000a TTP-Monitoring Card V2.0 -036f Trigem Computer Inc. -0403 Future Technology Devices International Ltd 0432 SCM Microsystems, Inc. 0001 Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet] -0482 Kyocera -# vendor code used for (at a minimum) RSA cards -04b3 IBM Corp. - 4001 Remote System Administration device [RSA2] -050d Belkin -05a9 OmniVision - 8519 OV519 series -05e3 CyberDoor - 0701 CBD516 -066f SigmaTel - 3410 SMTP3410 - 3500 SMTP3500 0675 Dynalink 1700 IS64PH ISDN Adapter 1702 IS64PH ISDN Adapter 1703 ISDN Adapter (PCI Bus, DV, W) 1704 ISDN Adapter (PCI Bus, D, C) -069d Hughes Network Systems (HNS) 0721 Sapphire, Inc. 0777 Ubiquiti Networks, Inc. -# Atheros, 6th Generation, AR5414, 802.11a, 5GHz - 3005 XtremeRange5 0795 Wired Inc. 6663 Butane II (MPEG2 encoder board) 6666 MediaPress (MPEG2 encoder board) -07ca AVerMedia Technologies Inc. -# Expresscard DVB-T tuner sold by Fujitsu for notebooks - 534a Slim mobile Express DVB-T (Fujitsu) - a301 AVerTV 301 - b808 AVerTV DVB-T Volar (USB 2.0) -07d0 ITT Geospatial Systems 07d1 D-Link System Inc -07e2 ELMEG Communication Systems GmbH -0842 NPG, Personal Grand Technology -# Nee Gemplus International, SA -08e6 Gemalto NV -08ff AuthenTec - afe4 [Anchor] AF-S2 FingerLoc Sensor Module 0925 VIA Technologies, Inc. (Wrong ID) - 1234 VT82C686/A/B USB Controller -093a PixArt Imaging Inc. - 010e Innovage Mini Digital Camera - 010f SDC-300 Webcam - 020f Digital Photo Viewer - 2468 CIF Single Chip - 2600 PAC7311 - 2603 Philips Webcam SPC500NC - 2608 Maxell MaxCam RotaWeb - 2620 C3 Tech Mod. 153 -09c1 Arris - 0704 CM 200E Cable Modem 0a89 BREA Technologies Inc 0b0b Rhino Equipment Corp. 0105 Rhino R1T1 @@ -152,9 +87,6 @@ 0905 R1T3 Single T3 Digital Telephony Card 0906 RCB24FXX 24-channel modular analog telphony card 0a06 RCB672FXX 672-channel modular analog telphony card -0b3d Brontes Technologies -0ccd TerraTec Electronic GmbH - 0038 Cinergy T^2 DVB-T Receiver 0e11 Compaq Computer Corporation 0001 PCI to EISA Bridge 0002 PCI to ISA Bridge @@ -262,7 +194,6 @@ c000 Remote Insight Lights-Out Edition f130 NetFlex-3/P ThunderLAN 1.0 f150 NetFlex-3/P ThunderLAN 2.3 -0e21 Cowon Systems, Inc. 0e55 HaSoTec GmbH 0eac SHF Communication Technologies AG 0008 Ethernet Powerlink Managing Node 01 @@ -328,6 +259,7 @@ 4c53 1300 P017 mezzanine (32-bit PMC) 4c53 1310 P017 mezzanine (64-bit PMC) 002f MegaRAID SAS 2208 IOV [Thunderbolt] + 1028 1f39 SPERC8-e 1028 1f3e SPERC 8 0030 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI 0e11 00da ProLiant ML 350 @@ -381,8 +313,23 @@ 005b MegaRAID SAS 2208 [Thunderbolt] 1000 9265 MegaRAID SAS 9265-8i 1000 9266 MegaRAID SAS 9266-8i + 1000 9267 MegaRAID SAS 9267-8i 1000 9268 MegaRAID SAS 9265CV-8i / 9270CV-8i + 1000 9269 MegaRAID SAS 9266-4i + 1000 9270 MegaRAID SAS 9270-8i + 1000 9271 MegaRAID SAS 9271-8i + 1000 9272 MegaRAID SAS 9272-8i + 1000 9273 MegaRAID SAS 9270CV-8i + 1000 9274 MegaRAID SAS 9270-4i + 1000 9275 MegaRAID SAS 9271-8iCC + 1000 9276 MegaRAID SAS 9271-4i + 1000 9285 MegaRAID SAS 9285-8e + 1000 9288 MegaRAID SAS 9285CV-8e + 1000 9290 MegaRAID SAS 9286-8e + 1000 9291 MegaRAID SAS 9286CV-8e + 1000 9295 MegaRAID SAS 9286CV-8eCC 1014 040b ServeRAID M5110 SAS/SATA Controller + 1014 040c ServeRAID M5120 SAS/SATA Controller 1014 0412 ServeRAID M5110e SAS/SATA Controller 1028 1f2d PERC H810 Adapter 1028 1f30 PERC H710 Embedded @@ -392,11 +339,31 @@ 1028 1f35 PERC H710 Adapter 1028 1f37 PERC H710 Mini (for blades) 1028 1f38 PERC H710 Mini (for monolithics) + 15d9 0690 LSI MegaRAID ROMB + 8086 3510 RMS25PB080 RAID Controller 8086 3513 RMS25CB080 RAID Controller 005c SAS1064A PCI-X Fusion-MPT SAS 005d MegaRAID SAS-3 3108 [Invader] + 1000 9361 MegaRAID SAS 9361-8i + 1028 1f41 PERC H830 Adapter + 1028 1f42 PERC H730P Adapter + 1028 1f43 PERC H730 Adapter + 1028 1f47 PERC H730P Mini + 1028 1f48 PERC H730P Mini (for blades) + 1028 1f49 PERC H730 Mini + 1028 1f4a PERC H730 Mini (for blades) + 1028 1f4d PERC FD33xS + 1028 1f4f PERC H730P Slim + 1028 1f54 PERC FD33xD + 17aa 1052 ThinkServer RAID 720i + 17aa 1053 ThinkServer RAID 720ix 005e SAS1066 PCI-X Fusion-MPT SAS 005f MegaRAID SAS-3 3008 [Fury] + 1028 1f44 PERC H330 Adapter + 1028 1f4b PERC H330 Mini + 1028 1f4c PERC H330 Mini (for blades) + 1028 1f4d PERC H330 Embedded (for monolithic) + 1054 306a SAS 3004 iMR ROMB 0060 MegaRAID SAS 1078 1000 1006 MegaRAID SAS 8888ELP 1000 100a MegaRAID SAS 8708ELP @@ -460,8 +427,11 @@ 1137 0073 2008 ROMB 1137 00b0 UCSC RAID SAS 2008M-8i 1137 00b1 UCSC RAID SAS 2008M-8i + 1137 00c2 UCS E-Series Double Wide + 1137 00c3 UCS E-Series Single Wide 15d9 0400 Supermicro SMC2008-iMR 1734 1177 RAID Ctrl SAS 6G 0/1 (D2607) + 17aa 1051 ThinkServer RAID 510i 8086 350d RMS2AF040 RAID Controller 8086 9240 RAID Controller RS2WC080 8086 9241 RAID Controller RS2WC040 @@ -522,6 +492,8 @@ 0095 SAS3108 PCI-Express Fusion-MPT SAS-3 0096 SAS3004 PCI-Express Fusion-MPT SAS-3 0097 SAS3008 PCI-Express Fusion-MPT SAS-3 + 1028 1f45 12GB/s HBA internal + 1028 1f46 12Gbps HBA 0407 MegaRAID 1000 0530 MegaRAID 530 SCSI 320-0X RAID Controller 1000 0531 MegaRAID 531 SCSI 320-4X RAID Controller @@ -605,6 +577,7 @@ 1028 0533 PowerEdge Expandable RAID Controller 4/QC 8086 0520 MegaRAID RAID Controller SRCU41L 8086 0523 MegaRAID RAID Controller SRCS16 + 3050 SAS2008 PCI-Express Fusion-MPT SAS-2 6001 DX1 Multiformat Broadcast HD/SD Encoder/Decoder 1001 Kolter Electronic 0010 PCI 1616 Measurement card with 32 digital I/O lines @@ -616,91 +589,112 @@ 0016 PCI-MFB Analogue I/O board 0017 PROTO-3 PCI Prototyping board 9100 INI-9100/9100W SCSI Host -# nee ATI Technologies Inc. -1002 Advanced Micro Devices [AMD] nee ATI - 1314 Wrestler HDMI Audio [Radeon HD 6250/6310] - 174b 1001 Sapphire PURE Fusion Mini +# nee ATI Technologies, Inc. +1002 Advanced Micro Devices, Inc. [AMD/ATI] + 1304 Kaveri + 1305 Kaveri + 1306 Kaveri + 1307 Kaveri + 1308 Kaveri HDMI/DP Audio Controller + 1309 Kaveri [Radeon R6/R7 Graphics] + 130a Kaveri [Radeon R6 Graphics] + 130b Kaveri [Radeon R4 Graphics] + 130c Kaveri [Radeon R7 Graphics] + 130d Kaveri [Radeon R6 Graphics] + 130e Kaveri [Radeon R5 Graphics] + 130f Kaveri [Radeon R7 Graphics] + 1310 Kaveri + 1311 Kaveri + 1312 Kaveri + 1313 Kaveri [Radeon R7 Graphics] + 1314 Wrestler HDMI Audio + 174b 1001 PURE Fusion Mini + 1315 Kaveri [Radeon R5 Graphics] + 1316 Kaveri [Radeon R5 Graphics] + 1317 Kaveri + 1318 Kaveri [Radeon R5 Graphics] + 131b Kaveri [Radeon R4 Graphics] + 131c Kaveri [Radeon R7 Graphics] + 131d Kaveri [Radeon R6 Graphics] 1714 BeaverCreek HDMI Audio [Radeon HD 6500D and 6400G-6600G series] 103c 168b ProBook 4535s - 3150 M24 1P [Radeon Mobility X600] + 3150 RV380/M24 [Mobility Radeon X600] 103c 0934 nx8220 - 3151 M24 [FireMV 2400] - 3152 RV370 [Mobility Radeon X300] - 3154 M24GL [Mobility FireGL V3200] - 3171 M24 [FireMV 2400] (Secondary) - 3e50 RV380 0x3e50 [Radeon X600] - 3e54 RV380 0x3e54 [FireGL V3200] + 3151 RV380 GL [FireMV 2400] + 3152 RV370/M22 [Mobility Radeon X300] + 3154 RV380/M24 GL [Mobility FireGL V3200] + 3155 RV380 GL [FireMV 2400] + 3171 RV380 GL [FireMV 2400] (Secondary) + 3e50 RV380 [Radeon X600] + 3e54 RV380 GL [FireGL V3200] 3e70 RV380 [Radeon X600] (Secondary) - 4136 RS100 [Radeon IGP320(M)] - 4137 RS200 [Radeon IGP330/340/350] - 4144 R300 AD [Radeon 9500 Pro] - 4145 R300 AE [Radeon 9700 Pro] - 4146 R300 AF [Radeon 9700 Pro] - 4147 R300 AG [FireGL Z1/X1] - 4148 R350 AH [Radeon 9800] - 4149 R350 AI [Radeon 9800] - 414a R350 AJ [Radeon 9800] - 414b R350 AK [FireGL X2] - 4150 RV350 AP [Radeon 9600] + 4136 RS100 [Mobility IGP 320M] + 4137 RS200 [Radeon IGP 340] + 4144 R300 [Radeon 9500] + 4146 R300 [Radeon 9700 PRO] + 4147 R300 GL [FireGL Z1] + 4148 R350 [Radeon 9800/9800 SE] + 4150 RV350 [Radeon 9550/9600/X1050 Series] 1002 0002 R9600 Pro primary (Asus OEM for HP) 1002 0003 R9600 Pro secondary (Asus OEM for HP) 1002 4722 All-in-Wonder 2006 AGP Edition - 1458 4024 Giga-Byte GV-R96128D (Primary) - 148c 2064 PowerColor R96A-C3N - 148c 2066 PowerColor R96A-C3N - 174b 7c19 Sapphire Atlantis Radeon 9600 Pro - 174b 7c29 GC-R9600PRO [Sapphire] (Primary) + 1458 4024 GV-R96128D + 148c 2064 R96A-C3N + 148c 2066 R96A-C3N + 174b 7c19 Atlantis Radeon 9600 Pro + 174b 7c29 GC-R9600PRO 17ee 2002 Radeon 9600 256Mb Primary 18bc 0101 GC-R9600PRO (Primary) - 4151 RV350 AQ [Radeon 9600] + 4151 RV350 [Radeon 9600 Series] 1043 c004 A9600SE - 4152 RV350 AR [Radeon 9600] + 174b 7c37 Radeon 9600 SE + 4152 RV360 [Radeon 9600/X1050 Series] 1002 0002 Radeon 9600XT 1002 4772 All-in-Wonder 9600 XT 1043 c002 Radeon 9600 XT TVD 1043 c01a A9600XT/TD - 174b 7c29 Sapphire Radeon 9600XT + 1462 9510 RX9600XT (MS-8951) + 174b 7c29 Radeon 9600XT 1787 4002 Radeon 9600 XT - 4153 RV350 AS [Radeon 9550] + 4153 RV350 [Radeon 9550] 1043 010c A9550GE/TD 1462 932c RX9550SE-TD128 (MS-8932) - 4154 RV350 AT [FireGL T2] - 4155 RV350 AU [FireGL T2] - 4156 RV350 AV [FireGL T2] - 4157 RV350 AW [FireGL T2] - 4158 68800AX [Mach32] - 4164 R300 AD [Radeon 9500 Pro] (Secondary) - 4165 R300 AE [Radeon 9700 Pro] (Secondary) - 4166 R300 AF [Radeon 9700 Pro] (Secondary) - 4168 R350 [Radeon 9800] (Secondary) - 4170 RV350 AP [Radeon 9600] (Secondary) + 4154 RV350 GL [FireGL T2] + 4155 RV350 [Radeon 9600] + 4157 RV350 GL [FireGL T2] + 4158 68800AX [Graphics Ultra Pro PCI] + 4164 R300 [Radeon 9500 PRO] (Secondary) + 4165 R300 [Radeon 9700 PRO] (Secondary) + 4166 R300 [Radeon 9700 PRO] (Secondary) + 4168 RV350 [Radeon 9800 SE] (Secondary) + 4170 RV350 [Radeon 9550/9600/X1050 Series] (Secondary) 1002 0003 R9600 Pro secondary (Asus OEM for HP) 1002 4723 All-in-Wonder 2006 AGP Edition (Secondary) - 1458 4025 Giga-Byte GV-R96128D (Secondary) - 148c 2067 PowerColor R96A-C3N (Secondary) - 174b 7c28 GC-R9600PRO [Sapphire] (Secondary) + 1458 4025 GV-R96128D (Secondary) + 148c 2067 R96A-C3N (Secondary) + 174b 7c28 GC-R9600PRO (Secondary) 17ee 2003 Radeon 9600 256Mb (Secondary) 18bc 0100 GC-R9600PRO (Secondary) - 4171 RV350 AQ [Radeon 9600] (Secondary) + 4171 RV350 [Radeon 9600] (Secondary) 1043 c005 A9600SE (Secondary) - 4172 RV350 AR [Radeon 9600] (Secondary) + 174b 7c36 Radeon 9600 SE (secondary) + 4172 RV350 [Radeon 9600/X1050 Series] (Secondary) 1002 0003 Radeon 9600XT (Secondary) 1002 4773 All-in-Wonder 9600 XT (Secondary) 1043 c003 A9600XT (Secondary) 1043 c01b A9600XT/TD (Secondary) - 174b 7c28 Sapphire Radeon 9600XT (Secondary) + 174b 7c28 Radeon 9600XT (Secondary) 1787 4003 Radeon 9600 XT (Secondary) - 4173 RV350 AS [Radeon 9550] (Secondary) + 4173 RV350 [Radeon 9550] (Secondary) 1043 010d A9550GE/TD (Secondary) - 4237 RS250 [Radeon Mobility 7000 IGP] - 4242 R200 BB [Radeon All in Wonder 8500DV] + 4242 R200 [All-In-Wonder Radeon 8500 DV] 1002 02aa Radeon 8500 AIW DV Edition - 4243 R200 BC [Radeon All in Wonder 8500] - 4336 RS100 [Radeon IGP320M] + 4243 R200 PCI Bridge [All-in-Wonder Radeon 8500DV] + 4336 RS100 [Radeon IGP 320M] 1002 4336 Pavilion ze4300 ATI Radeon Mobility U1 (IGP 320 M) 103c 0024 Pavilion ze4400 builtin Video 161f 2029 eMachines M5312 builtin Video - 4337 RS200 [Radeon IGP330M/340M/350M] + 4337 RS200M [Radeon IGP 330M/340M/345M/350M] 1014 053a ThinkPad R40e 103c 0850 Radeon IGP 345M 4341 IXP150 AC'97 Audio Controller @@ -711,7 +705,7 @@ 4349 Dual Channel Bus Master PCI IDE Controller 434d IXP AC'97 Modem 4353 SMBus - 4354 215CT [Mach64 CT] + 4354 215CT [Mach64 CT PCI] 4358 210888CX [Mach64 CX] 4361 IXP SB300 AC'97 Audio Controller 4363 SMBus @@ -724,36 +718,36 @@ 105b 0c81 Realtek ALC 653 107b 0300 MX6421 1462 0131 MS-1013 Notebook - 4371 IXP SB400 PCI-PCI Bridge + 4371 IXP SB4x0 PCI-PCI Bridge 103c 308b MX6125 1462 7217 Aspire L250 - 4372 IXP SB400 SMBus Controller + 4372 IXP SB4x0 SMBus Controller 1025 0080 Aspire 5024WLMMi 103c 2a20 Pavilion t3030.de Desktop PC 103c 308b MX6125 1462 0131 MS-1013 Notebook 1462 7217 Aspire L250 - 4373 IXP SB400 USB2 Host Controller + 4373 IXP SB4x0 USB2 Host Controller 1025 0080 Aspire 5024WLMMi 103c 2a20 Pavilion t3030.de Desktop PC 103c 308b MX6125 1462 7217 Aspire L250 - 4374 IXP SB400 USB Host Controller + 4374 IXP SB4x0 USB Host Controller 103c 2a20 Pavilion t3030.de Desktop PC 103c 308b MX6125 1462 7217 Aspire L250 - 4375 IXP SB400 USB Host Controller + 4375 IXP SB4x0 USB Host Controller 1025 0080 Aspire 5024WLMMi 103c 2a20 Pavilion t3030.de Desktop PC 103c 308b MX6125 1462 7217 Aspire L250 - 4376 IXP SB400 IDE Controller + 4376 IXP SB4x0 IDE Controller 1025 0080 Aspire 5024WLMMi 103c 2a20 Pavilion t3030.de Desktop PC 103c 308b MX6125 1462 0131 MS-1013 Notebook 1462 7217 Aspire L250 - 4377 IXP SB400 PCI-ISA Bridge + 4377 IXP SB4x0 PCI-ISA Bridge 1025 0080 Aspire 5024WLMi 103c 2a20 Pavilion t3030.de Desktop PC 103c 308b MX6125 @@ -762,7 +756,7 @@ 1025 0080 Aspire 5024WLMMi 103c 308b MX6125 1462 0131 MS-1013 Notebook - 4379 IXP SB400 Serial ATA Controller + 4379 IXP SB4x0 Serial ATA Controller 1462 7141 Aspire L250 437a IXP SB400 Serial ATA Controller 1002 4379 4379 Serial ATA Controller @@ -780,9 +774,10 @@ 1458 b005 Gigabyte GA-MA69G-S3H Motherboard 1462 7327 K9AG Neo2 17f2 5999 KI690-AM2 Motherboard - 4381 SB400 SATA Controller (RAID 5 mode) + 4381 SB600 SATA Controller (RAID 5 mode) 4382 SB600 AC97 Audio 4383 SBx00 Azalia (Intel HDA) + 1019 2120 A785GM-M 103c 1611 Pavilion DM1Z-3000 103c 280a DC5750 Microtower 1043 8230 M3A78-EH Motherboard @@ -794,6 +789,7 @@ 17f2 5000 KI690-AM2 Motherboard 4384 SBx00 PCI to PCI Bridge 4385 SBx00 SMBus Controller + 1019 2120 A785GM-M 103c 1611 Pavilion DM1Z-3000 103c 280a DC5750 Microtower 1043 82ef M3A78-EH Motherboard @@ -802,7 +798,7 @@ 1458 4385 GA-MA770-DS3rev2.0 Motherboard 1462 7368 K9AG Neo2 15d9 a811 H8DGU - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini 17f2 5000 KI690-AM2 Motherboard 4386 SB600 USB Controller (EHCI) 103c 280a DC5750 Microtower @@ -855,45 +851,51 @@ 103c 1611 Pavilion DM1Z-3000 1043 82ef M3A78-EH Motherboard 1043 8443 M5A88-V EVO - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini 4392 SB7x0/SB8x0/SB9x0 SATA Controller [Non-RAID5 mode] 4393 SB7x0/SB8x0/SB9x0 SATA Controller [RAID5 mode] 4394 SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] 4395 SB8x0/SB9x0 SATA Controller [Storage mode] 4396 SB7x0/SB8x0/SB9x0 USB EHCI Controller + 1019 2120 A785GM-M 103c 1611 Pavilion DM1Z-3000 1043 82ef M3A78-EH Motherboard 1043 8443 M5A88-V EVO 15d9 a811 H8DGU - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini 4397 SB7x0/SB8x0/SB9x0 USB OHCI0 Controller + 1019 2120 A785GM-M 103c 1611 Pavilion DM1Z-3000 1043 82ef M3A78-EH Motherboard 1043 8443 M5A88-V EVO 15d9 a811 H8DGU - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini 4398 SB7x0 USB OHCI1 Controller + 1019 2120 A785GM-M 1043 82ef M3A78-EH Motherboard 15d9 a811 H8DGU 4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller + 1019 2120 A785GM-M 1043 82ef M3A78-EH Motherboard 1043 8443 M5A88-V EVO - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini 439c SB7x0/SB8x0/SB9x0 IDE Controller + 1019 2120 A785GM-M 1043 82ef M3A78-EH Motherboard 439d SB7x0/SB8x0/SB9x0 LPC host controller + 1019 2120 A785GM-M 103c 1611 Pavilion DM1Z-3000 1043 82ef M3A78-EH Motherboard 1043 8443 M5A88-V EVO - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini 43a0 SB700/SB800/SB900 PCI to PCI bridge (PCIE port 0) 43a1 SB700/SB800/SB900 PCI to PCI bridge (PCIE port 1) 43a2 SB900 PCI to PCI bridge (PCIE port 2) 43a3 SB900 PCI to PCI bridge (PCIE port 3) - 4437 RS250 [Radeon Mobility 7000 IGP] + 4437 RS250 [Mobility Radeon 7000 IGP] 4554 210888ET [Mach64 ET] 4654 Mach64 VT - 4742 3D Rage Pro AGP 1X/2X + 4742 3D Rage PRO AGP 2X 1002 0040 Rage Pro Turbo AGP 2X 1002 0044 Rage Pro Turbo AGP 2X 1002 0061 Rage Pro AIW AGP 2X @@ -909,14 +911,12 @@ 1028 c082 Rage Pro Turbo AGP 2X 8086 4152 Xpert 98D AGP 2X 8086 464a Rage Pro Turbo AGP 2X - 4744 3D Rage Pro AGP 1X + 4744 3D Rage PRO AGP 1X 1002 4744 Rage Pro Turbo AGP 8086 4d55 Rage 3D Pro AGP 1X [Intel MU440EX] - 4747 3D Rage Pro - 4749 3D Rage Pro + 4749 3D Rage PRO PCI 1002 0061 Rage Pro AIW 1002 0062 Rage Pro AIW - 474c Rage XC 474d Rage XL AGP 2X 1002 0004 Xpert 98 RXL AGP 2X 1002 0008 Xpert 98 RXL AGP 2X @@ -929,14 +929,13 @@ 474f Rage XL 1002 0008 Rage XL 1002 474f Rage XL - 4750 3D Rage Pro 215GP + 4750 3D Rage Pro PCI 1002 0040 Rage Pro Turbo 1002 0044 Rage Pro Turbo 1002 0080 Rage Pro Turbo 1002 0084 Rage Pro Turbo 1002 4750 Rage Pro Turbo - 4751 3D Rage Pro 215GQ - 4752 Rage XL + 4752 Rage XL PCI 0e11 001e Proliant Rage XL 1002 0008 Rage XL 1002 4752 Proliant Rage XL @@ -949,16 +948,18 @@ 1028 014a PowerEdge 1750 1028 0165 PowerEdge 750 103c 10e1 NetServer Rage XL + 103c 3208 ProLiant DL140 G2 107b 6400 6400 Server 1734 007a PRIMERGY RX/TX series onboard VGA + 1734 1073 Primergy Econel 200 D2020 mainboard 8086 3411 SDS2 Mainboard 8086 3427 S875WP1-E mainboard 8086 5744 S845WD1-E mainboard 4753 Rage XC 1002 4753 Rage XC - 4754 3D Rage I/II 215GT [Mach64 GT] - 4755 3D Rage II+ 215GTB [Mach64 GTB] - 4756 3D Rage IIC 215IIC [Mach64 GT IIC] + 4754 3D Rage II/II+ PCI [Mach64 GT] + 4755 Mach64 GTB [3D Rage II+ DVD] + 4756 3D Rage IIC PCI [Mach64 GT IIC] 1002 4756 Rage IIC 4757 3D Rage IIC AGP 1002 4757 Rage IIC AGP @@ -967,49 +968,44 @@ 1028 4082 Rage 3D IIC 1028 8082 Rage 3D IIC 1028 c082 Rage 3D IIC - 4758 210888GX [Mach64 GX] - 4759 3D Rage IIC + 4758 210888GX [Mach64 GX PCI] + 4759 3D Rage IIC PCI 475a 3D Rage IIC AGP 1002 0084 Rage 3D Pro AGP 2x XPERT 98 1002 0087 Rage 3D IIC 1002 475a Rage IIC AGP - 4964 RV250 Id [Radeon 9000] - 4965 RV250 Ie [Radeon 9000] - 4966 R250 If [Radeon 9000] + 4966 RV250 [Radeon 9000 Series] 10f1 0002 RV250 If [Tachyon G9000 PRO] 148c 2039 RV250 If [Radeon 9000 Pro "Evil Commando"] 1509 9a00 RV250 If [Radeon 9000 "AT009"] 1681 0040 RV250 If [3D prophet 9000] - 174b 7176 RV250 If [Sapphire Radeon 9000 Pro] + 174b 7176 Radeon 9000 Pro 174b 7192 RV250 If [Radeon 9000 "Atlantis"] 17af 2005 RV250 If [Excalibur Radeon 9000 Pro] 17af 2006 RV250 If [Excalibur Radeon 9000] - 4967 RV250 Ig [Radeon 9000] 496e RV250 [Radeon 9000] (Secondary) - 4a48 R420 JH [Radeon X800] - 4a49 R420 JI [Radeon X800PRO] - 4a4a R420 JJ [Radeon X800SE] - 4a4b R420 JK [Radeon X800] - 4a4c R420 JL [Radeon X800] - 4a4d R420 JM [FireGL X3] - 4a4e R420 JN [Mobility Radeon 9800] - 4a4f R420 [Radeon X800 AGP] - 4a50 R420 JP [Radeon X800XT] - 4a54 R420 [Radeon X800 VE] + 4a49 R420 [Radeon X800 PRO/GTO AGP] + 174b 2620 R420 [Radeon X800 GTO AGP] + 4a4a R420 [Radeon X800 GT AGP] + 4a4b R420 [Radeon X800 AGP Series] + 4a4d R420 GL [FireGL X3-256] + 4a4e RV420/M18 [Mobility Radeon 9800] + 4a4f R420 [Radeon X850 AGP] + 4a50 R420 [Radeon X800 XT Platinum Edition AGP] + 4a54 R420 [Radeon X800 VE AGP] + 1002 4422 All-In-Wonder X800 VE AGP 4a69 R420 [Radeon X800 PRO/GTO] (Secondary) 4a6a R420 [Radeon X800] (Secondary) - 4a6b R420 [Radeon X800] (Secondary) - 4a70 R420 [X800XT-PE] (Secondary) + 4a6b R420 [Radeon X800 XT AGP] (Secondary) + 4a70 R420 [Radeon X800 XT Platinum Edition AGP] (Secondary) 4a74 R420 [Radeon X800 VE] (Secondary) - 4b48 R481 [Radeon X850 PCIe] - 4b49 R480 [Radeon X850XT] - 4b4a R480 [Radeon X850SE AGP] - 4b4b R480 [Radeon X850Pro] - 4b4c R481 [Radeon X850XT-PE] - 4b69 R480 [Radeon X850XT] (Secondary) - 4b6b R480 [Radeon X850Pro] (Secondary) - 4b6c R481 [Radeon X850XT-PE] (Secondary) - 4c42 3D Rage LT Pro AGP-133 + 4b49 R481 [Radeon X850 XT AGP] + 4b4b R481 [Radeon X850 PRO AGP] + 4b4c R481 [Radeon X850 XT Platinum Edition AGP] + 4b69 R481 [Radeon X850 XT AGP] (Secondary) + 4b6b R481 [Radeon X850 PRO AGP] (Secondary) + 4b6c R481 [Radeon X850 XT Platinum Edition AGP] (Secondary) + 4c42 3D Rage LT PRO AGP 2X 0e11 b0e7 Rage LT Pro (Compaq Presario 5240) 0e11 b0e8 Rage 3D LT Pro 0e11 b10e 3D Rage LT Pro (Compaq Armada 1750) @@ -1018,19 +1014,17 @@ 1002 4c42 Rage LT Pro AGP 2X 1002 8001 Rage LT Pro AGP 2X 1028 0085 Rage 3D LT Pro - 4c44 3D Rage LT Pro AGP-66 - 4c45 Rage Mobility M3 AGP - 4c46 Rage Mobility M3 AGP 2x + 4c46 Rage Mobility 128 AGP 2X/Mobility M3 1002 0155 IBM Thinkpad A22p 1014 0155 IBM Thinkpad A22p 1028 00b1 Latitude C600 - 4c47 3D Rage LT-G 215LG - 4c49 3D Rage LT Pro + 4c47 3D Rage IIC PCI / Mobility Radeon 7500/7500C + 4c49 3D Rage LT PRO PCI 1002 0004 Rage LT Pro 1002 0040 Rage LT Pro 1002 0044 Rage LT Pro 1002 4c49 Rage LT Pro - 4c4d Rage Mobility P/M AGP 2x + 4c4d Rage Mobility AGP 2x Series 0e11 b111 Armada M700 0e11 b160 Armada E500 1002 0084 Xpert 98 AGP 2X (Mobility) @@ -1039,23 +1033,20 @@ 1028 00bb Latitude CPx 1179 ff00 Satellite 1715XCDS laptop 13bd 1019 PC-AR10 - 4c4e Rage Mobility L AGP 2x - 4c50 3D Rage LT Pro + 4c50 3D Rage LT PRO PCI 1002 4c50 Rage LT Pro - 4c51 3D Rage LT Pro - 4c52 Rage Mobility P/M + 4c52 Rage Mobility-M1 PCI 1033 8112 Versa Note VXi - 4c53 Rage Mobility L 4c54 264LT [Mach64 LT] - 4c57 RV200 [Mobility Radeon 7500] + 4c57 RV200/M7 [Mobility Radeon 7500] 1014 0517 ThinkPad T30 - 1014 0530 ThinkPad T42 2373-4WU + 1014 0530 ThinkPad T4x Series 1028 00e6 Radeon Mobility M7 LW (Dell Inspiron 8100) 1028 012a Latitude C640 1043 1622 Mobility Radeon M7 (L3C/S) 144d c006 Radeon Mobility M7 LW in vpr Matrix 170B4 - 4c58 Radeon RV200 LX [Mobility FireGL 7800 M7] - 4c59 RV100 LY [Mobility Radeon 7000] + 4c58 RV200/M7 GL [Mobility FireGL 7800] + 4c59 RV100/M6 [Rage/Radeon Mobility Series] 0e11 b111 Evo N600c 1014 0235 ThinkPad A30/A30p (2652/2653) 1014 0239 ThinkPad X22/X23/X24 @@ -1063,66 +1054,56 @@ 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 104d 8140 PCG-Z1SP laptop 1509 1930 Medion MD9703 - 4c5a RV100 LZ [Mobility Radeon 7000] - 4c64 Radeon RV250 Ld [Radeon Mobility 9000 M9] - 4c65 Radeon RV250 Le [Radeon Mobility 9000 M9] - 4c66 Radeon RV250 [Mobility FireGL 9000] + 4c66 RV250/M9 GL [Mobility FireGL 9000/Radeon 9000] 1014 054d ThinkPad T41 - 4c67 Radeon RV250 Lg [Radeon Mobility 9000 M9] -# Secondary chip to the Lf - 4c6e Radeon RV250 Ln [Radeon Mobility 9000 M9] (Secondary) - 4d46 Rage Mobility M4 AGP - 4d4c Rage Mobility M4 AGP + 4c6e RV250/M9 [Mobility Radeon 9000] (Secondary) + 4d46 Rage Mobility 128 AGP 4X/Mobility M4 4d52 Theater 550 PRO PCI [ATI TV Wonder 550] 4d53 Theater 550 PRO PCIe - 4e44 Radeon R300 ND [Radeon 9700 Pro] + 4e44 R300 [Radeon 9700/9700 PRO] 1002 515e Radeon ES1000 1002 5965 Radeon ES1000 - 4e45 Radeon R300 NE [Radeon 9500 Pro] + 4e45 R300 [Radeon 9500 PRO/9700] 1002 0002 Radeon R300 NE [Radeon 9500 Pro] 1681 0002 Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] - 4e46 R300 NF [Radeon 9600 TX] - 4e47 Radeon R300 NG [FireGL X1] - 4e48 Radeon R350 [Radeon 9800 Pro] - 4e49 Radeon R350 [Radeon 9800] - 4e4a R360 NJ [Radeon 9800 XT] + 4e46 R300 [Radeon 9600 TX] + 4e47 R300 GL [FireGL X1] + 4e48 R350 [Radeon 9800 Series] + 4e49 R350 [Radeon 9800] + 4e4a R360 [Radeon 9800 XXL/XT] 1002 4e4a R360 [Radeon 9800 XT] - 4e4b R350 NK [FireGL X2] - 4e50 RV350 [Mobility Radeon 9600 M10] + 4e4b R350 GL [FireGL X2 AGP Pro] + 4e50 RV350/M10 / RV360/M11 [Mobility Radeon 9600 (PRO) / 9700] 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: ATI RV360/M11 [Mobility Radeon 9700] 103c 088c NC8000 laptop 103c 0890 NC6000 laptop 144d c00c P35 notebook 1462 0311 MSI M510A 1734 1055 Amilo M1420W - 4e51 RV350 NQ [Mobility Radeon 9600] - 4e52 RV350 [Mobility Radeon 9600 M10] + 4e51 RV350 [Radeon 9550/9600/X1050 Series] + 4e52 RV350/M10 [Mobility Radeon 9500/9700 SE] 144d c00c P35 notebook - 4e53 RV350 NS [Mobility Radeon 9600] - 4e54 M10 NT [FireGL Mobility T2] - 4e56 M11 NV [FireGL Mobility T2e] - 4e64 Radeon R300 [Radeon 9700 Pro] (Secondary) - 4e65 Radeon R300 [Radeon 9500 Pro] (Secondary) + 4e54 RV350/M10 GL [Mobility FireGL T2] + 4e56 RV360/M12 [Mobility Radeon 9550] + 4e64 R300 [Radeon 9700 PRO] (Secondary) + 4e65 R300 [Radeon 9500 PRO] (Secondary) 1002 0003 Radeon R300 NE [Radeon 9500 Pro] 1681 0003 Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary) - 4e66 RV350 NF [Radeon 9600] (Secondary) - 4e67 Radeon R300 [FireGL X1] (Secondary) - 4e68 Radeon R350 [Radeon 9800 Pro] (Secondary) - 4e69 Radeon R350 [Radeon 9800] (Secondary) - 4e6a RV350 NJ [Radeon 9800 XT] (Secondary) + 4e66 RV350 [Radeon 9600] (Secondary) + 4e67 R300 GL [FireGL X1] (Secondary) + 4e68 R350 [Radeon 9800 PRO] (Secondary) + 4e69 R350 [Radeon 9800] (Secondary) + 4e6a RV350 [Radeon 9800 XT] (Secondary) 1002 4e6a R360 [Radeon 9800 XT] (Secondary) 1002 4e71 M10 NQ [Radeon Mobility 9600] - 4e71 M10 NQ [Radeon Mobility 9600] (Secondary) + 4e71 RV350/M10 [Mobility Radeon 9600] (Secondary) 4f72 RV250 [Radeon 9000 Series] - 4f73 Radeon RV250 [Radeon 9000 Series] (Secondary) - 5041 Rage 128 PA/PRO - 5042 Rage 128 PB/PRO AGP 2x - 5043 Rage 128 PC/PRO AGP 4x - 5044 Rage 128 PD/PRO TMDS + 4f73 RV250 [Radeon 9000 Series] (Secondary) + 5044 All-In-Wonder 128 PCI 1002 0028 Rage 128 AIW 1002 0029 Rage 128 AIW - 5045 Rage 128 PE/PRO AGP 2x TMDS - 5046 Rage 128 PF/PRO AGP 4x TMDS + 5046 Rage 128 PRO AGP 4x TMDS 1002 0004 Rage Fury Pro 1002 0008 Rage Fury Pro/Xpert 2000 Pro 1002 0014 Rage Fury Pro @@ -1132,26 +1113,10 @@ 1002 0048 Rage Fury Pro 1002 2000 Rage Fury MAXX AGP 4x (TMDS) (VGA device) 1002 2001 Rage Fury MAXX AGP 4x (TMDS) (Extra device?!) - 5047 Rage 128 PG/PRO - 5048 Rage 128 PH/PRO AGP 2x - 5049 Rage 128 PI/PRO AGP 4x - 504a Rage 128 PJ/PRO TMDS - 504b Rage 128 PK/PRO AGP 2x TMDS - 504c Rage 128 PL/PRO AGP 4x TMDS - 504d Rage 128 PM/PRO - 504e Rage 128 PN/PRO AGP 2x - 504f Rage 128 PO/PRO AGP 4x - 5050 Rage 128 PP/PRO TMDS [Xpert 128] + 5050 Rage128 [Xpert 128 PCI] 1002 0008 Xpert 128 - 5051 Rage 128 PQ/PRO AGP 2x TMDS - 5052 Rage 128 PR/PRO AGP 4x TMDS - 5053 Rage 128 PS/PRO - 5054 Rage 128 PT/PRO AGP 2x - 5055 Rage 128 PU/PRO AGP 4x - 5056 Rage 128 PV/PRO TMDS - 5057 Rage 128 PW/PRO AGP 2x TMDS - 5058 Rage 128 PX/PRO AGP 4x TMDS - 5144 Radeon R100 QD [Radeon 7200] + 5052 Rage 128 PRO AGP 4X TMDS + 5144 R100 [Radeon 7200 / All-In-Wonder Radeon] 1002 0008 Radeon 7000/Radeon VE 1002 0009 Radeon 7000/Radeon 1002 000a Radeon 7000/Radeon @@ -1165,30 +1130,20 @@ 1002 028a Radeon 7000/Radeon 1002 02aa Radeon AIW 1002 053a Radeon 7000/Radeon - 5145 Radeon R100 QE - 5146 Radeon R100 QF - 5147 Radeon R100 QG - 5148 Radeon R200 QH [Radeon 8500] + 5148 R200 GL [FireGL 8800] 1002 010a FireGL 8800 64Mb 1002 0152 FireGL 8800 128Mb 1002 0162 FireGL 8700 32Mb 1002 0172 FireGL 8700 64Mb - 5149 Radeon R200 QI - 514a Radeon R200 QJ - 514b Radeon R200 QK - 514c Radeon R200 QL [Radeon 8500 LE] + 514c R200 [Radeon 8500/8500 LE] 1002 003a Radeon R200 QL [Radeon 8500 LE] 1002 013a Radeon 8500 148c 2026 R200 QL [Radeon 8500 Evil Master II Multi Display Edition] 1681 0010 Radeon 8500 [3D Prophet 8500 128Mb] - 174b 7149 Radeon R200 QL [Sapphire Radeon 8500 LE] + 174b 7149 Radeon 8500 LE 1787 0f08 Radeon R200 QL [PowerMagic Radeon 8500] - 514d Radeon R200 QM [Radeon 9100] - 514e Radeon R200 QN [Radeon 8500LE] - 514f Radeon R200 QO [Radeon 8500LE] - 5154 R200 QT [Radeon 8500] - 5155 R200 QU [Radeon 9100] - 5157 RV200 QW [Radeon 7500] + 514d R200 [Radeon 9100] + 5157 RV200 [Radeon 7500/7500 LE] 1002 013a Radeon 7500 1002 0f2b ALL-IN-WONDER VE PCI 1002 103a Dell Optiplex GX260 @@ -1197,11 +1152,10 @@ 148c 2025 RV200 QW [Radeon 7500 Evil Master Multi Display Edition] 148c 2036 RV200 QW [Radeon 7500 PCI Dual Display] 174b 7146 RV200 QW [Radeon 7500 LE] - 174b 7147 RV200 QW [Sapphire Radeon 7500LE] + 174b 7147 Radeon 7500 LE 174b 7161 Radeon RV200 QW [Radeon 7500 LE] 17af 0202 RV200 QW [Excalibur Radeon 7500LE] - 5158 RV200 QX [Radeon 7500] - 5159 RV100 QY [Radeon 7000/VE] + 5159 RV100 [Radeon 7000 / Radeon VE] 1002 000a Radeon 7000/Radeon VE 1002 000b Radeon 7000 1002 0038 Radeon 7000/Radeon VE @@ -1221,12 +1175,12 @@ 1458 4002 RV100 QY [RADEON 7000 PRO MAYA AV Series] 148c 2003 RV100 QY [Radeon 7000 Multi-Display Edition] 148c 2023 RV100 QY [Radeon 7000 Evil Master Multi-Display] + 148c 2081 RV6DE 174b 0280 Radeon RV100 QY [Radeon 7000/VE] - 174b 7112 RV100 QY [Sapphire Radeon VE 7000] - 174b 7c28 Sapphire Radeon VE 7000 DDR + 174b 7112 Radeon VE 7000 + 174b 7c28 Radeon VE 7000 DDR 1787 0202 RV100 QY [Excalibur Radeon 7000] 17ee 1001 Radeon 7000 64MB DDR + DVI - 515a RV100 QZ [Radeon 7000/VE] 515e ES1000 1028 01bb PowerEdge 1955 Embedded ATI ES1000 1028 01df PowerEdge SC440 @@ -1242,45 +1196,32 @@ 1028 023c PowerEdge R200 Embedded ATI ES1000 103c 1304 Integrity iLO2 Advanced KVM VGA [AD307A] 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 S5000PSLSATA Server Board - 515f ES1000 - 5168 Radeon R200 Qh - 5169 Radeon R200 Qi - 516a Radeon R200 Qj - 516b Radeon R200 Qk -# This one is not in ATI documentation, but is in XFree86 source code - 516c Radeon R200 Ql - 5245 Rage 128 RE/SG + 5245 Rage 128 GL PCI 1002 0008 Xpert 128 1002 0028 Rage 128 AIW 1002 0029 Rage 128 AIW 1002 0068 Rage 128 AIW - 5246 Rage 128 RF/SG AGP + 5246 Rage Fury/Xpert 128/Xpert 2000 AGP 2x 1002 0004 Magnum/Xpert 128/Xpert 99 1002 0008 Magnum/Xpert128/X99/Xpert2000 1002 0028 Rage 128 AIW AGP 1002 0044 Rage Fury/Xpert 128/Xpert 2000 1002 0068 Rage 128 AIW AGP 1002 0448 Rage Fury - 5247 Rage 128 RG - 524b Rage 128 RK/VR - 524c Rage 128 RL/VR AGP + 524b Rage 128 VR PCI + 524c Rage 128 VR AGP 1002 0008 Xpert 99/Xpert 2000 1002 0088 Xpert 99 - 5345 Rage 128 SE/4x 5346 Rage 128 SF/4x AGP 2x 1002 0048 RAGE 128 16MB VGA TVOUT AMC PAL - 5347 Rage 128 SG/4x AGP 4x - 5348 Rage 128 SH - 534b Rage 128 SK/4x - 534c Rage 128 SL/4x AGP 2x - 534d Rage 128 SM/4x AGP 4x + 534d Rage 128 4X AGP 4x 1002 0008 Xpert 99/Xpert 2000 1002 0018 Xpert 2000 - 534e Rage 128 4x 5354 Mach 64 VT 1002 5654 Mach 64 reference - 5446 Rage 128 Pro Ultra TF + 5446 Rage 128 PRO Ultra AGP 4x 1002 0004 Rage Fury Pro 1002 0008 Rage Fury Pro/Xpert 2000 Pro 1002 0018 Rage Fury Pro/Xpert 2000 Pro @@ -1289,124 +1230,115 @@ 1002 002a Rage 128 AIW Pro AGP 1002 002b Rage 128 AIW 1002 0048 Xpert 2000 Pro - 544c Rage 128 Pro Ultra TL - 5452 Rage 128 Pro Ultra TR + 5452 Rage 128 PRO Ultra4XL VR-R AGP 1002 001c Rage 128 Pro 4XL 103c 1279 Rage 128 Pro 4XL - 5453 Rage 128 Pro Ultra TS - 5454 Rage 128 Pro Ultra TT - 5455 Rage 128 Pro Ultra TU - 5460 RV370 [Mobility Radeon X300] + 5460 RV370/M22 [Mobility Radeon X300] 1775 1100 CR11/VR11 Single Board Computer - 5461 RV370 [Mobility Radeon X300] - 5462 RV380 [Mobility Radeon X600] - 5464 RV370 [Mobility FireGL V3100] - 5548 R423 UH [Radeon X800 (PCIE)] - 5549 R423 UI [Radeon X800PRO (PCIE)] - 554a R423 UJ [Radeon X800LE (PCIE)] - 554b R423 UK [Radeon X800SE (PCIE)] - 554c R430 [Radeon X800XTP PCIe] - 554d R430 [Radeon X800 XL] (PCIe) + 5461 RV370/M22 [Mobility Radeon X300] + 5462 RV380/M24C [Mobility Radeon X600 SE] + 5464 RV370/M22 GL [Mobility FireGL V3100] + 5549 R423 [Radeon X800 GTO] + 554a R423 [Radeon X800 XT Platinum Edition] + 554b R423 [Radeon X800 GT/SE] + 1002 0302 Radeon X800 SE + 554d R430 [Radeon X800 XL] + 1002 0322 All-In-Wonder X800 XL 1458 2124 GV-R80L256V-B (AGP) - 554e R430 [Radeon X800 SE PCIe] - 554f R430 [Radeon X800 (PCIE)] - 5550 R423 [FireGL V7100] - 5551 R423 [FireGL V5100 (PCIE)] - 5552 R423 UR [FireGL V5100 (PCIE)] - 5554 R423 UT [FireGL V7100 (PCIE)] - 5555 R430 GL PRO - 5569 R423 UI [Radeon X800PRO (PCIE)] (Secondary) - 556b Radeon R423 UK (PCIE) [X800 SE] (Secondary) - 556d R430 [Radeon X800 XL] (PCIe) (Secondary) + 554e R430 [All-In-Wonder X800 GT] + 554f R430 [Radeon X800] + 5550 R423 GL [FireGL V7100] + 5551 R423 GL [FireGL V5100] + 5569 R423 [Radeon X800 PRO] (Secondary) + 556b R423 [Radeon X800 GT] (Secondary) + 556d R430 [Radeon X800 XL] (Secondary) 1458 2125 GV-R80L256V-B (AGP) - 556f R430 [Radeon X800] (PCIE) (Secondary) - 5571 R423GL-SE [FireGL V5100 (PCIE)] (Secondary) - 564a M26 [Mobility FireGL V5000] - 564b M26 [Mobility FireGL V5000] - 564f M26 [Radeon Mobility X700 XL (PCIE)] - 5652 M26 [Radeon Mobility X700] - 5653 Radeon Mobility X700 (PCIE) + 556f R430 [Radeon X800] (Secondary) + 5571 R423 GL [FireGL V5100] (Secondary) + 564b RV410/M26 GL [Mobility FireGL V5000] + 564f RV410/M26 [Mobility Radeon X700 XL] + 5652 RV410/M26 [Mobility Radeon X700] + 5653 RV410/M26 [Mobility Radeon X700] 1025 0080 Aspire 5024WLMi 103c 0940 HP Compaq NW8240 Mobile Workstation 5654 264VT [Mach64 VT] 1002 5654 Mach64VT Reference 5655 264VT3 [Mach64 VT3] 5656 264VT4 [Mach64 VT4] - 5657 Radeon X550/X700 Series (RV410) + 5657 RV410 [Radeon X550 XTX / X700] 5830 RS300 Host Bridge 5831 RS300 Host Bridge 5832 RS300 Host Bridge - 5833 Radeon 9100 IGP Host Bridge + 5833 RS300 Host Bridge 5834 RS300 [Radeon 9100 IGP] - 5835 RS300M AGP [Radeon Mobility 9100IGP] - 5838 Radeon 9100 IGP AGP Bridge - 5854 Radeon Xpress Series (RS480) - 5874 Radeon Xpress Series (RS482) + 5835 RS300M [Mobility Radeon 9100 IGP] + 5838 RS300 AGP Bridge + 5854 RS480 [Radeon Xpress 200 Series] (Secondary) + 5874 RS480 [Radeon Xpress 1150] (Secondary) 5940 RV280 [Radeon 9200 PRO] (Secondary) 17af 2021 Excalibur Radeon 9250 (Secondary) 5941 RV280 [Radeon 9200] (Secondary) - 1458 4019 Gigabyte Radeon 9200 - 174b 7c12 Sapphire Radeon 9200 + 1458 4019 Radeon 9200 + 174b 7c12 Radeon 9200 17af 200d Excalibur Radeon 9200 - 18bc 0050 GeXcube GC-R9200-C3 (Secondary) - 5944 RV280 [Radeon 9200 SE (PCI)] - 5950 RS480 Host Bridge + 18bc 0050 GC-R9200-C3 (Secondary) + 5944 RV280 [Radeon 9200 SE PCI] + 5950 RS480/RS482/RS485 Host Bridge 1025 0080 Aspire 5024WLMMi 103c 280a DC5750 Microtower 103c 2a20 Pavilion t3030.de Desktop PC 103c 308b MX6125 1462 0131 MS-1013 Notebook 1462 7217 Aspire L250 - 5951 Radeon Xpress 200 (RS480/RS482/RX480/RX482) Chipset - Host bridge - 5952 RD580 [CrossFire Xpress 3200] Chipset Host Bridge - 5954 RS480 [Radeon Xpress 200G Series] + 5951 RX480/RX482 Host Bridge + 5952 RD580 Host Bridge + 5954 RS480 [Radeon Xpress 200 Series] 1002 5954 RV370 [Radeon Xpress 200G Series] - 5955 Radeon XPRESS 200M 5955 (PCIE) + 5955 RS480M [Mobility Radeon Xpress 200] 1002 5955 RS480 0x5955 [Radeon XPRESS 200M 5955 (PCIE)] 103c 308b MX6125 1462 0131 MS-1013 Notebook - 5956 RD790 Northbridge only dual slot PCI-e_GFX and HT3 K8 part - 5957 RX780/RX790 Chipset Host Bridge + 5956 RD790 Host Bridge + 5957 RX780/RX790 Host Bridge 1849 5957 A770CrossFire Motherboard - 5958 RD780 Northbridge only dual slot PCI-e_GFX and HT1 K8 part + 5958 RD780 Host Bridge 5960 RV280 [Radeon 9200 PRO] 17af 2020 Excalibur Radeon 9250 5961 RV280 [Radeon 9200] 1002 2f72 All-in-Wonder 9200 Series 1019 4c30 Radeon 9200 VIVO 12ab 5961 YUAN SMARTVGA Radeon 9200 - 1458 4018 Gigabyte Radeon 9200 - 174b 7c13 Sapphire Radeon 9200 + 1458 4018 Radeon 9200 + 174b 7c13 Radeon 9200 17af 200c Excalibur Radeon 9200 18bc 0050 Radeon 9200 Game Buster - 18bc 0051 GeXcube GC-R9200-C3 + 18bc 0051 GC-R9200-C3 18bc 0053 Radeon 9200 Game Buster VIVO 5962 RV280 [Radeon 9200] 5964 RV280 [Radeon 9200 SE] 1002 5964 Radeon 9200 SE, 64-bit 128MB DDR, 200/166MHz - 1043 c006 ASUS Radeon 9200 SE / TD / 128M + 1043 c006 Radeon 9200 SE / TD / 128M 1458 4018 Radeon 9200 SE 1458 4032 Radeon 9200 SE 128MB 147b 6191 R9200SE-DT 148c 2073 CN-AG92E - 174b 7c13 Sapphire Radeon 9200 SE + 174b 7c13 Radeon 9200 SE 1787 5964 Excalibur 9200SE VIVO 128M 17af 2012 Radeon 9200 SE Excalibur 18bc 0170 Sapphire Radeon 9200 SE 128MB Game Buster 18bc 0173 GC-R9200L(SE)-C3H [Radeon 9200 Game Buster] - 5965 RV280 [FireMV 2200 PCI] - 5969 ES1000 - 5974 RS482 [Radeon Xpress 200] + 5965 RV280 GL [FireMV 2200 PCI] + 5974 RS482/RS485 [Radeon Xpress 1100/1150] 103c 280a DC5750 Microtower 1462 7141 Aspire L250 - 5975 RS482 [Radeon Xpress 200M] - 5978 RD790 PCI to PCI bridge (external gfx0 port A) + 5975 RS482M [Mobility Radeon Xpress 200] + 5978 RX780/RD790 PCI to PCI bridge (external gfx0 port A) 1849 5957 A770CrossFire Motherboard 5979 RD790 PCI to PCI bridge (external gfx0 port B) 597a RD790 PCI to PCI bridge (PCI express gpp port A) - 597b RD790 PCI to PCI bridge (PCI express gpp port B) + 597b RX780/RD790 PCI to PCI bridge (PCI express gpp port B) 597c RD790 PCI to PCI bridge (PCI express gpp port C) - 597d RD790 PCI to PCI bridge (PCI express gpp port D) + 597d RX780/RD790 PCI to PCI bridge (PCI express gpp port D) 597e RD790 PCI to PCI bridge (PCI express gpp port E) 1849 5957 A770CrossFire Motherboard 597f RD790 PCI to PCI bridge (PCI express gpp port F) @@ -1435,23 +1367,20 @@ 15d9 a811 H8DGU 5a20 RD890S PCI Express bridge for GPP2 port 1 5a23 RD990 I/O Memory Management Unit (IOMMU) - 5a33 Radeon Xpress 200 Host Bridge - 5a34 RS480 PCI-X Root Port -# Comes in pair with 5a3f - 5a36 RS480 PCI Bridge - 5a37 RS480 PCI Bridge - 5a38 RS480 PCI Bridge -# Comes in pair with 5a38 - 5a39 RS480 PCI Bridge - 5a3f RS480 PCI Bridge + 5a31 RC410 Host Bridge + 5a33 RS400 Host Bridge + 5a34 RS4xx PCI Express Port [ext gfx] + 5a36 RC4xx/RS4xx PCI Express Port 1 + 5a37 RC4xx/RS4xx PCI Express Port 2 + 5a38 RC4xx/RS4xx PCI Express Port 3 + 5a39 RC4xx/RS4xx PCI Express Port 4 + 5a3f RC4xx/RS4xx PCI Bridge [int gfx] 1462 7217 Aspire L250 5a41 RS400 [Radeon Xpress 200] - 5a42 RS400 [Radeon Xpress 200M] - 5a43 Radeon Xpress Series (RS400) - 5a61 RC410 [Radeon Xpress 200] - 5a62 RC410 [Radeon Xpress 200M] - 5a63 Radeon Xpress Series (RC410) - 5b60 RV370 5B60 [Radeon X300 (PCIE)] + 5a42 RS400M [Radeon Xpress 200M] + 5a61 RC410 [Radeon Xpress 200/1100] + 5a62 RC410M [Mobility Radeon Xpress 200M] + 5b60 RV370 [Radeon X300] 1043 002a Extreme AX300SE-X 1043 032e Extreme AX300/TD 1458 2102 GV-RX30S128D (X300SE) @@ -1459,294 +1388,1500 @@ 1462 0402 RX300SE-TD128E (MS-8940) 174b 0500 Radeon X300 (PCIE) 196d 1086 X300SE HM - 5b62 RV380 [Radeon X600 (PCIE)] - 5b63 RV370 [Radeon X550] - 5b64 RV370 5B64 [FireGL V3100 (PCIE)] - 5b65 RV370 5B65 [FireGL D1100 (PCIE)] + 5b62 RV370 [Radeon X600/X600 SE] + 5b63 RV370 [Radeon X300/X550/X1050 Series] + 5b64 RV370 GL [FireGL V3100] + 5b65 RV370 GL [FireMV 2200] 5b66 RV370X - 5b70 RV370 [Radeon X300SE] - 1462 0403 RX300SE-TD128E (MS-8940) (secondary display) - 174b 0501 Radeon X300SE - 196d 1087 X300SE HM - 5b72 RV380 [Radeon X600] - 5b73 RV370 secondary [Sapphire X550 Silent] - 5b74 RV370 5B64 [FireGL V3100 (PCIE)] (Secondary) - 5b75 RV370 5B75 [FireGL D1100 (PCIE)] (Secondary) - 5c61 M9+ 5C61 [Radeon Mobility 9200 (AGP)] - 5c63 M9+ 5C63 [Radeon Mobility 9200 (AGP)] + 5b70 RV370 [Radeon X300 SE] +# RX300SE-TD128E + 1462 0403 Radeon X300 SE 128MB DDR + 174b 0501 Radeon X300 SE + 196d 1087 Radeon X300 SE HyperMemory + 5b72 RV380 [Radeon X300/X550/X1050 Series] (Secondary) + 5b73 RV370 [Radeon X300/X550/X1050 Series] (Secondary) + 5b74 RV370 GL [FireGL V3100] (Secondary) + 5b75 RV370 GL [FireMV 2200] (Secondary) + 5c61 RV280/M9+ [Mobility Radeon 9200 AGP] + 5c63 RV280/M9+ [Mobility Radeon 9200 AGP] 1002 5c63 Apple iBook G4 2004 144d c00c P30 notebook 5d44 RV280 [Radeon 9200 SE] (Secondary) 1458 4019 Radeon 9200 SE (Secondary) 1458 4032 Radeon 9200 SE 128MB 147b 6190 R9200SE-DT (Secondary) - 174b 7c12 Sapphire Radeon 9200 SE (Secondary) + 174b 7c12 Radeon 9200 SE (Secondary) 1787 5965 Excalibur 9200SE VIVO 128M (Secondary) 17af 2013 Radeon 9200 SE Excalibur (Secondary) 18bc 0171 Radeon 9200 SE 128MB Game Buster (Secondary) 18bc 0172 GC-R9200L(SE)-C3H [Radeon 9200 Game Buster] - 5d45 RV280 [FireMV 2200 PCI] (secondary) - 5d48 M28 [Radeon Mobility X800XT] - 5d49 M28 [Mobility FireGL V5100] - 5d4a Mobility Radeon X800 - 5d4c Radeon X850 (PCIE) - 5d4d R480 [Radeon X850XT Platinum (PCIE)] - 5d4e Radeon X850 SE (R480) (PCIE) - 5d4f R480 [Radeon X800 GTO (PCIE)] - 5d50 R480 [FireGL V7200 (PCIE)] - 5d51 R480 GL 12P - 5d52 R480 [Radeon X850XT (PCIE)] (Primary) + 5d45 RV280 GL [FireMV 2200 PCI] (Secondary) + 5d48 R423/M28 [Mobility Radeon X800 XT] + 5d49 R423/M28 GL [Mobility FireGL V5100] + 5d4a R423/M28 [Mobility Radeon X800] + 5d4d R480 [Radeon X850 XT Platinum Edition] + 5d4e R480 [Radeon X850 SE] + 5d4f R480 [Radeon X800 GTO] + 5d50 R480 GL [FireGL V7200] + 5d52 R480 [Radeon X850 XT] 1002 0b12 PowerColor X850XT PCIe (Primary) + 5d57 R423 [Radeon X800 XT] + 5d6d R480 [Radeon X850 XT Platinum Edition] (Secondary) + 5d6f R480 [Radeon X800 GTO] (Secondary) + 5d72 R480 [Radeon X850 XT] (Secondary) 1002 0b13 PowerColor X850XT PCIe (Secondary) - 5d57 R423 5F57 [Radeon X800XT (PCIE)] - 5d6d R480 [Radeon X850XT Platinum (PCIE)] (Secondary) - 5d6f R480 [Radeon X800 GTO (PCIE)] (Secondary) - 5d72 R480 [Radeon X850XT (PCIE)] (Secondary) - 5d77 R423 5F57 [Radeon X800XT (PCIE)] (Secondary) - 5e48 RV410 [FireGL V5000] - 5e49 RV410 [FireGL V3300] - 5e4a RV410 [Radeon X700XT] - 5e4b RV410 [Radeon X700 Pro (PCIE)] - 5e4c RV410 [Radeon X700SE] - 5e4d RV410 [Radeon X700 (PCIE)] - 148c 2116 PowerColor Bravo X700 + 5d77 R423 [Radeon X800 XT] (Secondary) + 5e48 RV410 GL [FireGL V5000] + 5e49 RV410 [Radeon X700 Series] + 5e4a RV410 [Radeon X700 XT] + 5e4b RV410 [Radeon X700 PRO] + 5e4c RV410 [Radeon X700 SE] + 5e4d RV410 [Radeon X700] + 148c 2116 Bravo X700 5e4f RV410 [Radeon X700] - 5e6b RV410 [Radeon X700 Pro (PCIE)] (Secondary) - 5e6d RV410 [Radeon X700 (PCIE)] (Secondary) - 148c 2117 PowerColor Bravo X700 - 5f57 R423 [Radeon X800XT (PCIE)] - 6600 Mars [Radeon HD 8600/8700M Series] - 6601 Mars [Radeon HD 8500/8700M Series] - 6606 Mars [Radeon HD 8790M] - 6610 Oland [Radeon HD 8600 Series] - 6611 Oland [Radeon HD 8500 Series] + 1569 1e4f Radeon X550 XT + 5e6b RV410 [Radeon X700 PRO] (Secondary) + 5e6d RV410 [Radeon X700] (Secondary) + 148c 2117 Bravo X700 (Secondary) + 5f57 R423 [Radeon X800 XT] + 6600 Mars [Radeon HD 8670A/8670M/8750M] + 103c 1952 ProBook 455 G1 + 6601 Mars [Radeon HD 8730M] + 103c 2100 FirePro M4100 + 6602 Mars + 6603 Mars + 6604 Opal XT [Radeon R7 M265] + 103c 8006 FirePro M4170 + 17aa 3643 Radeon R7 A360 + 6605 Opal PRO [Radeon R7 M260] + 6606 Mars XTX [Radeon HD 8790M] + 1028 0684 FirePro W4170M + 6607 Mars LE [Radeon HD 8530M / R5 M240] + 6608 Oland GL [FirePro W2100] + 6610 Oland XT [Radeon HD 8670 / R7 250/350] + 1019 0030 Radeon HD 8670 + 1028 2120 Radeon R7 250 + 1028 2322 Radeon R7 250 + 1462 2910 Radeon HD 8670 + 1462 2911 Radeon HD 8670 + 148c 7350 Radeon R7 350 + 1642 3c81 Radeon HD 8670 + 1642 3c91 Radeon HD 8670 + 1642 3f09 Radeon R7 350 + 6611 Oland [Radeon HD 8570 / R7 240/340 OEM] + 1028 210b Radeon R5 240 OEM + 174b 4248 Radeon R7 240 OEM + 174b a240 Radeon R7 240 OEM + 174b d340 Radeon R7 340 OEM + 1b0a 90d3 Radeon R7 240 OEM + 6613 Oland PRO [Radeon R7 240/340] + 148c 7340 Radeon R7 340 + 1682 7240 R7 240 2048 MB + 6620 Mars + 6621 Mars PRO + 6623 Mars + 6631 Oland + 6640 Saturn XT [FirePro M6100] + 6641 Saturn PRO [Radeon HD 8930M] + 6646 Bonaire XT [Radeon R9 M280X] + 6647 Bonaire PRO [Radeon R9 M270X] + 6649 Bonaire [FirePro W5100] + 6650 Bonaire + 6651 Bonaire + 6658 Bonaire XTX [Radeon R7 260X/360] + 148c 0907 Radeon R7 360 + 1682 0907 Radeon R7 360 + 1682 7360 Radeon R7 360 + 665c Bonaire XT [Radeon HD 7790/8770 / R7 360 / R9 260/360 OEM] + 1043 0452 Radeon HD 7790 DirectCU II OC +# R7790-1GD5/OC + 1462 2930 Radeon HD 7790 OC + 1462 2932 Radeon HD 8770 + 1462 2934 Radeon R9 260 OEM + 1462 2938 Radeon R9 360 OEM + 148c 0907 Radeon R7 360 + 148c 9260 Radeon R9 260 OEM + 148c 9360 Radeon R9 360 OEM + 1682 0907 Radeon R7 360 +# FX-779A-CDB4 / FX-779A-CDBC + 1682 3310 Radeon HD 7790 Black Edition 2 GB +# 100356OCL / 11210-01-20G + 174b e253 Radeon HD 7790 Dual-X OC + 1787 2329 Radeon HD 7790 TurboDuo + 665d Bonaire [Radeon R7 200 Series] + 665f Tobago PRO [Radeon R7 360 / R9 360 OEM] + 1028 0b04 Radeon R9 360 OEM + 1462 2938 Radeon R9 360 OEM + 1462 3271 Radeon R9 360 OEM + 1682 7360 Radeon R7 360 + 6660 Sun XT [Radeon HD 8670A/8670M/8690M / R5 M330] + 17aa 3809 Radeon R5 M330 + 17aa 390c Radeon R5 M330 + 6663 Sun PRO [Radeon HD 8570A/8570M] + 1025 0846 Radeon HD 8570A + 6664 Jet XT [Radeon R5 M240] + 6665 Jet PRO [Radeon R5 M230] + 17aa 368f Radeon R5 A230 + 6667 Jet ULT [Radeon R5 M230] + 666f Sun LE [Radeon HD 8550M / R5 M230] 6704 Cayman PRO GL [FirePro V7900] 6707 Cayman LE GL [FirePro V5900] 6718 Cayman XT [Radeon HD 6970] 6719 Cayman PRO [Radeon HD 6950] - 671d Antilles [AMD Radeon HD 6990] - 671f Cayman [Radeon HD 6900 Series] - 6720 Blackcomb [Radeon HD 6900M series] - 6738 Barts XT [Radeon HD 6800 Series] - 6739 Barts PRO [Radeon HD 6800 Series] + 671c Antilles [Radeon HD 6990] + 671d Antilles [Radeon HD 6990] + 671f Cayman CE [Radeon HD 6930] + 6720 Blackcomb [Radeon HD 6970M/6990M] + 1028 048f Radeon HD 6990M + 1028 0490 Alienware M17x R3 Radeon HD 6970M + 1028 04a4 FirePro M8900 + 1028 04ba Radeon HD 6990M + 1028 053f FirePro M8900 + 106b 0b00 Radeon HD 6970M + 1558 5102 Radeon HD 6970M + 1558 5104 Radeon HD 6990M + 1558 7201 Radeon HD 6990M + 174b e188 Radeon HD 6970M + 6738 Barts XT [Radeon HD 6870] +# HD-687A-ZDFC + 1682 3103 Radeon HD 8670 + 1787 201a Barts XT [Radeon HD 6870 X2] + 1787 201b Barts XT [Radeon HD 6870 X2] + 6739 Barts PRO [Radeon HD 6850] 1043 03b4 EAH6850 [Radeon HD 6850] - 673e Barts LE [AMD Radeon HD 6700 Series] - 6740 Whistler XT [AMD Radeon HD 6700M Series] - 6741 Whistler [AMD Radeon HD 6600M Series] + 673e Barts LE [Radeon HD 6790] + 148c 7720 Radeon HD 7720 OEM + 6740 Whistler [Radeon HD 6730M/6770M/7690M XT] + 1019 238c Radeon HD 6730M + 1019 238e Radeon HD 6730M + 1019 2391 Radeon HD 6730M + 1019 2392 Radeon HD 6770M + 1028 04a3 Precision M4600 + 1028 053e FirePro M5950 + 103c 1630 FirePro M5950 + 103c 1631 FirePro M5950 + 103c 164b Radeon HD 6730M + 103c 164e Radeon HD 6730M + 103c 1657 Radeon HD 6770M + 103c 1658 Radeon HD 6770M + 103c 165a Radeon HD 6770M + 103c 165b Radeon HD 6770M + 103c 1688 Radeon HD 6770M + 103c 1689 Radeon HD 6770M + 103c 168a Radeon HD 6770M + 103c 185e Radeon HD 7690M XT + 103c 3388 Radeon HD 6770M + 103c 3389 Radeon HD 6770M + 103c 3582 Radeon HD 6770M + 103c 366c Radeon HD 6730M + 1043 1d02 Radeon HD 6730M + 1043 1d12 Radeon HD 6730M + 104d 9084 Radeon HD 6730M + 104d 9085 Radeon HD 6730M + 144d b074 Radeon HD 6730M + 144d b077 Radeon HD 6730M + 144d b084 Radeon HD 6730M + 144d b088 Radeon HD 6730M + 17aa 3982 Radeon HD 6730M + 6741 Whistler [Radeon HD 6630M/6650M/6750M/7670M/7690M] + 1019 238e Radeon HD 6650M + 1019 238f Radeon HD 6650M + 1025 0379 Radeon HD 6650M + 1025 037b Radeon HD 6650M + 1025 037e Radeon HD 6650M + 1025 0382 Radeon HD 6650M + 1025 0384 Radeon HD 6650M + 1025 0385 Radeon HD 6650M + 1025 0386 Radeon HD 6650M + 1025 0387 Radeon HD 6650M + 1025 0388 Radeon HD 6650M + 1025 0442 Radeon HD 6650M + 1025 0451 Radeon HD 6650M + 1025 0489 Radeon HD 6650M + 1025 048b Radeon HD 6650M + 1025 048c Radeon HD 6650M + 1025 050a Radeon HD 6650M + 1025 050b Radeon HD 6650M + 1025 050c Radeon HD 6650M + 1025 050e Radeon HD 6650M + 1025 050f Radeon HD 6650M + 1025 0513 Radeon HD 6650M + 1025 0514 Radeon HD 6650M + 1025 0515 Radeon HD 6650M + 1025 0516 Radeon HD 6650M + 1025 051e Radeon HD 6650M + 1025 051f Radeon HD 6650M + 1025 0520 Radeon HD 6650M + 1025 0521 Radeon HD 6650M + 1025 052a Radeon HD 6650M + 1025 0555 Radeon HD 6650M + 1025 0556 Radeon HD 6650M + 1025 055d Radeon HD 6650M + 1025 055e Radeon HD 6650M + 1025 056d Radeon HD 6650M + 1025 059a Radeon HD 6650M + 1025 059b Radeon HD 6650M + 1025 059e Radeon HD 6650M + 1025 059f Radeon HD 6650M + 1025 0600 Radeon HD 6650M + 1025 0605 Radeon HD 6650M + 1025 0606 Radeon HD 6650M + 1025 0619 Radeon HD 6650M + 1028 04c1 Radeon HD 6630M + 1028 04c5 Radeon HD 6630M + 1028 04cd Radeon HD 6630M + 1028 04d7 Radeon HD 6630M + 1028 04d9 Radeon HD 6630M + 1028 052d Radeon HD 6630M + 103c 1617 Radeon HD 6650M + 103c 1646 Radeon HD 6750M + 103c 1647 Radeon HD 6650M + 103c 164b Radeon HD 6650M + 103c 164e Radeon HD 6650M + 103c 1688 Radeon HD 6750M + 103c 1689 Radeon HD 6750M + 103c 168a Radeon HD 6750M + 103c 1860 Radeon HD 7690M + 103c 3385 Radeon HD 6630M + 103c 3560 Radeon HD 6750M + 103c 358d Radeon HD 6750M + 103c 3590 Radeon HD 6750M + 103c 3593 Radeon HD 6750M + 103c 366c Radeon HD 6650M + 1043 1cd2 Radeon HD 6650M + 1043 2121 Radeon HD 6650M + 1043 2122 Radeon HD 6650M + 1043 2123 Radeon HD 6650M + 1043 2125 Radeon HD 7670M + 1043 2127 Radeon HD 7670M + 104d 907b Radeon HD 6630M + 104d 9080 Radeon HD 6630M + 104d 9081 Radeon HD 6630M 106b 00e2 MacBookPro8,2 [Core i7, 15", Late 2011] - 6742 Whistler LE [AMD Radeon HD 6625M Graphics] + 1179 fd63 Radeon HD 6630M + 1179 fd65 Radeon HD 6630M + 144d c093 Radeon HD 6650M + 144d c0ac Radeon HD 6650M + 144d c0b3 Radeon HD 6750M + 144d c539 Radeon HD 6630M + 144d c609 Radeon HD 6630M + 152d 0914 Radeon HD 6650M + 17aa 21e1 Radeon HD 6630M + 17aa 3970 Radeon HD 6650M + 17aa 3976 Radeon HD 6650M + 1854 0907 Radeon HD 6650M + 6742 Whistler LE [Radeon HD 6610M/7610M] + 1002 6570 Turks [Radeon HD 6570] + 1019 2393 Radeon HD 6610M + 1043 1d82 K53SK Laptop Radeon HD 7610M + 1179 fb22 Radeon HD 7610M + 1179 fb23 Radeon HD 7610M + 1179 fb27 Radeon HD 7610M + 1179 fb2a Radeon HD 7610M + 1179 fb2c Radeon HD 7610M + 1179 fb30 Radeon HD 7610M + 1179 fb31 Radeon HD 7610M + 1179 fb32 Radeon HD 7610M + 1179 fb38 Radeon HD 7610M + 1179 fb39 Radeon HD 7610M + 1179 fb3a Radeon HD 7610M + 1179 fb3b Radeon HD 7610M + 1179 fb40 Radeon HD 7610M + 1179 fb41 Radeon HD 7610M + 1179 fb47 Radeon HD 7610M + 1179 fb48 Radeon HD 7610M + 1179 fb49 Radeon HD 7610M + 1179 fb51 Radeon HD 7610M + 1179 fb52 Radeon HD 7610M + 1179 fb53 Radeon HD 7610M + 1179 fb56 Radeon HD 7610M + 1179 fb81 Radeon HD 7610M + 1179 fb82 Radeon HD 7610M + 1179 fb83 Radeon HD 7610M + 1179 fc56 Radeon HD 7610M + 1179 fcd4 Radeon HD 7610M + 1179 fcee Radeon HD 7610M + 1458 6570 Turks [Radeon HD 6570] + 1462 6570 Turks [Radeon HD 6570] + 148c 6570 Turks [Radeon HD 6570] + 1682 6570 Turks [Radeon HD 6570] + 174b 5570 Turks [Radeon HD 5570] + 174b 6570 Turks [Radeon HD 6570] + 174b 7570 Turks [Radeon HD 7570] + 174b 8510 Turks [Radeon HD 8510] + 174b 8570 Turks [Radeon HD 8570] + 1787 6570 Turks [Radeon HD 6570] + 17af 6570 Turks [Radeon HD 6570] + 8086 2111 Radeon HD 6625M 6743 Whistler [Radeon E6760] - 6749 Turks [FirePro V4900] - 674a Turks [AMD FirePro V3900] - 6750 Turks [AMD Radeon HD 6570] - 6751 Turks [Radeon HD 7600A Series] - 6758 Turks [Radeon HD 6670] - 6759 Turks [Radeon HD 6570] - 675d Turks [Radeon HD 7500 Series] - 6760 Caicos [Radeon HD 6400M/7400M Series] + 6749 Turks GL [FirePro V4900] + 674a Turks GL [FirePro V3900] + 6750 Onega [Radeon HD 6650A/7650A] + 1462 2670 Radeon HD 6670A + 17aa 3079 Radeon HD 7650A + 17aa 307a Radeon HD 6650A + 17aa 3087 Radeon HD 7650A + 17aa 3618 Radeon HD 6650A + 17aa 3623 Radeon HD 6650A + 17aa 3627 Radeon HD 6650A + 6751 Turks [Radeon HD 7650A/7670A] + 1028 0548 Radeon HD 7650A + 1462 2671 Radeon HD 7670A + 1462 2672 Radeon HD 7670A + 1462 2680 Radeon HD 7650A + 1462 2681 Radeon HD 7650A + 17aa 3087 Radeon HD 7650A + 6758 Turks XT [Radeon HD 6670/7670] + 1028 0b0e Radeon HD 6670 + 103c 6882 Radeon HD 6670 + 1462 250a Radeon HD 7670 + 148c 7670 Radeon HD 7670 + 1545 7670 Radeon HD 7670 + 1682 3300 Radeon HD 7670 + 174b 7670 Radeon HD 7670 + 174b e181 Radeon HD 6670 + 1787 2309 Radeon HD 6670 + 6759 Turks PRO [Radeon HD 6570/7570/8550] + 103c 3130 Radeon HD 6570 + 1043 0403 Radeon HD 6570 + 1462 2500 Radeon HD 6570 + 1462 2509 Radeon HD 7570 + 148c 7570 Radeon HD 7570 + 1642 3a67 Radeon HD 6570 + 1682 3280 Radeon HD 7570 + 1682 3530 Radeon HD 8550 + 174b 7570 Radeon HD 7570 + 174b e142 Radeon HD 6570 + 174b e181 Radeon HD 6570 + 1b0a 908f Radeon HD 6570 + 1b0a 9090 Radeon HD 6570 + 1b0a 9091 Radeon HD 6570 + 1b0a 9092 Radeon HD 6570 + 1b0a 909e Radeon HD 6570 + 1b0a 90b5 Radeon HD 7570 + 1b0a 90b6 Radeon HD 7570 + 675b Turks [Radeon HD 7600 Series] + 675d Turks PRO [Radeon HD 7570] + 675f Turks LE [Radeon HD 5570/6510/7510/8510] + 148c 6510 Radeon HD 6510 + 148c 6530 Radeon HD 6530 + 148c 7510 Radeon HD 7510 + 1545 7570 Radeon HD 7570 + 174b 6510 Radeon HD 6510 + 174b 7510 Radeon HD 7510 + 174b 8510 Radeon HD 8510 + 1787 2012 Radeon HD 5570 2GB GDDR3 + 1787 2314 Radeon HD 5570 1GB DDR2/GDDR3 + 6760 Seymour [Radeon HD 6400M/7400M Series] + 1002 0124 Radeon HD 6470M + 1002 0134 Radeon HD 6470M + 1019 238b Radeon HD 6470M + 1019 238e Radeon HD 6470M + 1019 2390 Radeon HD 6470M + 1019 9985 Radeon HD 6470M + 1028 04c1 Radeon HD 6470M + 1028 04c3 Radeon HD 6470M + 1028 04ca Radeon HD 6470M + 1028 04cb Radeon HD 6470M 1028 04cc Vostro 3350 + 1028 04d1 Radeon HD 6470M + 1028 04d3 Radeon HD 6470M + 1028 04d7 Radeon HD 6470M + 1028 0502 Radeon HD 6470M + 1028 0503 Radeon HD 6470M + 1028 0506 Radeon HD 6470M + 1028 0507 Radeon HD 6470M + 1028 0514 Radeon HD 6470M + 1028 051c Radeon HD 6450M + 1028 051d Radeon HD 6450M + 103c 161a Radeon HD 6470M + 103c 161b Radeon HD 6470M + 103c 161e Radeon HD 6470M + 103c 161f Radeon HD 6470M + 103c 1622 Radeon HD 6450M + 103c 1623 Radeon HD 6450M + 103c 164a Radeon HD 6470M + 103c 164d Radeon HD 6470M + 103c 1651 Radeon HD 6470M + 103c 1656 Radeon HD 6490M + 103c 1658 Radeon HD 6490M + 103c 1659 Radeon HD 6490M + 103c 165b Radeon HD 6490M + 103c 165d Radeon HD 6470M + 103c 165f Radeon HD 6470M + 103c 1661 Radeon HD 6470M + 103c 1663 Radeon HD 6470M + 103c 1665 Radeon HD 6470M + 103c 1667 Radeon HD 6470M + 103c 1669 Radeon HD 6470M + 103c 166b Radeon HD 6470M + 103c 166c Radeon HD 6470M + 103c 166e Radeon HD 6470M + 103c 1670 Radeon HD 6470M + 103c 1672 Radeon HD 6470M + 103c 167a Radeon HD 6470M + 103c 167b Radeon HD 6470M + 103c 167d Radeon HD 6490M + 103c 167f Radeon HD 6490M + 103c 168c Radeon HD 6470M + 103c 168f Radeon HD 6470M + 103c 1694 Radeon HD 6470M + 103c 1696 Radeon HD 6470M + 103c 1698 Radeon HD 6470M + 103c 169a Radeon HD 6470M + 103c 169c Radeon HD 6490M + 103c 1855 Radeon HD 7450M + 103c 1859 Radeon HD 7450M + 103c 185c Radeon HD 7450M + 103c 185d Radeon HD 7470M + 103c 185f Radeon HD 7470M + 103c 1863 Radeon HD 7450M + 103c 355c Radeon HD 6490M + 103c 355f Radeon HD 6490M + 103c 3563 Radeon HD 6470M + 103c 3565 Radeon HD 6470M + 103c 3567 Radeon HD 6470M + 103c 3569 Radeon HD 6470M + 103c 3581 Radeon HD 6490M + 103c 3584 Radeon HD 6470M + 103c 358c Radeon HD 6490M + 103c 358f Radeon HD 6490M + 103c 3592 Radeon HD 6490M + 103c 3596 Radeon HD 6490M + 103c 366b Radeon HD 6470M + 103c 3671 FirePro M3900 + 103c 3673 Radeon HD 6470M + 1043 100a Radeon HD 7470M + 1043 100c Radeon HD 6470M + 1043 101b Radeon HD 6470M + 1043 101c Radeon HD 6470M + 1043 102a Radeon HD 7450M + 1043 102c Radeon HD 6470M + 1043 104b Radeon HD 7470M + 1043 105d Radeon HD 7470M + 1043 106b Radeon HD 7470M + 1043 106d Radeon HD 7470M + 1043 107d Radeon HD 7470M + 1043 1cb2 Radeon HD 6470M + 1043 1d22 Radeon HD 6470M + 1043 1d32 Radeon HD 6470M + 1043 2001 Radeon HD 6470M + 1043 2002 Radeon HD 7470M + 1043 2107 Radeon HD 7470M + 1043 2108 Radeon HD 7470M + 1043 2109 Radeon HD 7470M + 1043 84a0 Radeon HD 6470M + 1043 84e9 Radeon HD 6470M + 1043 8515 Radeon HD 7470M + 1043 8517 Radeon HD 7470M + 1043 855a Radeon HD 7470M + 104d 907b Radeon HD 6470M + 104d 9081 Radeon HD 6470M + 104d 9084 Radeon HD 6470M + 104d 9085 Radeon HD 6470M + 1179 0001 Radeon HD 6450M + 1179 0003 Radeon HD 6450M + 1179 0004 Radeon HD 6450M + 1179 fb22 Radeon HD 7470M + 1179 fb23 Radeon HD 7470M + 1179 fb2c Radeon HD 7470M + 1179 fb31 Radeon HD 7470M + 1179 fb32 Radeon HD 7470M + 1179 fb33 Radeon HD 7470M + 1179 fb38 Radeon HD 7470M + 1179 fb39 Radeon HD 7470M + 1179 fb3a Radeon HD 7470M + 1179 fb40 Radeon HD 7470M + 1179 fb41 Radeon HD 7470M + 1179 fb42 Radeon HD 7470M + 1179 fb47 Radeon HD 7470M + 1179 fb48 Radeon HD 7470M + 1179 fb51 Radeon HD 7470M + 1179 fb52 Radeon HD 7470M + 1179 fb53 Radeon HD 7470M + 1179 fb81 Radeon HD 7470M + 1179 fb82 Radeon HD 7470M + 1179 fb83 Radeon HD 7470M + 1179 fc51 Radeon HD 6470M + 1179 fc52 Radeon HD 7470M + 1179 fc56 Radeon HD 7470M + 1179 fcd3 Radeon HD 7470M + 1179 fcd4 Radeon HD 7470M + 1179 fcee Radeon HD 7470M + 1179 fdee Radeon HD 7470M + 144d b074 Radeon HD 6470M + 144d b084 Radeon HD 6470M + 144d c095 Radeon HD 6470M + 144d c0b3 Radeon HD 6490M + 144d c538 Radeon HD 6470M + 144d c581 Radeon HD 6470M + 144d c589 Radeon HD 6470M + 144d c609 Radeon HD 7470M + 144d c625 Radeon HD 7470M + 144d c636 Radeon HD 7450M + 1462 10ac Radeon HD 6470M + 152d 0916 Radeon HD 6470M + 17aa 21e5 Radeon HD 6470M + 17aa 3900 Radeon HD 7450M + 17aa 3902 Radeon HD 7450M + 17aa 3969 Radeon HD 6470M + 17aa 3970 Radeon HD 7450M + 17aa 3976 Radeon HD 6470M + 17aa 397b Radeon HD 6470M + 17aa 397d Radeon HD 6470M + 17aa 5101 Radeon HD 7470M + 17aa 5102 Radeon HD 7450M + 17aa 5103 Radeon HD 7450M + 17aa 5106 Radeon HD 7450M + 1854 0897 Radeon HD 6470M + 1854 0900 Radeon HD 6470M + 1854 0908 Radeon HD 6470M + 1854 2015 Radeon HD 6470M 6761 Seymour LP [Radeon HD 6430M] 6763 Seymour [Radeon E6460] - 6770 Caicos [Radeon HD 6400 Series] - 6772 Caicos [Radeon HD 7400A Series] - 6778 Caicos [Radeon HD 7000 Series] - 6779 Caicos [Radeon HD 6450] - 174b e164 Sapphire HD 6450 1GB DDR3 - 677b Caicos [Radeon HD 7400 Series] - 6798 Tahiti XT [Radeon HD 7970] - 6799 New Zealand [Radeon HD 7990] - 679a Tahiti PRO [Radeon HD 7950] - 679e Tahiti LE [Radeon HD 7800 Series] + 6764 Seymour [Radeon HD 6400M Series] + 6765 Seymour [Radeon HD 6400M Series] + 6766 Caicos + 6767 Caicos + 6768 Caicos + 6770 Caicos [Radeon HD 6450A/7450A] + 17aa 308d Radeon HD 7450A + 17aa 3623 Radeon HD 6450A + 17aa 3627 Radeon HD 6450A + 17aa 3629 Radeon HD 6450A + 17aa 363c Radeon HD 6450A + 17aa 3658 Radeon HD 7470A + 6771 Caicos XTX [Radeon HD 8490 / R5 235X OEM] + 6772 Caicos [Radeon HD 7450A] + 6778 Caicos XT [Radeon HD 7470/8470 / R5 235/310 OEM] + 1019 0024 Radeon HD 7470 + 1019 0027 Radeon HD 8470 + 1028 2120 Radeon HD 7470 + 1462 b491 Radeon HD 8470 + 1462 b492 Radeon HD 8470 + 1462 b493 Radeon HD 8470 OEM + 1462 b499 Radeon R5 235 OEM + 1642 3c65 Radeon HD 8470 + 1642 3c75 Radeon HD 8470 + 174b 8145 Radeon HD 8470 + 174b d145 Radeon R5 235 OEM + 174b d335 Radeon R5 310 OEM + 174b e145 Radeon HD 7470 + 17aa 3694 Radeon R5 A220 + 6779 Caicos [Radeon HD 6450/7450/8450 / R5 230 OEM] + 1019 0016 Radeon HD 6450 + 1019 0017 Radeon HD 6450 + 1019 0018 Radeon HD 6450 + 1028 2120 Radeon HD 6450 + 103c 2128 Radeon HD 6450 + 103c 2aee Radeon HD 7450A + 1462 2125 Radeon HD 6450 + 1462 2346 Radeon HD 7450 + 1462 2490 Radeon HD 6450 + 1462 2494 Radeon HD 6450 + 1462 2496 Radeon HD 7450 + 148c 7450 Radeon HD 7450 + 148c 8450 Radeon HD 8450 OEM + 1545 7470 Radeon HD 7470 + 1642 3a65 Radeon HD 6450 + 1642 3a66 Radeon HD 7450 + 1642 3a75 Radeon HD 6450 + 1642 3a76 Radeon HD 7450 + 1682 3200 Radeon HD 7450 + 174b 7450 Radeon HD 7450 + 174b e127 Radeon HD 6450 + 174b e153 Radeon HD 6450 + 174b e164 Radeon HD 6450 1 GB DDR3 + 174b e180 Radeon HD 6450 + 174b e201 Radeon HD 6450 + 17af 8450 Radeon HD 8450 OEM + 1b0a 9096 Radeon HD 6450 + 1b0a 9097 Radeon HD 6450 + 1b0a 90a8 Radeon HD 6450A + 1b0a 90b1 Radeon HD 6450 + 1b0a 90b3 Radeon HD 7450A + 1b0a 90bb Radeon HD 7450A + 677b Caicos PRO [Radeon HD 7450] + 6780 Tahiti XT GL [FirePro W9000] + 6784 Tahiti [FirePro Series Graphics Adapter] + 6788 Tahiti [FirePro Series Graphics Adapter] + 678a Tahiti PRO GL [FirePro Series] + 1002 030c FirePro W8000 + 1002 0310 FirePro S9000 + 1002 0420 Radeon Sky 700 + 1002 0422 Radeon Sky 900 + 1002 0710 FirePro S9050 + 1002 0b0e FirePro S10000 Passive + 1002 0b2a FirePro S10000 + 1028 030c FirePro W8000 + 1028 0710 FirePro S9000 + 6798 Tahiti XT [Radeon HD 7970/8970 OEM / R9 280X] + 1002 3000 Tahiti XT2 [Radeon HD 7970 GHz Edition] + 1002 3001 Tahiti XTL [Radeon R9 280X] + 1002 4000 Radeon HD 8970 OEM + 1043 041c HD 7970 DirectCU II + 1043 0420 HD 7970 DirectCU II TOP + 1043 0444 HD 7970 DirectCU II TOP + 1043 0448 HD 7970 DirectCU II TOP + 1043 044a Tahiti XT2 [Matrix HD 7970] + 1043 044c Tahiti XT2 [Matrix HD 7970 Platinum] + 1043 3001 Tahiti XTL [ROG Matrix R9 280X] + 1043 3006 Tahiti XTL [Radeon R9 280X DirectCU II TOP] + 1043 9999 ARES II + 1092 3000 Tahiti XT2 [Radeon HD 7970 GHz Edition] + 1458 2261 Tahiti XT2 [Radeon HD 7970 GHz Edition OC] +# GV-R928XOC-3GD + 1458 3001 Tahiti XTL [Radeon R9 280X OC] + 1462 2774 MSI R7970 TF 3GD5/OC BE + 1682 3211 Double D HD 7970 Black Edition +# FX-797A-TNBC + 1682 3213 HD 7970 Black Edition + 1682 3214 Double D HD 7970 + 1787 201c HD 7970 IceQ X² +# Radeon HD 7970 X2 + 1787 2317 Radeon HD 7990 + 1787 3000 Tahiti XT2 [Radeon HD 7970 GHz Edition] + 6799 New Zealand [Radeon HD 7900 Series] + 679a Tahiti PRO [Radeon HD 7950/8950 OEM / R9 280] + 1002 0b01 Radeon HD 8950 OEM + 1002 3000 Tahiti PRO2 [Radeon HD 7950 Boost] + 1462 3000 Radeon HD 8950 OEM + 174b a003 Radeon R9 280 + 679b Malta [Radeon HD 7990] + 1002 0b28 Radeon HD 8990 OEM + 1002 0b2a Radeon HD 7990 + 1462 8036 Radeon HD 8990 OEM + 148c 8990 Radeon HD 8990 OEM + 679e Tahiti LE [Radeon HD 7870 XT] + 679f Tahiti + 67a0 Hawaii XT GL [FirePro W9100] + 1002 0335 FirePro S9150 + 1028 031f FirePro W9100 + 1028 0335 FirePro S9150 + 67a1 Hawaii PRO GL [FirePro W8100] + 1002 0335 FirePro S9100 + 1028 0335 FirePro S9100 + 67a2 Hawaii GL + 67a8 Hawaii + 67a9 Hawaii + 67aa Hawaii + 67b0 Hawaii XT [Radeon R9 290X] + 1043 046a R9 290X DirectCU II + 1043 046c R9 290X DirectCU II OC + 1043 0474 Matrix R9 290X Platinum + 1043 0476 ARES III + 1458 227c R9 290X WindForce 3X OC + 1458 2281 R9 290X WindForce 3X OC + 1458 228c R9 290X WindForce 3X + 1458 228d R9 290X WindForce 3X OC + 1458 2290 R9 290X WindForce 3X + 1462 3070 R9 290X Lightning + 1462 3071 R9 290X Lightning + 1462 3072 R9 290X Lightning LE + 1462 3080 R9 290X Gaming + 1462 3082 R9 290X Gaming OC + 148c 2347 Devil 13 Dual Core R9 290X + 1682 9290 Double Dissipation R9 290X + 174b e282 Vapor-X R9 290X Tri-X OC + 174b e285 R9 290X Tri-X OC + 1787 2020 R9 290X IceQ X² Turbo + 67b1 Hawaii PRO [Radeon R9 290] + 67b9 Vesuvius [Radeon R9 295X2] + 67be Hawaii LE 6800 Wimbledon XT [Radeon HD 7970M] - 6818 Pitcairn [Radeon HD 7800] - 6819 Pitcairn PRO [Radeon HD 7800] - 6820 Radeon HD 8800M Series - 6821 Radeon HD 8800M Series - 6823 Radeon HD 8800M Series - 6825 Cape Verde [Radeon HD 7800M Series] - 682b Radeon HD 8800M Series - 682f Cape Verde [Radeon HD 7700M Series] - 683b Cape Verde [Radeon HD 7700 Series] - 683d Cape Verde [Radeon HD 7700 Series] - 683f Cape Verde PRO [Radeon HD 7700 Series] - 6840 Thames XT/GL [Radeon HD 7600M Series] - 6841 Thames [Radeon 7500M/7600M Series] + 1002 0124 Radeon HD 7970M + 8086 2110 Radeon HD 7970M + 8086 2111 Radeon HD 7970M + 6801 Neptune XT [Radeon HD 8970M] + 1002 0124 Radeon HD 8970M + 1462 1117 Radeon R9 M290X + 8086 2110 Radeon HD 8970M + 8086 2111 Radeon HD 8970M + 6802 Wimbledon + 6806 Neptune + 6808 Pitcairn XT GL [FirePro W7000] + 1002 0310 FirePro S7000 + 1002 0420 Radeon Sky 500 + 6809 Pitcairn LE GL [FirePro W5000] + 6810 Curacao XT [Radeon R7 370 / R9 270X/370 OEM] + 148c 0908 Radeon R9 370 OEM + 1682 7370 Radeon R7 370 + 6811 Curacao PRO [Radeon R7 370 / R9 270/370 OEM] + 1028 0b00 Trinidad PRO [Radeon R9 370 OEM] + 1043 2016 Trinidad PRO [Radeon R9 370 OEM] + 1458 2016 Trinidad PRO [Radeon R9 370 OEM] + 1462 2016 Trinidad PRO [Radeon R9 370 OEM] + 148c 2016 Trinidad PRO [Radeon R9 370 OEM] + 1682 2015 Trinidad PRO [Radeon R7 370] + 174b 2016 Trinidad PRO [Radeon R9 370 OEM] + 1787 2016 Trinidad PRO [Radeon R9 370 OEM] + 6816 Pitcairn + 6817 Pitcairn + 6818 Pitcairn XT [Radeon HD 7870 GHz Edition] + 1002 0b05 Radeon HD 8870 OEM + 174b 8b04 Radeon HD 8860 + 6819 Pitcairn PRO [Radeon HD 7850 / R7 265 / R9 270 1024SP] + 1682 7269 Radeon R9 270 1024SP + 1682 9278 Radeon R9 270 1024SP + 174b a008 Radeon R9 270 1024SP + 174b e221 Radeon HD 7850 2GB GDDR5 DVI-I/DVI-D/HDMI/DP + 6820 Venus XTX [Radeon HD 8890M / R9 M275X/M375X] + 103c 1851 Radeon HD 7750M + 17aa 3643 Radeon R9 A375 + 17aa 3801 Radeon R9 M275 + 17aa 3824 Radeon R9 M375 + 6821 Venus XT [Radeon HD 8870M / R9 M270X/M370X] + 1002 031e FirePro SX4000 + 1028 05cc FirePro M5100 + 1028 15cc FirePro M5100 + 106b 0149 Radeon R9 M370X Mac Edition + 6822 Venus PRO [Radeon E8860] + 6823 Venus PRO [Radeon HD 8850M / R9 M265X] + 6825 Heathrow XT [Radeon HD 7870M] + 1028 053f FirePro M6000 + 1028 05cd FirePro M6000 + 1028 15cd FirePro M6000 + 103c 176c FirePro M6000 + 8086 2111 Chelsea PRO + 6826 Chelsea LP [Radeon HD 7700M Series] + 6827 Heathrow PRO [Radeon HD 7850M/8850M] + 6828 Cape Verde PRO [FirePro W600] + 6829 Cape Verde + 682a Venus PRO + 682b Venus LE [Radeon HD 8830M] + 682c Cape Verde GL [FirePro W4100] + 682d Chelsea XT GL [FirePro M4000] + 682f Chelsea LP [Radeon HD 7730M] + 103c 1851 Radeon HD 7750M + 6830 Cape Verde [Radeon HD 7800M Series] + 6831 Cape Verde [AMD Radeon HD 7700M Series] + 6835 Cape Verde PRX [Radeon R9 255 OEM] + 6837 Cape Verde LE [Radeon HD 7730/8730] + 1462 2796 Radeon HD 8730 + 1462 8092 Radeon HD 8730 + 148c 8730 Radeon HD 8730 + 1787 3000 Radeon HD 6570 + 683d Cape Verde XT [Radeon HD 7770/8760 / R7 250X] + 1002 0030 Radeon HD 8760 OEM + 1019 0030 Radeon HD 8760 OEM + 103c 6890 Radeon HD 8760 OEM + 1043 8760 Radeon HD 8760 OEM + 1462 2710 R7770-PMD1GD5 + 174b 8304 Radeon HD 8760 OEM + 683f Cape Verde PRO [Radeon HD 7750/8740 / R7 250E] + 1462 2790 Radeon HD 8740 + 1462 2791 Radeon HD 8740 + 1642 3b97 Radeon HD 8740 + 6840 Thames [Radeon HD 7500M/7600M Series] + 1025 050e Radeon HD 7670M + 1025 050f Radeon HD 7670M + 1025 0513 Radeon HD 7670M + 1025 0514 Radeon HD 7670M + 1025 056d Radeon HD 7670M + 1025 059a Radeon HD 7670M + 1025 059b Radeon HD 7670M + 1025 059e Radeon HD 7670M + 1025 0600 Radeon HD 7670M + 1025 0606 Radeon HD 7670M + 1025 0696 Radeon HD 7650M + 1025 0697 Radeon HD 7650M + 1025 0698 Radeon HD 7650M + 1025 0699 Radeon HD 7650M + 1025 0757 Radeon HD 7670M + 1028 056a Radeon HD 7670M + 1028 056e Radeon HD 7670M + 1028 0598 Radeon HD 7670M + 1028 059d Radeon HD 7670M + 1028 05a3 Radeon HD 7670M + 1028 05b9 Radeon HD 7670M + 1028 05bb Radeon HD 7670M + 103c 1789 FirePro M2000 + 103c 17f1 Radeon HD 7570M + 103c 17f4 Radeon HD 7650M + 103c 1813 Radeon HD 7590M + 103c 182f Radeon HD 7670M + 103c 1830 Radeon HD 7670M + 103c 1835 Radeon HD 7670M + 103c 183a Radeon HD 7670M + 103c 183c Radeon HD 7670M + 103c 183e Radeon HD 7670M + 103c 1840 Radeon HD 7670M + 103c 1842 Radeon HD 7670M + 103c 1844 Radeon HD 7670M + 103c 1848 Radeon HD 7670M + 103c 184a Radeon HD 7670M + 103c 184c Radeon HD 7670M + 103c 1895 Radeon HD 7670M + 103c 1897 Radeon HD 7670M + 103c 18a5 Radeon HD 7670M + 103c 18a7 Radeon HD 7670M + 103c 18f4 Radeon HD 7670M + 1043 100a Radeon HD 7670M + 1043 104b Radeon HD 7670M + 1043 10dc Radeon HD 7670M + 1043 2121 Radeon HD 7670M + 1043 2122 Radeon HD 7670M + 1043 2123 Radeon HD 7670M + 1043 2125 Radeon HD 7670M + 1043 2127 Radeon HD 7670M + 1179 fb11 Radeon HD 7670M + 1179 fb22 Radeon HD 7670M + 1179 fb23 Radeon HD 7670M + 1179 fb2c Radeon HD 7670M + 1179 fb31 Radeon HD 7670M + 1179 fb32 Radeon HD 7670M + 1179 fb38 Radeon HD 7670M + 1179 fb39 Radeon HD 7670M + 1179 fb3a Radeon HD 7670M + 1179 fb40 Radeon HD 7670M + 1179 fb41 Radeon HD 7670M + 1179 fb47 Radeon HD 7670M + 1179 fb48 Radeon HD 7670M + 1179 fb51 Radeon HD 7670M + 1179 fb52 Radeon HD 7670M + 1179 fb53 Radeon HD 7670M + 1179 fb81 Radeon HD 7670M + 1179 fb82 Radeon HD 7670M + 1179 fb83 Radeon HD 7670M + 1179 fc56 Radeon HD 7670M + 1179 fcd4 Radeon HD 7670M + 1179 fcee Radeon HD 7670M + 144d c0c5 Radeon HD 7690M + 144d c0ce Radeon HD 7670M + 144d c0da Radeon HD 7670M + 17aa 3970 Radeon HD 7670M + 17aa 397b Radeon HD 7670M + 17aa 5101 Radeon HD 7670M + 17aa 5102 Radeon HD 7670M + 17aa 5103 Radeon HD 7670M + 6841 Thames [Radeon HD 7550M/7570M/7650M] + 1028 0561 Radeon HD 7650M + 1028 056c Radeon HD 7650M + 1028 057f Radeon HD 7570M + 103c 17f1 Radeon HD 7570M + 103c 17f4 Radeon HD 7650M + 103c 1813 Radeon HD 7570M + 103c 183a Radeon HD 7650M + 103c 183c Radeon HD 7650M + 103c 183e Radeon HD 7650M + 103c 1840 Radeon HD 7650M + 103c 1842 Radeon HD 7650M + 103c 1844 Radeon HD 7650M + 1043 100a Radeon HD 7650M + 1043 104b Radeon HD 7650M + 1043 10dc Radeon HD 7650M + 1043 2134 Radeon HD 7650M + 1179 0001 Radeon HD 7570M + 1179 0002 Radeon HD 7570M + 1179 fb43 Radeon HD 7550M + 1179 fb91 Radeon HD 7550M + 1179 fb92 Radeon HD 7550M + 1179 fb93 Radeon HD 7550M + 1179 fba2 Radeon HD 7550M + 1179 fba3 Radeon HD 7550M + 144d c0c7 Radeon HD 7550M 6842 Thames LE [Radeon HD 7000M Series] 6843 Thames [Radeon HD 7670M] - 6850 Lombok GL AIO [Radeon HD 7570] - 6858 Lombok [Radeon HD 7400 series] - 6888 Cypress [FirePro 3D V8800] - 6889 Cypress [FirePro V7800] - 688a Cypress XT [FirePro 3D V9800] - 688c Cypress [AMD FireStream 9370] - 688d Cypress [AMD FireStream 9350] + 6888 Cypress XT [FirePro V8800] + 6889 Cypress PRO [FirePro V7800] + 1002 0301 FirePro V7800P + 688a Cypress XT [FirePro V9800] + 1002 030c FirePro V9800P + 688c Cypress XT GL [FireStream 9370] + 688d Cypress PRO GL [FireStream 9350] 6898 Cypress XT [Radeon HD 5870] - 1462 8032 R5870 PM2D1G - 6899 Cypress PRO [Radeon HD 5800 Series] - 1043 0330 EAH5850 [Radeon HD5850] - 689b Cypress [Radeon HD 6800 Series] - 689c Hemlock [Radeon HD 5900 Series] - 689e Cypress LE [Radeon HD 5800 Series] - 68a0 Broadway XT [Mobility Radeon HD 5800 Series] - 103c 1520 Broadway XT [FirePro M7820] - 68a1 Broadway PRO [Mobility Radeon HD 5800 Series] - 68a8 Broadway [ATI Mobility Radeon HD 6800 Series] - 68a9 Juniper XT [FirePro 3D V5800] - 68b8 Juniper [Radeon HD 5700 Series] + 1002 0b00 Radeon HD 5870 Eyefinity⁶ Edition + 106b 00d0 Radeon HD 5870 Mac Edition +# R5870-PM2D1G + 1462 8032 Radeon HD 5870 1 GB GDDR5 + 174b 6870 Radeon HD 6870 1600SP Edition + 6899 Cypress PRO [Radeon HD 5850] +# EAH5850 + 1043 0330 Radeon HD 5850 + 174b 237b Radeon HD 5850 X2 + 174b 6850 Radeon HD 6850 1440SP Edition + 689b Cypress PRO [Radeon HD 6800 Series] + 689c Hemlock [Radeon HD 5970] + 1043 0352 ARES + 689d Hemlock [Radeon HD 5970] + 689e Cypress LE [Radeon HD 5830] + 68a0 Broadway XT [Mobility Radeon HD 5870] + 1028 12ef FirePro M7820 + 103c 1520 FirePro M7820 + 68a1 Broadway PRO [Mobility Radeon HD 5850] + 106b 00cc iMac MC511 Mobility Radeon HD 5850 MXM Module + 68a8 Granville [Radeon HD 6850M/6870M] + 1025 0442 Radeon HD 6850M + 1025 0451 Radeon HD 6850M + 1025 050a Radeon HD 6850M + 1025 050b Radeon HD 6850M + 1025 050c Radeon HD 6850M + 1025 050e Radeon HD 6850M + 1025 050f Radeon HD 6850M + 1025 0513 Radeon HD 6850M + 1025 0514 Radeon HD 6850M + 1025 0515 Radeon HD 6850M + 1025 0516 Radeon HD 6850M + 1025 0525 Radeon HD 6850M + 1025 0526 Radeon HD 6850M + 1025 056d Radeon HD 6850M + 1028 048f Radeon HD 6870M + 1028 0490 Radeon HD 6870M + 1028 04b9 Radeon HD 6870M + 1028 04ba Radeon HD 6870M + 103c 159b Radeon HD 6850M + 144d c0ad Radeon HD 6850M + 68a9 Juniper XT [FirePro V5800] + 68b8 Juniper XT [Radeon HD 5770] 106b 00cf MacPro5,1 [Mac Pro 2.8GHz DDR3] - 68b9 Juniper [Radeon HD 5600/5700] - 68ba Juniper XT [AMD Radeon HD 6000 Series] - 68be Juniper [Radeon HD 5700 Series] - 68bf Juniper LE [Radeon HD 6700 Series] - 68c0 Madison [Mobility Radeon HD 5000 Series] + 68b9 Juniper LE [Radeon HD 5670 640SP Edition] + 68ba Juniper XT [Radeon HD 6770] + 68be Juniper PRO [Radeon HD 5750] + 148c 3000 Radeon HD 6750 + 68bf Juniper PRO [Radeon HD 6750] + 174b 6750 Radeon HD 6750 + 68c0 Madison [Mobility Radeon HD 5730 / 6570M] + 1019 2383 Mobility Radeon HD 5730 + 1028 02a2 Mobility Radeon HD 5730 + 1028 02fe Mobility Radeon HD 5730 + 1028 0419 Mobility Radeon HD 5730 + 103c 147d Mobility Radeon HD 5730 103c 1521 Madison XT [FirePro M5800] - 68c1 Madison [Radeon HD 5000M Series] + 103c 1593 Mobility Radeon HD 6570 + 103c 1596 Mobility Radeon HD 6570 + 103c 1599 Mobility Radeon HD 6570 + 1043 1c22 Mobility Radeon HD 5730 + 17aa 3927 Mobility Radeon HD 5730 + 17aa 3952 Mobility Radeon HD 5730 + 17aa 3978 Radeon HD 6570M + 68c1 Madison [Mobility Radeon HD 5650/5750 / 6530M/6550M] + 1025 0205 Mobility Radeon HD 5650 + 1025 0293 Mobility Radeon HD 5650 + 1025 0294 Mobility Radeon HD 5650 + 1025 0296 Mobility Radeon HD 5650 + 1025 0308 Mobility Radeon HD 5650 + 1025 030a Mobility Radeon HD 5650 + 1025 0311 Mobility Radeon HD 5650 + 1025 0312 Mobility Radeon HD 5650 + 1025 031c Mobility Radeon HD 5650 + 1025 031d Mobility Radeon HD 5650 1025 033d Mobility Radeon HD 5650 + 1025 033e Mobility Radeon HD 5650 + 1025 033f Mobility Radeon HD 5650 + 1025 0346 Mobility Radeon HD 5650 1025 0347 Aspire 7740G + 1025 0348 Mobility Radeon HD 5650 + 1025 0356 Mobility Radeon HD 5650 + 1025 0357 Mobility Radeon HD 5650 + 1025 0358 Mobility Radeon HD 5650 + 1025 0359 Mobility Radeon HD 5650 + 1025 035a Mobility Radeon HD 5650 + 1025 035b Mobility Radeon HD 5650 + 1025 035c Mobility Radeon HD 5650 + 1025 035d Mobility Radeon HD 5650 + 1025 035e Mobility Radeon HD 5650 + 1025 0360 Mobility Radeon HD 5650 + 1025 0362 Mobility Radeon HD 5650 + 1025 0364 Mobility Radeon HD 5650 + 1025 0365 Mobility Radeon HD 5650 + 1025 0366 Mobility Radeon HD 5650 + 1025 0367 Mobility Radeon HD 5650 + 1025 0368 Mobility Radeon HD 5650 + 1025 036c Mobility Radeon HD 5650 + 1025 036d Mobility Radeon HD 5650 + 1025 036e Mobility Radeon HD 5650 + 1025 036f Mobility Radeon HD 5650 + 1025 0372 Mobility Radeon HD 5650 + 1025 0373 Mobility Radeon HD 5650 + 1025 0377 Mobility Radeon HD 5650 + 1025 0378 Mobility Radeon HD 5650 + 1025 0379 Mobility Radeon HD 5650 + 1025 037a Mobility Radeon HD 5650 + 1025 037b Mobility Radeon HD 5650 + 1025 037e Mobility Radeon HD 5650 + 1025 037f Mobility Radeon HD 5650 + 1025 0382 Mobility Radeon HD 5650 + 1025 0383 Mobility Radeon HD 5650 + 1025 0384 Mobility Radeon HD 5650 + 1025 0385 Mobility Radeon HD 5650 + 1025 0386 Mobility Radeon HD 5650 + 1025 0387 Mobility Radeon HD 5650 + 1025 0388 Mobility Radeon HD 5650 + 1025 038b Mobility Radeon HD 5650 + 1025 038c Mobility Radeon HD 5650 + 1025 039a Mobility Radeon HD 5650 + 1025 0411 Mobility Radeon HD 5650 + 1025 0412 Mobility Radeon HD 5650 + 1025 0418 Mobility Radeon HD 5650 + 1025 0419 Mobility Radeon HD 5650 + 1025 0420 Mobility Radeon HD 5650 + 1025 0421 Mobility Radeon HD 5650 + 1025 0425 Mobility Radeon HD 5650 + 1025 042a Mobility Radeon HD 5650 + 1025 042e Mobility Radeon HD 5650 + 1025 042f Mobility Radeon HD 5650 + 1025 0432 Mobility Radeon HD 5650 + 1025 0433 Mobility Radeon HD 5650 + 1025 0442 Mobility Radeon HD 5650 + 1025 044c Mobility Radeon HD 5650 + 1025 044e Mobility Radeon HD 5650 + 1025 0451 Mobility Radeon HD 5650 + 1025 0454 Mobility Radeon HD 5650 + 1025 0455 Mobility Radeon HD 5650 + 1025 0475 Mobility Radeon HD 5650 + 1025 0476 Mobility Radeon HD 5650 + 1025 0487 Mobility Radeon HD 5650 + 1025 0489 Mobility Radeon HD 5650 + 1025 0498 Mobility Radeon HD 5650 + 1025 0517 Radeon HD 6550M + 1025 051a Radeon HD 6550M + 1025 051b Radeon HD 6550M + 1025 051c Radeon HD 6550M + 1025 051d Radeon HD 6550M + 1025 0525 Radeon HD 6550M + 1025 0526 Radeon HD 6550M + 1025 052b Radeon HD 6550M + 1025 052c Radeon HD 6550M + 1025 053c Radeon HD 6550M + 1025 053d Radeon HD 6550M + 1025 053e Radeon HD 6550M + 1025 053f Radeon HD 6550M + 1025 0607 Radeon HD 6550M + 1028 041b Mobility Radeon HD 5650 + 1028 0447 Mobility Radeon HD 5650 + 1028 0448 Mobility Radeon HD 5650 + 1028 0456 Mobility Radeon HD 5650 + 1028 0457 Mobility Radeon HD 5650 + 103c 1436 Mobility Radeon HD 5650 + 103c 1437 Mobility Radeon HD 5650 + 103c 1440 Mobility Radeon HD 5650 + 103c 1448 Mobility Radeon HD 5650 + 103c 1449 Mobility Radeon HD 5650 + 103c 144a Mobility Radeon HD 5650 + 103c 144b Mobility Radeon HD 5650 + 103c 147b Mobility Radeon HD 5650 + 103c 149c Mobility Radeon HD 5650 + 103c 149e Mobility Radeon HD 5650 103c 1521 Madison Pro [FirePro M5800] - 68c7 Pinewood [Radeon HD 5570] - 68c8 FirePro V4800 - 68d8 Redwood [Radeon HD 5670] - 68d9 Redwood PRO [Radeon HD 5500 Series] - 68da Redwood PRO [Radeon HD 5500 Series] - 68e0 Manhattan [Mobility Radeon HD 5400 Series] + 1043 1bc2 Mobility Radeon HD 5650 + 104d 9071 Mobility Radeon HD 5650 + 104d 9077 Mobility Radeon HD 5650 + 104d 9081 Mobility Radeon HD 5650 + 1179 fd00 Mobility Radeon HD 5650 + 1179 fd12 Mobility Radeon HD 5650 + 1179 fd1a Mobility Radeon HD 5650 + 1179 fd30 Mobility Radeon HD 5650 + 1179 fd31 Mobility Radeon HD 5650 + 1179 fd50 Mobility Radeon HD 5650 + 1179 fd52 Radeon HD 6530M + 1179 fd63 Radeon HD 6530M + 1179 fd65 Radeon HD 6530M + 1179 fdd0 Mobility Radeon HD 5650 + 1179 fdd2 Radeon HD 6530M + 144d c07e Mobility Radeon HD 5650 + 144d c085 Mobility Radeon HD 5650 + 14c0 0043 Mobility Radeon HD 5650 + 14c0 004d Mobility Radeon HD 5650 + 17aa 3928 Mobility Radeon HD 5650 + 17aa 3951 Mobility Radeon HD 5650 + 17aa 3977 Radeon HD 6550M + 68c7 Madison [Mobility Radeon HD 5570/6550A] + 1462 2241 Mobility Radeon HD 5570 + 1462 2243 Mobility Radeon HD 5570 + 1462 2244 Mobility Radeon HD 5570 + 1462 2245 Radeon HD 6550A + 1462 2246 Radeon HD 6550A + 68c8 Redwood XT GL [FirePro V4800] + 68c9 Redwood PRO GL [FirePro V3800] + 68d8 Redwood XT [Radeon HD 5670/5690/5730] + 1028 68e0 Radeon HD 5670 + 174b 5690 Radeon HD 5690 + 174b 5730 Radeon HD 5730 + 174b e151 Radeon HD 5670 + 1787 3000 Radeon HD 5730 + 17af 3010 Radeon HD 5730 + 17af 3011 Radeon HD 5690 + 68d9 Redwood PRO [Radeon HD 5550/5570/5630/6510/6610/7570] + 103c 6870 Radeon HD 5570 + 103c 6872 Radeon HD 5570 + 1043 03ce Radeon HD 5550 + 1462 2151 Radeon HD 5570 + 1462 2240 Radeon HD 5570 + 148c 3000 Radeon HD 6510 + 148c 3001 Radeon HD 6610 + 1545 5550 Radeon HD 5550 + 1545 7570 Radeon HD 7570 + 1642 3985 Radeon HD 5570 + 1642 3996 Radeon HD 5570 + 174b 3000 Radeon HD 6510 + 174b 6510 Radeon HD 6510 + 174b 6610 Radeon HD 6610 + 174b e142 Radeon HD 5570 + 1787 3000 Radeon HD 6510 + 17af 3000 Radeon HD 6510 + 17af 3010 Radeon HD 5630 + 68da Redwood LE [Radeon HD 5550/5570/5630/6390/6490/7570] + 148c 3000 Radeon HD 6390 + 148c 3001 Radeon HD 6490 + 1545 7570 Radeon HD 7570 + 174b 3000 Radeon HD 6390 + 174b 5570 Radeon HD 5570 + 174b 5630 Radeon HD 5630 + 174b 6490 Radeon HD 6490 + 1787 3000 Radeon HD 5630 + 17af 3000 Radeon HD 6390 + 17af 3010 Radeon HD 5630 + 68de Redwood + 68e0 Park [Mobility Radeon HD 5430/5450/5470] + 1028 0404 Mobility Radeon HD 5450 + 1028 0414 Mobility Radeon HD 5450 + 1028 0434 Mobility Radeon HD 5450 + 103c 1433 Mobility Radeon HD 5450 + 103c 1434 Mobility Radeon HD 5450 + 103c 1469 Mobility Radeon HD 5450 + 103c 146b Mobility Radeon HD 5450 103c 1486 TouchSmart tm2-2050er discrete GPU (Mobility Radeon HD 5450) - 68e1 Manhattan [Mobility Radeon HD 5430 Series] - 68e4 Robson CE [AMD Radeon HD 6300 Series] - 68e5 Robson LE [AMD Radeon HD 6300M Series] - 68f1 Cedar [FirePro 2460] - 68f2 Cedar [FirePro 2270] - 68f9 Cedar PRO [Radeon HD 5450/6350] + 103c 1622 Mobility Radeon HD 5450 + 103c 1623 Mobility Radeon HD 5450 + 103c eeee Mobility Radeon HD 5450 + 104d 9076 Mobility Radeon HD 5450 + 1682 304e Caicos [Radeon HD 5450] + 1682 6000 Caicos [Radeon HD 5450] + 17aa 9e52 FirePro M3800 + 17aa 9e53 FirePro M3800 + 68e1 Park [Mobility Radeon HD 5430] + 1043 041f Caicos [Radeon HD 7350] + 1043 3000 Caicos [Radeon HD 5450] + 148c 3000 Caicos [Radeon HD 5450] + 148c 3001 Caicos [Radeon HD 6230] + 148c 3002 Caicos [Radeon HD 6250] + 148c 3003 Caicos [Radeon HD 6350] + 148c 7350 Caicos [Radeon HD 7350] + 148c 8350 Caicos [Radeon HD 8350] + 1545 5450 Caicos [Radeon HD 5450] + 1545 7350 Caicos [Radeon HD 7350] + 1682 3000 Caicos [Radeon HD 5450] + 1682 6000 Caicos [Radeon HD 5450] + 1682 7350 Caicos [Radeon HD 7350] + 174b 3000 Caicos [Radeon HD 5450] + 174b 5470 Caicos [Radeon HD 5470] + 174b 6000 Caicos [Radeon HD 5450] + 174b 6230 Caicos [Radeon HD 6230] + 174b 6350 Caicos [Radeon HD 6350] + 174b 7350 Caicos [Radeon HD 7350] + 1787 3000 Caicos [Radeon HD 5450] + 17af 3000 Caicos [Radeon HD 5450] + 17af 3001 Caicos [Radeon HD 6230] + 17af 3014 Caicos [Radeon HD 6350] + 17af 3015 Caicos [Radeon HD 7350] + 17af 8350 Caicos [Radeon HD 8350 OEM] + 68e4 Robson CE [Radeon HD 6370M/7370M] + 1019 2386 Radeon HD 6350M + 1019 2387 Radeon HD 6350M + 1019 238d Radeon HD 6370M + 1019 238e Radeon HD 6370M + 1025 0382 Radeon HD 6370M + 1025 0489 Radeon HD 6370M + 1025 048a Radeon HD 6370M + 1025 048b Radeon HD 6370M + 1025 048c Radeon HD 6370M + 1028 04c1 Radeon HD 6370M + 1028 04ca Radeon HD 6370M + 1028 04cc Radeon HD 6370M + 1028 04cd Radeon HD 6370M + 1028 04d7 Radeon HD 6370M + 103c 1411 Radeon HD 6370M + 103c 1421 Radeon HD 6370M + 103c 1426 Radeon HD 6370M + 103c 1428 Radeon HD 6370M + 103c 142a Radeon HD 6370M + 103c 142b Radeon HD 6370M + 103c 143a Radeon HD 6370M + 103c 143c Radeon HD 6370M + 103c 1445 Radeon HD 6370M + 103c 162c Radeon HD 6370M + 103c 162d Radeon HD 6370M + 103c 162e Radeon HD 6370M + 103c 162f Radeon HD 6370M + 103c 1639 Radeon HD 6370M + 103c 163a Radeon HD 6370M + 103c 163b Radeon HD 6370M + 103c 163c Radeon HD 6370M + 103c 163d Radeon HD 6370M + 103c 163e Radeon HD 6370M + 103c 163f Radeon HD 6370M + 103c 1641 Radeon HD 6370M + 103c 1643 Radeon HD 6370M + 103c 3578 Radeon HD 6370M + 103c 357a Radeon HD 6370M + 103c 3673 Radeon HD 6370M + 103c 3675 Radeon HD 6370M + 1043 1c92 Radeon HD 6370M + 1043 84a1 Radeon HD 6370M + 1043 84ad Radeon HD 6370M + 104d 9081 Radeon HD 6370M + 1545 7350 Cedar [Radeon HD 7350] + 1558 4510 Radeon HD 6370M + 1558 5505 Radeon HD 6370M + 174b 5450 Cedar [Radeon HD 5450] + 17aa 21dd Radeon HD 6370M + 17aa 21e9 Radeon HD 6370M + 17aa 3971 Radeon HD 6370M + 17aa 3972 Radeon HD 7370M + 17aa 397a Radeon HD 6370M/7370M + 17aa 397b Radeon HD 6370M/7370M + 17aa 397f Radeon HD 7370M + 68e5 Robson LE [Radeon HD 6330M] + 1179 fd3c Radeon HD 6330M + 1179 fd50 Radeon HD 6330M + 1179 fd52 Radeon HD 6330M + 1179 fd63 Radeon HD 6330M + 1179 fd65 Radeon HD 6330M + 1179 fd73 Radeon HD 6330M + 1179 fd75 Radeon HD 6330M + 1179 fdd0 Radeon HD 6330M + 1179 fdd2 Radeon HD 6330M + 1179 fdea Radeon HD 6330M + 1179 fdf8 Radeon HD 6330M + 148c 5450 Cedar [Radeon HD 5450] + 148c 6350 Cedar [Radeon HD 6350] + 148c 7350 Cedar [Radeon HD 7350] + 148c 8350 Cedar [Radeon HD 8350] + 1545 7350 Cedar [Radeon HD 7350] + 68e8 Cedar + 68e9 Cedar [ATI FirePro (FireGL) Graphics Adapter] + 68f1 Cedar GL [FirePro 2460] + 68f2 Cedar GL [FirePro 2270] + 68f8 Cedar [Radeon HD 7300 Series] + 68f9 Cedar [Radeon HD 5000/6000/7350/8350 Series] + 1019 0001 Radeon HD 5450 + 1019 0002 Radeon HD 5450 + 1019 0019 Radeon HD 6350 + 1025 0518 Radeon HD 5450 + 1025 0519 Radeon HD 5450 1028 010e XPS 8300 - 68fa EG Cedar [Radeon HD 7300 Series] - 700f PCI Bridge [IGP 320M] - 7010 PCI Bridge [IGP 340M] - 7100 R520 [Radeon X1800] - 7102 M58 [Radeon Mobility X1800] - 7103 M58 [Mobility FireGL V7200] - 7104 R520GL [FireGL V7200] (Primary) - 7105 R520 [FireGL] - 7106 M58 [Mobility FireGL V7100] - 7108 M58 [Radeon Mobility X1800] - 7109 R520 [Radeon X1800] + 1028 2126 Radeon HD 6350 + 103c 2126 Radeon HD 6350 + 103c 2aac Radeon HD 5450 + 103c 2aae Radeon HD 5450 + 103c 3580 Radeon HD 5450 + 1043 0386 Radeon HD 5450 + 1043 03c2 EAH5450 SILENT/DI/512MD2 (LP) + 1462 2130 Radeon HD 5450 + 1462 2131 Radeon HD 5450 + 1462 2133 Radeon HD 6350 + 1462 2180 Radeon HD 5450 + 1462 2181 Radeon HD 5450 + 1462 2182 Radeon HD 6350 + 1462 2183 Radeon HD 6350 + 1462 2230 Radeon HD 5450 + 1462 2231 Radeon HD 5450 + 1462 2495 Radeon HD 6350 + 148c 3001 Radeon HD 5530/6250 + 148c 3002 Radeon HD 6290 + 148c 3003 Radeon HD 6230 + 148c 3004 Radeon HD 6350 + 148c 7350 Radeon HD 7350 + 148c 8350 Radeon HD 8350 + 1545 7350 Radeon HD 7350 + 1642 3983 Radeon HD 5450 + 1642 3984 Radeon HD 6350 + 1642 3987 Radeon HD 6350 + 1642 3997 Radeon HD 5450 + 1642 3a05 Radeon HD 5450 + 1642 3b31 Radeon HD 6350A + 1682 3270 Radeon HD 7350 + 174b 3000 Radeon HD 6230 + 174b 3987 Radeon HD 6350 + 174b 5470 Radeon HD 5470 + 174b 5490 Radeon HD 5490 + 174b 5530 Radeon HD 5530 + 174b 6230 Radeon HD 6230 + 174b 6250 Radeon HD 6250 + 174b 6290 Radeon HD 6290 + 174b 6350 Radeon HD 6350 + 174b 7350 Radeon HD 7350 + 174b 8350 Radeon HD 8350 + 174b e127 Radeon HD 5450 + 174b e145 Radeon HD 5450 + 174b e153 Radeon HD 5450 + 1787 3000 Radeon HD 5470 + 1787 3001 Radeon HD 5530 + 1787 3002 Radeon HD 5490 + 17aa 3602 Radeon HD 5450 + 17aa 3603 Radeon HD 5450 + 17aa 360f Radeon HD 5450 + 17aa 3619 Radeon HD 5450 + 17af 3000 Radeon HD 6250 + 17af 3001 Radeon HD 6230 + 17af 3002 Radeon HD 6290 + 17af 3011 Radeon HD 5470 + 17af 3012 Radeon HD 5490 + 17af 3013 Radeon HD 5470 + 17af 3014 Radeon HD 6350 + 68fa Cedar [Radeon HD 7350/8350 / R5 220] + 1019 0019 Radeon HD 7350 + 1019 0021 Radeon HD 7350 + 1019 0022 Radeon HD 7350 + 1019 0026 Radeon HD 8350 + 103c 2adf Radeon HD 7350A + 103c 2ae8 Radeon HD 7350A + 1043 8350 Radeon HD 8350 + 1462 2128 Radeon HD 7350 + 1462 2184 Radeon HD 7350 + 1462 2186 Radeon HD 7350 + 1462 2495 Radeon HD 7350 + 1462 b490 Radeon HD 7350 + 1642 3985 Radeon HD 7350 + 174b 3510 Radeon HD 8350 + 174b 3521 Radeon R5 220 + 174b 3522 Radeon R5 220 + 174b 7350 Radeon HD 7350 + 174b 8153 Radeon HD 8350 + 174b e127 Radeon HD 7350 + 174b e153 Radeon HD 7350 + 174b e180 Radeon HD 7350 + 17af 3015 Radeon HD 7350 + 68fe Cedar LE + 6900 Topaz XT [Radeon R7 M260/M265] + 1028 0640 Radeon R7 M265 + 103c 2269 Radeon R7 M260 + 103c 22c8 Radeon R7 M260 + 1179 f903 Radeon R7 M260 + 1179 f934 Radeon R7 M260 + 6901 Topaz PRO [Radeon R5 M255] + 6921 Amethyst XT [Radeon R9 M295X] + 6929 Tonga PRO GL [FirePro Series] + 692b Tonga PRO GL [FirePro W7100] + 692f Tonga XT GL [FirePro W8100] + 6938 Amethyst XT [Radeon R9 M295X Mac Edition] + 6939 Tonga PRO [Radeon R9 285/380] + 148c 9380 Radeon R9 380 + 700f RS100 AGP Bridge + 7010 RS200/RS250 AGP Bridge + 7100 R520 [Radeon X1800 XT] + 7101 R520/M58 [Mobility Radeon X1800 XT] + 7102 R520/M58 [Mobility Radeon X1800] + 7104 R520 GL [FireGL V7200] + 7109 R520 [Radeon X1800 XL] 1002 0322 All-in-Wonder X1800XL 1002 0d02 Radeon X1800 CrossFire Edition - 710a R520 [Radeon X1800] - 710b R520 [Radeon X1800] - 710c R520 [Radeon X1800] + 710a R520 [Radeon X1800 GTO] + 1002 0b12 Radeon X1800 GTO² + 710b R520 [Radeon X1800 GTO] 7120 R520 [Radeon X1800] (Secondary) - 7124 R520GL [FireGL V7200] (Secondary) + 7124 R520 GL [FireGL V7200] (Secondary) 7129 R520 [Radeon X1800] (Secondary) - 1002 0323 All-in-Wonder X1800XL (Secondary) + 1002 0323 All-In-Wonder X1800 XL (Secondary) 1002 0d03 Radeon X1800 CrossFire Edition (Secondary) - 7140 RV515 [Radeon X1600] + 7140 RV515 [Radeon X1300/X1550/X1600 Series] 7142 RV515 PRO [Radeon X1300/X1550 Series] 1002 0322 All-in-Wonder 2006 PCI-E Edition 1043 0142 EAX1300PRO/TD/256M - 7143 RV505 [Radeon X1550 Series] - 7145 Radeon Mobility X1400 + 7143 RV505 [Radeon X1300/X1550 Series] + 7145 RV515/M54 [Mobility Radeon X1400] 17aa 2006 Thinkpad T60 model 2007 - 7146 RV515 [Radeon X1300] + 7146 RV515 [Radeon X1300/X1550] 1002 0322 All-in-Wonder 2006 PCI-E Edition 1545 1996 Radeon X1300 512MB PCI-e 7147 RV505 [Radeon X1550 64-bit] - 7149 M52 [Mobility Radeon X1300] - 714a M52 [Mobility Radeon X1300] - 714b M52 [Mobility Radeon X1300] - 714c M52 [Mobility Radeon X1300] - 714d RV515 [Radeon X1300] - 714e RV515LE [Radeon X1300] - 7152 RV515GL [FireGL V3300] (Primary) - 7153 RV515GL [FireGL V3350] - 715e RV515 [Radeon X1300] + 7149 RV515/M52 [Mobility Radeon X1300] + 714a RV515/M52 [Mobility Radeon X1300] + 7152 RV515 GL [FireGL V3300] + 7153 RV515 GL [FireGL V3350] 715f RV505 CE [Radeon X1550 64-bit] 7162 RV515 PRO [Radeon X1300/X1550 Series] (Secondary) 1002 0323 All-in-Wonder 2006 PCI-E Edition (Secondary) 7163 RV505 [Radeon X1550 Series] (Secondary) - 7166 RV515 [Radeon X1300] (Secondary) + 7166 RV515 [Radeon X1300/X1550 Series] (Secondary) 1002 0323 All-in-Wonder 2006 PCI-E Edition (Secondary) 1545 1997 Radeon X1300 512MB PCI-e (Secondary) 7167 RV515 [Radeon X1550 64-bit] (Secondary) - 716e RV515LE [Radeon X1300] Secondary - 7172 RV515GL [FireGL V3300] (Secondary) - 7173 RV515GL [FireGL V3350] (Secondary) - 7180 RV516 [Radeon X1300/X1550 Series] - 7181 RV516 XT Radeon X1600 Series (Primary) + 7172 RV515 GL [FireGL V3300] (Secondary) + 7173 RV515 GL [FireGL V3350] (Secondary) + 7181 RV516 [Radeon X1600/X1650 Series] 7183 RV516 [Radeon X1300/X1550 Series] - 7186 RV515 [Radeon Mobility X1450] + 7186 RV516/M64 [Mobility Radeon X1450] 7187 RV516 [Radeon X1300/X1550 Series] - 7188 M64-S [Mobility Radeon X2300] + 7188 RV516/M64-S [Mobility Radeon X2300] 103c 30c1 6910p - 718a Mobility Radeon X2300 - 718c M62CSP64 [Mobility Radeon X1350] - 718d M64CSP128 [Mobility Radeon X1450] + 718a RV516/M64 [Mobility Radeon X2300] + 718b RV516/M62 [Mobility Radeon X1350] + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] + 718c RV516/M62-CSP64 [Mobility Radeon X1350] + 718d RV516/M64-CSP128 [Mobility Radeon X1450] 7193 RV516 [Radeon X1550 Series] - 7196 RV516 [Mobility Radeon X1350] - 719b FireMV 2250 - 719f RV516LE [Radeon X1550 64-bit] + 7196 RV516/M62-S [Mobility Radeon X1350] + 719b RV516 GL [FireMV 2250] + 719f RV516 [Radeon X1550 Series] 71a0 RV516 [Radeon X1300/X1550 Series] (Secondary) - 71a1 RV516 XT Radeon X1600 Series (Secondary) - 71a3 RV516 [Radeon X1300 Pro] (Secondary) + 71a1 RV516 [Radeon X1600/X1650 Series] (Secondary) + 71a3 RV516 [Radeon X1300/X1550 Series] (Secondary) 71a7 RV516 [Radeon X1300/X1550 Series] (Secondary) - 71bb FireMV 2250 (Secondary) - 71c0 RV530 [Radeon X1600] - 71c1 Radeon X1650 Pro - 71c2 RV530 [Radeon X1600] - 71c4 M56GL [Mobility FireGL V5200] + 71bb RV516 GL [FireMV 2250] (Secondary) + 71c0 RV530 [Radeon X1600 XT/X1650 GTO] + 1002 e160 Radeon X1650 GTO + 174b e160 Radeon X1650 GTO + 71c1 RV535 [Radeon X1650 PRO] + 174b 0880 Radeon X1700 FSC + 71c2 RV530 [Radeon X1600 PRO] + 71c4 RV530/M56 GL [Mobility FireGL V5200] 17aa 2007 ThinkPad T60p - 71c5 M56P [Radeon Mobility X1600] + 71c5 RV530/M56-P [Mobility Radeon X1600] 103c 309f Compaq nx9420 Notebook 103c 30a3 Compaq NW8440 1043 10b2 A6J-Q008 106b 0080 MacBook Pro 71c6 RV530LE [Radeon X1600/X1650 PRO] - 71c7 RV535 [Radeon X1650 Series] - 71ce RV530LE [Radeon X1600] - 71d2 RV530GL [FireGL V3400] - 71d4 M66GL [ATI Mobility FireGL V5250] - 71d5 M66-P [Mobility Radeon X1700] - 71d6 M66-XT [Mobility Radeon X1700] - 71de RV530LE [Radeon X1600] + 71c7 RV535 [Radeon X1650 PRO] + 1787 3000 PowerColor X1650 PRO AGP + 71ce RV530 [Radeon X1300 XT/X1600 PRO] + 71d2 RV530 GL [FireGL V3400] + 71d4 RV530/M66 GL [Mobility FireGL V5250] + 71d5 RV530/M66-P [Mobility Radeon X1700] + 71d6 RV530/M66-XT [Mobility Radeon X1700] + 71de RV530/M66 [Mobility Radeon X1700/X2500] 71e0 RV530 [Radeon X1600] (Secondary) - 71e1 Radeon X1650 Pro (Secondary) + 174b e161 Radeon X1600 GTO (Secondary) + 71e1 RV535 [Radeon X1650 PRO] (Secondary) + 174b 0881 Radeon X1700 FSC (Secondary) 71e2 RV530 [Radeon X1600] (Secondary) - 71e6 RV530LE [Radeon X1650 PRO] (Secondary) - 71e7 RV535 [Radeon X1650 Series] - 71f2 RV530GL [FireGL V3400 (Secondary)] - 7210 M71 [Mobility Radeon X2100] - 7211 M71 [Mobility Radeon X2100] (Secondary) - 7240 R580 [Radeon X1900] - 7241 R580 [Radeon X1900] - 7242 R580 [Radeon X1900] - 7243 R580 [Radeon X1900] - 7244 R580 [Radeon X1900] - 7245 R580 [Radeon X1900] - 7246 R580 [Radeon X1900] - 7247 R580 [Radeon X1900] - 7248 R580 [Radeon X1900] - 7249 R580 [Radeon X1900 XT] (Primary) - 724a R580 [Radeon X1900] - 724b R580 [Radeon X1900] + 71e6 RV530 [Radeon X1650] (Secondary) + 71e7 RV535 [Radeon X1650 PRO] (Secondary) + 1787 3001 Radeon X1650 PRO AGP + 71f2 RV530 GL [FireGL V3400] (Secondary) + 7210 RV550/M71 [Mobility Radeon HD 2300] + 7211 RV550/M71 [Mobility Radeon X2300 HD] + 7240 R580+ [Radeon X1950 XTX] + 1002 0d02 Radeon X1950 CrossFire Edition + 7244 R580+ [Radeon X1950 XT] + 7248 R580 [Radeon X1950] + 7249 R580 [Radeon X1900 XT] + 1002 0412 All-In-Wonder X1900 + 1002 0b12 Radeon X1900 XT/XTX + 1002 0d02 Radeon X1900 CrossFire Edition + 1043 0160 Radeon X1900 XTX 512 MB GDDR3 + 724b R580 [Radeon X1900 GT] 1002 0b12 Radeon X1900 (Primary) 1002 0b13 Radeon X1900 (Secondary) - 724c R580 [Radeon X1900] - 724d R580 [Radeon X1900] - 724e R580 [AMD Stream Processor] + 724e R580 GL [FireGL V7350] 7269 R580 [Radeon X1900 XT] (Secondary) - 726b R580 [Radeon X1900] + 726b R580 [Radeon X1900 GT] (Secondary) 726e R580 [AMD Stream Processor] (Secondary) - 7280 RV570 [Radeon X1950 Pro] - 7288 Radeon X1950 GT - 7291 Radeon X1650 XT (Primary) (PCIE) - 7293 Radeon X1650 Series - 72a0 RV570 [Radeon X1950 Pro] (secondary) - 72a8 Radeon X1950 GT (Secondary) - 72b1 Radeon X1650 XT (Secondary) (PCIE) - 72b3 Radeon X1650 Series (Secondary) - 7833 Radeon 9100 IGP Host Bridge - 7834 Radeon 9100 PRO IGP - 7835 Radeon Mobility 9200 IGP - 7838 Radeon 9100 IGP PCI/AGP Bridge + 7280 RV570 [Radeon X1950 PRO] + 7288 RV570 [Radeon X1950 GT] + 7291 RV560 [Radeon X1650 XT] + 1462 0810 Radeon X1700 SE + 7293 RV560 [Radeon X1650 GT] + 72a0 RV570 [Radeon X1950 PRO] (Secondary) + 72a8 RV570 [Radeon X1950 GT] (Secondary) + 72b1 RV560 [Radeon X1650 XT] (Secondary) + 72b3 RV560 [Radeon X1650 GT] (Secondary) + 7300 Fiji XT [Radeon R9 FURY X] + 7833 RS350 Host Bridge + 7834 RS350 [Radeon 9100 PRO/XT IGP] + 7835 RS350M [Mobility Radeon 9000 IGP] + 7838 RS350 AGP Bridge 7910 RS690 Host Bridge 1179 ff50 Satellite P305D-S8995E 17f2 5000 KI690-AM2 Motherboard @@ -1757,13 +2892,13 @@ 7916 RS690 PCI to PCI Bridge (PCI Express Port 2) 7917 RS690 PCI to PCI Bridge (PCI Express Port 3) 1002 7910 RS690 PCI to PCI Bridge - 7919 Radeon X1200 Series Audio Controller + 7919 RS690 HDMI Audio [Radeon Xpress 1200 Series] 1179 7919 Satellite P305D-S8995E 17f2 5000 KI690-AM2 Motherboard - 791e RS690 [Radeon X1200 Series] + 791e RS690 [Radeon X1200] 1462 7327 K9AG Neo2 17f2 5000 KI690-AM2 Motherboard - 791f RS690M [Radeon X1200 Series] + 791f RS690M [Radeon Xpress 1200/1250/1270] 1179 ff50 Satellite P305D-S8995E 7930 RS600 Host Bridge 7932 RS600 PCI to PCI Bridge (Internal gfx) @@ -1772,161 +2907,297 @@ 7936 RS600 PCI to PCI Bridge (PCI Express Port 2) 7937 RS690 PCI to PCI Bridge (PCI Express Port 3) 793b RS600 HDMI Audio [Radeon Xpress 1250] - 793f RS600 [Radeon Xpress 1250] + 793f RS690M [Radeon Xpress 1200/1250/1270] (Secondary) 7941 RS600 [Radeon Xpress 1250] - 7942 RS600 [Radeon Xpress 1250] - 796e Radeon 2100 - 7c37 RV350 AQ [Radeon 9600 SE] - 9400 R600 [Radeon HD 2900 Series] - 1002 3000 Sapphire Radeon HD 2900 XT + 7942 RS600M [Radeon Xpress 1250] + 796e RS740 [Radeon 2100] + 9400 R600 [Radeon HD 2900 PRO/XT] + 1002 2552 Radeon HD 2900 XT + 1002 3000 Radeon HD 2900 PRO 1002 3142 HIS Radeon HD 2900XT 512MB GDDR3 VIVO PCIe + 9401 R600 [Radeon HD 2900 XT] 9403 R600 [Radeon HD 2900 PRO] - 940a R600GL [Fire GL V8650] - 940b R600GL [Fire GL V8600] - 940f R600 [FireGL V7600] + 9405 R600 [Radeon HD 2900 GT] + 940a R600 GL [FireGL V8650] + 940b R600 GL [FireGL V8600] + 940f R600 GL [FireGL V7600] 9440 RV770 [Radeon HD 4870] 9441 R700 [Radeon HD 4870 X2] 9442 RV770 [Radeon HD 4850] - 1002 0502 MSI R4850-T2D512 - 174b e810 Sapphire HD 4850 512MB GDDR3 PCI-E Dual Slot Fansink - 9443 R700 [Radeon HD 4850] - 944a M98L [Mobility Radeon HD 4850] - 944c RV770 LE [Radeon HD 4800 Series] + 1002 0502 MSI Radeon HD 4850 512MB GDDR3 + 174b e810 Radeon HD 4850 512MB GDDR3 + 9443 R700 [Radeon HD 4850 X2] + 9444 RV770 GL [FirePro V8750] + 9446 RV770 GL [FirePro V7760] + 944a RV770/M98L [Mobility Radeon HD 4850] + 944b RV770/M98 [Mobility Radeon HD 4850 X2] + 944c RV770 LE [Radeon HD 4830] 944e RV770 CE [Radeon HD 4710] - 9450 RV770 [FireStream 9270] - 9452 RV770 [FireStream 9250] - 945a M98 XT [Mobility Radeon HD 4870] + 174b 3261 Radeon HD 4810 + 9450 RV770 GL [FireStream 9270] + 9452 RV770 GL [FireStream 9250] + 9456 RV770 GL [FirePro V8700] + 945a RV770/M98-XT [Mobility Radeon HD 4870] 9460 RV790 [Radeon HD 4890] - 9462 RV790LE [Radeon HD 4800 Series] - 9480 M96 [Mobility Radeon HD 4650] - 103c 3628 ATI Mobility Radeon HD 4650 [dv6-1190en] - 9485 RV740 Pro [Radeon HD 4770] - 9488 RV730 XT [Mobility Radeon HD 4670] - 9489 M96 XT [Mobility FireGL V5725] - 9490 RV730XT [Radeon HD 4670] - 174b e880 Radeon HD 4670 512MB DDR3 - 9491 M96 CSP [ATI RADEON E4690] - 9495 RV730 Pro AGP [Radeon HD 4600 Series] - 1002 9495 RV730 XT [PowerColor Radeon HD4670 AGP 1GB DDR] - 1458 0028 HD4650 + 9462 RV790 [Radeon HD 4860] + 946a RV770 GL [FirePro M7750] + 9480 RV730/M96 [Mobility Radeon HD 4650/5165] + 103c 3628 Mobility Radeon HD 4650 [dv6-1190en] + 9488 RV730/M96-XT [Mobility Radeon HD 4670] + 9489 RV730/M96 GL [Mobility FireGL V5725] + 9490 RV730 XT [Radeon HD 4670] + 174b e880 Radeon HD 4670 512MB GDDR3 Dual DVI-I/TVO + 9491 RV730/M96-CSP [Radeon E4690] + 9495 RV730 [Radeon HD 4600 AGP Series] + 1002 0028 Radeon HD 4650/4670 AGP + 1092 0028 Radeon HD 4670 AGP 512MB DDR2 + 1458 0028 Radeon HD 4650 AGP + 1682 0028 Radeon HD 4650 AGP + 174b 0028 Radeon HD 4650 AGP DDR2 9498 RV730 PRO [Radeon HD 4650] - 949e RV370 [FirePro V5700] - 949f RV730 [FirePro V5700] - 94a0 Mobility Radeon HD 4830 [M97] - 94a1 [M97 XT] Mobility Radeon HD 4860 - 94a3 M97 GL [ATI FirePro M7740] - 94b3 Radeon HD 4770 [RV740] - 94b4 RV740 LE [ATI Radeon HD 4700 Series] - 94c1 RV610 [Radeon HD 2400 XT] + 949c RV730 GL [FirePro V7750] + 949e RV730 GL [FirePro V5700] + 949f RV730 GL [FirePro V3750] + 94a0 RV740/M97 [Mobility Radeon HD 4830] + 94a1 RV740/M97-XT [Mobility Radeon HD 4860] + 94a3 RV740/M97 GL [FirePro M7740] + 94b3 RV740 PRO [Radeon HD 4770] + 94b4 RV740 PRO [Radeon HD 4750] + 94c1 RV610 [Radeon HD 2400 PRO/XT] 1028 0211 Optiplex 755 1028 0d02 Optiplex 755 - 94c3 RV610 video device [Radeon HD 2400 PRO] - 1002 94c3 Radeon HD 2400PRO + 94c3 RV610 [Radeon HD 2400 PRO] 1028 0302 Radeon HD 2400 Pro - 174b e400 Sapphire HD 2400 PRO video device - 18bc 3550 GeCube Radeon HD2400 PRO - 94c4 RV610 LE AGP [Radeon HD 2400 PRO AGP] - 94c8 Radeon HD 2400 XT - 94c9 Mobility Radeon HD 2400 + 174b e400 Radeon HD 2400 PRO + 18bc 3550 Radeon HD 2400 PRO + 94c4 RV610 LE [Radeon HD 2400 PRO AGP] + 94c5 RV610 [Radeon HD 2400 LE] + 94c7 RV610 [Radeon HD 2350] + 94c8 RV610/M74 [Mobility Radeon HD 2400 XT] + 94c9 RV610/M72-S [Mobility Radeon HD 2400] 1002 94c9 Radeon HD2400 - 94cb Radeon E2400 - 94cc RV610 LE [Radeon HD 2400 Pro PCI] + 94cb RV610 [Radeon E2400] + 94cc RV610 LE [Radeon HD 2400 PRO PCI] + 9500 RV670 [Radeon HD 3850 X2] 9501 RV670 [Radeon HD 3870] - 174b e620 Sapphire Radeon HD 3870 PCIe 2.0 - 9504 RV670 [Mobility Radeon HD 3850] - 9505 RV670PRO [Radeon HD 3850] - 9507 RV670 [Radeon HD 3850] - 9508 M88 XT Mobility Radeon HD 3870] - 950f R680 [Radeon HD 3870 x2] - 9511 RV670 [FireGL 7700] - 9515 RV670 AGP [Radeon HD 3850] - 9519 RV670 [FireStream 9170] + 174b e620 Radeon HD 3870 + 9504 RV670/M88 [Mobility Radeon HD 3850] + 9505 RV670 [Radeon HD 3690/3850] + 148c 3000 Radeon HD 3850 + 174b 3000 Radeon HD 3690/3850 + 1787 3000 Radeon HD 3690 + 9506 RV670/M88 [Mobility Radeon HD 3850 X2] + 9507 RV670 [Radeon HD 3830] + 9508 RV670/M88-XT [Mobility Radeon HD 3870] + 9509 RV670/M88 [Mobility Radeon HD 3870 X2] + 950f R680 [Radeon HD 3870 X2] + 9511 RV670 GL [FireGL V7700] + 9513 RV670 [Radeon HD 3850 X2] + 9515 RV670 PRO [Radeon HD 3850 AGP] + 9519 RV670 GL [FireStream 9170] 9540 RV710 [Radeon HD 4550] - 954f RV710 [Radeon HD 4350] + 954f RV710 [Radeon HD 4350/4550] 1462 1618 R4350 MD512H (MS-V161) - 9552 RV710 [Mobility Radeon HD 4300 Series] - 9553 RV710 [Mobility Radeon HD 4500/5100 Series] + 9552 RV710/M92 [Mobility Radeon HD 4330/4350/4550] + 1028 1103 M92 [Mobility Radeon HD 4330] +# GV-R435OC-512I/FF1 + 1458 21ac Radeon HD 4350 +# GV-R455HM-512I/F41 + 1458 21ed Radeon HD 4550 +# 113-100928-J01 + 148c 3000 Radeon HD 4350 Go! Green 512MB GDDR3 +# 113-2E172001-003 + 174b 3000 Radeon HD 4350/4550 HyperMemory DDR2 + 9553 RV710/M92 [Mobility Radeon HD 4530/4570/545v] + 1025 015e Mobility Radeon HD 4570 + 1025 017d Mobility Radeon HD 4570 + 1025 0205 Mobility Radeon HD 4570 + 1025 0206 Mobility Radeon HD 4570 + 1025 0237 Mobility Radeon HD 4570 + 1028 02be Mobility Radeon HD 4570 + 1028 02e8 Mobility Radeon HD 4530 + 103c 3624 Mobility Radeon HD 4530 + 103c 3628 Mobility Radeon HD 4530 + 103c 3636 Mobility Radeon HD 4530 + 1043 1b32 Mobility Radeon HD 4570 + 1043 1b42 Mobility Radeon HD 4570 + 104d 9056 Mobility Radeon HD 4570 1179 ff82 Satellite L505-13T GPU (Mobility Radeon HD 5145) - 9555 RV710 [Mobility Radeon HD 4300/4500 Series] + 9555 RV710/M92 [Mobility Radeon HD 4350/4550] 103c 1411 ProBook 4720s GPU (Mobility Radeon HD 4350) - 9559 RV635 [Mobility Radeon HD 3600 Series] - 955f RV710 [Mobility Radeon HD 4330] - 9581 RV630 [Mobility Radeon HD 2600] - 9583 RV630 [Mobility Radeon HD 2600 XT] - 9586 RV 630 XT AGP [Radeon HD 2600 XT AGP] - 9587 RV630 PRO AGP [Radeon HD 2600 PRO AGP] - 9588 RV630 [Radeon HD 2600XT] + 9557 RV711 GL [FirePro RG220] + 955f RV710/M92 [Mobility Radeon HD 4330] + 9580 RV630 [Radeon HD 2600 PRO] + 9581 RV630/M76 [Mobility Radeon HD 2600] + 9583 RV630/M76 [Mobility Radeon HD 2600 XT/2700] + 106b 0083 iMac 7,1 + 1734 1107 Mobility Radeon HD 2700 + 9586 RV630 XT [Radeon HD 2600 XT AGP] + 9587 RV630 PRO [Radeon HD 2600 PRO AGP] + 9588 RV630 XT [Radeon HD 2600 XT] 1458 216c Radeon HD 2600 XT, 256MB GDDR3, 2x DVI, TV-out, PCIe (GV-RX26T256H) - 9589 RV630 [Radeon HD 2600 Series] - 958c RV630GL [FireGL v5600] - 958d RV630 [FireGL V3600] - 9591 RV635 [Mobility Radeon HD 3650] + 9589 RV630 PRO [Radeon HD 2600 PRO] +# Rebranded HD 2600 PRO + 1787 3000 Radeon HD 3610 + 958a RV630 [Radeon HD 2600 X2] + 958b RV630/M76 [Mobility Radeon HD 2600 XT] + 958c RV630 GL [FireGL V5600] + 958d RV630 GL [FireGL V3600] + 9591 RV635/M86 [Mobility Radeon HD 3650] 1002 9591 Mobility Radeon HD 3650 - 9593 RV635 [Mobility Radeon HD 3670] - 9595 M86GL [Mobility FireGL V5700] - 9596 RV635 PRO AGP [Radeon HD 3650] + 9593 RV635/M86 [Mobility Radeon HD 3670] + 9595 RV635/M86 GL [Mobility FireGL V5700] + 9596 RV635 PRO [Radeon HD 3650 AGP] 1043 0028 EAH3650 SILENT/HTDI/512M/A - 9598 RV630 [Radeon HD 3600 Series] + 9597 RV635 PRO [Radeon HD 3650 AGP] + 9598 RV635 [Radeon HD 3650/3750/4570/4580] 1002 9598 Mobility Radeon HD 3600 1043 01d6 EAH3650 Silent + 1043 3001 Radeon HD 4570 + 174b 3001 Radeon HD 3750 + 174b 4580 RV635 PRO [Radeon HD 4580] + 9599 RV635 PRO [Radeon HD 3650 AGP] 95c0 RV620 PRO [Radeon HD 3470] 1002 95c0 Mobility Radeon HD 3470 - 95c4 RV620 [Mobility Radeon HD 3400 Series] + 95c2 RV620/M82 [Mobility Radeon HD 3410/3430] + 95c4 RV620/M82 [Mobility Radeon HD 3450/3470] 1002 95c4 Mobility Radeon HD 3400 95c5 RV620 LE [Radeon HD 3450] 1028 0342 OptiPlex 980 - 95c6 RV620 LE AGP [Radeon HD 3450] - 95c7 RV620 CE [Radeon HD 3430] - 95c9 RV620 PCI [Radeon HD 3450] - 95cc RV620 [ATI FireGL V3700] - 95cd RV620 [FireMV 2450] - 95ce RV620 [FirePro 2260] - 95cf RV620 [FirePro 2260] - 960f RS780 HDMI Audio [Radeon HD 3000-3300 Series] + 95c6 RV620 LE [Radeon HD 3450 AGP] + 95c9 RV620 LE [Radeon HD 3450 PCI] + 95cc RV620 GL [FirePro V3700] + 95cd RV620 [FirePro 2450] + 95cf RV620 GL [FirePro 2260] + 960f RS780 HDMI Audio [Radeon (HD) 3000 Series] 9610 RS780 [Radeon HD 3200] 1458 d000 GA-MA78GM-S2H Motherboard - 9611 RS780C [Radeon HD 3100] - 9612 RS780M/RS780MN [Mobility Radeon HD 3200 Graphics] - 9613 RS780MC [Mobility Radeon HD 3100 Graphics] + 9611 RS780C [Radeon 3100] + 9612 RS780M [Mobility Radeon HD 3200] + 9613 RS780MC [Mobility Radeon HD 3100] 9614 RS780D [Radeon HD 3300] - 9615 RS780E [Radeon HD 3200] - 9616 RS780L [Radeon HD 3000] + 9616 RS780L [Radeon 3000] 9640 BeaverCreek [Radeon HD 6550D] - 9641 BeaverCreek [Mobility Radeon HD 6620G] + 9641 BeaverCreek [Radeon HD 6620G] + 9642 Sumo [Radeon HD 6370D] + 9643 Sumo [Radeon HD 6380G] + 9644 Sumo [Radeon HD 6410D] + 9645 Sumo [Radeon HD 6410D] 9647 BeaverCreek [Radeon HD 6520G] + 9648 Sumo [Radeon HD 6480G] + 9649 Sumo [Radeon HD 6480G] 964a BeaverCreek [Radeon HD 6530D] + 964b Sumo + 964c Sumo + 964e Sumo + 964f Sumo 970f RS880 HDMI Audio [Radeon HD 4200 Series] + 1019 2120 A785GM-M 1043 83a2 M4A785TD Motherboard 1043 843e M5A88-V EVO 9710 RS880 [Radeon HD 4200] + 1019 2120 A785GM-M 1043 83a2 M4A785TD Motherboard - 9712 RS880M [Mobility Radeon HD 4200 Series] + 9712 RS880M [Mobility Radeon HD 4225/4250] 9713 RS880M [Mobility Radeon HD 4100] 9714 RS880 [Radeon HD 4290] 9715 RS880 [Radeon HD 4250] 1043 843e M5A88-V EVO # Radeon HD 6250 too? 9802 Wrestler [Radeon HD 6310] - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini + 9803 Wrestler [Radeon HD 6310] 9804 Wrestler [Radeon HD 6250] + 9805 Wrestler [Radeon HD 6250] 9806 Wrestler [Radeon HD 6320] 9807 Wrestler [Radeon HD 6290] + 9808 Wrestler [Radeon HD 7340] + 9809 Wrestler [Radeon HD 7310] + 980a Wrestler [Radeon HD 7290] + 9830 Kabini [Radeon HD 8400 / R3 Series] + 9831 Kabini [Radeon HD 8400E] + 9832 Kabini [Radeon HD 8330] + 9833 Kabini [Radeon HD 8330E] + 9834 Kabini [Radeon HD 8210] + 9835 Kabini [Radeon HD 8310E] + 9836 Kabini [Radeon HD 8280 / R3 Series] + 9837 Kabini [Radeon HD 8280E] + 9838 Kabini [Radeon HD 8240 / R3 Series] + 9839 Kabini [Radeon HD 8180] + 983d Temash [Radeon HD 8250/8280G] + 9840 Kabini HDMI/DP Audio + 9850 Mullins [Radeon R3 Graphics] + 9851 Mullins [Radeon R4/R5 Graphics] + 9852 Mullins [Radeon R2 Graphics] + 9853 Mullins [Radeon R2 Graphics] + 9854 Mullins [Radeon R3E Graphics] + 9855 Mullins [Radeon R6 Graphics] + 9856 Mullins [Radeon R1E/R2E Graphics] + 9857 Mullins [Radeon APU XX-2200M with R2 Graphics] + 9858 Mullins + 9859 Mullins + 985a Mullins + 985b Mullins + 985c Mullins + 985d Mullins + 985e Mullins + 985f Mullins + 9874 Carrizo + 9900 Trinity [Radeon HD 7660G] # AMD A10-5800K CPU 9901 Trinity [Radeon HD 7660D] + 9902 Trinity HDMI Audio Controller + 103c 194e ProBook 455 G1 Notebook + 9903 Trinity [Radeon HD 7640G] + 103c 194e ProBook 455 G1 Notebook + 103c 1952 ProBook 455 G1 Notebook + 9904 Trinity [Radeon HD 7560D] + 9905 Trinity [FirePro A300 Series Graphics] + 9906 Trinity [FirePro A300 Series Graphics] + 9907 Trinity [Radeon HD 7620G] + 9908 Trinity [Radeon HD 7600G] + 9909 Trinity [Radeon HD 7500G] + 990a Trinity [Radeon HD 7500G] + 990b Richland [Radeon HD 8650G] + 990c Richland [Radeon HD 8670D] + 990d Richland [Radeon HD 8550G] + 990e Richland [Radeon HD 8570D] + 990f Richland [Radeon HD 8610G] + 9910 Trinity [Radeon HD 7660G] + 9913 Trinity [Radeon HD 7640G] + 9917 Trinity [Radeon HD 7620G] + 9918 Trinity [Radeon HD 7600G] + 9919 Trinity [Radeon HD 7500G] 9990 Trinity [Radeon HD 7520G] - aa00 R600 Audio Device [Radeon HD 2900 Series] - aa08 RV630 audio device [Radeon HD 2600 Series] + 9991 Trinity [Radeon HD 7540D] + 9992 Trinity [Radeon HD 7420G] + 9993 Trinity [Radeon HD 7480D] + 9994 Trinity [Radeon HD 7400G] + 9995 Richland [Radeon HD 8450G] + 9996 Richland [Radeon HD 8470D] + 9997 Richland [Radeon HD 8350G] + 9998 Richland [Radeon HD 8370D] + 9999 Richland [Radeon HD 8510G] + 999a Richland [Radeon HD 8410G] + 999b Richland [Radeon HD 8310G] + 999c Richland +# AMD Quad-Core A8-Series APU A8-6500T with Radeon HD 8550D + 999d Richland [Radeon HD 8550D] + 99a0 Trinity [Radeon HD 7520G] + 99a2 Trinity [Radeon HD 7420G] + 99a4 Trinity [Radeon HD 7400G] + aa00 R600 HDMI Audio [Radeon HD 2900 Series] + aa08 RV630 HDMI Audio [Radeon HD 2600 Series] aa10 RV610 HDMI Audio [Radeon HD 2350/2400 Series] - 174b aa10 Sapphire HD 2400 PRO audio device - 18bc aa10 GeCube Radeon HD 2400 PRO HDCP-capable digital-only audio device + 174b aa10 Radeon HD 2400 PRO + 18bc aa10 Radeon HD 2400 PRO aa18 RV670/680 HDMI Audio [Radeon HD 3690/3800 Series] aa20 RV635 HDMI Audio [Radeon HD 3600 Series] aa28 RV620 HDMI Audio [Radeon HD 3400 Series] aa30 RV770 HDMI Audio [Radeon HD 4850/4870] - 174b aa30 Sapphire HD 4850 512MB GDDR3 PCI-E Dual Slot Fansink + 174b aa30 Radeon HD 4850 512MB GDDR3 PCI-E Dual Slot Fansink aa38 RV710/730 HDMI Audio [Radeon HD 4000 series] - 103c 3628 ATI RV710/730 [dv6-1190en] - 174b aa38 R700 Audio Device [Radeon HD 4000 Series] + 103c 3628 dv6-1190en aa50 Cypress HDMI Audio [Radeon HD 5800 Series] aa58 Juniper HDMI Audio [Radeon HD 5700 Series] # 5500, 5600 and mobile 5700 series @@ -1938,16 +3209,18 @@ aa80 Cayman/Antilles HDMI Audio [Radeon HD 6900 Series] aa88 Barts HDMI Audio [Radeon HD 6800 Series] aa90 Turks/Whistler HDMI Audio [Radeon HD 6000 Series] + 1028 04a3 Precision M4600 aa98 Caicos HDMI Audio [Radeon HD 6400 Series] - 174b aa98 Sapphire HD 6450 1GB DDR3 + 174b aa98 Radeon HD 6450 1GB DDR3 aaa0 Tahiti XT HDMI Audio [Radeon HD 7970 Series] + aab0 Cape Verde/Pitcairn HDMI Audio [Radeon HD 7700/7800 Series] ac00 Theater 600 Pro ac02 TV Wonder HD 600 PCIe ac12 Theater HD T507 (DVB-T) TV tuner/capture device - cab0 RS100 AGP Bridge [IGP 320M] - cab2 RS200/RS200M AGP Bridge [IGP 340M] - cab3 R200 AGP Bridge [Mobility Radeon 7000 IGP] - cbb2 RS200/RS200M AGP Bridge [IGP 340M] + cab0 RS100 Host Bridge + cab2 RS200 Host Bridge + cab3 RS250 Host Bridge + cbb2 RS200 Host Bridge 1003 ULSI Systems 0201 US201 1004 VLSI Technology Inc @@ -2007,6 +3280,7 @@ 103c 0024 Pavilion ze4400 builtin Network 12d9 000c Aculab E1/T1 PMXc cPCI carrier card 1385 f311 FA311 / FA312 (FA311 with WoL HW) + 1385 f312 FA312 (rev. A1) Fast Ethernet PCI Adapter 0021 PC87200 PCI to ISA Bridge 0022 DP83820 10/100/1000 Ethernet Controller 1186 4900 DGE-500T @@ -2075,7 +3349,7 @@ 2646 0001 KNE100TX Fast Ethernet 000a 21230 Video Codec 000d PBXGB [TGA2] - 000f PCI-to-PDQ Interface Chip [PFI] + 000f DEFPA FDDI PCI-to-PDQ Interface Chip [PFI] 1011 def1 FDDI controller (DEFPA) 103c def1 FDDI controller (3X-DEFPA) 0014 DECchip 21041 [Tulip Pass 3] @@ -2108,6 +3382,7 @@ 1186 1101 DFE-500TX Fast Ethernet 1186 1102 DFE-500TX Fast Ethernet 1186 1112 DFE-570TX Quad Fast Ethernet + 11f0 4235 21143 [FASTLine-II UTP 10/100] 1259 2800 AT-2800Tx Fast Ethernet 1266 0004 Eagle Fast EtherMAX 12af 0019 NetFlyer Cardbus Fast Ethernet @@ -2163,6 +3438,7 @@ 00ac GD 5436 [Alpine] 00b0 GD 5440 00b8 GD 5446 + 1af4 1100 QEMU Virtual Machine 00bc GD 5480 1013 00bc CL-GD5480 00d0 GD 5462 @@ -2248,7 +3524,6 @@ 0054 GXT500P/GXT550P Graphics Adapter 0057 MPEG PCI Bridge 0058 SSA Adapter [Advanced SerialRAID/X] - 005c i82557B 10/100 005e GXT800P Graphics Adapter 007c ATM Controller (14107c00) 007d 3780IDSP [MWave] @@ -2265,13 +3540,12 @@ 009f PCI 4758 Cryptographic Accelerator 00a5 ATM Controller (1410a500) 00a6 ATM 155MBPS MM Controller (1410a600) - 00b7 256-bit Graphics Rasterizer [FireGL1] + 00b7 GXT2000P Graphics Adapter 1092 00b8 FireGL1 AGP 32Mb 00b8 GXT2000P Graphics Adapter 00be ATM 622MBPS Controller (1410be00) 00dc Advanced Systems Management Adapter (ASMA) 00fc CPC710 Dual Bridge and Memory Controller (PCI-64) - 0104 Gigabit Ethernet-SX Adapter 0105 CPC710 Dual Bridge and Memory Controller (PCI-32) 010f Remote Supervisor Adapter (RSA) 0142 Yotta Video Compositor Input @@ -2283,6 +3557,10 @@ 0160 64bit/66MHz PCI ATM 155 MMF 016e GXT4000P Graphics Adapter 0170 GXT6000P Graphics Adapter + 1092 0172 Fire GL2 + 1092 0173 Fire GL3 + 1092 0174 Fire GL4 + 1092 0184 Fire GL4s 017d GXT300P Graphics Adapter 0180 Snipe chipset SCSI controller 1014 0241 iSeries 2757 DASD IOA @@ -2311,9 +3589,6 @@ 021b GXT6500P Graphics Adapter 021c GXT4500P Graphics Adapter 0233 GXT135P Graphics Adapter - 0266 PCI-X Dual Channel SCSI - 0268 Gigabit Ethernet-SX Adapter (PCI-X) - 0269 10/100/1000 Base-TX Ethernet Adapter (PCI-X) 028c Citrine chipset SCSI controller 1014 028d Dual Channel PCI-X DDR SAS RAID Adapter (572E) 1014 02be Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B) @@ -2332,6 +3607,7 @@ 0339 Obsidian-E PCI-E SCSI controller 1014 030a PCIe 3Gb SAS RAID Adapter (574E) 1014 033a PCIe 3Gb SAS Adapter (57B3) + 1014 035c PCIe x8 Internal 3Gb SAS adapter (57CC) 1014 0360 PCI-E Auxiliary Cache Adapter (57B7) 033d PCI-E IPR SAS Adapter (FPGA) 1014 033c PCIe2 1.8GB Cache 6Gb SAS RAID Adapter Tri-port (57B5) @@ -2345,6 +3621,18 @@ 1014 0357 PCIe2 6Gb SAS Adapter Quad-port (57C6) 1014 035d PCIe3 1.8GB Cache RAID SAS Adapter Quad-port 6GB (57C8) 1014 035e PCIe2 3.6GB Cache 6Gb SAS RAID Adapter Quad-port (57CE) + 1014 03fb PCIe3 28GB Cache RAID SAS Enclosure 6Gb x 16 (57D5) + 1014 03fe PCIe3 x8 Cache SAS RAID Internal Adapter 6Gb (57D8) + 1014 03ff PCIe3 x8 SAS RAID Internal Adapter 6Gb (57D7) + 1014 0474 PCIe3 x16 Cache SAS RAID Internal Adapter 6Gb (57EB) + 1014 0475 PCIe3 x16 SAS RAID Internal Adapter 6Gb (57EC) + 1014 0499 PCIe3 x16 Cache SAS RAID Internal Adapter 6Gb (57ED) + 1014 049a PCIe3 x16 SAS RAID Internal Adapter 6Gb (57EE) + 1014 04c7 PCIe3 x 8 Cache SAS RAID Internal Adapter 6GB(2CCA) + 1014 04c8 PCIe3 x 8 Cache SAS RAID Internal Adapter 6GB(2CD2) + 1014 0c49 PCIe3 x 8 Cache SAS RAID Internal Adapter 6GB(2CCD) + 044b GenWQE Accelerator Adapter + 04aa Flash Adapter 90 (PCIe2 0.9TB) 3022 QLA3022 Network Adapter 4022 QLA3022 Network Adapter ffff MPIC-2 interrupt controller @@ -2404,6 +3692,7 @@ 1028 0493 PowerEdge RAID Controller 3/DC 1028 0511 PowerEdge Cost Effective RAID Controller ATA100/4Ch 103c 60e7 NetRAID-1M + 103c 60e8 NetRaid 2M [AMI MegaRaid 493] 9010 MegaRAID 428 Ultra RAID Controller 9030 EIDE Controller 9031 EIDE Controller @@ -2416,7 +3705,7 @@ 101f PictureTel 1020 Hitachi Computer Products 1021 OKI Electric Industry Co. Ltd. -1022 Advanced Micro Devices [AMD] +1022 Advanced Micro Devices, Inc. [AMD] 1100 K8 [Athlon64/Opteron] HyperTransport Technology Configuration 1101 K8 [Athlon64/Opteron] Address Map 1102 K8 [Athlon64/Opteron] DRAM Controller @@ -2446,14 +3735,31 @@ 1417 Family 15h (Models 10h-1fh) Processor Root Port 1418 Family 15h (Models 10h-1fh) Processor Root Port 1419 Family 15h (Models 10h-1fh) I/O Memory Management Unit + 141a Family 15h (Models 30h-3fh) Processor Function 0 + 141b Family 15h (Models 30h-3fh) Processor Function 1 + 141c Family 15h (Models 30h-3fh) Processor Function 2 + 141d Family 15h (Models 30h-3fh) Processor Function 3 + 141e Family 15h (Models 30h-3fh) Processor Function 4 + 141f Family 15h (Models 30h-3fh) Processor Function 5 + 1422 Family 15h (Models 30h-3fh) Processor Root Complex + 1423 Family 15h (Models 30h-3fh) I/O Memory Management Unit + 1426 Family 15h (Models 30h-3fh) Processor Root Port + 1439 Family 16h Processor Functions 5:1 1510 Family 14h Processor Root Complex - 174b 1001 Sapphire PURE Fusion Mini + 174b 1001 PURE Fusion Mini 1512 Family 14h Processor Root Port - 174b 1001 Sapphire PURE Fusion Mini 1513 Family 14h Processor Root Port 1514 Family 14h Processor Root Port 1515 Family 14h Processor Root Port 1516 Family 14h Processor Root Port + 1530 Family 16h Processor Function 0 + 1531 Family 16h Processor Function 1 + 1532 Family 16h Processor Function 2 + 1533 Family 16h Processor Function 3 + 1534 Family 16h Processor Function 4 + 1535 Family 16h Processor Function 5 + 1536 Family 16h Processor Root Complex + 1538 Family 16h Processor Function 0 1600 Family 15h Processor Function 0 1601 Family 15h Processor Function 1 1602 Family 15h Processor Function 2 @@ -2504,6 +3810,7 @@ 1668 0299 ActionLink Home Network Adapter 2003 Am 1771 MBW [Alchemy] 2020 53c974 [PCscsi] + 1af4 1100 QEMU Virtual Machine 2040 79c974 2080 CS5536 [Geode companion] Host Bridge 2081 Geode LX Video @@ -2576,32 +3883,56 @@ 161f 3017 HDAMB 746e AMD-8111 MC97 Modem 756b AMD-8111 ACPI - 7800 Hudson SATA Controller [IDE mode] - 7801 Hudson SATA Controller [AHCI mode] - 7802 Hudson SATA Controller [RAID mode] - 7803 Hudson SATA Controller [RAID mode] - 7804 Hudson SATA Controller [AHCI mode] - 7805 Hudson SATA Controller [RAID mode] - 7806 Hudson SD Flash Controller - 7807 Hudson USB OHCI Controller - 7808 Hudson USB EHCI Controller - 7809 Hudson USB OHCI Controller - 780b Hudson SMBus Controller - 780c Hudson IDE Controller - 780d Hudson Azalia Controller - 780e Hudson LPC Bridge - 780f Hudson PCI Bridge - 7812 Hudson USB XHCI Controller + 7800 FCH SATA Controller [IDE mode] + 7801 FCH SATA Controller [AHCI mode] + 103c 168b ProBook 4535s Notebook + 103c 194e ProBook 455 G1 Notebook + 7802 FCH SATA Controller [RAID mode] + 7803 FCH SATA Controller [RAID mode] + 7804 FCH SATA Controller [AHCI mode] + 7805 FCH SATA Controller [RAID mode] + 7806 FCH SD Flash Controller + 7807 FCH USB OHCI Controller + 103c 194e ProBook 455 G1 Notebook + 7808 FCH USB EHCI Controller + 103c 194e ProBook 455 G1 Notebook + 7809 FCH USB OHCI Controller + 103c 194e ProBook 455 G1 Notebook + 780b FCH SMBus Controller + 103c 194e ProBook 455 G1 Notebook + 780c FCH IDE Controller + 780d FCH Azalia Controller + 103c 194e ProBook 455 G1 Notebook + 1043 8444 F2A85-M Series + 780e FCH LPC Bridge + 103c 194e ProBook 455 G1 Notebook + 780f FCH PCI Bridge + 7812 FCH USB XHCI Controller + 7813 FCH SD Flash Controller + 7814 FCH USB XHCI Controller + 103c 194e ProBook 455 G1 Notebook + 7900 FCH SATA Controller [IDE mode] + 7901 FCH SATA Controller [AHCI mode] + 7902 FCH SATA Controller [RAID mode] + 7903 FCH SATA Controller [RAID mode] + 7904 FCH SATA Controller [AHCI mode] + 7906 FCH SD Flash Controller + 7908 FCH USB EHCI Controller + 790b FCH SMBus Controller + 790e FCH LPC Bridge + 790f FCH PCI Bridge + 7914 FCH USB XHCI Controller 9600 RS780 Host Bridge 1043 82f1 M3A78-EH Motherboard 9601 RS880 Host Bridge + 1019 2120 A785GM-M 1043 843e M5A88-V EVO 9602 RS780/RS880 PCI to PCI bridge (int gfx) 9603 RS780 PCI to PCI bridge (ext gfx port 0) 9604 RS780/RS880 PCI to PCI bridge (PCIE port 0) 9605 RS780/RS880 PCI to PCI bridge (PCIE port 1) 9606 RS780 PCI to PCI bridge (PCIE port 2) - 9607 RS780 PCI to PCI bridge (PCIE port 3) + 9607 RS780/RS880 PCI to PCI bridge (PCIE port 3) 9608 RS780/RS880 PCI to PCI bridge (PCIE port 4) 9609 RS780/RS880 PCI to PCI bridge (PCIE port 5) 960a RS780 PCI to PCI bridge (NB-SB link) @@ -2764,6 +4095,8 @@ 1028 1f03 PERC 5/i Integrated RAID Controller 0016 PowerEdge Expandable RAID controller S300 1028 1f24 PERC S300 Controller +# NV-RAM Adapter used in Dell DR appliances + 0073 NV-RAM Adapter 1029 Siemens Nixdorf IS 102a LSI Logic 0000 HYDRA @@ -2796,6 +4129,7 @@ 102b 2100 MGA-2164W Millennium II 051e MGA 1064SG [Mystique] AGP 051f MGA 2164W [Millennium II] AGP + 102b 2100 MGA-2164WA [Millennium II A] 0520 MGA G200 102b dbc2 G200 Multi-Monitor 102b dbc8 G200 Multi-Monitor @@ -2836,10 +4170,11 @@ 102b f806 Mystique G200 Video AGP 102b ff00 MGA-G200 AGP 102b ff02 Mystique G200 AGP - 102b ff03 Millennium G200 AGP + 102b ff03 Millennium G200A AGP 102b ff04 Marvel G200 AGP 110a 0032 MGA-G200 AGP 0522 MGA G200e [Pilot] ServerEngines (SEP1) + 103c 31fa ProLiant DL140 G3 0525 MGA G400/G450 0e11 b16f MGA-G400 AGP 102b 0328 Millennium G400 16Mb SDRAM @@ -2935,6 +4270,7 @@ 1028 028d PowerEdge T410 MGA G200eW WPCM450 1028 029c PowerEdge M710 MGA G200eW WPCM450 1028 02a4 PowerEdge T310 MGA G200eW WPCM450 + 15d9 0624 X9SCM-F Motherboard 15d9 a811 H8DGU 0533 MGA G200EH 103c 3381 iLO4 @@ -2966,6 +4302,8 @@ 110a 001e MGA-G100 AGP 2007 MGA Mistral 2527 Millennium G550 +# PCI\VEN_102B&DEV_2527&SUBSYS_0F42102B&REV_01 + 102b 0f42 Matrox G550 Low Profile PCI 102b 0f83 Millennium G550 102b 0f84 Millennium G550 Dual Head DDR 32Mb 102b 1e41 Millennium G550 @@ -3050,10 +4388,15 @@ 47c2 Solios COM port 4949 Radient frame grabber family 102b 0010 Radient eCL (Single-full) frame grabber + 102b 0011 Radient eCLV (Single-full) frame grabber 102b 0020 Radient eCL (Dual-base) frame grabber 102b 0030 Radient eCL (Dual-full) frame grabber 102b 0040 Radient eCL (Quad-base) frame grabber 102b 0050 Radient eCL (Golden) frame grabber + 102b 1010 Radient eV-CXP (quad CXP-6) frame grabber + 102b 1015 Radient eV-CXP (dual CXP-6) frame grabber + 102b 1020 Radient eV-CXP (quad CXP-3) frame grabber + 102b 1050 Radient eV-CXP (Golden) frame grabber 4cdc Morphis JPEG2000 accelerator 4f54 Morphis (e)Quad frame grabber 4fc5 Morphis (e)Dual frame grabber @@ -3131,8 +4474,8 @@ 002a PowerVR 3D 002c Star Alpha 2 002d PCI to C-bus Bridge - 0035 USB - 1033 0035 Hama USB 2.0 CardBus + 0035 OHCI USB Controller + 1033 0035 USB Controller 103c 1293 USB add-in card 103c 1294 USB 2.0 add-in card 1179 0001 USB @@ -3166,7 +4509,7 @@ 12ee 8011 Root hub 00ce uPD72871 [Firewarden] IEEE1394a OHCI 1.0 Link/1-port PHY Controller 00df Vr4131 - 00e0 USB 2.0 + 00e0 uPD72010x USB 2.0 Controller 12ee 7001 Root hub 14c2 0205 PTI-205N USB 2.0 Host Controller 1799 0002 Root Hub @@ -3178,9 +4521,12 @@ 0125 uPD720400 PCI Express - PCI/PCI-X Bridge 013a Dual Tuner/MPEG Encoder 0194 uPD720200 USB 3.0 Host Controller + 1028 04a3 Precision M4600 1028 04b2 Vostro 3350 1028 04da Vostro 3750 1043 8413 P8P67 Deluxe Motherboard + 104d 907a Vaio VPCF1 + 1af4 1100 QEMU Virtual Machine 1b96 0001 USB 3.0 PCIe Card 01e7 uPD72873 [Firewarden] IEEE1394a OHCI 1.1 Link/2-port PHY Controller 01f2 uPD72874 [Firewarden] IEEE1394a OHCI 1.1 Link/3-port PHY Controller @@ -3195,12 +4541,15 @@ 0002 AGP Port (virtual PCI-to-PCI bridge) 0003 AGP Port (virtual PCI-to-PCI bridge) 0004 PCI-to-PCI bridge + 1039 0000 PCIe x16 port 0006 85C501/2/3 0008 SiS85C503/5513 (LPC Bridge) 0009 5595 Power Management Controller 000a PCI-to-PCI bridge + 1039 0000 PCIe x1 port 0016 SiS961/2/3 SMBus controller 0018 SiS85C503/5513 (LPC Bridge) + 0163 163 802.11b/g Wireless LAN Adapter 0180 RAID bus controller 180 SATA/PATA [SiS] 0181 SATA 0182 182 SATA/RAID Controller @@ -3208,6 +4557,7 @@ 0186 AHCI Controller (0106) 0190 190 Ethernet Adapter 0191 191 Gigabit Ethernet Adapter + 1043 8139 P5SD2-FM/S mainboard 0200 5597/5598/6326 VGA 1039 0000 SiS5597 SVGA (Shared RAM) 0204 82C204 @@ -3254,7 +4604,7 @@ 1734 1099 D2030-A1 Motherboard 0900 SiS900 PCI Fast Ethernet 1019 0a14 K7S5A motherboard - 1039 0900 SiS900 10/100 Ethernet Adapter onboard [Asus P4SC-EA] + 1039 0900 SiS900 10/100 Ethernet Adapter onboard 1043 8035 CUSI-FX motherboard 1043 80a7 Motherboard P4S800D-X 1462 0900 MS-6701 motherboard @@ -3267,7 +4617,9 @@ 0968 SiS968 [MuTIOL Media IO] 1180 SATA Controller / IDE mode 1182 SATA Controller / RAID mode + 1039 0180 SiS 966 4-port SATA controller 1183 SATA Controller / IDE mode + 1039 0180 SiS 966 4-port SATA controller 1184 AHCI Controller / RAID mode 1185 AHCI IDE Controller (0106) 3602 83C602 @@ -3331,9 +4683,10 @@ 7007 FireWire Controller 1462 701d MS-6701 7012 SiS7012 AC'97 Sound Controller + 1019 0f05 A928 (i-Buddie) 1039 7012 SiS 7012 onboard [Asus P4SC-EA] AC'97 Sound Controller 1043 818f A8S-X Motherboard - 13f6 0300 CMI9739(A) on ECS K7SOM+ motherboard + 13f6 0300 CMI9739(A) on ECS K7S series motherboard 1462 5850 MSI 648 Max (MS-6585) 1462 7010 MS-6701 motherboard 15bd 1001 DFI 661FX motherboard @@ -3370,12 +4723,10 @@ a0a0 0022 SiS PCI Audio Accelerator 7019 SiS7019 Audio Accelerator 7502 Azalia Audio Controller + 1043 81a1 P5SD2-FM/S mainboard 103a Seiko Epson Corporation 103b Tatung Corp. Of America 103c Hewlett-Packard Company - 0025 XE4500 Notebook - 002a NX9000 Notebook - 08bc NX5000 Notebook 1005 A4977A Visualize EG 1008 Visualize FX 1028 Tach TL Fibre Channel Host Adapter @@ -3411,7 +4762,6 @@ 10ed TopTools Remote Control 10f0 rio System Bus Adapter 10f1 rio I/O Controller - 1200 82557B 10/100 NIC 1219 NetServer PCI Hot-Plug Controller 121a NetServer SMIC Controller 121b NetServer Legacy COM Port Decoder @@ -3428,22 +4778,10 @@ 12eb sx2000 System Bus Adapter 12ec sx2000 I/O Controller 12ee PCI-X 2.0 Local Bus Adapter - 12f8 Broadcom BCM4306 802.11b/g Wireless LAN - 12fa BCM4306 802.11b/g Wireless LAN Controller 1302 RMP-3 Shared Memory Driver 1303 RMP-3 (Remote Management Processor) - 1361 BCM4312 802.11a/b/g WLAN Controller - 1371 Broadcom Corporation BCM4312 802.11a/b/g (rev 02) - 1717 Intel 82571EB dual 1 Gb Ethernet controller - 179b EliteBook 8470p Notebook - 179d EliteBook 8470p Notebook 2910 E2910A PCIBus Exerciser 2925 E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer - 3080 Pavilion ze2028ea - 3085 Realtek RTL8139/8139C/8139C+ - 30a3 Compaq NW8440 Notebook - 30b5 Compaq Presario V3000Z - 31fb DL365 ATI ES1000 VGA controller 3206 Adaptec Embedded Serial ATA HostRAID 3220 Smart Array P600 103c 3225 3 Gb/s SAS RAID @@ -3456,6 +4794,25 @@ 3238 Smart Array E200i (SAS Controller) 103c 3211 Smart Array E200i 103c 3212 Smart Array E200 + 3239 Smart Array Gen9 Controllers + 103c 21bd P244br + 103c 21be Smart Array + 103c 21bf H240ar + 103c 21c0 P440ar + 103c 21c1 Smart Array + 103c 21c2 P440 + 103c 21c3 P441 + 103c 21c4 Smart Array + 103c 21c5 Smart Array + 103c 21c6 H244br + 103c 21c7 H240 + 103c 21c8 H241 + 103c 21c9 Smart Array + 103c 21ca Smart Array + 103c 21cb P840 + 103c 21cc Smart Array + 103c 21cd Smart Array + 103c 21ce Smart Array 323a Smart Array G6 controllers 103c 3241 Smart Array P212 103c 3243 Smart Array P410 @@ -3470,6 +4827,15 @@ 103c 3352 P421 103c 3354 P420i 103c 3355 P220i + 323c Smart Array Gen8+ Controllers + 103c 1920 P430i + 103c 1921 P830i + 103c 1922 P430 + 103c 1923 P431 + 103c 1924 P830 + 103c 1925 Smart Array + 103c 1926 P731m + 103c 1928 P230i 3300 Integrated Lights-Out Standard Virtual USB Controller 103c 3304 iLO2 103c 3305 iLO2 @@ -3492,6 +4858,8 @@ 103c 330e iLO3 103c 3381 iLO4 3307 Integrated Lights-Out Standard Management Processor Support and Messaging +# HP DL380 G6 + 103c 3309 iLO 2 103c 330e iLO3 103c 3381 iLO4 3308 Integrated Lights-Out Standard MS Watchdog Timer @@ -3502,8 +4870,6 @@ 4031 zx2 I/O Controller 4037 PCIe Local Bus Adapter 403b PCIe Root Port - 60e8 NetRAID-2M : ZX1/M (OEM AMI MegaRAID 493) - 780d Hudson Azalia Controller (rev 01) - Soundcard 103e Solliday Engineering 103f Synopsys/Logic Modeling Group 1040 Accelgraphics Inc. @@ -3515,39 +4881,13 @@ 3010 Samurai_1 3020 Samurai_IDE 1043 ASUSTeK Computer Inc. + 0464 Radeon R9 270x GPU 0675 ISDNLink P-IN100-ST-D 0675 1704 ISDN Adapter (PCI Bus, D, C) 0675 1707 ISDN Adapter (PCI Bus, DV, W) 10cf 105e ISDN Adapter (PCI Bus, DV, W) - 0c11 A7N8X Motherboard nForce2 IDE/USB/SMBus - 4015 v7100 SDRAM [GeForce2 MX] - 4021 v7100 Combo Deluxe [GeForce2 MX + TV tuner] - 4057 v8200 GeForce 3 - 8043 v8240 PAL 128M [P4T] Motherboard - 8047 v8420 Deluxe [GeForce4 Ti4200] - 807b v9280/TD [GeForce4 TI4200 8X With TV-Out and DVI] - 8095 A7N8X Motherboard nForce2 AC97 Audio - 80ac A7N8X Motherboard nForce2 AGP/Memory - 80bb v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out] - 80c5 nForce3 chipset motherboard [SK8N] - 80df v9520 Magic/T - 815a A8N-SLI Motherboard nForce4 SATA - 8168 Realtek PCI-E Gigabit Ethernet Controller (RTL8111B) - 8187 802.11a/b/g Wireless LAN Card - 8188 Tiger Hybrid TV Capture Device -# Found on ASUS M2V motherboard - 81e7 Realtek ALC-660 6-channel CODEC - 81f4 EN7300TC512/TD/128M/A(C262G) [Graphics Card EN7300TC512] - 8233 EEE-PC 701 Netbook - 82ca G96 GeForce 9500 GT - 82e8 M3N72-D - 8383 P7P55D Series Motherboard - 83a4 Motherboard M2N68-AM SE2 -# Onboard audio for M4A89 series motherboards. - 8410 SBx00 [Azalia] - 843e M5A88-V EVO -# wrong vendor ID (should have been AMD) - 9602 RS880 PCI to PCI bridge (int gfx) +# Should be 1022:9602 + 9602 AMD RS780/RS880 PCI to PCI bridge (int gfx) 1043 83a2 M4A785TD Motherboard 1044 Adaptec (formerly DPT) 1012 Domino RAID Engine @@ -3633,6 +4973,11 @@ 0008 STG 2000X 0009 STG 1764X 0010 STG4000 [3D Prophet Kyro Series] + 104a 4018 ST PowerVR Kyro (64MB AGP TVO) +# 64MB AGP + 1681 0010 PowerVR Kyro II [3D Prophet 4500] + 1681 0028 3D Prophet 4000XT + 1681 c010 3D Prophet 4500 TV-Out 1681 c069 3D Prophet 4000XT 0201 STPC Vega Northbridge 0209 STPC Consumer/Industrial North- and Southbridge @@ -3720,15 +5065,16 @@ 8022 TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link) [iOHCI-Lynx] 104c 8023 TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) 8023 TSB43AB22A IEEE-1394a-2000 Controller (PHY/Link) [iOHCI-Lynx] + 1028 0168 Precision Workstation 670 Mainboard 103c 088c NC8000 laptop - 1043 808b K8N4-E Mainboard + 1043 808b K8N4/A8N Series Mainboard 1043 815b P5W DH Deluxe Motherboard 1443 8023 FireCard400 8086 5044 Desktop Board DP35DP 8024 TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) 107d 6620 Winfast DV2000 FireWire Controller 1443 8024 FireBoard Blue - 1458 1000 GA-EP45-DS5/GA-EG45M-DS2H Motherboard + 1458 1000 Motherboard 8025 TSB82AA2 IEEE-1394b Link Layer Controller 1043 813c P5P series mainboard 1443 8025 FireBoard800 @@ -3742,6 +5088,7 @@ 103c 006a NX9500 1043 808d A7V333 mainboard. 8027 PCI4451 IEEE-1394 Controller + 1028 00e5 Latitude C810 1028 00e6 PCI4451 IEEE-1394 Controller (Dell Inspiron 8100) 8029 PCI4510 IEEE-1394 Controller 1028 0163 Latitude D505 @@ -3753,16 +5100,19 @@ 802e PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller 1028 018d Inspiron 700m/710m 8031 PCIxx21/x515 Cardbus Controller + 1025 0064 Extensa 3000 series laptop 1025 0080 Aspire 5024WLMi 103c 0934 Compaq nw8240/nx8220 103c 099c NX6110/NC6120 103c 308b MX6125 8032 OHCI Compliant IEEE 1394 Host Controller + 1025 0064 Extensa 3000 series laptop 1025 0080 Aspire 5024WLMi 103c 0934 Compaq nw8240/nx8220 103c 099c NX6110/NC6120 103c 308b MX6125 8033 PCIxx21 Integrated FlashMedia Controller + 1025 0064 Extensa 3000 series laptop 1025 0080 Aspire 5024WLMi 103c 0934 Compaq nw8240/nx8220 103c 099c NX6110/NC6120 @@ -3801,7 +5151,7 @@ 103c 30aa nc6310 8101 TSB43DB42 IEEE-1394a-2000 Controller (PHY/Link) 8201 PCI1620 Firmware Loading Function - 8204 PCI7410,7510,7610 PCI Firmware Loading Function + 8204 PCI7410/7510/7610 PCI Firmware Loading Function 1028 0139 Latitude D400 1028 014e Latitude D800 8231 XIO2000(A)/XIO2200A PCI Express-to-PCI Bridge @@ -3827,6 +5177,8 @@ 0308 3404 G-102 v1 802.11g Wireless Cardbus Adapter 0308 3406 G-162 v2 802.11g Wireless Cardbus Adapter 104c 9066 WL212 Sitecom Wireless Network PCI-Card 100M (Version 1) +# Found in Philips ADSL ANNEX A WLAN Router SNA6500/18 sold by Belgacom + 104c 9067 TNETW1130GVF 104c 9096 Trendnet TEW-412PC Wireless PCI Adapter (Version A) 1186 3b04 DWL-G520+ Wireless PCI Adapter 1186 3b05 DWL-G650+ AirPlusG+ CardBus Wireless LAN @@ -3892,7 +5244,7 @@ 1028 014e Latitude D800 ac48 PCI7610 PC Card Cardbus Controller ac49 PCI7410 PC Card Cardbus Controller - ac4a PCI7510,7610 PC card Cardbus Controller + ac4a PCI7510/7610 CardBus Bridge 1028 0139 Latitude D400 1028 014e Latitude D800 ac4b PCI7610 SD/MMC controller @@ -3930,7 +5282,7 @@ ac8d PCI 7620 ac8e PCI7420 CardBus Controller 1028 018d Inspiron 700m/710m - ac8f PCI7420/7620 Combo CardBus, 1394a-2000 OHCI and SD/MS-Pro Controller + ac8f PCI7420/7620 SD/MS-Pro Controller 1028 018d Inspiron 700m/710m b001 TMS320C6424 fe00 FireWire Host Controller @@ -3942,7 +5294,6 @@ 8056 Rockwell HCF 56K modem 808a Memory Stick Controller 81ce SxS Pro memory card - 902d VAIO VGN-NR120E 104e Oak Technology, Inc 0017 OTI-64017 0107 OTI-107 [Spitfire] @@ -3988,6 +5339,7 @@ 3020 FIVE-EX based Fibre Channel to PCIe HBA 302c M001 PCI Express Switch Upstream Port 302d M001 PCI Express Switch Downstream Port + 3070 Hitachi FIVE-FX Fibre Channel to PCIe HBA 3505 SH7751 PCI Controller (PCIC) 350e SH7751R PCI Controller (PCIC) 1055 Efar Microsystems @@ -4039,7 +5391,6 @@ 18c0 MPC8265A/8266/8272 18c1 MPC8271/MPC8272 3052 SM56 Data Fax Modem - 3055 SM56 Data Fax Modem 3410 DSP56361 Digital Signal Processor ecc0 0050 Gina24 rev.0 ecc0 0051 Gina24 rev.1 @@ -4095,6 +5446,7 @@ 1275 20275 3318 PDC20318 (SATA150 TX4) 3319 PDC20319 (FastTrak S150 TX4) + 105a 3319 FastTrak S150 TX4 4 port SATA PCI board 8086 3427 S875WP1-E mainboard 3371 PDC20371 (FastTrak S150 TX2plus) 3373 PDC20378 (FastTrak 378/SATA 378) @@ -4167,7 +5519,6 @@ c350 80333 [SuperTrak EX12350] e350 80333 [SuperTrak EX24350] 105b Foxconn International, Inc. - 0c4d SiS AC'97 Sound Controller 105c Wipro Infotech Limited 105d Number 9 Computer Company 2309 Imagine 128 @@ -4316,6 +5667,7 @@ 003b UniNorth/Intrepid ATA/100 003e KeyLargo/Intrepid Mac I/O 003f KeyLargo/Intrepid USB + 1af4 1100 QEMU Virtual Machine 0040 K2 KeyLargo USB 0041 K2 KeyLargo Mac/IO 0042 K2 FireWire @@ -4347,7 +5699,8 @@ 006a Intrepid2 Firewire 006b Intrepid2 GMAC (Sun GEM) 0074 U4 HT Bridge - 1645 Tigon3 Gigabit Ethernet NIC (BCM5701) +# should be 14e4:1645 + 1645 Broadcom NetXtreme BCM5701 Gigabit Ethernet 106c Hynix Semiconductor 8139 8139c 100BaseTX Ethernet Controller 8801 Dual Pentium ISA/PCI Motherboard @@ -4405,6 +5758,8 @@ 1240 ISP1240 SCSI Host Adapter 1280 ISP1280 SCSI Host Adapter 2020 ISP2020A Fast!SCSI Basic Adapter + 2031 ISP8324-based 16Gb Fibre Channel to PCI Express Adapter + 103c 8002 3830C 16G Fibre Channel Host Bus Adapter 2100 QLA2100 64-bit Fibre Channel Adapter 1077 0001 QLA2100 64-bit Fibre Channel Adapter 2200 QLA2200 64-bit Fibre Channel Adapter @@ -4418,7 +5773,9 @@ 103c 12d7 4Gb Fibre Channel [AB379A] 103c 12dd 4Gb Fibre Channel [AB429A] 2432 ISP2432-based 4Gb Fibre Channel to PCI Express HBA + 103c 7040 FC1142SR 4Gb 1-port PCIe Fibre Channel Host Bus Adapter [HPAE311A] 2532 ISP2532-based 8Gb Fibre Channel to PCI Express HBA + 103c 3262 StorageWorks 81Q 1077 0167 QME2572 Dual Port FC8 HBA Mezzanine 3022 ISP4022-based Ethernet NIC 3032 ISP4032-based Ethernet IPv6 NIC @@ -4433,6 +5790,7 @@ 8000 10GbE Converged Network Adapter (TCP/IP Networking) 8001 10GbE Converged Network Adapter (FCoE) 8020 cLOM8214 1/10GbE Controller + 1028 1f64 QMD8262-k 10G DP bNDC KR 103c 3346 CN1000Q Dual Port Converged Network Adapter 103c 3733 NC523SFP 10Gb 2-port Server Adapter 1077 0203 8200 Series Single Port 10GbE Converged Network Adapter (TCP/IP Networking) @@ -4441,12 +5799,20 @@ 1077 020c 3200 Series Quad Port 1Gb Intelligent Ethernet Adapter 1077 020f 3200 Series Single Port 10Gb Intelligent Ethernet Adapter 1077 0210 QME8242-k 10GbE Dual Port Mezzanine Card + 1077 0233 QME8262-k 10GbE Dual Port Mezzanine Card 8021 8200 Series 10GbE Converged Network Adapter (FCoE) 103c 3348 CN1000Q Dual Port Converged Network Adapter 1077 0211 QME8242-k 10GbE Dual Port Mezzanine Card, FCoE 8022 8200 Series 10GbE Converged Network Adapter (iSCSI) 103c 3347 CN1000Q Dual Port Converged Network Adapter 1077 0212 QME8242-k 10GbE Dual Port Mezzanine Card, iSCSI + 8030 ISP8324 1/10GbE Converged Network Controller + 1077 0243 8300 Series Single Port 10GbE Converged Network Adapter (TCP/IP Networking) + 1077 0246 8300 Series Dual Port 10GbE Converged Network Adapter (TCP/IP Networking) + 8031 8300 Series 10GbE Converged Network Adapter (FCoE) + 8032 8300 Series 10GbE Converged Network Adapter (iSCSI) + 8430 ISP8324 1/10GbE Converged Network Controller (NIC VF) + 8431 8300 Series 10GbE Converged Network Adapter (FCoE VF) 8432 ISP2432M-based 10GbE Converged Network Adapter (CNA) 1078 Cyrix Corporation 0000 5510 [Grappa] @@ -4463,15 +5829,11 @@ 0403 ZFMicro Expansion Bus 1079 I-Bus 107a NetWorth -107b Gateway 2000 +# formerly Gateway 2000 / acquired by Acer Inc. +107b Gateway, Inc. 107c LG Electronics [Lucky Goldstar Co. Ltd] 107d LeadTek Research Inc. 0000 P86C850 - 2134 WinFast 3D S320 II - 6609 Winfast TV 2000 XP RM - 6654 Conexant CX23883 [WinFast DTV1800 H] - 6f22 WinFast PxTV1200 - 6f34 WinFast DVR3100 H 107e Interphase Corporation 0001 5515 ATM Adapter [Flipper] 0002 100 VG AnyLan Controller @@ -4501,7 +5863,6 @@ 1083 Forex Computer Corporation 0001 FR710 1084 Parador -1085 Tulip Computers Int.B.V. 1086 J. Bond Computer Systems 1087 Cache Computer 1088 Microcomputer Systems (M) Son @@ -4516,7 +5877,7 @@ 108d Olicom 0001 Token-Ring 16/4 PCI Adapter (3136/3137) 0002 16/4 Token Ring - 0004 RapidFire 3139 Token-Ring 16/4 PCI Adapter + 0004 RapidFire OC-3139/3140 Token-Ring 16/4 PCI Adapter 108d 0004 OC-3139/3140 RapidFire Token-Ring 16/4 Adapter 0005 GoCard 3250 Token-Ring 16/4 CardBus PC Card 0006 OC-3530 RapidFire Token-Ring 100 @@ -4633,82 +5994,712 @@ 1093 National Instruments 0160 PCI-DIO-96 0162 PCI-MIO-16XE-50 - 1150 PCI-DIO-32HS High Speed Digital I/O Board + 1150 PCI-6533 (PCI-DIO-32HS) 1170 PCI-MIO-16XE-10 1180 PCI-MIO-16E-1 1190 PCI-MIO-16E-4 11b0 PXI-6070E - 11c0 PXI-6040e - 11d0 PXI-6030e - 1270 PCI-6032e + 11c0 PXI-6040E + 11d0 PXI-6030E + 1270 PCI-6032E + 1290 PCI-6704 + 12b0 PCI-6534 1310 PCI-6602 + 1320 PXI-6533 1330 PCI-6031E - 1340 PCI-6033e + 1340 PCI-6033E 1350 PCI-6071E 1360 PXI-6602 + 13c0 PXI-6508 + 1490 PXI-6534 14e0 PCI-6110 14f0 PCI-6111 1580 PXI-6031E 15b0 PXI-6071E 1710 PXI-6509 + 17c0 PXI-5690 17d0 PCI-6503 1870 PCI-6713 1880 PCI-6711 18b0 PCI-6052E 18c0 PXI-6052E + 1920 PXI-6704 + 1930 PCI-6040E + 19c0 PCI-4472 + 1aa0 PXI-4110 + 1ad0 PCI-6133 + 1ae0 PXI-6133 + 1e30 PCI-6624 + 1e40 PXI-6624 + 1e50 PXI-5404 2410 PCI-6733 2420 PXI-6733 2430 PCI-6731 + 2470 PCI-4474 + 24a0 PCI-4065 + 24b0 PXI-4200 + 24f0 PXI-4472 + 2510 PCI-4472 + 2520 PCI-4474 + 27a0 PCI-6123 + 27b0 PXI-6123 2880 DAQCard-6601 2890 PCI-6036E + 28a0 PXI-4461 + 28b0 PCI-6013 28c0 PCI-6014 + 28d0 PCI-5122 + 28e0 PXI-5122 + 29f0 PXI-7334 + 2a00 PXI-7344 2a60 PCI-6023E 2a70 PCI-6024E 2a80 PCI-6025E - 2ab0 PXI-6025e + 2ab0 PXI-6025E + 2b10 PXI-6527 + 2b20 PCI-6527 2b80 PXI-6713 2b90 PXI-6711 2c60 PCI-6601 2c70 PXI-6601 2c80 PCI-6035E + 2c90 PCI-6703 2ca0 PCI-6034E + 2cb0 PCI-7344 2cc0 PXI-6608 + 2d20 PXI-5600 2db0 PCI-6608 - 70a9 PCI-6528 (Digital I/O at 60V) + 2dc0 PCI-4070 + 2dd0 PXI-4070 + 2eb0 PXI-4472 + 2ec0 PXI-6115 + 2ed0 PCI-6115 + 2ee0 PXI-6120 + 2ef0 PCI-6120 + 2fd1 PCI-7334 + 2fd2 PCI-7350 + 2fd3 PCI-7342 + 2fd5 PXI-7350 + 2fd6 PXI-7342 + 7003 PCI-6551 + 7004 PXI-6551 + 700b PXI-5421 + 700c PCI-5421 + 7023 PXI-2593 + 702c PXI-7831R + 702d PCI-7831R + 702e PXI-7811R + 702f PCI-7811R + 7030 PCI-CAN (Series 2) + 7031 PCI-CAN/2 (Series 2) + 7032 PCI-CAN/LS (Series 2) + 7033 PCI-CAN/LS2 (Series 2) + 7034 PCI-CAN/DS (Series 2) + 7035 PXI-8460 (Series 2, 1 port) + 7036 PXI-8460 (Series 2, 2 ports) + 7037 PXI-8461 (Series 2, 1 port) + 7038 PXI-8461 (Series 2, 2 ports) + 7039 PXI-8462 (Series 2) + 703f PXI-2566 + 7040 PXI-2567 + 7044 MXI-4 Connection Monitor + 7047 PXI-6653 + 704c PXI-2530 + 704f PXI-4220 + 7050 PXI-4204 + 7055 PXI-7830R + 7056 PCI-7830R + 705a PCI-CAN/XS (Series 2) + 705b PCI-CAN/XS2 (Series 2) + 705c PXI-8464 (Series 2, 1 port) + 705d PXI-8464 (Series 2, 2 ports) + 705e cRIO-9102 + 7060 PXI-5610 + 7064 PXI-1045 Trigger Routing Module + 7065 PXI-6652 + 7066 PXI-6651 + 7067 PXI-2529 + 7068 PCI-CAN/SW (Series 2) + 7069 PCI-CAN/SW2 (Series 2) + 706a PXI-8463 (Series 2, 1 port) + 706b PXI-8463 (Series 2, 2 ports) + 7073 PCI-6723 + 7074 PXI-7833R + 7075 PXI-6552 + 7076 PCI-6552 + 707c PXI-1428 + 707e PXI-4462 + 7080 PXI-8430/2 (RS-232) Interface + 7081 PXI-8431/2 (RS-485) Interface + 7083 PCI-7833R + 7085 PCI-6509 + 7086 PXI-6528 + 7087 PCI-6515 + 7088 PCI-6514 + 708c PXI-2568 + 708d PXI-2569 + 70a9 PCI-6528 70aa PCI-6229 70ab PCI-6259 70ac PCI-6289 + 70ad PXI-6251 70ae PXI-6220 70af PCI-6221 70b0 PCI-6220 + 70b1 PXI-6229 + 70b2 PXI-6259 + 70b3 PXI-6289 70b4 PCI-6250 + 70b5 PXI-6221 70b6 PCI-6280 70b7 PCI-6254 - 70b8 PCI-6251 [M Series - High Speed Multifunction DAQ] + 70b8 PCI-6251 + 70b9 PXI-6250 + 70ba PXI-6254 + 70bb PXI-6280 70bc PCI-6284 70bd PCI-6281 + 70be PXI-6284 70bf PXI-6281 70c0 PCI-6143 + 70c3 PCI-6511 + 70c4 PXI-7330 + 70c5 PXI-7340 + 70c6 PCI-7330 + 70c7 PCI-7340 + 70c8 PCI-6513 + 70c9 PXI-6515 + 70ca PCI-1405 + 70cc PCI-6512 + 70cd PXI-6514 + 70ce PXI-1405 + 70cf PCIe-GPIB + 70d0 PXI-2570 + 70d1 PXI-6513 + 70d2 PXI-6512 + 70d3 PXI-6511 + 70d4 PCI-6722 + 70d6 PXI-4072 + 70d7 PXI-6541 + 70d8 PXI-6542 + 70d9 PCI-6541 + 70da PCI-6542 + 70db PCI-8430/2 (RS-232) Interface + 70dc PCI-8431/2 (RS-485) Interface + 70dd PXI-8430/4 (RS-232) Interface + 70de PXI-8431/4 (RS-485) Interface + 70df PCI-8430/4 (RS-232) Interface + 70e0 PCI-8431/4 (RS-485) Interface + 70e1 PXI-2532 + 70e2 PXI-8430/8 (RS-232) Interface + 70e3 PXI-8431/8 (RS-485) Interface + 70e4 PCI-8430/8 (RS-232) Interface + 70e5 PCI-8431/8 (RS-485) Interface + 70e6 PXI-8430/16 (RS-232) Interface + 70e7 PCI-8430/16 (RS-232) Interface + 70e8 PXI-8432/2 (Isolated RS-232) Interface + 70e9 PXI-8433/2 (Isolated RS-485) Interface + 70ea PCI-8432/2 (Isolated RS-232) Interface + 70eb PCI-8433/2 (Isolated RS-485) Interface + 70ec PXI-8432/4 (Isolated RS-232) Interface + 70ed PXI-8433/4 (Isolated RS-485) Interface + 70ee PCI-8432/4 (Isolated RS-232) Interface + 70ef PCI-8433/4 (Isolated RS-485) Interface + 70f0 PXI-5922 + 70f1 PCI-5922 70f2 PCI-6224 - 7144 PXI-5124 (12-bit 200 MS/s Digitizer) + 70f3 PXI-6224 + 70f6 cRIO-9101 + 70f7 cRIO-9103 + 70f8 cRIO-9104 + 70ff PXI-6723 + 7100 PXI-6722 + 7104 PCIx-1429 + 7105 PCIe-1429 + 710a PXI-4071 + 710d PXI-6143 + 710e PCIe-GPIB + 710f PXI-5422 + 7110 PCI-5422 + 7111 PXI-5441 + 7119 PXI-6561 + 711a PXI-6562 + 711b PCI-6561 + 711c PCI-6562 + 7120 PCI-7390 + 7121 PXI-5122EX + 7122 PCI-5122EX + 7123 PXIe-5653 + 7124 PCI-6510 + 7125 PCI-6516 + 7126 PCI-6517 + 7127 PCI-6518 + 7128 PCI-6519 + 7137 PXI-2575 + 713c PXI-2585 + 713d PXI-2586 + 7142 PXI-4224 + 7144 PXI-5124 + 7145 PCI-5124 + 7146 PCI-6132 + 7147 PXI-6132 + 7148 PCI-6122 + 7149 PXI-6122 + 714c PXI-5114 + 714d PCI-5114 + 7150 PXI-2564 + 7152 PCI-5640R + 7156 PXI-1044 Trigger Routing Module + 715d PCI-1426 + 7167 PXI-5412 + 7168 PCI-5412 + 716b PCI-6230 716c PCI-6225 - 717d PCIE-6251 + 716d PXI-6225 + 716f PCI-4461 + 7170 PCI-4462 + 7171 PCI-6010 + 7174 PXI-8360 + 7177 PXI-6230 + 717d PCIe-6251 717f PCIe-6259 - 71bc PCI-6221 (37pin) - 71d0 PXI-6143 - b001 IMAQ-PCI-1408 - b011 IMAQ-PXI-1408 - b021 IMAQ-PCI-1424 - b031 IMAQ-PCI-1413 - b041 IMAQ-PCI-1407 - b051 IMAQ-PXI-1407 - b061 IMAQ-PCI-1411 - b071 IMAQ-PCI-1422 - b081 IMAQ-PXI-1422 - b091 IMAQ-PXI-1411 - c4c4 PXIe-4353 + 7187 PCI-1410 + 718b PCI-6521 + 718c PXI-6521 + 7191 PCI-6154 + 7193 PXI-7813R + 7194 PCI-7813R + 7195 PCI-8254R + 7197 PXI-5402 + 7198 PCI-5402 + 719f PCIe-6535 + 71a0 PCIe-6536 + 71a3 PXI-5650 + 71a4 PXI-5652 + 71a5 PXI-2594 + 71a7 PXI-2595 + 71a9 PXI-2596 + 71aa PXI-2597 + 71ab PXI-2598 + 71ac PXI-2599 + 71ad PCI-GPIB+ + 71ae PCIe-1430 + 71b7 PXI-1056 Trigger Routing Module + 71b8 PXI-1045 Trigger Routing Module + 71b9 PXI-1044 Trigger Routing Module + 71bb PXI-2584 + 71bc PCI-6221 (37-pin) + 71bf PCIe-1427 + 71c5 PCI-6520 + 71c6 PXI-2576 + 71c7 cRIO-9072 + 71dc PCI-1588 + 71e0 PCI-6255 + 71e1 PXI-6255 + 71e2 PXI-5406 + 71e3 PCI-5406 + 71fc PXI-4022 + 7209 PCI-6233 + 720a PXI-6233 + 720b PCI-6238 + 720c PXI-6238 + 7260 PXI-5142 + 7261 PCI-5142 + 726d PXI-5651 + 7273 PXI-4461 + 7274 PXI-4462 + 7279 PCI-6232 + 727a PXI-6232 + 727b PCI-6239 + 727c PXI-6239 + 727e SMBus Controller + 1093 75ac PXIe-8388 + 1093 75ad PXIe-8389 + 1093 7650 PXIe-8381 + 1093 8360 PXIe-8360 + 1093 8370 PXIe-8370 + 1093 8375 PXIe-8375 + 7281 PCI-6236 + 7282 PXI-6236 + 7283 PXI-2554 + 7288 PXIe-5611 + 7293 PCIe-8255R + 729d cRIO-9074 + 72a4 PCIe-4065 + 72a7 PCIe-6537 + 72a8 PXI-5152 + 72a9 PCI-5152 + 72aa PXI-5105 + 72ab PCI-5105 + 72b8 PXI-6682 + 72d0 PXI-2545 + 72d1 PXI-2546 + 72d2 PXI-2547 + 72d3 PXI-2548 + 72d4 PXI-2549 + 72d5 PXI-2555 + 72d6 PXI-2556 + 72d7 PXI-2557 + 72d8 PXI-2558 + 72d9 PXI-2559 + 72e8 PXIe-6251 + 72e9 PXIe-6259 + 72ef PXI-4498 + 72f0 PXI-4496 + 72fb PXIe-6672 + 730e PXI-4130 + 730f PXI-5922EX + 7310 PCI-5922EX + 731c PXI-2535 + 731d PXI-2536 + 7322 PXIe-6124 + 7327 PXI-6529 + 7331 PXIe-5602 + 7332 PXIe-5601 + 7333 PXI-5900 + 7335 PXI-2533 + 7336 PXI-2534 + 7342 PXI-4461 + 7349 PXI-5154 + 734a PCI-5154 + 7357 PXI-4065 + 7359 PXI-4495 + 7370 PXI-4461 + 7373 sbRIO-9601 + 7374 IOtech-9601 + 7375 sbRIO-9602 + 7378 sbRIO-9641 + 737d PXI-5124EX + 7384 PXI-7851R + 7385 PXI-7852R + 7386 PCIe-7851R + 7387 PCIe-7852R + 7390 PXI-7841R + 7391 PXI-7842R + 7392 PXI-7853R + 7393 PCIe-7841R + 7394 PCIe-7842R + 7397 sbRIO-9611 + 7398 sbRIO-9612 + 7399 sbRIO-9631 + 739a sbRIO-9632 + 739b sbRIO-9642 + 73a1 PXIe-4498 + 73a2 PXIe-4496 + 73a5 PXIe-5641R + 73a7 PXI-8250 Chassis Monitor Module + 73a8 PXI-8511 CAN/LS + 73a9 PXI-8511 CAN/LS + 73aa PXI-8512 CAN/HS + 73ab PXI-8512 CAN/HS + 73ac PXI-8513 CAN/XS + 73ad PXI-8513 CAN/XS + 73af PXI-8516 LIN + 73b1 PXI-8517 FlexRay + 73b2 PXI-8531 CANopen + 73b3 PXI-8531 CANopen + 73b4 PXI-8532 DeviceNet + 73b5 PXI-8532 DeviceNet + 73b6 PCI-8511 CAN/LS + 73b7 PCI-8511 CAN/LS + 73b8 PCI-8512 CAN/HS + 73b9 PCI-8512 CAN/HS + 73ba PCI-8513 CAN/XS + 73bb PCI-8513 CAN/XS + 73bd PCI-8516 LIN + 73bf PCI-8517 FlexRay + 73c0 PCI-8531 CANopen + 73c1 PCI-8531 CANopen + 73c2 PCI-8532 DeviceNet + 73c3 PCI-8532 DeviceNet + 73c5 PXIe-2527 + 73c6 PXIe-2529 + 73c8 PXIe-2530 + 73c9 PXIe-2532 + 73ca PXIe-2569 + 73cb PXIe-2575 + 73cc PXIe-2593 + 73d5 PXI-7951R + 73d6 PXI-7952R + 73d7 PXI-7953R + 73e1 PXI-7854R + 73ec PXI-7954R + 73ed cRIO-9073 + 73f0 PXI-5153 + 73f1 PCI-5153 + 73f4 PXI-2515 + 73f6 cRIO-9111 + 73f7 cRIO-9112 + 73f8 cRIO-9113 + 73f9 cRIO-9114 + 73fa cRIO-9116 + 73fb cRIO-9118 + 7404 PXI-4132 + 7405 PXIe-6674T + 7406 PXIe-6674 + 740e PCIe-8430/16 (RS-232) Interface + 740f PCIe-8430/8 (RS-232) Interface + 7410 PCIe-8431/16 (RS-485) Interface + 7411 PCIe-8431/8 (RS-485) Interface + 7414 PCIe-GPIB+ + 741c PXI-5691 + 741d PXI-5695 + 743c CSC-3059 + 7448 PXI-2510 + 7454 PXI-2512 + 7455 PXI-2514 + 7456 PXIe-2512 + 7457 PXIe-2514 + 745a PXI-6682H + 745e PXI-5153EX + 745f PCI-5153EX + 7460 PXI-5154EX + 7461 PCI-5154EX + 746d PXIe-5650 + 746e PXIe-5651 + 746f PXIe-5652 + 7472 PXI-2800 + 7495 PXIe-5603 + 7497 PXIe-5605 + 74ae PXIe-2515 + 74b4 PXI-2531 + 74b5 PXIe-2531 + 74c1 PXIe-8430/16 (RS-232) Interface + 74c2 PXIe-8430/8 (RS-232) Interface + 74c3 PXIe-8431/16 (RS-485) Interface + 74c4 PXIe-8431/8 (RS-485) Interface + 74d5 PXIe-5630 + 74d9 PCIe-8432/2 (Isolated RS-232) Interface + 74da PCIe-8433/2 (Isolated RS-485) Interface + 74db PCIe-8432/4 (Isolated RS-232) Interface + 74dc PCIe-8433/4 (Isolated RS-485) Interface + 74e8 NI 9148 + 7515 PCIe-8430/2 (RS-232) Interface + 7516 PCIe-8430/4 (RS-232) Interface + 7517 PCIe-8431/2 (RS-485) Interface + 7518 PCIe-8431/4 (RS-485) Interface + 751b cRIO-9081 + 751c cRIO-9082 + 7528 PXIe-4497 + 7529 PXIe-4499 + 752a PXIe-4492 + 7539 NI 9157 + 753a NI 9159 + 7598 PXI-2571 + 75a4 PXI-4131A + 75b1 PCIe-7854R + 75ba PXI-2543 + 75bb PXIe-2543 + 75e5 PXI-6683 + 75e6 PXI-6683H + 75ef PXIe-5632 + 761f PXI-2540 + 7620 PXIe-2540 + 7621 PXI-2541 + 7622 PXIe-2541 + 7626 NI 9154 + 7627 NI 9155 + 7638 PXI-2720 + 7639 PXI-2722 + 763a PXIe-2725 + 763b PXIe-2727 + 763c PXI-4465 + 764b PXIe-2790 + 764c PXI-2520 + 764d PXI-2521 + 764e PXI-2522 + 764f PXI-2523 + 7654 PXI-2796 + 7655 PXI-2797 + 7656 PXI-2798 + 7657 PXI-2799 + 765d PXI-2542 + 765e PXIe-2542 + 765f PXI-2544 + 7660 PXIe-2544 + 766d PCIe-6535B + 766e PCIe-6536B + 766f PCIe-6537B + 76a3 PXIe-6535B + 76a4 PXIe-6536B + 76a5 PXIe-6537B + 9020 PXI-2501 + 9030 PXI-2503 + 9040 PXI-2527 + 9050 PXI-2565 + 9060 PXI-2590 + 9070 PXI-2591 + 9080 PXI-2580 + 9090 PCI-4021 + 90a0 PXI-4021 + b001 PCI-1408 + b011 PXI-1408 + b021 PCI-1424 + b022 PXI-1424 + b031 PCI-1413 + b041 PCI-1407 + b051 PXI-1407 + b061 PCI-1411 + b071 PCI-1422 + b081 PXI-1422 + b091 PXI-1411 + b0b1 PCI-1409 + b0c1 PXI-1409 + b0e1 PCI-1428 + c4c4 PXIe/PCIe Device + 1093 728a PXIe-5421 + 1093 728b PXIe-5442 + 1093 728d PXIe-5451 + 1093 72a2 PXIe-5122 + 1093 72da PXIe-5422 + 1093 72f7 PXIe-6535 + 1093 72f8 PXIe-6536 + 1093 72f9 PXIe-6537 + 1093 7326 PCIe-6509 + 1093 736c PXIe-4140 + 1093 738b PXIe-5622 + 1093 73c4 PXIe-5450 + 1093 73c7 PXIe-6545 + 1093 73d4 PXIe-6544 + 1093 7425 PCIe-6320 + 1093 7427 PCIe-6321 + 1093 7428 PXIe-6323 + 1093 7429 PCIe-6323 + 1093 742a PXIe-6341 + 1093 742b PCIe-6341 + 1093 742c PXIe-6343 + 1093 742d PCIe-6343 + 1093 742f PCIe-6351 + 1093 7431 PCIe-6353 + 1093 7432 PXIe-6361 + 1093 7433 PCIe-6361 + 1093 7434 PXIe-6363 + 1093 7435 PCIe-6363 + 1093 7436 PXIe-6356 + 1093 7437 PXIe-6358 + 1093 7438 PXIe-6366 + 1093 7439 PXIe-6368 + 1093 7468 PXIe-5185 + 1093 7469 PXIe-5186 + 1093 7492 PXIe-4300 + 1093 7498 PXIe-6548 + 1093 7499 PXIe-6547 + 1093 74a8 PXIe-4330 + 1093 74a9 PXIe-4331 + 1093 74b1 PXIe-4154 + 1093 74b2 PXIe-4353 + 1093 74b6 PCIe-1433 + 1093 74cd PXIe-5643R + 1093 74d0 PXIe-7961R + 1093 74dd PXIe-6376 + 1093 74de PXIe-6378 + 1093 74e2 PXIe-7962R + 1093 74e3 PXIe-7965R + 1093 74e5 PXIe-4844 + 1093 74f3 PCIe-5140 + 1093 753c PXIe-1435 + 1093 7548 PXIe-5622 (25MHz DDC) + 1093 754d PCIe-5155 + 1093 7551 PXIe-6556 + 1093 7553 PCIe-1473R + 1093 7570 PCIe-1474R + 1093 7571 PXIe-1475R + 1093 7572 PXIe-1476R + 1093 75a2 PXIe-5693 + 1093 75a3 PXIe-5694 + 1093 75a5 PXIe-4141 + 1093 75ce PXIe-7966R + 1093 75cf PXIe-4357 + 1093 75d2 PXIe-RevB-5643R + 1093 75d3 PXIe-5644R + 1093 75ee PXIe-5645R + 1093 7613 PXIe-6555 + 1093 7619 PXIe-5185 + 1093 761a PXIe-5186 + 1093 7629 PXIe-4142 + 1093 762a PXIe-4143 + 1093 762b PXIe-4138 + 1093 762c PXIe-4144 + 1093 762d PXIe-4145 + 1093 7644 PXIe-4841 + 1093 7658 PXIe-5162 (4CH) + 1093 76ab PXIe-4322 + 1093 76ad PXIe-4112 + 1093 76ae PXIe-4113 + 1093 76b5 PXIe-7971R + 1093 76b6 PXIe-7972R + 1093 76b7 PXIe-7975R + 1093 76c8 PXIe-6614 + 1093 76c9 PXIe-6612 + 1093 76cb PXIe-5646R + 1093 76cc PXIe-5162 (2CH) + 1093 76d0 PXIe-5160 (2CH) + 1093 76d1 PXIe-5160 (4CH) + 1093 76dc PXIe-4610 + 1093 76fb PCIe-1473R-LX110 + 1093 76fe PXIe-5644R + 1093 76ff PXIe-5644R + 1093 7700 PXIe-5644R + 1093 7701 PXIe-5645R + 1093 7702 PXIe-5645R + 1093 7703 PXIe-5645R + 1093 770c PXIe-4139 + 1093 7711 PXIe-4464 + 1093 7716 PCIe-6612 + 1093 771e PXIe-4339 + 1093 7735 cRIO-9033 + 1093 774b cRIO-9031 + 1093 774d cRIO-9034 + 1093 7755 cRIO-9030 + 1093 7777 PXIe-7976R + 1093 7782 PXIe-5646R + 1093 7783 PXIe-5646R + 1093 7784 PXIe-5646R + 1093 77a5 PXIe-6345 + 1093 77a6 PXIe-6355 + 1093 77a7 PXIe-6365 + 1093 77a8 PXIe-6375 + 1093 77b4 PXIe-7820R + 1093 77b5 PXIe-7821R + 1093 77b6 PXIe-7822R + 1093 77b9 cRIO-9038 c801 PCI-GPIB - c831 PCI-GPIB bridge + c811 PCI-GPIB+ + c821 PXI-GPIB + c831 PMC-GPIB + c840 PCI-GPIB + d130 PCI-232/2 Interface + d140 PCI-232/4 Interface + d150 PCI-232/8 Interface + d160 PCI-485/2 Interface + d170 PCI-485/4 Interface + d190 PXI-8422/2 (Isolated RS-232) Interface + d1a0 PXI-8422/4 (Isolated RS-232) Interface + d1b0 PXI-8423/2 (Isolated RS-485) Interface + d1c0 PXI-8423/4 (Isolated RS-485) Interface + d1d0 PXI-8420/2 (RS-232) Interface + d1e0 PXI-8420/4 (RS-232) Interface + d1f0 PXI-8420/8 (RS-232) Interface + d1f1 PXI-8420/16 (RS-232) Interface + d230 PXI-8421/2 (RS-485) Interface + d240 PXI-8421/4 (RS-485) Interface + d250 PCI-232/2 (Isolated) Interface + d260 PCI-485/2 (Isolated) Interface + d270 PCI-232/4 (Isolated) Interface + d280 PCI-485/4 (Isolated) Interface + d290 PCI-485/8 Interface + d2a0 PXI-8421/8 (RS-485) Interface + d2b0 PCI-232/16 Interface + e111 PCI-CAN + e131 PXI-8461 (1 port) + e141 PCI-CAN/LS + e151 PXI-8460 (1 port) + e211 PCI-CAN/2 + e231 PXI-8461 (2 ports) + e241 PCI-CAN/LS2 + e251 PXI-8460 (2 ports) + e261 PCI-CAN/DS + e271 PXI-8462 1094 First International Computers [FIC] # nee CMD Technology Inc 1095 Silicon Image, Inc. @@ -4735,6 +6726,7 @@ 1095 6112 SiI 3112 SATARaid Controller 9005 0250 SATAConnect 1205SA Host Controller 3114 SiI 3114 [SATALink/SATARaid] Serial ATA Controller + 1043 8167 A8N-SLI Deluxe/Premium Mainboard 1095 3114 SiI 3114 SATALink Controller 1095 6114 SiI 3114 SATARaid Controller 3124 SiI 3124 PCI-X Serial ATA Controller @@ -4744,6 +6736,7 @@ 1095 3512 SiI 3512 SATALink Controller 1095 6512 SiI 3512 SATARaid Controller 3531 SiI 3531 [SATALink/SATARaid] Serial ATA Controller + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] 1096 Alacron 1097 Appian Technology 1098 Quantum Designs (H.K.) Ltd @@ -4791,6 +6784,38 @@ 1852 1852 FlyVideo'98 - Video (with FM Tuner) 18ac d500 DViCO FusionHDTV5 Lite 270f fc00 Digitop DTT-1000 +# Vendor/ID appear to be randomly chosen + aa00 1460 Spectra8 CardA Input0 +# Vendor/ID appear to be randomly chosen + aa01 1461 Spectra8 CardA Input1 +# Vendor/ID appear to be randomly chosen + aa02 1462 Spectra8 CardA Input2 +# Vendor/ID appear to be randomly chosen + aa03 1463 Spectra8 CardA Input3 +# Vendor/ID appear to be randomly chosen + aa04 1464 Spectra8 CardB Input0 +# Vendor/ID appear to be randomly chosen + aa05 1465 Spectra8 CardB Input1 +# Vendor/ID appear to be randomly chosen + aa06 1466 Spectra8 CardB Input2 +# Vendor/ID appear to be randomly chosen + aa07 1467 Spectra8 CardB Input3 +# Vendor/ID appear to be randomly chosen + aa08 1468 Spectra8 CardC Input0 +# Vendor/ID appear to be randomly chosen + aa09 1469 Spectra8 CardC Input1 +# Vendor/ID appear to be randomly chosen + aa0a 146a Spectra8 CardC Input2 +# Vendor/ID appear to be randomly chosen + aa0b 146b Spectra8 CardC Input3 +# Vendor/ID appear to be randomly chosen + aa0c 146c Spectra8 CardD Input0 +# Vendor/ID appear to be randomly chosen + aa0d 146d Spectra8 CardD Input1 +# Vendor/ID appear to be randomly chosen + aa0e 146e Spectra8 CardD Input2 +# Vendor/ID appear to be randomly chosen + aa0f 146f Spectra8 CardD Input3 bd11 1200 PCTV pro (TV + FM stereo receiver) 036f Bt879 Video Capture 127a 0044 Bt879 Video Capture NTSC @@ -4932,6 +6957,8 @@ 4002 TIO-CE PCI Express Port 8001 O2 1394 8002 G-net NT +# PCIe x1 Low Profile + 802b REACT external interrupt controller 10aa ACC Microelectronics 0000 ACCM 2188 2051 2051 CPU bridge @@ -4958,6 +6985,10 @@ 10b4 237e Velocity 4400 10b5 PLX Technology, Inc. 0001 i960 PCI bus interface + 0557 PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 Digium Tormenta 2 T400P-SS7 or E400P-SS7 Quad T1 or E1 PCI card + 1000 PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 ATCOM AT400P Quad T1 PCI card 1024 Acromag, Inc. IndustryPack Carrier Card 1042 Brandywine / jxi2, Inc. - PMC-SyncClock32, IRIG A & B, Nasa 36 106a Dual OX16C952 4 port serial adapter [Megawolf Romulus/4] @@ -4967,9 +6998,17 @@ 1103 VScom 200 2 port serial adaptor 1146 VScom 010 1 port parallel adaptor 1147 VScom 020 2 port parallel adaptor + 2000 PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 ATCOM AE400P Quad E1 PCI card 2540 IXXAT CAN-Interface PC-I 04/PCI 2724 Thales PCSM Security Card 3376 Cosateq 4 Port CAN Card + 4000 PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 Tormenta 3 Varion V400P/ATCOM TE400P Quad E1/T1/J1 PCI card + 4001 PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 ATCOM A400PE Quad E1 PCI card + 4002 PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 ATCOM A400PT Quad T1 PCI card 6140 PCI6140 32-bit 33MHz PCI-to-PCI Bridge 6150 PCI6150 32-bit 33MHz PCI-to-PCI Bridge 6152 PCI6152 32-bit 66MHz PCI-to-PCI Bridge @@ -5027,7 +7066,11 @@ 8664 PEX 8664 64-lane, 16-Port PCI Express Gen 2 (5.0 GT/s) Switch 8680 PEX 8680 80-lane, 20-Port PCI Express Gen 2 (5.0 GT/s) Multi-Root Switch 8696 PEX 8696 96-lane, 24-Port PCI Express Gen 2 (5.0 GT/s) Multi-Root Switch + 8717 PEX 8717 16-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch with DMA + 8718 PEX 8718 16-Lane, 5-Port PCI Express Gen 3 (8.0 GT/s) Switch 8732 PEX 8732 32-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch + 8734 PEX 8734 32-lane, 8-Port PCI Express Gen 3 (8.0GT/s) Switch + 8747 PEX 8747 48-Lane, 5-Port PCI Express Gen 3 (8.0 GT/s) Switch # This is the Non-Transparent-Bridge Virtualized Port as presented by the PLX PEX 8732 chip, the physical bridges show up at 10b5:8732 87b0 PEX 8732 32-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch 9016 PLX 9016 8-port serial controller @@ -5133,9 +7176,11 @@ 10b5 3354 Alpermann+Velte PCL PCIe LV: Timecode Reader Board 10b5 3355 Alpermann+Velte PCL PCIe L: Timecode Reader Board 10b5 3415 Alpermann+Velte PCIe TS: Time Synchronisation Board + 10b5 3493 Alpermann+Velte PCL PCIe 3G: Timecode Reader Board 1369 c001 LX6464ES 1369 c201 LX1616ES 14b4 d10a DekTec DTA-110T + 14b4 d128 Dektec DTA-140 14b4 d140 Dektec DTA-140 1a0e 006f Dektec DTA-111 9060 PCI9060 32-bit 33MHz PCI <-> IOBus Bridge @@ -5162,11 +7207,20 @@ 1517 000f ECDR-GC314-PMC Receiver 1885 0700 Tsunami FPGA PMC with Altera Stratix S40 1885 0701 Tsunami FPGA PMC with Altera Stratix S30 + 9733 PEX 9733 33-lane, 9-port PCI Express Gen 3 (8.0 GT/s) Switch + 9749 PEX 9749 49-lane, 13-port PCI Express Gen 3 (8.0 GT/s) Switch a100 Blackmagic Design DeckLink bb04 B&B 3PCIOSD1A Isolated PCI Serial c001 CronyxOmega-PCI (8-port RS232) + d00d PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 Digium Tormenta 2 T400P or E400P Quad T1 or E1 PCI card + d33d PCI9030 32-bit 33MHz PCI <-> IOBus Bridge + 10b5 9030 Tormenta 3 Varion V401PT Quad T1/J1 PCI card d44d PCI9030 32-bit 33MHz PCI <-> IOBus Bridge - 10b5 17f6 entVoice E1 Card + 10b5 17f6 Allo CP100P/E 1-port E1/T1/J1 PCI/PCIe card + 10b5 17f7 Allo CP400P/E 4-port E1/T1/J1 PCI/PCIe card + 10b5 17f8 Allo CP200P/E 2-port E1/T1/J1 PCI/PCIe card + 10b5 9030 Tormenta 3 Varion V401PE Quad E1 PCI card 10b6 Madge Networks 0001 Smart 16/4 PCI Ringnode 0002 Smart 16/4 PCI Ringnode Mk2 @@ -5183,8 +7237,8 @@ 10b6 0007 Presto PCI 0009 Smart 100/16/4 PCI-HS Ringnode 10b6 0009 Smart 100/16/4 PCI-HS Ringnode - 000a Smart 100/16/4 PCI Ringnode - 10b6 000a Smart 100/16/4 PCI Ringnode + 000a Token Ring 100/16/4 Ringnode/Ringrunner + 10b6 000a Token Ring 100/16/4 Ringnode/Ringrunner 000b 16/4 CardBus Adapter Mk2 10b6 0008 16/4 CardBus Adapter Mk2 10b6 000b 16/4 Cardbus Adapter Mk2 @@ -5194,6 +7248,8 @@ 1001 Collage 155 ATM Server Adapter 10b7 3Com Corporation 0001 3c985 1000BaseSX (SX/TX) +# wrong ID? + 9850 0001 3c985B-SX 0013 AR5212 802.11abg NIC (3CRDAG675) 10b7 2031 3CRDAG675 11a/b/g Wireless PCI Adapter 0910 3C910-A01 @@ -5242,7 +7298,7 @@ 10b7 656b 3CCFEM656 10/100 LAN+56K Modem CardBus 6564 3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado] 7646 3cSOHO100-TX Hurricane - 7770 3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect] + 7770 3CRWE777 PCI Wireless Adapter [Airconnect] 7940 3c803 FDDILink UTP Controller 7980 3c804 FDDILink SAS Controller 7990 3c805 FDDILink DAS Controller @@ -5389,7 +7445,7 @@ 1681 M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR] 1687 M1687 K8 Northbridge [AGP8X and HyperTransport] 1689 M1689 K8 Northbridge [Super K8 Single Chip] - 1695 M1695 K8 Northbridge [PCI Express and HyperTransport] + 1695 M1695 Host Bridge 1697 M1697 HTT Host Bridge 3141 M3141 3143 M3143 @@ -5482,7 +7538,6 @@ 10c1 ICM Co., Ltd. 10c2 Auspex Systems Inc. 10c3 Samsung Semiconductors, Inc. - 1100 Smartether100 SC1100 LAN Adapter (i82557B) 10c4 Award Software International Inc. 10c5 Xerox Corporation 10c6 Rambus Inc. @@ -5544,8 +7599,8 @@ 10cd Advanced System Products, Inc 1100 ASC1100 1200 ASC1200 [(abp940) Fast SCSI-II] - 1300 ABP940-U / ABP960-U - 10cd 1310 ASC1300 SCSI Adapter + 1300 ASC1300 / ASC3030 [ABP940-U / ABP960-U / ABP3925] + 10cd 1310 ASC1300/3030 SCSI adapter 1195 1320 Ultra-SCSI CardBus PC Card REX CB31 2300 ABP940-UW 2500 ABP940-U2W @@ -5598,7 +7653,7 @@ 10de NVIDIA Corporation 0008 NV1 [EDGE 3D] 0009 NV1 [EDGE 3D] - 0020 NV4 [RIVA TNT] + 0020 NV4 [Riva TNT] 1043 0200 V3400 TNT 1048 0c18 Erazor II SGRAM 1048 0c19 Erazor II @@ -5622,7 +7677,7 @@ 10de 0020 Riva TNT 1102 1015 Graphics Blaster CT6710 1102 1016 Graphics Blaster RIVA TNT - 0028 NV5 [RIVA TNT2/TNT2 Pro] + 0028 NV5 [Riva TNT2 / TNT2 Pro] 1043 0200 AGP-V3800 SGRAM 1043 0201 AGP-V3800 SDRAM 1043 0205 PCI-V3800 @@ -5641,6 +7696,7 @@ 1092 4a00 Viper V770 1092 4a02 Viper V770 Ultra 1092 5a00 RIVA TNT2/TNT2 Pro + 1092 5a40 Viper V770D AGP 1092 6a02 Viper V770 Ultra 1092 7a02 Viper V770 Ultra 10de 0005 RIVA TNT2 Pro @@ -5649,7 +7705,7 @@ 1102 1026 3D Blaster RIVA TNT2 Digital 1462 8806 MS-8806 AGPhantom Graphics Card 14af 5810 Maxi Gamer Xentor - 0029 NV5 [RIVA TNT2 Ultra] + 0029 NV5 [Riva TNT2 Ultra] 1043 0200 AGP-V3800 Deluxe 1043 0201 AGP-V3800 Ultra SDRAM 1043 0205 PCI-V3800 Ultra @@ -5660,32 +7716,39 @@ 1102 1029 3D Blaster RIVA TNT2 Ultra 1102 102f 3D Blaster RIVA TNT2 Ultra 14af 5820 Maxi Gamer Xentor 32 + 4843 4f34 Dynamite 002a NV5 [Riva TNT2] 002b NV5 [Riva TNT2] - 002c NV6 [Vanta/Vanta LT] + 002c NV5 [Vanta / Vanta LT] 1043 0200 AGP-V3800 Combat SDRAM 1043 0201 AGP-V3800 Combat 1048 0c20 TNT2 Vanta 1048 0c21 TNT2 Vanta + 1048 0c25 TNT2 Vanta 16MB 1092 6820 Viper V730 1102 1031 CT6938 VANTA 8MB 1102 1034 CT6894 VANTA 16MB 14af 5008 Maxi Gamer Phoenix 2 - 002d NV5M64 [RIVA TNT2 Model 64/Model 64 Pro] + 002d NV5 [Riva TNT2 Model 64 / Model 64 Pro] 1043 0200 AGP-V3800M 1043 0201 AGP-V3800M 1048 0c3a Erazor III LT 1048 0c3b Erazor III LT + 107d 2137 WinFast 3D S325 10de 0006 RIVA TNT2 Model 64/Model 64 Pro 10de 001e M64 AGP4x 1102 1023 CT6892 RIVA TNT2 Value 1102 1024 CT6932 RIVA TNT2 Value 32Mb 1102 102c CT6931 RIVA TNT2 Value [Jumper] + 1102 1030 CT6931 RIVA TNT2 Value +# S26361-D1243-V116 + 110a 006f GM1000-16 +# S26361-D1243-V216 + 110a 0081 GM1000-16 1462 8808 MSI-8808 + 14af 5620 Gamer Cougar Video Edition 1554 1041 Pixelview RIVA TNT2 M64 1569 002d Palit Microsystems Daytona TNT2 M64 - 002e NV6 [Vanta] - 002f NV6 [Vanta] 0034 MCP04 SMBus 0035 MCP04 IDE 0036 MCP04 Serial ATA Controller @@ -5699,19 +7762,21 @@ 0040 NV40 [GeForce 6800 Ultra] 0041 NV40 [GeForce 6800] 1043 817b V9999 Gamer Edition - 0042 NV40.2 [GeForce 6800 LE] - 0043 NV40.3 [GeForce 6800 XE] + 107d 2992 WinFast A400 + 1458 310f Geforce 6800 GV-N6812 + 0042 NV40 [GeForce 6800 LE] + 107d 299b WinFast A400 LE + 0043 NV40 [GeForce 6800 XE] 0044 NV40 [GeForce 6800 XT] 0045 NV40 [GeForce 6800 GT] - 0046 NV45 [GeForce 6800 GT] + 1043 817d V9999GT + 1458 3140 GV-N68T256D 0047 NV40 [GeForce 6800 GS] 1682 2109 GeForce 6800 GS 0048 NV40 [GeForce 6800 XT] - 0049 NV40GL - 004d NV40GL [Quadro FX 4000] 004e NV40GL [Quadro FX 4000] 0050 CK804 ISA Bridge - 1043 815a K8N4-E or A8N-E Mainboard + 1043 815a K8N4/A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1458 0c11 GA-K8N Ultra-9 Mainboard 1462 7100 MSI K8N Diamond @@ -5722,7 +7787,7 @@ 1028 0225 PowerEdge T105 ISA Bridge 0052 CK804 SMBus 1028 0225 PowerEdge T105 SMBus - 1043 815a K8N4-E or A8N-E Mainboard + 1043 815a K8N4/A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1458 0c11 GA-K8N Ultra-9 Mainboard 1462 7100 MSI K8N Diamond @@ -5730,7 +7795,7 @@ 147b 1c1a KN8-Ultra Mainboard 1565 3402 NF4 AM2L Mainboard 0053 CK804 IDE - 1043 815a K8N4-E or A8N-E Mainboard + 1043 815a K8N4/A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1458 5002 GA-K8N Ultra-9 Mainboard 1462 7100 MSI K8N Diamond @@ -5739,7 +7804,7 @@ 1565 3402 NF4 AM2L Mainboard 0054 CK804 Serial ATA Controller 1028 0225 PowerEdge T105 Serial ATA - 1043 815a A8N-E Mainboard + 1043 815a A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1458 b003 GA-K8N Ultra-9 Mainboard 1462 7100 MSI K8N Diamond @@ -5748,7 +7813,7 @@ 1565 5401 NF4 AM2L Mainboard 0055 CK804 Serial ATA Controller 1028 0225 PowerEdge T105 Serial ATA - 1043 815a K8N4-E or A8N-E Mainboard + 1043 815a K8N4/A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1458 b003 GA-K8N Ultra-9 Mainboard 1462 7125 K8N Neo4-F mainboard @@ -5756,7 +7821,7 @@ 1565 5401 NF4 AM2L Mainboard 0056 CK804 Ethernet Controller 0057 CK804 Ethernet Controller - 1043 8141 K8N4-E or A8N-E Mainboard + 1043 8141 K8N4/A8N Series Mainboard 10de cb84 NF4 Lanparty 10f1 2865 Tomcat K8E (S2865) 1458 e000 GA-K8N Ultra-9 Mainboard @@ -5766,14 +7831,14 @@ 1565 2501 NF4 AM2L Mainboard 0058 CK804 AC'97 Modem 0059 CK804 AC'97 Audio Controller - 1043 812a K8N4-E or A8N-E Mainboard + 1043 812a K8N4/A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1462 7585 K8N Neo4-F mainboard 147b 1c1a KN8-Ultra Mainboard 1565 8211 NF4 AM2L Mainboard 005a CK804 USB Controller 1028 0225 PowerEdge T105 onboard USB - 1043 815a K8N4-E or A8N-E Mainboard + 1043 815a K8N4/A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1458 5004 GA-K8N Ultra-9 Mainboard 1462 7100 MSI K8N Diamond @@ -5782,7 +7847,7 @@ 1565 3402 NF4 AM2L Mainboard 005b CK804 USB Controller 1028 0225 PowerEdge T105 onboard USB - 1043 815a K8N4-E or A8N-E Mainboard + 1043 815a K8N4/A8N Series Mainboard 10f1 2865 Tomcat K8E (S2865) 1458 5004 GA-K8N Ultra-9 Mainboard 1462 7100 MSI K8N Diamond @@ -5793,7 +7858,7 @@ 005d CK804 PCIE Bridge 005e CK804 Memory Controller 1028 0225 PowerEdge T105 Memory Controller - 1043 815a A8N-E Mainboard + 1043 815a A8N Series Mainboard 10de 005e ECS Elitegroup NFORCE3-A939 motherboard. 10f1 2865 Tomcat K8E (S2865) 10f1 2891 Thunder K8SRE Mainboard @@ -5854,21 +7919,26 @@ 0092 G70 [GeForce 7800 GT] 0093 G70 [GeForce 7800 GS] 0095 G70 [GeForce 7800 SLI] - 0098 G70 [GeForce Go 7800] - 0099 G70 [GeForce Go 7800 GTX] + 0097 G70 [GeForce GTS 250] + 0098 G70M [GeForce Go 7800] + 0099 G70M [GeForce Go 7800 GTX] 009d G70GL [Quadro FX 4500] 00a0 NV5 [Aladdin TNT2] 14af 5810 Maxi Gamer Xentor 00c0 NV41 [GeForce 6800 GS] - 00c1 NV41.1 [GeForce 6800] - 00c2 NV41.2 [GeForce 6800 LE] - 00c3 NV42 [GeForce 6800 XT] - 00c8 NV41.8 [GeForce Go 6800] - 00c9 NV41.9 [GeForce Go 6800 Ultra] - 00cc NV41 [Quadro FX Go1400] - 00cd NV41 [Quadro FX 3450/4000 SDI] - 10de 029b wx4300 Workstation + 00c1 NV41 [GeForce 6800] + 00c2 NV41 [GeForce 6800 LE] + 00c3 NV41 [GeForce 6800 XT] + 00c5 NV41 + 00c6 NV41 + 00c7 NV41 + 00c8 NV41M [GeForce Go 6800] + 00c9 NV41M [GeForce Go 6800 Ultra] + 00cc NV41GLM [Quadro FX Go1400] + 00cd NV42GL [Quadro FX 3450/4000 SDI] + 10de 029b Quadro FX 3450 00ce NV41GL [Quadro FX 1400] + 00cf NV41 00d0 nForce3 LPC Bridge 00d1 nForce3 Host Bridge 00d2 nForce3 AGP Bridge @@ -5935,7 +8005,6 @@ 147b 1c0b NF8 Mainboard 00ed nForce3 250Gb PCI-to-PCI Bridge 00ee nForce3 Serial ATA Controller 2 - 00f0 NV40 [GeForce 6800 Ultra] 00f1 NV43 [GeForce 6600 GT] 1043 81a6 N6600GT TD 128M AGP 1043 81c6 N6600GT TD 128M AGP @@ -5947,15 +8016,15 @@ 1682 211c GeForce 6600 256MB DDR DUAL DVI TV 00f3 NV43 [GeForce 6200] 00f4 NV43 [GeForce 6600 LE] - 00f5 G70 [GeForce 7800 GS] - 00f6 NV43 [GeForce 6800 GS] + 00f5 G71 [GeForce 7800 GS] + 00f6 NV43 [GeForce 6800 GS/XT] 1682 217e XFX GeForce 6800 XTreme 256MB DDR3 AGP - 00f8 NV45GL [Quadro FX 3400/4400] - 00f9 NV45 [GeForce 6800 GTO] + 00f8 NV40GL [Quadro FX 3400/4400] + 00f9 NV40 [GeForce 6800 GT/GTO/Ultra] 10de 00f9 NV40 [GeForce 6800 GT] 1682 2120 GEFORCE 6800 GT PCI-E 00fa NV36 [GeForce PCX 5750] - 00fb NV35 [GeForce PCX 5900] + 00fb NV38 [GeForce PCX 5900] 00fc NV37GL [Quadro FX 330/GeForce PCX 5300] 00fd NV37GL [Quadro PCI-E Series] 00fe NV38GL [Quadro FX 1300] @@ -5970,13 +8039,13 @@ 1048 0c48 Synergy Force 1102 102d CT6941 GeForce 256 14af 5022 3D Prophet SE - 0101 NV10DDR [GeForce 256 DDR] + 0101 NV10 [GeForce 256 DDR] 1043 0202 AGP-V6800 DDR 1043 400a AGP-V6800 DDR SGRAM 1043 400b AGP-V6800 DDR SDRAM 1048 0c42 Erazor X 107d 2822 WinFast GeForce 256 - 1102 102e CT6971 GeForce 256 DDR + 1102 102e CT6970/CT6971 14af 5021 3D Prophet DDR-DVI 0103 NV10GL [Quadro] 1048 0c40 GLoria II-64 @@ -5994,81 +8063,99 @@ 1048 0c64 Gladiac 511TV-OUT 64MB 1048 0c65 Gladiac 511TWIN 1048 0c66 Gladiac 311 + 10b0 0001 GeForce2 MX Jumbo TV 10de 0091 Dell OEM GeForce 2 MX 400 10de 00a1 Apple OEM GeForce2 MX + 1462 8523 MS-8852 1462 8817 MSI GeForce2 MX400 Pro32S [MS-8817] 14af 7102 3D Prophet II MX 14af 7103 3D Prophet II MX Dual-Display 1545 0023 Xtasy Rev. B2 - 0111 NV11DDR [GeForce2 MX200] - 0112 NV11 [GeForce2 Go] + 1554 1081 MVGA-NVG11AM(400) + 0111 NV11 [GeForce2 MX200] + 0112 NV11M [GeForce2 Go] 0113 NV11GL [Quadro2 MXR/EX/Go] 0140 NV43 [GeForce 6600 GT] + 1458 3125 GV-NX66T128D + 1458 3126 GV-NX66T256DE + 1462 8939 MS-8983 0141 NV43 [GeForce 6600] 1043 81b0 EN6600 Silencer + 107d 593a LR2A22 128MB TV OUT + 107d 597b WINFAST PX6600 1458 3124 GV-NX66128DP Turbo Force Edition 0142 NV43 [GeForce 6600 LE] 0143 NV43 [GeForce 6600 VE] - 0144 NV43 [GeForce Go 6600] + 0144 NV43M [GeForce Go 6600] 0145 NV43 [GeForce 6610 XL] - 0146 NV43 [GeForce Go 6600TE/6200TE] + 0146 NV43M [GeForce Go6200 TE / 6600 TE] 0147 NV43 [GeForce 6700 XL] - 0148 NV43 [GeForce Go 6600] - 0149 NV43 [GeForce Go 6600 GT] + 0148 NV43M [GeForce Go 6600] + 0149 NV43M [GeForce Go 6600 GT] 014a NV43 [Quadro NVS 440] - 014c NV43 [Quadro FX 540 MXM] + 014b NV43 014d NV43GL [Quadro FX 550] 014e NV43GL [Quadro FX 540] 014f NV43 [GeForce 6200] 0150 NV15 [GeForce2 GTS/Pro] 1043 4016 V7700 AGP Video Card + 1043 402a AGP-V7700 1048 0c50 Gladiac 1048 0c52 Gladiac-64 107d 2840 WinFast GeForce2 GTS with TV output 107d 2842 WinFast GeForce 2 Pro 10de 002e GeForce2 GTS + 1462 815a MS-8815 1462 8831 Creative GeForce2 Pro - 0151 NV15DDR [GeForce2 Ti] + 0151 NV15 [GeForce2 Ti] 1043 405f V7700Ti 1462 5506 Creative 3D Blaster GeForce2 Titanium - 0152 NV15BR [GeForce2 Ultra, Bladerunner] + 1462 8364 MS-8836 + 0152 NV15 [GeForce2 Ultra] 1048 0c56 GLADIAC Ultra 0153 NV15GL [Quadro2 Pro] 0160 NV44 [GeForce 6500] - 0161 NV44 [GeForce 6200 TurboCache(TM)] - 0162 NV44 [GeForce 6200SE TurboCache (TM)] + 0161 NV44 [GeForce 6200 TurboCache] + 0162 NV44 [GeForce 6200 SE TurboCache] 0163 NV44 [GeForce 6200 LE] - 0164 NV44 [GeForce Go 6200] + 0164 NV44M [GeForce Go 6200] 0165 NV44 [Quadro NVS 285] - 0166 NV44 [GeForce Go 6400] - 0167 NV44 [GeForce Go 6200] - 0168 NV44 [GeForce Go 6400] + 0166 NV44M [GeForce Go 6400] + 0167 NV44M [GeForce Go 6200] + 0168 NV44M [GeForce Go 6400] 0169 NV44 [GeForce 6250] 016a NV44 [GeForce 7100 GS] + 016d NV44 + 016e NV44 + 016f NV44 0170 NV17 [GeForce4 MX 460] + 1462 8630 MS-8863 0171 NV17 [GeForce4 MX 440] 10b0 0002 Gainward Pro/600 TV 10de 0008 Apple OEM GeForce4 MX 440 1462 8661 G4MX440-VTP 1462 8730 MX440SES-T (MS-8873) + 1462 8743 MS-8874 1462 8852 GeForce4 MX440 PCI 147b 8f00 Abit Siluro GeForce4MX440 0172 NV17 [GeForce4 MX 420] + 1462 8730 MS-8873 + 1462 8784 MS-8878 0173 NV17 [GeForce4 MX 440-SE] - 0174 NV17 [GeForce4 440 Go] - 0175 NV17 [GeForce4 420 Go] - 0176 NV17 [GeForce4 420 Go 32M] + 0174 NV17M [GeForce4 440 Go] + 0175 NV17M [GeForce4 420 Go] + 0176 NV17M [GeForce4 420 Go 32M] 103c 08b0 tc1100 tablet 144d c005 X10 Laptop 4c53 1090 Cx9 / Vx9 mainboard - 0177 NV17 [GeForce4 460 Go] + 0177 NV17M [GeForce4 460 Go] 0178 NV17GL [Quadro4 550 XGL] - 0179 NV17 [GeForce4 440 Go 64M] + 0179 NV17M [GeForce4 440 Go 64M] 10de 0179 GeForce4 MX (Mac) 017a NV17GL [Quadro NVS] 017b NV17GL [Quadro4 550 XGL] 017c NV17GL [Quadro4 500 GoGL] - 017d NV17 [GeForce4 410 Go 16M] + 017f NV17 0181 NV18 [GeForce4 MX 440 AGP 8x] 1043 8063 GeForce4 MX 440 AGP 8X 1043 806f V9180 Magic @@ -6089,14 +8176,16 @@ 018b NV18GL [Quadro4 380 XGL] 018c NV18GL [Quadro NVS 50 PCI] 018d NV18M [GeForce4 448 Go] + 018f NV18 + 0190 G80 [GeForce 8800 GTS / 8800 GTX] 0191 G80 [GeForce 8800 GTX] + 0192 G80 [GeForce 8800 GTS] 0193 G80 [GeForce 8800 GTS] 107d 20bd WinFast PX 8800 GTS TDH 0194 G80 [GeForce 8800 Ultra] -# Found in GPU server Tesla D870 and S870 - 0197 G80 [Tesla C870] - 019d G80 [Quadro FX 5600] - 019e G80 [Quadro FX 4600] + 0197 G80GL [Tesla C870] + 019d G80GL [Quadro FX 5600] + 019e G80GL [Quadro FX 4600] 01a0 nForce 220/420 NV11 [GeForce2 MX] 01a4 nForce CPU bridge 01ab nForce 420 Memory Controller (DDR) @@ -6114,9 +8203,14 @@ 01c3 nForce Ethernet Controller 01d0 G72 [GeForce 7350 LE] 01d1 G72 [GeForce 7300 LE] + 107d 5efa WinFast PX7300LE-TD128 + 107d 5efb WinFast PX7300LE-TD256 1462 0345 7300LE PCI Express Graphics Adapter 01d2 G72 [GeForce 7550 LE] - 01d3 G72 [GeForce 7300 SE/7200 GS] + 01d3 G72 [GeForce 7200 GS / 7300 SE] + 1043 8203 EN7300SE + 1043 8250 EN7200GS + 01d5 G72 01d6 G72M [GeForce Go 7200] 01d7 G72M [Quadro NVS 110M/GeForce Go 7300] 01d8 G72M [GeForce Go 7400] @@ -6124,11 +8218,11 @@ 01d9 G72M [GeForce Go 7450] 01da G72M [Quadro NVS 110M] 01db G72M [Quadro NVS 120M] - 01dc G72GL [Quadro FX 350M] + 01dc G72GLM [Quadro FX 350M] 01dd G72 [GeForce 7500 LE] 01de G72GL [Quadro FX 350] 10de 01dc Quadro FX Go350M - 01df G71 [GeForce 7300 GS] + 01df G72 [GeForce 7300 GS] 01e0 nForce2 IGP2 147b 1c09 NV7 Motherboard 01e8 nForce2 AGP @@ -6145,7 +8239,7 @@ a0a0 03b9 UK79G-1394 motherboard 01ef nForce2 Memory Controller 5 a0a0 03b9 UK79G-1394 motherboard - 01f0 NV18 [GeForce4 MX - nForce GPU] + 01f0 C17 [GeForce4 MX IGP] a0a0 03b5 UK79G-1394 motherboard 0200 NV20 [GeForce3] 1043 402f AGP-V8200 DDR @@ -6154,7 +8248,7 @@ 0202 NV20 [GeForce3 Ti 500] 1043 405b V8200 T5 1545 002f Xtasy 6964 - 0203 NV20DCC [Quadro DCC] + 0203 NV20GL [Quadro DCC] 0211 NV48 [GeForce 6800] 0212 NV48 [GeForce 6800 LE] 0215 NV48 [GeForce 6800 GT] @@ -6163,6 +8257,7 @@ 1043 81e1 N6200/TD/256M/A 3842 a341 256A8N341DX 0222 NV44 [GeForce 6200 A-LE] + 0224 NV44 0240 C51PV [GeForce 6150] 1043 81cd A8N-VM CSM 1462 7207 K8NGM2 series @@ -6287,7 +8382,7 @@ 0280 NV28 [GeForce4 Ti 4800] 0281 NV28 [GeForce4 Ti 4200 AGP 8x] 0282 NV28 [GeForce4 Ti 4800 SE] - 0286 NV28 [GeForce4 Ti 4200 Go AGP 8x] + 0286 NV28M [GeForce4 Ti 4200 Go AGP 8x] 0288 NV28GL [Quadro4 980 XGL] 0289 NV28GL [Quadro4 780 XGL] 028c NV28GLM [Quadro4 Go700] @@ -6301,15 +8396,16 @@ 1043 8225 GeForce 7950 GT 107d 2a68 WinFast PX7950GT TDH 1462 0663 NX7950GT-VT2D512EZ-HD - 0297 G71 [GeForce Go 7950 GTX] - 0298 G71 [GeForce Go 7900 GS] - 0299 G71 [GeForce Go 7900 GTX] - 029a G71 [Quadro FX 2500M] - 029b G71 [Quadro FX 1500M] - 029c G71 [Quadro FX 5500] + 0297 G71M [GeForce Go 7950 GTX] + 0298 G71M [GeForce Go 7900 GS] + 0299 G71M [GeForce Go 7900 GTX] + 029a G71GLM [Quadro FX 2500M] + 029b G71GLM [Quadro FX 1500M] + 029c G71GL [Quadro FX 5500] 029d G71GL [Quadro FX 3500] - 029e G71 [Quadro FX 1500] - 029f G70 [Quadro FX 4500 X2] + 1028 019b G71GLM [Quadro FX 3500M] + 029e G71GL [Quadro FX 1500] + 029f G71GL [Quadro FX 4500 X2] # Xbox Graphics Processing Unit (Integrated). GeForce3 derivative (NV20 < NV2A < NV25). 02a0 NV2A [XGPU] 02a5 MCPX CPU Bridge @@ -6343,6 +8439,7 @@ 1458 5000 GA-M55plus-S3G 1462 7207 K8NGM2 series 02f9 C51 Memory Controller 4 + 103c 2a34 Pavilion a1677c 103c 30b7 Presario V6133CL 1043 81cd A8N-VM CSM Mainboard 1458 5000 GA-M55plus-S3G @@ -6377,22 +8474,19 @@ 0309 NV30GL [Quadro FX 1000] 0311 NV31 [GeForce FX 5600 Ultra] 0312 NV31 [GeForce FX 5600] - 0313 NV31 0314 NV31 [GeForce FX 5600XT] 1043 814a V9560XT/TD 0316 NV31M - 0317 NV31M Pro + 0318 NV31GL 031a NV31M [GeForce FX Go5600] 031b NV31M [GeForce FX Go5650] - 031c NV31 [Quadro FX Go700] - 031d NV31GLM - 031e NV31GLM Pro - 031f NV31GLM Pro + 031c NV31GLM [Quadro FX Go700] 0320 NV34 [GeForce FX 5200] 0321 NV34 [GeForce FX 5200 Ultra] 0322 NV34 [GeForce FX 5200] 1043 02fb V9250 Magic 1043 8180 V9520-X/TD/128M + 107d 2967 WinFast A340T 128MB 1462 9110 MS-8911 (FX5200-TD128) 1462 9171 MS-8917 (FX5200-T128) 1462 9360 MS-8936 (FX5200-T128) @@ -6412,9 +8506,10 @@ 10de 0010 Powerbook G4 032a NV34GL [Quadro NVS 280 PCI] 032b NV34GL [Quadro FX 500/600 PCI] - 032c NV34GLM [GeForce FX Go 5300] - 032d NV34 [GeForce FX Go5100] - 032f NV34GL + 032c NV34M [GeForce FX Go5300 / Go5350] + 032d NV34M [GeForce FX Go5100] + 032e NV34 + 032f NV34 [GeForce FX 5200] 0330 NV35 [GeForce FX 5900 Ultra] 1043 8137 V9950 Ultra / 256 MB 0331 NV35 [GeForce FX 5900] @@ -6425,20 +8520,17 @@ 1462 9373 FX5900ZT-VTD128 (MS-8937) 0338 NV35GL [Quadro FX 3000] 033f NV35GL [Quadro FX 700] - 0341 NV36.1 [GeForce FX 5700 Ultra] + 0341 NV36 [GeForce FX 5700 Ultra] 1462 9380 MS-8938 (FX5700U-TD128) - 0342 NV36.2 [GeForce FX 5700] + 0342 NV36 [GeForce FX 5700] 0343 NV36 [GeForce FX 5700LE] - 0344 NV36.4 [GeForce FX 5700VE] - 0345 NV36.5 - 0347 NV36 [GeForce FX Go5700] + 0344 NV36 [GeForce FX 5700VE] + 0347 NV36M [GeForce FX Go5700] 103c 006a NX9500 - 0348 NV36 [GeForce FX Go5700] - 0349 NV36M Pro - 034b NV36MAP + 0348 NV36M [GeForce FX Go5700] 034c NV36 [Quadro FX Go1000] + 034d NV36 034e NV36GL [Quadro FX 1100] - 034f NV36GL 0360 MCP55 LPC Bridge 0361 MCP55 LPC Bridge 1028 0221 PowerEdge R805 MCP55 LPC Bridge @@ -6450,7 +8542,7 @@ 0365 MCP55 LPC Bridge 0366 MCP55 LPC Bridge 0367 MCP55 LPC Bridge - 0368 MCP55 SMBus + 0368 MCP55 SMBus Controller 1028 020c PowerEdge M605 MCP55 SMBus 1028 0221 PowerEdge R805 MCP55 SMBus 147b 1c24 KN9 series mainboard @@ -6488,6 +8580,7 @@ 0390 G73 [GeForce 7650 GS] 0391 G73 [GeForce 7600 GT] 1458 3427 GV-NX76T128D-RH + 1462 0452 NX7600GT-VT2D256E 0392 G73 [GeForce 7600 GS] 1462 0622 NX7600GS-T2D256EH 0393 G73 [GeForce 7300 GT] @@ -6495,15 +8588,18 @@ 1462 0412 NX7300GT-TD256EH 0394 G73 [GeForce 7600 LE] 0395 G73 [GeForce 7300 GT] - 0397 G73 [GeForce Go 7700] - 0398 G73 [GeForce Go 7600] + 0396 G73 + 0397 G73M [GeForce Go 7700] + 0398 G73M [GeForce Go 7600] 1025 006c Acer 9814 WKMI - 0399 G73 [GeForce Go 7600 GT] + 0399 G73M [GeForce Go 7600 GT] 039a G73M [Quadro NVS 300M] - 039b G73 [GeForce Go 7900 SE] - 039c G73 [Quadro FX 550M] + 039b G73M [GeForce Go 7900 SE] + 039c G73GLM [Quadro FX 550M] 10de 039c Quadro FX 560M + 039d G73 039e G73GL [Quadro FX 560] + 039f G73 03a0 C55 Host Bridge 03a1 C55 Host Bridge 03a2 C55 Host Bridge @@ -6602,75 +8698,93 @@ 03f7 MCP61 SATA Controller 0400 G84 [GeForce 8600 GTS] 1043 8241 EN8600GTS - 0401 G84 [GeForce 8600GT] + 0401 G84 [GeForce 8600 GT] 0402 G84 [GeForce 8600 GT] 1458 3455 GV-NX86T512H 1462 0910 NX8600GT-T2D256EZ 0403 G84 [GeForce 8600 GS] 0404 G84 [GeForce 8400 GS] 1462 1230 NX8400GS-TD256E - 0405 G84 [GeForce 9500M GS] + 0405 G84M [GeForce 9500M GS] 0406 G84 [GeForce 8300 GS] - 0407 G84 [GeForce 8600M GT] - 0408 G84 [GeForce 9650M GS] - 0409 G84 [GeForce 8700M GT] - 040a G84 [Quadro FX 370] - 040b G84M [Quadro NVS 320M] - 040c G84M [Quadro FX 570M] + 0407 G84M [GeForce 8600M GT] + 0408 G84M [GeForce 9650M GS] + 0409 G84M [GeForce 8700M GT] + 040a G84GL [Quadro FX 370] + 040b G84GLM [Quadro NVS 320M] + 040c G84GLM [Quadro FX 570M] 17aa 20d9 ThinkPad T61p - 040d G84 [Quadro FX 1600M] - 040e G84 [Quadro FX 570] - 040f G84 [Quadro FX 1700] + 040d G84GLM [Quadro FX 1600M] + 040e G84GL [Quadro FX 570] + 040f G84GL [Quadro FX 1700] 0410 G92 [GeForce GT 330] + 0414 G92 [GeForce 9800 GT] 0420 G86 [GeForce 8400 SE] 0421 G86 [GeForce 8500 GT] 1462 0960 NX8500GT-TD512EH/M2 0422 G86 [GeForce 8400 GS] 0423 G86 [GeForce 8300 GS] 0424 G86 [GeForce 8400 GS] - 0425 G86 [GeForce 8600M GS] + 0425 G86M [GeForce 8600M GS] 1025 0121 Aspire 5920G - 0426 G86 [GeForce 8400M GT] - 0427 G86 [GeForce 8400M GS] + 0426 G86M [GeForce 8400M GT] + 0427 G86M [GeForce 8400M GS] 103c 30cc Pavilion dv6700 - 0428 G86 [GeForce 8400M G] - 0429 G86 [Quadro NVS 140M] + 103c 30cf Pavilion dv9668eg Laptop + 0428 G86M [GeForce 8400M G] + 0429 G86M [Quadro NVS 140M] 17aa 20d8 ThinkPad T61 042a G86M [Quadro NVS 130M] 042b G86M [Quadro NVS 135M] 042c G86 [GeForce 9400 GT] - 042d G86M [Quadro FX 360M] - 042e G86 [GeForce 9300M G] + 042d G86GLM [Quadro FX 360M] + 042e G86M [GeForce 9300M G] 042f G86 [Quadro NVS 290] 0440 MCP65 LPC Bridge 0441 MCP65 LPC Bridge 0442 MCP65 LPC Bridge + 103c 30cf Pavilion dv9668eg Laptop 0443 MCP65 LPC Bridge 0444 MCP65 Memory Controller + 103c 30cf Pavilion dv9668eg Laptop 0445 MCP65 Memory Controller 0446 MCP65 SMBus + 103c 30cf Pavilion dv9668eg Laptop 0447 MCP65 SMU + 103c 30cf Pavilion dv9668eg Laptop 0448 MCP65 IDE + 103c 30cf Pavilion dv9668eg Laptop 0449 MCP65 PCI bridge + 10de cb84 HP Pavilion dv9668eg Laptop 044a MCP65 High Definition Audio + 103c 30cf Pavilion dv9668eg Laptop 044b MCP65 High Definition Audio 044c MCP65 AHCI Controller 044d MCP65 AHCI Controller 044e MCP65 AHCI Controller 044f MCP65 AHCI Controller 0450 MCP65 Ethernet + 103c 30cf Pavilion dv9668eg Laptop 0451 MCP65 Ethernet 0452 MCP65 Ethernet 0453 MCP65 Ethernet - 0454 MCP65 USB Controller - 0455 MCP65 USB Controller + 0454 MCP65 USB 1.1 OHCI Controller + 103c 30cf Pavilion dv9668eg Laptop + 0455 MCP65 USB 2.0 EHCI Controller + 103c 30cf Pavilion dv9668eg Laptop 0456 MCP65 USB Controller 0457 MCP65 USB Controller 0458 MCP65 PCI Express bridge + 10de 0000 MCP65 PCI Express bridge 0459 MCP65 PCI Express bridge + 10de 0000 MCP65 PCI Express bridge 045a MCP65 PCI Express bridge + 10de 0000 MCP65 PCI Express bridge + 045b MCP65 PCI Express bridge + 10de 0000 MCP65 PCI Express bridge 045c MCP65 SATA Controller 045d MCP65 SATA Controller + 103c 30cf Pavilion dv9668eg Laptop 045e MCP65 SATA Controller 045f MCP65 SATA Controller 0531 C67 [GeForce 7150M / nForce 630M] @@ -6725,55 +8839,67 @@ 1849 0569 K10N78FullHD-hSLI R3.0 PCI Express Bridge 056a MCP73 [nForce 630i] USB 2.0 Controller (EHCI) 1019 297a MCP73PVT-SM - 056c MCP73 IDE + 147b 1c3e I-N73V motherboard + 056c MCP73 IDE Controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD 056d MCP73 PCI Express bridge 1019 297a MCP73PVT-SM + 10de cb73 MCP73 PCI Bridge 056e MCP73 PCI Express bridge 1019 297a MCP73PVT-SM + 10de 0000 MCP73 PCIe x16 port 056f MCP73 PCI Express bridge 1019 297a MCP73PVT-SM + 10de 0000 MCP73 PCIe x1 port 05b1 NF200 PCIe 2.0 switch 05b8 NF200 PCIe 2.0 switch for GTX 295 05be NF200 PCIe 2.0 switch for Quadro Plex S4 / Tesla S870 / Tesla S1070 / Tesla S2050 05e0 GT200b [GeForce GTX 295] 05e1 GT200 [GeForce GTX 280] -# GT200 [GTX 260] or GT200 [GTX 260-216] or GT200b [GTX 260-216] 05e2 GT200 [GeForce GTX 260] 05e3 GT200b [GeForce GTX 285] + 1682 2490 GX-285N-ZDF 05e6 GT200b [GeForce GTX 275] -# Found in GPU server Tesla S1070 - 05e7 GT200 [Tesla C1060] + 05e7 GT200GL [Tesla C1060 / M1060] + 10de 0595 Tesla T10 Processor + 10de 068f Tesla T10 Processor + 10de 0697 Tesla M1060 + 10de 0714 Tesla M1060 + 10de 0743 Tesla M1060 05ea GT200 [GeForce GTX 260] 05eb GT200 [GeForce GTX 295] 05ed GT200GL [Quadro Plex 2200 D2] + 05f1 GT200 [GeForce GTX 280] + 05f2 GT200 [GeForce GTX 260] 05f8 GT200GL [Quadro Plex 2200 S4] 05f9 GT200GL [Quadro CX] 05fd GT200GL [Quadro FX 5800] 05fe GT200GL [Quadro FX 4800] - 05ff GT200GL [NVIDIA Quadro FX 3800] + 05ff GT200GL [Quadro FX 3800] 0600 G92 [GeForce 8800 GTS 512] 0601 G92 [GeForce 9800 GT] 0602 G92 [GeForce 8800 GT] - 0603 G92 [GeForce GT 230] + 0603 G92 [GeForce GT 230 OEM] 0604 G92 [GeForce 9800 GX2] 0605 G92 [GeForce 9800 GT] 0606 G92 [GeForce 8800 GS] 0607 G92 [GeForce GTS 240] - 0608 G92 [GeForce 9800M GTX] - 0609 G92 [GeForce 8800M GTS] - 060a GT200 [GeForce GTX 280M] - 060b G92 [GeForce 9800M GT] - 060c G92 [GeForce 8800M GTX] + 0608 G92M [GeForce 9800M GTX] + 0609 G92M [GeForce 8800M GTS] + 106b 00a7 GeForce 8800 GS + 060a G92M [GeForce GTX 280M] + 060b G92M [GeForce 9800M GT] + 060c G92M [GeForce 8800M GTX] 060d G92 [GeForce 8800 GS] - 060f G92 [GeForce GTX 285M] + 060f G92M [GeForce GTX 285M] 0610 G92 [GeForce 9600 GSO] 1682 2385 GeForce 9600 GSO 768mb 0611 G92 [GeForce 8800 GT] 107d 2ab0 Winfast PX8800 GT PCI-E 19da 1040 ZT-88TES2P-FSP - 0612 G92 [GeForce 9800 GTX] + 0612 G92 [GeForce 9800 GTX / 9800 GTX+] 0613 G92 [GeForce 9800 GTX+] 0614 G92 [GeForce 9800 GT] 107d 2ab3 WinFast PX9800 GT (S-Fanpipe) @@ -6784,15 +8910,17 @@ 3842 1155 GeForce GTS 250 P/N 01G-P3-1155-TR # Overclocked 3842 1156 GeForce GTS 250 P/N 01G-P3-1156-TR - 0617 G92 [GeForce 9800M GTX] - 0618 G92 [GeForce GTX 260M] + 0617 G92M [GeForce 9800M GTX] + 0618 G92M [GeForce GTX 260M] 0619 G92GL [Quadro FX 4700 X2] - 061a G92 [Quadro FX 3700] + 061a G92GL [Quadro FX 3700] 061b G92GL [Quadro VX 200] - 061c G92M [Quadro FX 3600M] - 061d G92 [Quadro FX 2800M] - 061e G92 [Quadro FX 3700M] - 061f G92 [Quadro FX 3800M] + 061c G92GLM [Quadro FX 3600M] + 061d G92GLM [Quadro FX 2800M] + 061e G92GLM [Quadro FX 3700M] + 061f G92GLM [Quadro FX 3800M] + 0620 G94 [GeForce 9800 GT] + 0621 G94 [GeForce GT 230] 0622 G94 [GeForce 9600 GT] 107d 2ac1 WinFast PX9600GT 1024MB 1458 3481 GV-NX96T512HP @@ -6801,72 +8929,116 @@ 0625 G94 [GeForce 9600 GSO 512] 0626 G94 [GeForce GT 130] 0627 G94 [GeForce GT 140] - 0628 G94 [GeForce 9800M GTS] - 062a G94 [GeForce 9700M GTS] - 062b G94 [GeForce 9800M GS] - 062c G94 [GeForce 9800M GTS] + 0628 G94M [GeForce 9800M GTS] + 062a G94M [GeForce 9700M GTS] + 062b G94M [GeForce 9800M GS] + 062c G94M [GeForce 9800M GTS] 062d G94 [GeForce 9600 GT] 062e G94 [GeForce 9600 GT] + 106b 0605 GeForce GT 130 + 062f G94 [GeForce 9800 S] + 0630 G94 [GeForce 9600 GT] 0631 G94M [GeForce GTS 160M] 0632 G94M [GeForce GTS 150M] + 0633 G94 [GeForce GT 220] 0635 G94 [GeForce 9600 GSO] 0637 G94 [GeForce 9600 GT] - 0638 G94 [Quadro FX 1800] - 063a G94M [Quadro FX 2700M] + 0638 G94GL [Quadro FX 1800] + 063a G94GLM [Quadro FX 2700M] + 063f G94 [GeForce 9600 GE] 0640 G96 [GeForce 9500 GT] 0641 G96 [GeForce 9400 GT] + 1682 4009 PV-T94G-ZAFG + 0642 G96 [D9M-10] 0643 G96 [GeForce 9500 GT] 0644 G96 [GeForce 9500 GS] + 174b 9600 Geforce 9500GS 512M DDR2 V/D/HDMI 0645 G96 [GeForce 9500 GS] 0646 G96 [GeForce GT 120] - 0647 G96 [GeForce 9600M GT] - 0648 G96 [GeForce 9600M GS] - 0649 G96 [GeForce 9600M GT] - 064a G96 [GeForce 9700M GT] - 064b G96 [GeForce 9500M G] - 064c G96 [GeForce 9650M GT] - 0651 G96 [GeForce G 110M] - 0652 G96 [GeForce GT 130M] + 0647 G96M [GeForce 9600M GT] + 0648 G96M [GeForce 9600M GS] + 0649 G96M [GeForce 9600M GT] + 1043 202d GeForce GT 220M + 064a G96M [GeForce 9700M GT] + 064b G96M [GeForce 9500M G] + 064c G96M [GeForce 9650M GT] + 064d G96 [GeForce 9600 GT] + 064e G96 [GeForce 9600 GT / 9800 GT] + 0651 G96M [GeForce G 110M] + 0652 G96M [GeForce GT 130M] + 152d 0850 GeForce GT 240M LE 0653 G96M [GeForce GT 120M] - 0654 G96 [GeForce GT 220M] + 0654 G96M [GeForce GT 220M] + 1043 14a2 GeForce GT 320M + 1043 14d2 GeForce GT 320M + 0655 G96 [GeForce GT 120] 0656 G96 [GeForce 9650 S] - 0658 G96 [Quadro FX 380] - 0659 G96 [Quadro FX 580] - 065a G96 [Quadro FX 1700M] + 0658 G96GL [Quadro FX 380] + 0659 G96GL [Quadro FX 580] + 065a G96GLM [Quadro FX 1700M] 065b G96 [GeForce 9400 GT] - 065c G96M [Quadro FX 770M] + 065c G96GLM [Quadro FX 770M] + 065d G96 [GeForce 9500 GA / 9600 GT / GTS 250] + 065f G96 [GeForce G210] 06c0 GF100 [GeForce GTX 480] + 06c4 GF100 [GeForce GTX 465] + 06ca GF100M [GeForce GTX 480M] + 06cb GF100 [GeForce GTX 480] 06cd GF100 [GeForce GTX 470] - 06d1 GF100 [Tesla C2050 / C2070] - 06d2 GF100 [Tesla M2070] + 06d1 GF100GL [Tesla C2050 / C2070] + 10de 0771 Tesla C2050 + 10de 0772 Tesla C2070 + 06d2 GF100GL [Tesla M2070] + 10de 0774 Tesla M2070 + 10de 0830 Tesla M2070 + 10de 0842 Tesla M2070 + 10de 088f Tesla X2070 + 10de 0908 Tesla M2070 06d8 GF100GL [Quadro 6000] 06d9 GF100GL [Quadro 5000] + 06da GF100GLM [Quadro 5000M] + 06dc GF100GL [Quadro 6000] 06dd GF100GL [Quadro 4000] - 06de GF100 [Tesla S2050] - 06df GF100 [Tesla M2070Q] + 06de GF100GL [Tesla T20 Processor] + 10de 0773 Tesla S2050 + 10de 082f Tesla M2050 + 10de 0840 Tesla X2070 + 10de 0842 Tesla M2050 + 10de 0846 Tesla M2050 + 10de 0866 Tesla M2050 + 10de 0907 Tesla M2050 + 10de 091e Tesla M2050 + 06df GF100GL [Tesla M2070-Q] + 10de 084d Tesla M2070-Q + 10de 087f Tesla M2070-Q 06e0 G98 [GeForce 9300 GE] + 107d 5a96 Geforce 9300GE 06e1 G98 [GeForce 9300 GS] 06e2 G98 [GeForce 8400] 06e3 G98 [GeForce 8300 GS] - 06e4 G98 [GeForce 8400 GS] + 06e4 G98 [GeForce 8400 GS Rev. 2] 1458 3475 GV-NX84S256HE [GeForce 8400 GS] - 06e5 G98 [GeForce 9300M GS] + 06e5 G98M [GeForce 9300M GS] 06e6 G98 [GeForce G 100] 06e7 G98 [GeForce 9300 SE] - 06e8 G98 [GeForce 9200M GS] - 06e9 G98 [GeForce 9300M GS] + 06e8 G98M [GeForce 9200M GS] + 103c 360b GeForce 9200M GE + 06e9 G98M [GeForce 9300M GS] 1043 19b2 U6V laptop - 06ea G86M [Quadro NVS 150M] + 06ea G98M [Quadro NVS 150M] 06eb G98M [Quadro NVS 160M] 06ec G98M [GeForce G 105M] + 06ed G98 [GeForce 9600 GT / 9800 GT] + 06ee G98 [GeForce 9600 GT / 9800 GT] 06ef G98M [GeForce G 103M] 06f1 G98M [GeForce G 105M] 06f8 G98 [Quadro NVS 420] - 06f9 G98 [Quadro FX 370 LP] + 06f9 G98GL [Quadro FX 370 LP] 06fa G98 [Quadro NVS 450] - 06fb G98 [Quadro FX 370M] + 06fb G98GLM [Quadro FX 370M] 06fd G98 [Quadro NVS 295] 06ff G98 [HICx16 + Graphics] + 10de 0711 HICx8 + Graphics 0751 MCP78S [GeForce 8200] Memory Controller 103c 2a9e Pavilion p6310f 1043 82e8 M3N72-D @@ -6955,49 +9127,65 @@ 07c1 MCP73 Host Bridge 1019 297a MCP73PVT-SM 07c2 MCP73 Host Bridge + 07c3 MCP73 Host Bridge + 147b 1c3e I-N73V motherboard 07c5 MCP73 Host Bridge 07c8 MCP73 Memory Controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07cb nForce 630i memory controller + 07cb nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07cd nForce 630i memory controller + 07cd nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07ce nForce 630i memory controller + 07ce nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07cf nForce 630i memory controller + 07cf nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07d0 nForce 630i memory controller + 07d0 nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07d1 nForce 630i memory controller + 07d1 nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07d2 nForce 630i memory controller + 07d2 nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07d3 nForce 630i memory controller + 07d3 nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD - 07d6 nForce 630i memory controller + 07d6 nForce 610i/630i memory controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD 07d7 MCP73 LPC Bridge 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD 07d8 MCP73 SMBus 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD 07d9 MCP73 Memory Controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD 07da MCP73 Co-processor 1afa 7150 JW-IN7150-HD 07dc MCP73 Ethernet + 147b 1c3e I-N73V motherboard 07dd MCP73 Ethernet 07de MCP73 Ethernet 07df MCP73 Ethernet @@ -7007,17 +9195,24 @@ 1019 297a MCP73PVT-SM 07e2 C73 [GeForce 7050 / nForce 630i] 07e3 C73 [GeForce 7050 / nForce 610i] + 147b 1c3e I-N73V motherboard 07e5 C73 [GeForce 7100 / nForce 620i] - 07f0 MCP73 IDE + 07f0 MCP73 SATA Controller (IDE mode) + 147b 1c3e I-N73V motherboard 07f4 GeForce 7100/nForce 630i SATA 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 07f8 MCP73 SATA RAID Controller + 147b 1c3e I-N73V motherboard 07fc MCP73 High Definition Audio 1019 297a MCP73PVT-SM 10de 07fc MCP73 High Definition Audio - 07fe GeForce 7100/nForce 630i USB + 147b 1c3e I-N73V motherboard + 07fe MCP73 OHCI USB 1.1 Controller 1019 297a MCP73PVT-SM + 147b 1c3e I-N73V motherboard 1afa 7150 JW-IN7150-HD + 0840 C77 [GeForce 8200M] 0844 C77 [GeForce 9100M G] 0845 C77 [GeForce 8200M G] 0846 C77 [GeForce 9200] @@ -7029,7 +9224,7 @@ 1849 0849 K10N78FullHD-hSLI R3.0 GeForce 8200 084a C77 [nForce 730a] 084b C77 [GeForce 8200] - 084c C77 [nForce 780a SLI] + 084c C77 [nForce 780a/980a SLI] 084d C77 [nForce 750a SLI] 1043 82e8 M3N72-D mGPU 084f C77 [GeForce 8100 / nForce 720a] @@ -7037,20 +9232,31 @@ 0861 C79 [GeForce 9400] 0862 C79 [GeForce 9400M G] 0863 C79 [GeForce 9400M] + 106b 00aa MacBook5,1 0864 C79 [GeForce 9300] - 0865 C79 [GeForce 9300] + 0865 C79 [GeForce 9300/ION] 0866 C79 [GeForce 9400M G] + 106b 00b1 GeForce 9400M 0867 C79 [GeForce 9400] + 106b 00ad iMac 9,1 0868 C79 [nForce 760i SLI] + 0869 MCP7A [GeForce 9400] 086a C79 [GeForce 9400] 086c C79 [GeForce 9300 / nForce 730i] 086d C79 [GeForce 9200] 086e C79 [GeForce 9100M G] - 086f C79 [GeForce 9200M G] + 086f MCP79 [GeForce 8200M G] 0870 C79 [GeForce 9400M] 0871 C79 [GeForce 9200] 0872 C79 [GeForce G102M] + 1043 19b4 GeForce G102M + 1043 1aa2 GeForce G102M + 1043 1c02 GeForce G102M + 1043 1c42 GeForce G205M 0873 C79 [GeForce G102M] + 1043 19b4 GeForce G102M + 1043 1c12 GeForce G102M + 1043 1c52 GeForce G205M 0874 C79 [ION] 0876 ION VGA [GeForce 9400M] 087a C79 [GeForce 9400] @@ -7058,47 +9264,100 @@ 19da a123 IONITX-F-E 087e ION LE VGA 087f ION LE VGA + 08a0 MCP89 [GeForce 320M] + 08a2 MCP89 [GeForce 320M] 08a3 MCP89 [GeForce 320M] 08a4 MCP89 [GeForce 320M] + 08a5 MCP89 [GeForce 320M] 0a20 GT216 [GeForce GT 220] 1043 8311 ENGT220/DI/1GD3(LP)/V2 - 0a23 GT218 [GeForce 210] - 0a28 GT216 [GeForce GT 230M] - 0a29 GT216 [GeForce GT 330M] - 0a2a GT216 [GeForce GT 230M] - 0a2b GT216 [GeForce GT 330M] - 0a2c GT216 [NVS 5100M] - 0a2d GT216 [GeForce GT 320M] - 0a34 GT216 [GeForce GT 240M] - 0a35 GT216 [GeForce GT 325M] + 0a21 GT216M [GeForce GT 330M] + 0a22 GT216 [GeForce 315] + 0a23 GT216 [GeForce 210] + 0a26 GT216 [GeForce 405] + 0a27 GT216 [GeForce 405] + 0a28 GT216M [GeForce GT 230M] + 0a29 GT216M [GeForce GT 330M] + 0a2a GT216M [GeForce GT 230M] + 0a2b GT216M [GeForce GT 330M] + 0a2c GT216M [NVS 5100M] + 0a2d GT216M [GeForce GT 320M] + 0a30 GT216 [GeForce 505] + 0a32 GT216 [GeForce GT 415] + 0a34 GT216M [GeForce GT 240M] + 0a35 GT216M [GeForce GT 325M] 0a38 GT216GL [Quadro 400] - 0a3c GT216 [Quadro FX 880M] + 0a3c GT216GLM [Quadro FX 880M] 0a60 GT218 [GeForce G210] 0a62 GT218 [GeForce 205] 0a63 GT218 [GeForce 310] 0a64 GT218 [ION] 0a65 GT218 [GeForce 210] 1043 8334 EN210 SILENT + 1462 8094 N210 [Geforce 210] PCIe graphics adapter 0a66 GT218 [GeForce 310] -# taken from nv_disp.inf 0a67 GT218 [GeForce 315] - 0a68 G98M [GeForce G105M] - 0a69 G98M [GeForce G105M] - 0a6a GT218 [NVS 2100M] - 0a6c GT218 [NVS 3100M] + 0a68 GT218M [GeForce G 105M] + 0a69 GT218M [GeForce G 105M] + 0a6a GT218M [NVS 2100M] + 0a6c GT218M [NVS 3100M] 1028 040b Latitude E6510 17aa 2142 ThinkPad T410 - 0a6e GT218 [GeForce 305M] + 0a6e GT218M [GeForce 305M] 0a6f GT218 [ION] - 0a70 GT218 [GeForce 310M] - 0a71 GT218 [GeForce 305M] - 0a72 GT218 [GeForce 310M] - 0a73 GT218 [GeForce 305M] - 0a74 GT218 [GeForce G210M] - 0a75 GT218 [GeForce 310M] + 0a70 GT218M [GeForce 310M] + 0a71 GT218M [GeForce 305M] + 0a72 GT218M [GeForce 310M] + 0a73 GT218M [GeForce 305M] + 0a74 GT218M [GeForce G210M] + 1b0a 903a GeForce G210 + 0a75 GT218M [GeForce 310M] 0a76 GT218 [ION 2] 0a78 GT218GL [Quadro FX 380 LP] - 0a7c GT218 [Quadro FX 380M] + 0a7a GT218M [GeForce 315M] + 104d 907e GeForce 315M + 1179 fc50 GeForce 315M + 1179 fc61 GeForce 315M + 1179 fc71 GeForce 315M + 1179 fc90 GeForce 315M + 1179 fcc0 GeForce 315M + 1179 fcd0 GeForce 315M + 1179 fce2 GeForce 315M + 1179 fcf2 GeForce 315M + 1179 fd16 GeForce 315M + 1179 fd40 GeForce 315M + 1179 fd50 GeForce 315M + 1179 fd52 GeForce 315M + 1179 fd61 GeForce 315M + 1179 fd71 GeForce 315M + 1179 fd92 GeForce 315M + 1179 fd96 GeForce 315M + 1179 fdd0 GeForce 315M + 1179 fdd2 GeForce 315M + 1179 fdfe GeForce 315M + 144d c0a2 GeForce 315M + 144d c0b2 GeForce 315M + 144d c581 GeForce 315M + 144d c587 GeForce 315M + 144d c588 GeForce 315M + 144d c597 GeForce 315M + 144d c606 GeForce 315M + 1462 aa51 GeForce 405 + 1462 aa58 GeForce 405 + 1462 ac71 GeForce 405 + 1462 ac81 GeForce 315M + 1462 ac82 GeForce 405 + 1462 ae33 GeForce 405 + 1642 3980 GeForce 405 + 17aa 3950 GeForce 405M + 17aa 397d GeForce 405M + 1b0a 2091 GeForce 315M + 1b0a 90b4 GeForce 405 + 1bfd 0003 GeForce 405 + 1bfd 8006 GeForce 405 + 1bfd 8007 GeForce 315M + 0a7b GT218 [GeForce 505] + 0a7c GT218GLM [Quadro FX 380M] 0a80 MCP79 Host Bridge 0a81 MCP79 Host Bridge 0a82 MCP79 Host Bridge @@ -7109,30 +9368,42 @@ 0a87 MCP79 Host Bridge 0a88 MCP79 Memory Controller 0a89 MCP79 Memory Controller + 0a98 MCP79 Memory Controller + 10de cb79 iMac 9,1 0aa0 MCP79 PCI Express Bridge + 10de cb79 Apple iMac 9,1 0aa2 MCP79 SMBus + 10de cb79 Apple iMac 9,1 19da a123 IONITX-F-E 0aa3 MCP79 Co-processor + 10de cb79 Apple iMac 9,1 19da a123 IONITX-F-E 0aa4 MCP79 Memory Controller 19da a123 IONITX-F-E 0aa5 MCP79 OHCI USB 1.1 Controller + 10de cb79 Apple iMac 9,1 19da a123 IONITX-F-E 0aa6 MCP79 EHCI USB 2.0 Controller + 10de cb79 Apple iMac 9,1 19da a123 IONITX-F-E 0aa7 MCP79 OHCI USB 1.1 Controller + 10de cb79 Apple iMac 9,1 19da a123 IONITX-F-E 0aa8 MCP79 OHCI USB 1.1 Controller 0aa9 MCP79 EHCI USB 2.0 Controller + 10de cb79 Apple iMac 9,1 19da a123 IONITX-F-E 0aaa MCP79 EHCI USB 2.0 Controller 0aab MCP79 PCI Bridge + 10de cb79 Apple iMac 9,1 0aac MCP79 LPC Bridge 0aad MCP79 LPC Bridge 19da a123 IONITX-F-E 0aae MCP79 LPC Bridge + 10de cb79 Apple iMac 9,1 0aaf MCP79 LPC Bridge 0ab0 MCP79 Ethernet + 10de cb79 Apple iMac 9,1 19da a123 IONITX-F-E 0ab1 MCP79 Ethernet 0ab2 MCP79 Ethernet @@ -7144,6 +9415,7 @@ 0ab7 MCP79 SATA Controller 0ab8 MCP79 AHCI Controller 0ab9 MCP79 AHCI Controller + 10de cb79 Apple iMac 9,1 0aba MCP79 AHCI Controller 0abb MCP79 AHCI Controller 0abc MCP79 RAID Controller @@ -7151,13 +9423,17 @@ 0abe MCP79 RAID Controller 0abf MCP79 RAID Controller 0ac0 MCP79 High Definition Audio + 10de cb79 Apple iMac 9,1 0ac1 MCP79 High Definition Audio 0ac2 MCP79 High Definition Audio 0ac3 MCP79 High Definition Audio 0ac4 MCP79 PCI Express Bridge + 10de cb79 Apple iMac 9,1 0ac5 MCP79 PCI Express Bridge 0ac6 MCP79 PCI Express Bridge + 10de cb79 Apple iMac 9,1 0ac7 MCP79 PCI Express Bridge + 10de cb79 Apple iMac 9,1 0ac8 MCP79 PCI Express Bridge 0ad0 MCP78S [GeForce 8200] SATA Controller (non-AHCI mode) 1462 7508 K9N2GM-FIH @@ -7167,35 +9443,37 @@ 1043 82e8 M3N72-D 1849 0ad4 K10N78FullHD-hSLI R3.0 AHCI Controller 0ad8 MCP78S [GeForce 8200] SATA Controller (RAID mode) - 0be2 High Definition Audio Controller + 0be2 GT216 HDMI Audio Controller 1043 8311 ENGT220/DI/1GD3(LP)/V2 0be3 High Definition Audio Controller 1028 040b Latitude E6510 10de 066d G98 [GeForce 8400GS] + 1462 8094 N210 [Geforce 210] PCIe graphics adapter 0be4 High Definition Audio Controller 0be5 GF100 High Definition Audio Controller 0be9 GF106 High Definition Audio Controller 1558 8687 CLEVO/KAPOK W860CU + 3842 1452 GeForce GTS 450 0bea GF108 High Definition Audio Controller 3842 1430 GeForce GT 430 0beb GF104 High Definition Audio Controller 1462 2322 N460GTX Cyclone 1GD5/OC 0bee GF116 High Definition Audio Controller + 0bf0 Tegra2 PCIe x4 Bridge + 0bf1 Tegra2 PCIe x2 Bridge 0ca0 GT215 [GeForce GT 330] 0ca2 GT215 [GeForce GT 320] 0ca3 GT215 [GeForce GT 240] 0ca4 GT215 [GeForce GT 340] -# taken from nv_disp.inf 0ca5 GT215 [GeForce GT 220] 0ca7 GT215 [GeForce GT 330] - 0ca8 GT215 [GeForce GTS 260M] - 0ca9 GT215 [GeForce GTS 250M] -# GT215, not GT216 per http://www.techpowerup.com/gpuz/594cm/ - 0cac GT215 [GeForce GT 220] - 0caf GT215 [GeForce GT 335M] - 0cb0 GT215 [GeForce GTS 350M] - 0cb1 GT215 [GeForce GTS 360M] - 0cbc GT215 [Quadro FX 1800M] + 0ca8 GT215M [GeForce GTS 260M] + 0ca9 GT215M [GeForce GTS 250M] + 0cac GT215 [GeForce GT 220/315] + 0caf GT215M [GeForce GT 335M] + 0cb0 GT215M [GeForce GTS 350M] + 0cb1 GT215M [GeForce GTS 360M] + 0cbc GT215GLM [Quadro FX 1800M] 0d60 MCP89 HOST Bridge 0d68 MCP89 Memory Controller 0d69 MCP89 Memory Controller @@ -7212,144 +9490,791 @@ 0d94 MCP89 High Definition Audio 0d9c MCP89 OHCI USB 1.1 Controller 0d9d MCP89 EHCI USB 2.0 Controller -# taken from nv_disp.inf - 0dc0 GF108 [GeForce GT 440] + 0dc0 GF106 [GeForce GT 440] 0dc4 GF106 [GeForce GTS 450] -# taken from nv_disp.inf - 0dc5 GF106 [GeForce GTS 450] -# taken from nv_disp.inf + 0dc5 GF106 [GeForce GTS 450 OEM] 0dc6 GF106 [GeForce GTS 450] - 0dcd GF106 [GeForce GT 555M] - 0dce GF106 [GeForce GT 555M] -# rev a1 - 0dd1 GF106 [GeForce GTX 460M] + 0dcd GF106M [GeForce GT 555M] + 0dce GF106M [GeForce GT 555M] + 0dd1 GF106M [GeForce GTX 460M] 1558 8687 CLEVO/KAPOK W860CU - 0dd2 GF106 [GeForce GT 445M] + 0dd2 GF106M [GeForce GT 445M] + 0dd3 GF106M [GeForce GT 435M] + 0dd6 GF106M [GeForce GT 550M] 0dd8 GF106GL [Quadro 2000] -# NVIDIA calls it GF106GML + 10de 0914 Quadro 2000D 0dda GF106GLM [Quadro 2000M] 0de0 GF108 [GeForce GT 440] 0de1 GF108 [GeForce GT 430] 3842 1430 GeForce GT 430 0de2 GF108 [GeForce GT 420] -# taken from nv_disp.inf + 0de3 GF108M [GeForce GT 635M] 0de4 GF108 [GeForce GT 520] -# taken from nv_disp.inf 0de5 GF108 [GeForce GT 530] - 0de9 GF108 [GeForce GT 630M] -# Not fully sure that it's GF108, might also be GF106. - 0deb GF108 [GeForce GT 555M] - 0dee GF108 [GeForce GT 415M] - 0def GF108 [Quadro NVS 5400M] - 0df0 GF108 [GeForce GT 425M] - 0df2 GF108 [GeForce GT 435M] - 0df4 GF108 [GeForce GT 540M] - 0df5 GF108 [GeForce GT 540M] - 0df7 GF108 [GeForce GT 520M] -# NVIDIA calls it GL + 0de7 GF108 [GeForce GT 610] + 0de8 GF108M [GeForce GT 620M] + 0de9 GF108M [GeForce GT 630M] + 1025 0692 GeForce GT 620M + 1025 0725 GeForce GT 620M + 1025 0728 GeForce GT 620M + 1025 072b GeForce GT 620M + 1025 072e GeForce GT 620M + 1025 0753 GeForce GT 620M + 1025 0754 GeForce GT 620M + 17aa 3977 GeForce GT 640M LE + 1b0a 2210 GeForce GT 635M + 0dea GF108M [GeForce 610M] + 17aa 365a GeForce 615 + 17aa 365b GeForce 615 + 17aa 365e GeForce 615 + 17aa 3660 GeForce 615 + 17aa 366c GeForce 615 + 0deb GF108M [GeForce GT 555M] + 0dec GF108M [GeForce GT 525M] + 0ded GF108M [GeForce GT 520M] + 0dee GF108M [GeForce GT 415M] + 0def GF108M [NVS 5400M] + 0df0 GF108M [GeForce GT 425M] + 0df1 GF108M [GeForce GT 420M] + 0df2 GF108M [GeForce GT 435M] + 0df3 GF108M [GeForce GT 420M] + 0df4 GF108M [GeForce GT 540M] + 152d 0952 GeForce GT 630M + 152d 0953 GeForce GT 630M + 0df5 GF108M [GeForce GT 525M] + 0df6 GF108M [GeForce GT 550M] + 0df7 GF108M [GeForce GT 520M] 0df8 GF108GL [Quadro 600] -# NVIDIA calls it GLM 0df9 GF108GLM [Quadro 500M] -# NVIDIA calls it GLM 0dfa GF108GLM [Quadro 1000M] + 0dfc GF108GLM [NVS 5200M] 0e08 GF119 HDMI Audio Controller +# 1024MB with passive cooling (heatsink) + 10b0 104a Gainward GeForce GT 610 0e09 GF110 High Definition Audio Controller 0e0a GK104 HDMI Audio Controller + 0e0b GK106 HDMI Audio Controller 0e0c GF114 HDMI Audio Controller + 0e0f GK208 HDMI/DP Audio Controller + 0e12 TegraK1 PCIe x4 Bridge + 0e13 TegraK1 PCIe x1 Bridge + 0e1a GK110 HDMI Audio + 0e1b GK107 HDMI Audio Controller + 103c 197b ZBook 15 + 1043 8428 GTX650-DC-1GD5 + 0e1c Tegra3+ PCIe x4 Bridge + 0e1d Tegra3+ PCIe x2 Bridge 0e22 GF104 [GeForce GTX 460] 1462 2322 N460GTX Cyclone 1GD5/OC -# taken from nv_disp.inf 0e23 GF104 [GeForce GTX 460 SE] -# taken from nv_disp.inf - 0e24 GF104 [GeForce GTX 460] - 0e3a GF104 [Quadro 3000M] - 0e3b GF104 [Quadro 4000M] -# taken from nv_disp.inf - 0f00 GK107 [GeForce GT 630] -# Probably GF108 - 0f01 GeForce GT 620 -# taken from nv_disp.inf - 0fc0 GK107 [GeForce GT 640] -# taken from nv_disp.inf + 0e24 GF104 [GeForce GTX 460 OEM] + 0e30 GF104M [GeForce GTX 470M] + 0e31 GF104M [GeForce GTX 485M] + 0e3a GF104GLM [Quadro 3000M] + 0e3b GF104GLM [Quadro 4000M] + 0f00 GF108 [GeForce GT 630] + 0f01 GF108 [GeForce GT 620] + 0f02 GF108 [GeForce GT 730] + 0fbb GM204 High Definition Audio Controller + 0fc0 GK107 [GeForce GT 640 OEM] 0fc1 GK107 [GeForce GT 640] - 0fd1 GK107 [GeForce GT 650M] + 0fc2 GK107 [GeForce GT 630 OEM] + 0fc6 GK107 [GeForce GTX 650] + 1043 8428 GTX650-DC-1GD5 + 0fc8 GK107 [GeForce GT 740] + 0fc9 GK107 [GeForce GT 730] + 0fcd GK107M [GeForce GT 755M] + 0fce GK107M [GeForce GT 640M LE] + 0fd1 GK107M [GeForce GT 650M] + 1043 1597 GeForce GT 650M + 1043 15a7 GeForce GT 650M 1043 2103 N56VZ - 0fd2 GK107 [GeForce GT 640M] - 0ff2 GK107 [VGX K1] - 0ffa GK107 [Quadro K600] - 0ffb GK107 [Quadro K2000M] - 0ffc GK107 [Quadro K1000M] - 0ffe GK107 [Quadro K2000] - 0fff GK107 [Quadro 410] + 1043 2105 GeForce GT 650M + 1043 2141 GeForce GT 650M + 0fd2 GK107M [GeForce GT 640M] + 1028 054f GeForce GT 640M + 1028 055f GeForce GT 640M + 1028 0595 GeForce GT 640M LE + 1028 05b2 GeForce GT 640M LE + 0fd3 GK107M [GeForce GT 640M LE] + 0fd4 GK107M [GeForce GTX 660M] + 0fd5 GK107M [GeForce GT 650M Mac Edition] + 0fd8 GK107M [GeForce GT 640M Mac Edition] + 0fd9 GK107M [GeForce GT 645M] + 0fdb GK107M + 0fdf GK107M [GeForce GT 740M] + 0fe0 GK107M [GeForce GTX 660M Mac Edition] + 0fe1 GK107M [GeForce GT 730M] + 0fe2 GK107M [GeForce GT 745M] + 0fe3 GK107M [GeForce GT 745M] + 103c 2b16 GeForce GT 745A + 17aa 3675 GeForce GT 745A + 0fe4 GK107M [GeForce GT 750M] + 0fe5 GK107 [GeForce K340 USM] + 0fe6 GK107 [GRID K1 NVS USM] +# GRID K1 USM + 0fe7 GK107GL [GRID K100 vGPU] + 10de 101e GRID K100 + 0fe9 GK107M [GeForce GT 750M Mac Edition] + 0fea GK107M [GeForce GT 755M Mac Edition] + 0fec GK107M [GeForce 710A] + 0fed GK107M [GeForce 820M] + 0fef GK107GL [GRID K340] + 0ff1 GK107 [NVS 1000] + 0ff2 GK107GL [GRID K1] + 0ff3 GK107GL [Quadro K420] + 0ff5 GK107GL [GRID K1 Tesla USM] + 0ff6 GK107GLM [Quadro K1100M] + 103c 197b ZBook 15 +# GRID K1 Quadro USM + 0ff7 GK107GL [GRID K140Q vGPU] + 10de 1037 GRID K140Q + 0ff8 GK107GLM [Quadro K500M] + 0ff9 GK107GL [Quadro K2000D] + 0ffa GK107GL [Quadro K600] + 0ffb GK107GLM [Quadro K2000M] + 0ffc GK107GLM [Quadro K1000M] + 0ffd GK107 [NVS 510] + 0ffe GK107GL [Quadro K2000] + 0fff GK107GL [Quadro 410] + 1001 GK110B [GeForce GTX TITAN Z] + 1003 GK110 [GeForce GTX Titan LE] + 1004 GK110 [GeForce GTX 780] + 3842 0784 GK110B [GeForce GTX 780 SC w/ ACX Cooler] + 3842 1784 GK110B [GeForce GTX 780 Dual FTW w/ ACX Cooler] + 3842 1788 GK110B [GeForce GTX 780 Dual Classified w/ ACX Cooler] + 1005 GK110 [GeForce GTX TITAN] + 1043 8451 GTXTITAN-6GD5 +# Reference Model + 10de 1035 GeForce GTX Titan +# 06G-P4-2790-KR + 3842 2790 GeForce GTX Titan +# 06G-P4-2791-KR + 3842 2791 GeForce GTX Titan SC +# 06G-P4-2793-KR + 3842 2793 GeForce GTX Titan SC Signature +# 06G-P4-2794-KR + 3842 2794 GeForce GTX Titan SC Hydro Copper +# 06G-P4-2795-KR + 3842 2795 GeForce GTX Titan SC Hydro Copper Signature + 1007 GK110 [GeForce GTX 780 Rev. 2] + 1008 GK110 [GeForce GTX 780 Ti Rev. 2] + 100a GK110B [GeForce GTX 780 Ti] + 100c GK110B [GeForce GTX TITAN Black] + 101e GK110GL [Tesla K20X] + 101f GK110GL [Tesla K20] + 1020 GK110GL [Tesla K20X] + 1021 GK110GL [Tesla K20Xm] + 1022 GK110GL [Tesla K20c] + 1023 GK110BGL [Tesla K40m] + 10de 097e 12GB Computational Accelerator + 1024 GK110BGL [Tesla K40c] + 1026 GK110GL [Tesla K20s] + 1027 GK110BGL [Tesla K40st] + 1028 GK110GL [Tesla K20m] + 1029 GK110BGL [Tesla K40s] + 102a GK110BGL [Tesla K40t] + 102d GK210GL [Tesla K80] + 102e GK110BGL [Tesla K40d] + 103a GK110GL [Quadro K6000] + 103c GK110GL [Quadro K5200] 1040 GF119 [GeForce GT 520] -# taken from nv_disp.inf 1042 GF119 [GeForce 510] -# taken from nv_disp.inf 1048 GF119 [GeForce 605] -# taken from nv_disp.inf - 1049 GF119 [GeForce GT 620] -# taken from nv_disp.inf + 1049 GF119 [GeForce GT 620 OEM] 104a GF119 [GeForce GT 610] - 1050 GF119 [GeForce GT 520M] - 1051 GF119 [GeForce GT 520MX] - 1056 GF119 [Quadro NVS 4200M] - 1057 GF119 [Quadro NVS 4200M] - 105a GF119 [GeForce 610M] - 107d GF119 [Quadro NVS 310] +# 1024MB with passive cooling (heatsink) + 10b0 104a Gainward GeForce GT 610 + 104b GF119 [GeForce GT 625 OEM] + 104c GF119 [GeForce GT 705] + 104d GF119 [GeForce GT 710] + 1050 GF119M [GeForce GT 520M] + 1051 GF119M [GeForce GT 520MX] + 1052 GF119M [GeForce GT 520M] + 1054 GF119M [GeForce 410M] + 1055 GF119M [GeForce 410M] + 1056 GF119M [NVS 4200M] + 1057 GF119M [Quadro NVS 4200M] + 1058 GF119M [GeForce 610M] + 103c 2aed GeForce 610 + 103c 2af1 GeForce 610 + 1043 10ac GeForce GT 610M + 1043 10bc GeForce GT 610M + 1043 1652 GeForce GT 610M + 17aa 367a GeForce 610M + 17aa 3682 GeForce 800A + 17aa 3687 GeForce 800A + 17aa 3692 GeForce 705A + 17aa 3695 GeForce 800A + 17aa a117 GeForce 610M + 1059 GF119M [GeForce 610M] + 105a GF119M [GeForce 610M] + 1043 2111 GeForce GT 610M + 1043 2112 GeForce GT 610M + 105b GF119M [GeForce 705M] + 103c 2afb GeForce 705A + 17aa 309d GeForce 705A + 17aa 30b1 GeForce 800A + 17aa 36a1 GeForce 800A + 107c GF119 [NVS 315] + 107d GF119 [NVS 310] 1080 GF110 [GeForce GTX 580] 1081 GF110 [GeForce GTX 570] 10de 087e Leadtek WinFast GTX 570 - 1082 GF110 [GeForce GTX 560 Ti] -# taken from nv_disp.inf - 1084 GF110 [GeForce GTX 560] - 1086 GF110 [GeForce GTX 570 HD] + 1082 GF110 [GeForce GTX 560 Ti OEM] + 1084 GF110 [GeForce GTX 560 OEM] + 1086 GF110 [GeForce GTX 570 Rev. 2] 1087 GF110 [GeForce GTX 560 Ti 448 Cores] -# taken from nv_disp.inf 1088 GF110 [GeForce GTX 590] -# taken from nv_disp.inf 1089 GF110 [GeForce GTX 580] -# taken from nv_disp.inf 108b GF110 [GeForce GTX 580] - 1091 Tesla M2090 - 1094 Tesla M2075 Dual-Slot Computing Processor Module - 1096 Tesla C2075 + 108e GF110GL [Tesla C2090] + 1091 GF110GL [Tesla M2090] + 10de 088e Tesla X2090 + 10de 0891 Tesla X2090 + 10de 0974 Tesla X2090 + 10de 098d Tesla X2090 + 1094 GF110GL [Tesla M2075] + 10de 0888 Tesla M2075 + 1096 GF110GL [Tesla C2050 / C2075] + 10de 0910 Tesla C2075 + 10de 0911 Tesla C2050 + 109a GF100GLM [Quadro 5010M] 109b GF100GL [Quadro 7000] - 10c3 GT218 [GeForce 8400 GS] - 10de 066d G98 [GeForce 8400GS] + 10de 0918 Quadro 7000 + 10c0 GT218 [GeForce 9300 GS Rev. 2] + 10c3 GT218 [GeForce 8400 GS Rev. 3] 10c5 GT218 [GeForce 405] - 10d8 GT218 [Quadro NVS 300] + 10d8 GT218 [NVS 300] + 1140 GF117M [GeForce 610M/710M/810M/820M / GT 620M/625M/630M/720M] + 1019 999f GeForce GT 720M + 1025 0600 GeForce GT 620M + 1025 0606 GeForce GT 620M + 1025 064a GeForce GT 620M + 1025 064c GeForce GT 620M + 1025 067a GeForce GT 620M + 1025 0680 GeForce GT 620M + 1025 0686 GeForce 710M + 1025 0689 GeForce 710M + 1025 068b GeForce 710M + 1025 068d GeForce 710M + 1025 068e GeForce 710M + 1025 0691 GeForce 710M + 1025 0692 GeForce GT 620M + 1025 0694 GeForce GT 620M + 1025 0702 GeForce GT 620M + 1025 0719 GeForce GT 620M + 1025 0725 GeForce GT 620M + 1025 0728 GeForce GT 620M + 1025 072b GeForce GT 620M + 1025 072e GeForce GT 620M + 1025 0732 GeForce GT 620M + 1025 0763 GeForce GT 720M + 1025 0773 GeForce 710M + 1025 0774 GeForce 710M + 1025 0776 GeForce GT 720M + 1025 077a GeForce 710M + 1025 077b GeForce 710M + 1025 077c GeForce 710M + 1025 077d GeForce 710M + 1025 077e GeForce 710M + 1025 077f GeForce 710M + 1025 0781 GeForce GT 720M + 1025 0798 GeForce GT 720M + 1025 0799 GeForce GT 720M + 1025 079b GeForce GT 720M + 1025 079c GeForce GT 720M + 1025 0807 GeForce GT 720M + 1025 0821 GeForce GT 720M + 1025 0823 GeForce GT 720M + 1025 0830 GeForce GT 720M + 1025 0833 GeForce GT 720M + 1025 0837 GeForce GT 720M + 1025 083e GeForce 820M + 1025 0841 GeForce 710M + 1025 0854 GeForce 820M + 1025 0855 GeForce 820M + 1025 0856 GeForce 820M + 1025 0857 GeForce 820M + 1025 0858 GeForce 820M + 1025 0863 GeForce 820M + 1025 0868 GeForce 820M + 1025 0869 GeForce 810M + 1025 0873 GeForce 820M + 1025 0878 GeForce 820M + 1025 087b GeForce 820M + 1025 087c GeForce 810M + 1025 0881 GeForce 820M + 1025 088a GeForce 820M + 1025 089b GeForce 820M + 1025 090f GeForce 820M + 1025 0921 GeForce 820M + 1025 092e GeForce 810M + 1025 092f GeForce 820M + 1025 0932 GeForce 820M + 1025 093a GeForce 820M + 1025 093c GeForce 820M + 1025 093f GeForce 820M + 1025 0941 GeForce 820M + 1025 0945 GeForce 820M + 1025 0954 GeForce 820M + 1025 0965 GeForce 820M + 1028 054d GeForce GT 630M + 1028 054e GeForce GT 630M + 1028 0554 GeForce GT 620M + 1028 0557 GeForce GT 620M + 1028 0562 GeForce GT 625M + 1028 0565 GeForce GT 630M + 1028 0568 GeForce GT 630M + 1028 0590 GeForce GT 630M + 1028 0592 GeForce GT 625M + 1028 0594 GeForce GT 625M + 1028 0595 GeForce GT 625M + 1028 05a2 GeForce GT 625M + 1028 05b1 GeForce GT 625M + 1028 05b3 GeForce GT 625M + 1028 05da GeForce GT 630M + 1028 05de GeForce GT 720M + 1028 05e0 GeForce GT 720M + 1028 05e8 GeForce GT 630M + 1028 05f4 GeForce GT 720M + 1028 060f GeForce GT 720M + 1028 064e GeForce 820M + 1028 0652 GeForce 820M + 1028 0653 GeForce 820M + 1028 0655 GeForce 820M + 1028 065e GeForce 820M + 1028 0662 GeForce 820M + 1028 068d GeForce 820M + 103c 18ef GeForce GT 630M + 103c 18f9 GeForce GT 630M + 103c 18fb GeForce GT 630M + 103c 18fd GeForce GT 630M + 103c 18ff GeForce GT 630M + 103c 2335 GeForce 820M + 103c 2337 GeForce 820M + 103c 2aef GeForce GT 720A + 103c 2af9 GeForce 710A + 1043 10dd NVS 5200M + 1043 10ed NVS 5200M + 1043 11fd GeForce GT 720M + 1043 124d GeForce GT 720M + 1043 126d GeForce GT 720M + 1043 131d GeForce GT 720M + 1043 13fd GeForce GT 720M + 1043 14c7 GeForce GT 720M + 1043 1507 GeForce GT 620M + 1043 15ad GeForce 820M + 1043 15ed GeForce 820M + 1043 160d GeForce 820M + 1043 163d GeForce 820M + 1043 166d GeForce 820M + 1043 16cd GeForce 820M + 1043 16dd GeForce 820M + 1043 170d GeForce 820M + 1043 176d GeForce 820M + 1043 178d GeForce 820M + 1043 179d GeForce 820M + 1043 17dd GeForce 820M + 1043 2132 GeForce GT 620M + 1043 2136 NVS 5200M + 1043 21ba GeForce GT 720M + 1043 21fa GeForce GT 720M + 1043 220a GeForce GT 720M + 1043 221a GeForce GT 720M + 1043 223a GeForce GT 710M + 1043 224a GeForce GT 710M + 1043 227a GeForce 820M + 1043 228a GeForce 820M + 1043 232a GeForce 820M + 1043 233a GeForce 820M + 1043 236a GeForce 820M + 1043 238a GeForce 820M + 1043 8595 GeForce GT 720M + 1043 85ea GeForce GT 720M + 1043 85eb GeForce 820M + 1043 85ec GeForce 820M + 1043 85ee GeForce GT 720M + 1043 85f3 GeForce 820M + 1043 860e GeForce 820M + 1043 861a GeForce 820M + 1043 861b GeForce 820M + 1043 8628 GeForce 820M + 1043 8643 GeForce 820M + 1043 864c GeForce 820M + 1043 8652 GeForce 820M + 105b 0dac GeForce GT 720M + 105b 0dad GeForce GT 720M + 105b 0ef3 GeForce GT 720M + 1072 152d GeForce GT 720M + 10cf 17f5 GeForce GT 720M + 1179 fa01 GeForce 710M + 1179 fa02 GeForce 710M + 1179 fa03 GeForce 710M + 1179 fa05 GeForce 710M + 1179 fa11 GeForce 710M + 1179 fa13 GeForce 710M + 1179 fa18 GeForce 710M + 1179 fa19 GeForce 710M + 1179 fa21 GeForce 710M + 1179 fa23 GeForce 710M + 1179 fa2a GeForce 710M + 1179 fa32 GeForce 710M + 1179 fa33 GeForce 710M + 1179 fa36 GeForce 710M + 1179 fa38 GeForce 710M + 1179 fa42 GeForce 710M + 1179 fa43 GeForce 710M + 1179 fa45 GeForce 710M + 1179 fa47 GeForce 710M + 1179 fa49 GeForce 710M + 1179 fa58 GeForce 710M + 1179 fa59 GeForce 710M + 1179 fa88 GeForce 710M + 1179 fa89 GeForce 710M + 144d b092 GeForce GT 620M + 144d c0d5 GeForce GT 630M + 144d c0d7 GeForce GT 620M + 144d c0e2 NVS 5200M + 144d c0e3 NVS 5200M + 144d c0e4 NVS 5200M + 144d c10d GeForce 820M + 144d c652 GeForce GT 620M + 144d c709 GeForce 710M + 144d c711 GeForce 710M + 144d c736 GeForce 710M + 144d c737 GeForce 710M + 144d c745 GeForce 820M + 144d c750 GeForce 820M + 1462 10b8 GeForce GT 710M + 1462 10e9 GeForce GT 720M + 1462 1116 GeForce 820M + 1462 aa33 GeForce 720M + 1462 aaa2 GeForce GT 720M + 1462 aaa3 GeForce 820M + 1462 acb2 GeForce GT 720M + 1462 acc1 GeForce GT 720M + 1462 ae61 GeForce 720M + 1462 ae65 GeForce GT 720M + 1462 ae6a GeForce 820M + 1462 ae71 GeForce GT 720M + 14c0 0083 GeForce 820M + 152d 0926 GeForce 620M + 152d 0982 GeForce GT 630M + 152d 0983 GeForce GT 630M + 152d 1005 GeForce GT 820M + 152d 1012 GeForce 710M + 152d 1019 GeForce 820M + 152d 1030 GeForce GT 630M + 152d 1055 GeForce 710M + 152d 1067 GeForce GT 720M + 152d 1072 GeForce GT 720M + 152d 1086 GeForce 820M + 152d 1092 GeForce 820M + 17aa 2200 NVS 5200M + 17aa 2213 GeForce GT 720M + 17aa 2220 GeForce GT 720M + 17aa 309c GeForce GT 720A + 17aa 30b4 GeForce 820A + 17aa 30b7 GeForce 720A + 17aa 361b GeForce 820A + 17aa 361c GeForce 820A + 17aa 3656 GeForce GT 620M + 17aa 365a GeForce 705M + 17aa 365e GeForce 800M + 17aa 3661 GeForce 820A + 17aa 366c GeForce 800M + 17aa 3685 GeForce 800M + 17aa 3686 GeForce 800M + 17aa 3687 GeForce 705A + 17aa 3696 GeForce 820A + 17aa 369b GeForce 820A + 17aa 369c GeForce 820A + 17aa 369d GeForce 820A + 17aa 369e GeForce 820A + 17aa 36a9 GeForce 820A + 17aa 36af GeForce 820A + 17aa 36b0 GeForce 820A + 17aa 36b6 GeForce 820A + 17aa 3800 GeForce GT 720M + 17aa 3801 GeForce GT 720M + 17aa 3802 GeForce GT 720M + 17aa 3803 GeForce GT 720M + 17aa 3804 GeForce GT 720M + 17aa 3806 GeForce GT 720M + 17aa 3808 GeForce GT 720M + 17aa 380d GeForce 820M + 17aa 380e GeForce 820M + 17aa 380f GeForce 820M + 17aa 3811 GeForce 820M + 17aa 3812 GeForce 820M + 17aa 3813 GeForce 820M + 17aa 3816 GeForce 820M + 17aa 3818 GeForce 820M + 17aa 381a GeForce 820M + 17aa 381c GeForce 820M + 17aa 3901 GeForce 610M / GT 620M + 17aa 3902 GeForce 710M + 17aa 3903 GeForce 610M/710M + 17aa 3904 GeForce GT 620M/625M + 17aa 3905 GeForce GT 720M + 17aa 3907 GeForce 820M + 17aa 3910 GeForce 720M + 17aa 3912 GeForce 720M + 17aa 3913 GeForce 820M + 17aa 3915 GeForce 820M + 17aa 3977 GeForce GT 720M + 17aa 3983 GeForce 610M + 17aa 5001 GeForce 610M + 17aa 5003 GeForce GT 720M + 17aa 5005 GeForce 705M + 17aa 500d GeForce GT 620M + 17aa 5014 GeForce 710M + 17aa 5017 GeForce 710M + 17aa 5019 GeForce 710M + 17aa 501a GeForce 710M + 17aa 501f GeForce GT 720M + 17aa 5025 GeForce 710M + 17aa 5027 GeForce 710M + 17aa 502a GeForce 710M + 17aa 502b GeForce GT 720M + 17aa 502d GeForce 710M + 17aa 502e GeForce GT 720M + 17aa 502f GeForce GT 720M + 17aa 5030 GeForce 705M + 17aa 5031 GeForce 705M + 17aa 5032 GeForce 820M + 17aa 5033 GeForce 820M + 17aa 503e GeForce 710M + 17aa 503f GeForce 820M + 17aa 5040 GeForce 820M + 1854 0177 GeForce 710M + 1854 0180 GeForce 710M + 1854 0190 GeForce GT 720M + 1854 0192 GeForce GT 720M + 1b0a 20dd GeForce GT 620M + 1b0a 20df GeForce GT 620M + 1b0a 210e GeForce 820M + 1b0a 2202 GeForce GT 720M + 1b0a 90d7 GeForce 820M + 1b0a 90dd GeForce 820M 1180 GK104 [GeForce GTX 680] + 1043 83f1 GTX680-DC2-2GD5 + 3842 3682 GeForce GTX 680 Mac Edition + 1182 GK104 [GeForce GTX 760 Ti] 1183 GK104 [GeForce GTX 660 Ti] + 1184 GK104 [GeForce GTX 770] + 1185 GK104 [GeForce GTX 660 OEM] + 10de 106f GK104 [GeForce GTX 760 OEM] + 1187 GK104 [GeForce GTX 760] 1188 GK104 [GeForce GTX 690] 1189 GK104 [GeForce GTX 670] - 11ba GK104 [Quadro K5000] - 11bc GK104 [Quadro K5000M] - 11bd GK104 [Quadro K4000M] - 11be GK104 [Quadro K3000M] - 11bf GK104GL [VGX K2] - 11fa GK104 [Quadro K4000] + 10de 1074 GK104 [GeForce GTX 760 Ti OEM] + 118a GK104GL [GRID K520] + 118b GK104GL [GRID K2 GeForce USM] + 118c GK104 [GRID K2 NVS USM] +# GRID K2 USM + 118d GK104GL [GRID K200 vGPU] + 10de 101d GRID K200 + 118e GK104 [GeForce GTX 760 OEM] + 118f GK104GL [Tesla K10] + 1191 GK104 [GeForce GTX 760 Rev. 2] + 1193 GK104 [GeForce GTX 760 Ti OEM] + 1194 GK104GL [Tesla K8] + 1195 GK104 [GeForce GTX 660 Rev. 2] + 1198 GK104M [GeForce GTX 880M] + 1199 GK104M [GeForce GTX 870M] + 119a GK104M [GeForce GTX 860M] + 119d GK104M [GeForce GTX 775M Mac Edition] + 119e GK104M [GeForce GTX 780M Mac Edition] + 119f GK104M [GeForce GTX 780M] + 11a0 GK104M [GeForce GTX 680M] + 11a1 GK104M [GeForce GTX 670MX] + 11a2 GK104M [GeForce GTX 675MX Mac Edition] + 11a3 GK104M [GeForce GTX 680MX] + 106b 010d iMac 13,2 + 11a7 GK104M [GeForce GTX 675MX] +# GRID K2 Quadro USM + 11b0 GK104GL [GRID K240Q\K260Q vGPU] + 10de 101a GRID K240Q + 10de 101b GRID K260Q + 11b1 GK104GL [GRID K2 Tesla USM] + 11b4 GK104GL [Quadro K4200] + 11b6 GK104GLM [Quadro K3100M] + 11b7 GK104GLM [Quadro K4100M] + 11b8 GK104GLM [Quadro K5100M] + 11ba GK104GL [Quadro K5000] + 11bb GK104GL [Quadro 4100] + 11bc GK104GLM [Quadro K5000M] + 11bd GK104GLM [Quadro K4000M] + 11be GK104GLM [Quadro K3000M] + 11bf GK104GL [GRID K2] + 11c0 GK106 [GeForce GTX 660] + 11c2 GK106 [GeForce GTX 650 Ti Boost] + 1043 845b GeForce GTX 650 Ti Boost DirectCU II OC + 1462 2874 GeForce GTX 650 Ti Boost TwinFrozr II OC + 1569 11c2 GeForce GTX 650 Ti Boost OC + 19da 1281 GeForce GTX 650 Ti Boost OC + 3842 3657 GeForce GTX 650 Ti Boost + 3842 3658 GeForce GTX 650 Ti Boost Superclocked + 11c3 GK106 [GeForce GTX 650 Ti OEM] + 10de 1030 GeForce GTX 650 Ti OEM + 11c4 GK106 [GeForce GTX 645 OEM] + 11c5 GK106 [GeForce GT 740] + 11c6 GK106 [GeForce GTX 650 Ti] + 11c7 GK106 [GeForce GTX 750 Ti] + 11c8 GK106 [GeForce GTX 650 OEM] + 11cb GK106 [GeForce GT 740] + 11e0 GK106M [GeForce GTX 770M] + 11e1 GK106M [GeForce GTX 765M] + 11e2 GK106M [GeForce GTX 765M] + 11e3 GK106M [GeForce GTX 760M] + 17aa 3683 GeForce GTX 760A + 11e7 GK106M + 11fa GK106GL [Quadro K4000] + 11fc GK106GLM [Quadro K2100M] 1200 GF114 [GeForce GTX 560 Ti] 1201 GF114 [GeForce GTX 560] + 1202 GF114 [GeForce GTX 560 Ti OEM] + 1203 GF114 [GeForce GTX 460 SE v2] 1205 GF114 [GeForce GTX 460 v2] -# taken from nv_disp.inf 1206 GF114 [GeForce GTX 555] -# taken from nv_disp.inf - 1207 GF114 [GeForce GTX 645] -# taken from nv_disp.inf + 1207 GF114 [GeForce GT 645 OEM] 1208 GF114 [GeForce GTX 560 SE] -# GT, not GTX - 1241 GF116 [GeForce GT 545] -# GT, not GTX + 1210 GF114M [GeForce GTX 570M] + 1211 GF114M [GeForce GTX 580M] + 1212 GF114M [GeForce GTX 675M] + 1213 GF114M [GeForce GTX 670M] + 1241 GF116 [GeForce GT 545 OEM] 1243 GF116 [GeForce GT 545] 1244 GF116 [GeForce GTX 550 Ti] - 1245 GF116 [GeForce GTS 450] - 1247 GF106 [GeForce GT 555M] -# taken from nv_disp.inf - 1249 GF116 [GeForce GTS 450] -# taken from nv_disp.inf - 124b GF116 [GeForce GT 640] + 1245 GF116 [GeForce GTS 450 Rev. 2] + 1246 GF116M [GeForce GT 550M] + 1247 GF116M [GeForce GT 555M/635M] + 1043 1752 GeForce GT 555M + 1043 2050 GeForce GT 555M + 1043 2051 GeForce GT 555M + 1043 212a GeForce GT 635M + 1043 212b GeForce GT 635M + 1043 212c GeForce GT 635M + 152d 0930 GeForce GT 635M + 1248 GF116M [GeForce GT 555M/635M] + 152d 0930 GeForce GT 635M + 17c0 10e7 GeForce GT 555M + 17c0 10e8 GeForce GT 555M + 17c0 10ea GeForce GT 555M + 1854 0890 GeForce GT 555M + 1854 0891 GeForce GT 555M + 1854 1795 GeForce GT 555M + 1854 1796 GeForce GT 555M + 1854 3005 GeForce GT 555M + 1249 GF116 [GeForce GTS 450 Rev. 3] + 124b GF116 [GeForce GT 640 OEM] + 124d GF116M [GeForce GT 555M/635M] + 1028 0491 GeForce GT 555M + 1028 0570 GeForce GT 555M + 1028 0571 GeForce GT 555M + 1462 108d GeForce GT 555M + 1462 10cc GeForce GT 635M + 1251 GF116M [GeForce GT 560M] + 1280 GK208 [GeForce GT 635] + 1281 GK208 [GeForce GT 710] + 1282 GK208 [GeForce GT 640 Rev. 2] + 1284 GK208 [GeForce GT 630 Rev. 2] + 1286 GK208 [GeForce GT 720] + 1287 GK208 [GeForce GT 730] + 1288 GK208 [GeForce GT 720] + 1289 GK208 [GeForce GT 710] + 1290 GK208M [GeForce GT 730M] + 103c 2afa GeForce GT 730A + 103c 2b04 GeForce GT 730A + 1043 13ad GeForce GT 730M + 1043 13cd GeForce GT 730M + 1291 GK208M [GeForce GT 735M] + 1292 GK208M [GeForce GT 740M] + 17aa 3675 GeForce GT 740A + 17aa 367c GeForce GT 740A + 17aa 3684 GeForce GT 740A + 1293 GK208M [GeForce GT 730M] + 1294 GK208M [GeForce GT 740M] + 1295 GK208M [GeForce 710M] + 103c 2b0d GeForce 710A + 103c 2b0f GeForce 710A + 103c 2b11 GeForce 710A + 103c 2b20 GeForce 810A + 103c 2b21 GeForce 810A + 103c 2b22 GeForce 810A + 17aa 367a GeForce 805A + 17aa 367c GeForce 710A + 1296 GK208M [GeForce 825M] + 1298 GK208M [GeForce GT 720M] + 1299 GK208M [GeForce 920M] + 129a GK208GL [N16V-GL] + 12a0 GK208 + 12b9 GK208GLM [Quadro K610M] + 12ba GK208GLM [Quadro K510M] + 1340 GM108M [GeForce 830M] + 103c 2b2b GeForce 830A + 1341 GM108M [GeForce 840M] + 17aa 3697 GeForce 840A + 17aa 3699 GeForce 840A + 17aa 369c GeForce 840A + 1344 GM108M [GeForce 845M] + 1346 GM108M [GeForce 930M] + 1347 GM108M [GeForce 940M] + 137a GM108GLM [Quadro K620M] + 137d GM108M [GeForce 940A] + 1380 GM107 [GeForce GTX 750 Ti] + 1381 GM107 [GeForce GTX 750] + 1382 GM107 [GeForce GTX 745] + 1389 GM107GL [GRID M30] + 1390 GM107M [GeForce 845M] + 1391 GM107M [GeForce GTX 850M] + 17aa 3697 GeForce GTX 850A + 17aa a125 GeForce GTX 850A + 1392 GM107M [GeForce GTX 860M] + 1393 GM107M [GeForce 840M] + 1398 GM107M [GeForce 845M] + 139a GM107M [GeForce GTX 950M] + 139b GM107M [GeForce GTX 960M] + 139c GM107M [GeForce 940M] + 13b0 GM107GLM [Quadro M2000M] + 13b1 GM107GLM [Quadro M1000M] + 13b2 GM107GLM [Quadro M600M] + 13b3 GM107GLM [Quadro K2200M] + 13ba GM107GL [Quadro K2200] + 13bb GM107GL [Quadro K620] + 13bc GM107GL [Quadro K1200] + 13bd GM107GL [GRID M40] + 13c0 GM204 [GeForce GTX 980] + 1043 8504 GTX980-4GD5 + 13c1 GM204 + 13c2 GM204 [GeForce GTX 970] + 13c3 GM204 + 13d7 GM204M [GeForce GTX 980M] + 13d8 GM204M [GeForce GTX 970M] + 13d9 GM204M [GeForce GTX 965M] + 13f0 GM204GL [Quadro M5000] + 13f1 GM204GL [Quadro M4000] + 13f2 GM204GL [Tesla M60] + 1401 GM206 [GeForce GTX 960] + 1617 GM204M [GeForce GTX 980M] + 1618 GM204M [GeForce GTX 970M] + 1619 GM204M [GeForce GTX 965M] + 17c2 GM200 [GeForce GTX TITAN X] + 17c8 GM200 [GeForce GTX 980 Ti] + 17f0 GM200GL [Quadro M6000] 10df Emulex Corporation 0720 OneConnect NIC (Skyhawk) + 103c 1934 HP FlexFabric 20Gb 2-port 650M Adapter + 103c 1935 HP FlexFabric 20Gb 2-port 650FLB Adapter + 103c 21d4 HP StoreFabric CN1200E 10Gb Converged Network Adapter + 103c 220a HP FlexFabric 10Gb 2-port 556FLR-SFP+ Adapter + 103c 803f HP Ethernet 10Gb 2-port 557SFP+ Adapter + 17aa 1056 ThinkServer OCm14102-UX-L AnyFabric + 17aa 1057 ThinkServer OCm14104-UX-L AnyFabric + 17aa 1059 ThinkServer OCm14104-UT-L AnyFabric + 17aa 4014 ThinkServer OCm14102-NX-L AnyFabric 0722 OneConnect iSCSI Initiator (Skyhawk) 0723 OneConnect iSCSI Initiator + Target (Skyhawk) 0724 OneConnect FCoE Initiator (Skyhawk) @@ -7364,6 +10289,8 @@ e200 Lancer-X: LightPulse Fibre Channel Host Adapter e208 LightPulse 16Gb Fibre Channel Host Adapter (Lancer-VF) e220 OneConnect NIC (Lancer) + 17aa 1054 ThinkServer LPm16002B-M6-L AnyFabric + 17aa 1055 ThinkServer LPm16004B-M8-L AnyFabric e240 OneConnect iSCSI Initiator (Lancer) e260 OneConnect FCoE Initiator (Lancer) e268 OneConnect 10Gb FCoE Converged Network Adapter (Lancer-VF) @@ -7470,6 +10397,7 @@ 8406 PCIcanx/PCIcan CAN interface [Kvaser AB] 8407 PCIcan II CAN interface (A1021, PCB-07, PCB-08) [Kvaser AB] 8851 S5933 on Innes Corp FM Radio Capture card + e004 X-Gene PCIe bridge 10e9 Alps Electric Co., Ltd. 10ea Integraphics 1680 IGA-1680 @@ -7486,43 +10414,38 @@ 0101 3GA 8111 Twist3 Frame Grabber 10ec Realtek Semiconductor Co., Ltd. - 0139 Zonet Zen3200 - 0260 Realtek 260 High Definition Audio - 0261 Realtek 261 High Definition Audio - 0262 Realtek 262 High Definition Audio - 0269 Realtek ALC269 High Definition Audio (82801G) - 0280 Realtek 280 High Definition Audio - 0660 Realtek 660 High Definition Audio - 0662 Realtek 662 High Definition Audio - 0861 Realtek 861 High Definition Audio - 0862 Realtek 862 High Definition Audio - 0880 Realtek 880 High Definition Audio - 0883 Realtek 883 High Definition Audio - 1025 1605 TravelMate 5600 series - 0885 Realtek 885 High Definition Audio - 0888 Realtek 888 High Definition Audio - 1028 020d Inspiron 530 - 0892 Realtek 892 High Definition Audio + 0139 RTL-8139/8139C/8139C+ Ethernet Controller + 5208 RTS5208 PCI Express Card Reader 5209 RTS5209 PCI Express Card Reader + 5227 RTS5227 PCI Express Card Reader + 17aa 220e ThinkPad T440p + 17aa 2214 ThinkPad X240 5229 RTS5229 PCI Express Card Reader - 5288 Barossa PCI Express Card Reader + 1025 0813 Aspire R7-571 + 103c 194e ProBook 455 G1 Notebook + 5249 RTS5249 PCI Express Card Reader + 103c 1909 ZBook 15 + 5288 RTS5288 PCI Express Card Reader + 5289 RTL8411 PCI Express Card Reader + 1043 1457 K55A Laptop 8029 RTL-8029(AS) 10b8 2011 EZ-Card (SMC1208) 10ec 8029 RTL-8029(AS) 1113 1208 EN1208 1186 0300 DE-528 1259 2400 AT-2400 - 1af4 1100 Qemu virtual machine + 1af4 1100 QEMU Virtual Machine 8129 RTL-8129 10ec 8129 RT8129 Fast Ethernet Adapter - 11ec 8129 RT8129 Fast Ethernet Adapter + 11ec 8129 RTL8111/8168 PCIe Gigabit Ethernet (misconfigured) 8136 RTL8101E/RTL8102E PCI Express Fast Ethernet controller - 103c 2ab1 Pavillion p6774 + 103c 2ab1 Pavilion p6774 103c 30cc Pavilion dv6700 1179 ff64 RTL8102E PCI-E Fast Ethernet NIC + 17c0 1053 AzureWave AW-NE766 802.11B/G/N Mini PCIe Card Model RT2700E 8138 RT8139 (B/C) Cardbus Fast Ethernet Adapter 10ec 8138 RT8139 (B/C) Fast Ethernet Adapter - 8139 RTL-8139/8139C/8139C+ + 8139 RTL-8100/8101L/8139 PCI Fast Ethernet Adapter 0357 000a TTP-Monitoring Card V2.0 1025 005a TravelMate 290 1025 8920 ALN-325 @@ -7534,8 +10457,10 @@ 1043 8109 P5P800-MX Mainboard 1071 8160 MIM2000 10bd 0320 EP-320X-R + 10ec 8139 RTL-8100/8101L/8139 PCI Fast Ethernet Adapter 10f7 8338 Panasonic CF-Y5 laptop - 1113 ec01 FNC-0107TX + 1113 ec01 LevelOne FNC-0107TX/FNC-0109TX + 1186 1104 DFE-520TX Fast Ethernet PCI Adapter (rev. D1) 1186 1300 DFE-538TX 1186 1320 SN5200 1186 8139 DRN-32TX @@ -7566,6 +10491,7 @@ 1799 5010 F5D5010 CardBus Notebook Network Card 187e 3303 FN312 1904 8139 RTL8139D Fast Ethernet Adapter + 1af4 1100 QEMU Virtual Machine 2646 0001 KNE120TX 8e2e 7000 KF-230TX 8e2e 7100 KF-230TX/2 @@ -7574,25 +10500,32 @@ 1458 e000 GA-MA69G-S3H Motherboard 1462 235c P965 Neo MS-7235 mainboard 1462 236c 945P Neo3-F motherboard - 8168 RTL8111/8168B PCI Express Gigabit Ethernet controller - 1019 8168 MCP73PVT-SM + 8168 RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller + 1019 8168 RTL8111/8168 PCI Express Gigabit Ethernet controller + 1028 0283 Vostro 220 1028 04b2 Vostro 3350 1028 04da Vostro 3750 103c 1611 Pavilion DM1Z-3000 + 103c 1950 ProBook 450/455 + 103c 2a6f Asus IPIBL-LB Motherboard 1043 11f5 A6J-Q008 1043 16d5 U6V/U31J laptop 1043 81aa P5B 1043 82c6 M3A78-EH Motherboard 1043 83a3 M4A785TD Motherboard 1043 8432 P8P67 and other motherboards - 10ec 8168 TEG-ECTX Gigabit PCI-E Adapter [Trendnet] - 1458 e000 GA-EP45-DS5/GA-EG45M-DS2H Motherboard + 1043 8505 P8 series motherboard + 105b 0d7c D270S/D250S Motherboard + 10ec 8168 RTL8111/8168 PCI Express Gigabit Ethernet controller + 1458 e000 Motherboard 1462 238c Onboard RTL8111b on MSI P965 Platinum Mainboard 1462 368c K9AG Neo2 + 1462 4180 Wind PC MS-7418 1462 7522 X58 Pro-E 1775 11cc CC11/CL11 1849 8168 Motherboard (one of many) - 8086 d615 Desktop Board D510MO + 7470 3468 TG-3468 Gigabit PCI Express Network Adapter + 8086 d615 Desktop Board D510MO/D525MW 8169 RTL8169 PCI Gigabit Ethernet Controller 1025 0079 Aspire 5024WLMi 10bd 3202 EP-320G-TX1 32-bit PCI Gigabit Ethernet Adapter @@ -7600,6 +10533,7 @@ 1259 c107 CG-LAPCIGT 1371 434e ProG-2000L 1385 311a GA311 + 1385 5200 GA511 Gigabit PC Card 1458 e000 GA-8I915ME-G Mainboard 1462 030c K8N Neo-FSR v2.0 mainboard 1462 065c Hetis 865GV-E (MS-7065) @@ -7614,19 +10548,26 @@ 8174 RTL8192SE Wireless LAN Controller 8176 RTL8188CE 802.11b/g/n WiFi Adapter 1a3b 1139 AW-NE139H Half-size Mini PCIe Card - 8177 RTL8188CE 802.11b/g/n WiFi Adapter - 8178 RTL8188CE 802.11b/g/n WiFi Adapter + 8177 RTL8191CE PCIe Wireless Network Adapter + 8178 RTL8192CE PCIe Wireless Network Adapter + 8179 RTL8188EE Wireless Network Adapter 8180 RTL8180L 802.11b MAC 1385 4700 MA521 802.11b Wireless PC Card 1737 0019 WPC11v4 802.11b Wireless-B Notebook Adapter 8185 RTL-8185 IEEE 802.11a/b/g Wireless LAN Controller - 8190 RTL8190 802.11n Wireless LAN - 8191 RTL8188CE 802.11b/g/n WiFi Adapter + 818b RTL8192EE PCIe Wireless Network Adapter + 8190 RTL8190 802.11n PCI Wireless Network Adapter + 8191 RTL8192CE PCIe Wireless Network Adapter 8192 RTL8192E/RTL8192SE Wireless LAN Controller 8193 RTL8192DE Wireless LAN Controller 8197 SmartLAN56 56K Modem 8199 RTL8187SE Wireless LAN Controller 1462 6894 MN54G2 / MS-6894 Wireless Mini PCIe Card + 8723 RTL8723AE PCIe Wireless Network Adapter + 8812 RTL8812AE 802.11ac PCIe Wireless Network Adapter + 8813 RTL8813AE 802.11ac PCIe Wireless Network Adapter + 8821 RTL8821AE 802.11ac PCIe Wireless Network Adapter + b723 RTL8723BE PCIe Wireless Network Adapter 10ed Ascii Corporation 7310 V7310 10ee Xilinx Corporation @@ -7719,8 +10660,10 @@ 1102 0053 SB0090 Audigy Player/OEM 1102 0058 SB0090 Audigy Player/OEM 1102 1002 SB Audigy2 Platinum + 1102 1003 SB0350 Audigy 2 1102 1007 SB0240 Audigy 2 Platinum 6.1 1102 1009 SB Audigy2 OEM HP + 1102 2001 SB Audigy 2 ZS Platinum Pro 1102 2002 SB Audigy 2 ZS (SB0350) 1102 4001 E-MU 1010 1102 4002 E-MU 0404 @@ -7744,8 +10687,9 @@ 0009 [SB X-Fi Xtreme Audio] CA0110-IBG 1102 0010 [SB X-Fi Xtreme Audio] CA0110-IBG 1102 0018 SB1040 - 000b X-Fi Titanium series [EMU20k2] - 1102 0041 SB X-Fi Titanium PCI-e [SB0880] + 000b EMU20k2 [X-Fi Titanium Series] + 1102 0041 SB0880 [SoundBlaster X-Fi Titanium PCI-e] + 0012 SB Recon3D 4001 SB Audigy FireWire Port 1102 0010 SB Audigy FireWire Port 7002 SB Live! Game Port @@ -7757,7 +10701,7 @@ 7005 SB Audigy LS Game Port 1102 1001 SB0310 Audigy LS MIDI/Game port 1102 1002 SB0312 Audigy LS MIDI/Game port - 7006 [SB X-Fi Xtreme Audio] CA0110-IBG PCI to PCIe Bridge + 7006 [SB X-Fi Xtreme Audio] CA0110-IBG PCIe to PCI Bridge 8938 Ectiva EV1938 1033 80e5 SlimTower-Jim (NEC) 1071 7150 Mitac 7150 @@ -7790,10 +10734,16 @@ 0620 RocketRAID 620 2 Port SATA-III Controller 0622 RocketRAID 622 2 Port SATA-III Controller 0640 RocketRAID 640 4 Port SATA-III Controller + 0641 RocketRAID 640L 4 Port SATA-III Controller + 0642 RocketRAID 642L SATA-III Controller (2 eSATA ports + 2 internal SATA ports) + 0644 RocketRAID 644 4 Port SATA-III Controller (eSATA) + 0645 RocketRAID 644L 4 Port SATA-III Controller (eSATA) + 0646 RocketRAID 644LS SATA-III Controller (4 eSATA devices connected by 1 SAS cable) 1720 RocketRAID 1720 (2x SATA II RAID Controller) 1740 RocketRAID 1740 1742 RocketRAID 1742 2210 RocketRAID 2210 SATA-II Controller + 11ab 11ab 88SX6042 2300 RocketRAID 230x 4 Port SATA-II Controller 2310 RocketRAID 2310 4 Port SATA-II Controller 2320 RocketRAID 2320 SATA-II Controller @@ -7849,6 +10799,7 @@ 147b a401 KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard 0308 PT880 Ultra/PT894 Host Bridge 1043 8199 P4V800D-X Mainboard + 1849 0308 Motherboard 0314 CN700/VN800/P4M800CE/Pro Host Bridge 0324 CX700/VX700 Host Bridge 0327 P4M890 Host Bridge @@ -7859,13 +10810,10 @@ 0364 CN896/VN896/P4M900 Host Bridge 1043 81ce P5VD2-VM mothervoard 0391 VT8371 [KX133] - 0397 VT1708S HD Audio - 1043 836c P7H55 - 1043 83c7 P5KPL-AM EPU 0409 VX855/VX875 Host Bridge: Host Control 0410 VX900 Host Bridge: Host Control 0415 VT6415 PATA IDE Host Controller - 1043 838f M5A88-V EVO + 1043 838f Motherboard 0501 VT8501 [Apollo MVP4] 0505 VT82C505 # Shares chip with :0576. The VT82C576M has :1571 instead of :0561. @@ -7887,7 +10835,8 @@ 1462 7120 KT4AV motherboard 1462 7181 K8MM3-V mainboard 147b 1407 KV8-MAX3 motherboard - 1849 0571 K7VT2/K7VT6 motherboard +# probably all K7VT2/4*/6 + 1849 0571 K7VT series Motherboards 0576 VT82C576 3V [Apollo Master] 0581 CX700/VX700 RAID Controller # Upgrade bios to get correct ID: 5324 instead of 0581 @@ -7925,6 +10874,12 @@ 1458 0691 VT82C691 Apollo Pro System Controller 0693 VT82C693 [Apollo Pro Plus] 0698 VT82C693A [Apollo Pro133 AGP] + 0709 VX11 Standard Host Bridge + 070a VX11 PCI Express Root Port + 070b VX11 PCI Express Root Port + 070c VX11 PCI Express Root Port + 070d VX11 PCI Express Root Port + 070e VX11 PCI Express Root Port 0926 VT82C926 [Amazon] 1000 VT82C570MV 1106 VT82C570MV @@ -7981,9 +10936,8 @@ 287d VT8251 PCIE Root Port 287e VT8237/8251 Ultra VLINK Controller 3022 CLE266 - 3038 VT82xxxxx UHCI USB 1.1 Controller -# possibly Hewlett-Packard D9840-60001 [Brio BA410 Motherboard] - 0925 1234 VA-502 Mainboard + 3038 VT82xx/62xx UHCI USB 1.1 Controller + 0925 1234 onboard UHCI USB 1.1 Controller 1019 0985 P6VXA Motherboard 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) 1043 8080 A7V333 motherboard @@ -7999,20 +10953,22 @@ 1462 7181 K8MM3-V mainboard 147b 1407 KV8-MAX3 motherboard 182d 201d CN-029 USB2.0 4 port PCI Card - 1849 3038 K7VT6 +# probably all K7VT2/4*/6 + 1849 3038 K7VT series Motherboards 19da a179 ZBOX nano VD01 + 1af4 1100 QEMU Virtual Machine 3040 VT82C586B ACPI 3043 VT86C100A [Rhine] 10bd 0000 VT86C100A Fast Ethernet Adapter 1106 0100 VT86C100A Fast Ethernet Adapter - 1186 1400 DFE-530TX rev A + 1186 1400 DFE-530TX PCI Fast Ethernet Adapter (rev. A) 3044 VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller 0010 0001 IEEE 1394 4port DCST 1394-3+1B 1025 005a TravelMate 290 103c 2a20 Pavilion t3030.de Desktop PC 103c 2a3b Media Center PC m7590n - 1043 808a A8V/A8N/P4P800 series motherboard - 1043 81fe M4A series motherboard + 1043 808a A8V/A8N/P4P800/P5SD2 series motherboard + 1043 81fe Motherboard 1458 1000 GA-7VT600-1394 Motherboard 1462 207d K8NGM2 series motherboard 1462 217d Aspire L250 @@ -8022,6 +10978,7 @@ 3050 VT82C596 Power Management 3051 VT82C596 Power Management 3053 VT6105M [Rhine-III] + 1186 1404 DFE-530TX PCI Fast Ethernet Adapter (rev. D) 3057 VT82C686 [Apollo Super ACPI] 1019 0985 P6VXA Motherboard 1019 0987 K7VZA Motherboard @@ -8044,9 +11001,11 @@ 1462 3091 MS-6309 Onboard Audio 1462 3092 MS-6309 v2.x Mainboard (VIA VT1611A codec) 1462 3300 MS-6330 Onboard Audio + 1462 3400 MS-6340 (VT8363) motherboard 15dd 7609 Onboard Audio 3059 VT8233/A/8235/8237 AC97 Audio Controller 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) + 1019 1841 M811 (VT8367/VT8235/VT6103) [KT333] motherboard 1019 1877 K8M800-M2 (V2.0) onboard audio 1043 8095 A7V8X Motherboard (Realtek ALC650 codec) 1043 80a1 A7V8X-X Motherboard @@ -8066,26 +11025,28 @@ 1462 5901 KT6 Delta-FIS2R (MS-6590) 1462 7181 K8MM3-V mainboard 147b 1407 KV8-MAX3 motherboard - 1695 300c EP-8KRA2+ Mainboard + 1695 300c Realtek ALC655 audio on EP-8KRA series mainboard 1849 0850 ASRock 775Dual-880 Pro onboard audio (Realtek ALC850) 1849 9739 P4VT8 Mainboard (C-Media CMI9739A codec) - 1849 9761 K7VT6 motherboard +# probably all K7VT2/4*/6 + 1849 9761 K7VT series Motherboards 4005 4710 MSI K7T266 Pro2-RU (MSI-6380 v2) onboard audio (Realtek/ALC 200/200P) a0a0 01b6 AK77-8XN onboard audio a0a0 0342 AK86-L motherboard - 3065 VT6102 [Rhine-II] + 3065 VT6102/VT6103 [Rhine-II] 1043 80a1 A7V8X-X Motherboard 1043 80ed A7V600-X Motherboard - 1106 0102 VT6102 [Rhine II] Embeded Ethernet Controller on VT8235 - 1186 1400 DFE-530TX rev A - 1186 1401 DFE-530TX rev B + 1106 0102 VT6102/6103 [Rhine II] Ethernet Controller + 1186 1400 DFE-530TX PCI Fast Ethernet Adapter (rev. A) + 1186 1401 DFE-530TX PCI Fast Ethernet Adapter (rev. B) + 1186 1402 DFE-530TX PCI Fast Ethernet Adapter (rev. B) 13b9 1421 LD-10/100AL PCI Fast Ethernet Adapter (rev.B) 1462 7061 MS-7061 1462 7181 K8MM3-V mainboard 147b 1c09 NV7 Motherboard 1695 3005 VT6103 - 1695 300c Realtek ALC655 sound chip - 1849 3065 K7VT6 motherboard +# probably all K7VT2/4*/6 + 1849 3065 K7VT series Motherboards # This hosts more than just the Intel 537 codec, it also hosts PCtel (SIL33) and SmartLink (SIL34) codecs 3068 AC'97 Modem Controller 1462 309e MS-6309 Saturn Motherboard @@ -8093,6 +11054,7 @@ 1043 8052 VT8233A 3091 VT8633 [Apollo Pro266] 3099 VT8366/A/7 [Apollo KT266/A/333] + 1019 1841 M811 (VT8367/VT8235/VT6103) [KT333] motherboard 1043 8064 A7V266-E Mainboard 1043 807f A7V333 Mainboard 1849 3099 K7VT2 motherboard @@ -8100,10 +11062,12 @@ 3102 VT8662 Host Bridge 3103 VT8615 Host Bridge 3104 USB 2.0 + 0925 1234 onboard EHCI USB 2.0 Controller 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) 1043 808c A7V8X motherboard 1043 80a1 A7V8X-X motherboard rev 1.01 1043 80ed A7V600/K8V-X/A8V Deluxe motherboard + 1106 3104 USB 2.0 Controller 1297 f641 FX41 motherboard 1458 5004 GA-7VAX Mainboard 1462 5901 KT6 Delta-FIS2R (MS-6590) @@ -8113,11 +11077,13 @@ 1462 7181 K8MM3-V mainboard 147b 1407 KV8-MAX3 motherboard 182d 201d CN-029 USB 2.0 4 port PCI Card - 1849 3104 K7VT6 motherboard +# probably all K7VT2/4*/6 + 1849 3104 K7VT series Motherboards 19da a179 ZBOX nano VD01 3106 VT6105/VT6106S [Rhine-III] 1106 0105 VT6106S [Rhine-III] - 1186 1403 DFE-530TX rev C + 1186 1403 DFE-530TX PCI Fast Ethernet Adapter (rev. C) + 1186 1405 DFE-520TX Fast Ethernet PCI Adapter 1186 1406 DFE-530TX+ rev F2 1186 1407 DFE-538TX 3108 K8M800/K8N800/K8N800A [S3 UniChrome Pro] @@ -8156,12 +11122,14 @@ 1849 3168 P4VT8 Mainboard 3177 VT8235 ISA Bridge 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) + 1019 1841 M811 (VT8367/VT8235/VT6103) [KT333] motherboard 1043 808c A7V8X motherboard 1043 80a1 A7V8X-X motherboard 1106 0000 KT4AV motherboard 1297 f641 FX41 motherboard 1458 5001 GA-7VAX Mainboard - 1849 3177 K7VT2 motherboard +# probably all K7VT2/4*/6 + 1849 3177 K7VT series Motherboards 3178 ProSavageDDR P4N333 Host Bridge 3188 VT8385 [K8T800 AGP] Host Bridge 1043 80a3 K8V Deluxe/K8V-X motherboard @@ -8170,7 +11138,16 @@ 1043 807f A7V8X motherboard 1106 0000 KT4AV motherboard (KT400A) 1458 5000 GA-7VAX Mainboard - 1849 3189 K7VT6 motherboard +# probably all K7VT2/4*/6 + 1849 3189 K7VT series Motherboards + 31b0 VX11 Standard Host Bridge + 31b1 VX11 Standard Host Bridge + 31b2 VX11 DRAM Controller + 31b3 VX11 Power Management Controller + 31b4 VX11 I/O APIC + 31b5 VX11 Scratch Device + 31b7 VX11 Standard Host Bridge + 31b8 VX11 PCI to PCI Bridge 3204 K8M800 Host Bridge 3205 VT8378 [KM400/A] Chipset Host Bridge 1458 5000 GA-7VM400M Motherboard @@ -8186,6 +11163,7 @@ 3230 K8M890CE/K8N890CE [Chrome 9] 3238 K8T890 Host Bridge 3249 VT6421 IDE/SATA Controller + 1106 3249 VT6421 IDE/SATA Controller 324a CX700/VX700 PCI to PCI Bridge 324b CX700/VX700 Host Bridge 324e CX700/VX700 Internal Module Bus @@ -8221,6 +11199,11 @@ 3409 VX855/VX875 DRAM Bus Control 3410 VX900 DRAM Bus Control 19da a179 ZBOX nano VD01 + 3432 VL80x xHCI USB 3.0 Controller + 3456 VX11 Standard Host Bridge + 345b VX11 Miscellaneous Bus + 3483 VL805 USB 3.0 Host Controller + 3a01 VX11 Graphics [Chrome 645/640] 4149 VIA VT6420 (ATA133) Controller 4204 K8M800 Host Bridge 4208 PT890 Host Bridge @@ -8241,11 +11224,9 @@ 4351 VT3351 Host Bridge 4353 VX800/VX820 Power Management Control 4364 CN896/VN896/P4M900 Host Bridge - 4397 VT1708B/1702S/1708S HD audio codec 4409 VX855/VX875 Power Management Control 4410 VX900 Power Management and Chip Testing Control 19da a179 ZBOX nano VD01 - 4428 VT1718S HD Audio Codec 5030 VT82C596 ACPI [Apollo PRO] 5122 VX855/VX875 Chrome 9 HCM Integrated Graphics 5208 PT890 I/O APIC Interrupt Controller @@ -8323,6 +11304,9 @@ 8d01 PN133/PN133T [S3 Twister] 8d04 KM266/P4M266/P4M266A/P4N266 [S3 ProSavageDDR] 9001 VX900 Serial ATA Controller + 9082 Standard AHCI 1.0 SATA Controller + 9140 HDMI Audio Device + 9201 USB3.0 Controller 9530 Secure Digital Memory Card Controller 95d0 SDIO Host Controller a208 PT890 PCI to PCI Bridge Controller @@ -8331,6 +11315,7 @@ a353 VX8xx South-North Module Interface Control a364 CN896/VN896/P4M900 PCI to PCI Bridge Controller a409 VX855/VX875 USB Device Controller + a410 VX900 PCI Express Root Port 0 b091 VT8633 [Apollo Pro266 AGP] b099 VT8366/A/7 [Apollo KT266/A/333 AGP] b101 VT8653 AGP Bridge @@ -8345,6 +11330,7 @@ b198 VT8237/VX700 PCI Bridge b213 VPX/VPX2 I/O APIC Interrupt Controller b353 VX855/VX875/VX900 PCI to PCI Bridge + b410 VX900 PCI Express Root Port 1 b999 [K8T890 North / VT8237 South] PCI Bridge c208 PT890 PCI to PCI Bridge Controller c238 K8T890 PCI to PCI Bridge Controller @@ -8353,16 +11339,18 @@ c353 VX800/VX820 PCI Express Root Port c364 CN896/VN896/P4M900 PCI to PCI Bridge Controller c409 VX855/VX875 EIDE Controller + c410 VX900 PCI Express Root Port 2 d104 VT8237R USB UDCI Controller d208 PT890 PCI to PCI Bridge Controller d213 VPX/VPX2 PCI to PCI Bridge Controller d238 K8T890 PCI to PCI Bridge Controller d340 PT900 PCI to PCI Bridge Controller + d410 VX900 PCI Express Root Port 3 e208 PT890 PCI to PCI Bridge Controller e238 K8T890 PCI to PCI Bridge Controller e340 PT900 PCI to PCI Bridge Controller e353 VX800/VX820 PCI Express Root Port - e721 VT1708B 8-channel High Definition Audio CODEC + e410 VX900 PCI Express Physical Layer Electrical Sub-block f208 PT890 PCI to PCI Bridge Controller f238 K8T890 PCI to PCI Bridge Controller f340 PT900 PCI to PCI Bridge Controller @@ -8380,7 +11368,7 @@ 013d P1690Plus 1109 Cogent Data Technologies, Inc. 1400 EM110TX [EX110TX] -110a Siemens Nixdorf AG +110a Siemens AG 0002 Pirahna 2-port 0005 Tulip controller, power management, switch extender 0006 FSC PINC (I/O-APIC) @@ -8393,10 +11381,24 @@ # Superfastcom-PCI (Commtech, Inc.) or DSCC4 WAN Adapter 2102 DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels 2104 Eicon Diva 2.02 compatible passive ISDN card - 3141 SIMATIC NET CP 5611 (Profibus Adapter) - 3142 SIMATIC NET CP 5613A1 (Profibus Adapter) + 3141 SIMATIC NET CP 5611 / 5621 + 3142 SIMATIC NET CP 5613 / 5614 + 3143 SIMATIC NET CP 1613 4021 SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter) - 4029 SIMATIC NET CP 5613A2 (Profibus Adapter) + 4029 SIMATIC NET CP 5613 A2 + 110a 4029 SIMATIC NET CP 5613 A2 + 110a c029 SIMATIC NET CP 5614 A2 + 4035 SIMATIC NET CP 1613 A2 + 4036 SIMATIC NET CP 1616 + 4038 SIMATIC NET CP 1604 + 4069 SIMATIC NET CP 5623 + 110a 4069 SIMATIC NET CP 5623 + 110a c069 SIMATIC NET CP 5624 + 407c SIMATIC NET CP 5612 + 407d SIMATIC NET CP 5613 A3 + 407e SIMATIC NET CP 5622 + 4083 SIMATIC NET CP 5614 A3 + 4084 SIMATIC NET CP 1626 4942 FPGA I-Bus Tracer for MBD 6120 SZB6120 110b Chromatic Research Inc. @@ -8544,7 +11546,7 @@ 111b Teledyne Electronic Systems 111c Tricord Systems Inc. 0001 Powerbis Bridge -111d Integrated Device Technology, Inc. +111d Integrated Device Technology, Inc. [IDT] 0001 IDT77201/77211 155Mbps ATM SAR Controller [NICStAR] 0003 IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller 0004 IDT77V252 155Mbps ATM MICRO ABR SAR Controller @@ -8590,6 +11592,18 @@ 806c PES16T4A/4T4G2 PCI Express Gen2 Switch 806e PES24T6G2 PCI Express Gen2 Switch 806f HIO524G2 PCI Express Gen2 Switch + 8088 PES32NT8BG2 PCI Express Switch + 1093 752f PXIe-8383mc Device + 1093 7543 PXIe-8383mc System Host + 1093 755c PXIe-8364 + 1093 755d PXIe-8374 + 1093 75ff PXIe-8383mc DMA + 1093 7600 PXIe-8383mc DMA + 1093 7602 PXIe-8384 +# 32 port / 8 lane PCIe Gen 2 packet switch + 808f PES32NT8AG2 + 80cf F32P08xG3 [PCIe boot mode] + 80d2 F32P08xG3 NVMe controller 111e Eldec 111f Precision Digital Images 4a47 Precision MX Video engine interface @@ -8693,6 +11707,7 @@ 1421 1370 Instant TV (saa7135) 1435 7330 VFG7330 1435 7350 VFG7350 + 1458 9001 GC-PTV-TAF Hybrid TV card 1458 9002 GT-PTV-TAF-RH DVB-T/Analog TV/FM tuner 1458 9003 GT-PTV-AF-RH Analog TV/FM tuner 1458 9004 GT-P8000 DVB-T/Analog TV/FM tuner @@ -8711,6 +11726,7 @@ 14c0 1212 LifeView FlyTV Platinum Mini2 153b 1160 Cinergy 250 PCI TV 153b 1162 Terratec Cinergy 400 mobile + 17de 7256 PlusTV All In One PI610 card 17de 7350 ATSC 110 Digital / Analog HDTV Tuner 17de 7352 ATSC 115 Digital / Analog HDTV Tuner 185b c100 VideoMate TV @@ -8735,7 +11751,12 @@ 5ace 6193 Behold TV M6 Extra 5ace 6290 Behold TV H6 5ace 7090 Behold TV A7 + 5ace 7150 Behold TV H75 + 5ace 7151 Behold TV H75 5ace 7190 Behold TV H7 + 5ace 7191 Behold TV H7 + 5ace 7290 Behold TV T7 + 5ace 7591 Behold TV X7 5ace 7595 Behold TV X7 7134 SAA7134/SAA7135HL Video Broadcast Decoder 0000 4036 Behold TV 403 @@ -8767,6 +11788,7 @@ 1894 a006 KNC One TV-Station DVR 1894 fe01 KNC One TV-Station RDS / Typhoon TV Tuner RDS 5168 0138 FLY TV PRIME 34FM + 5168 0300 FlyDVB-S 5ace 5070 Behold TV 507 FM 5ace 6070 Behold TV 607 FM 5ace 6071 Behold TV 607 FM @@ -8808,12 +11830,16 @@ 13c2 1019 S2-3200 13c2 1102 Technotrend/Hauppauge DVB card rev2.1 153b 1155 Cinergy 1200 DVB-S - 153b 1156 Terratec Cynergy 1200C + 153b 1156 Cinergy 1200 DVB-C 153b 1157 Cinergy 1200 DVB-T + 153b 1176 Cinergy 1200 DVB-C (MK3) 1894 0020 KNC One DVB-C V1.0 1894 0023 TVStation DVB-C plus +# http://www.knc1.com/gb.htm + 1894 0054 TV-Station DVB-S 7160 SAA7160 1458 9009 E8000 DVB-T/Analog TV/FM tuner + 1461 1455 AVerTV Hybrid Speedy PCI-E (H788) 7162 SAA7162 11bd 0101 Pinnacle PCTV 7010iX TV Card 7164 SAA7164 @@ -8835,9 +11861,18 @@ 0070 8993 WinTV HVR-2200 0070 89a0 WinTV HVR-2200 0070 89a1 WinTV HVR-2200 + 0070 f120 WinTV HVR-2205 + 0070 f123 WinTV HVR-2215 7231 SAA7231 5ace 8000 Behold TV H8 + 5ace 8001 Behold TV H8 + 5ace 8050 Behold TV H85 + 5ace 8051 Behold TV H85 5ace 8100 Behold TV A8 + 5ace 8101 Behold TV A8 + 5ace 8150 Behold TV A85 + 5ace 8151 Behold TV A85 + 5ace 8201 Behold TV T8 9730 SAA9730 Integrated Multimedia and Peripheral Controller 1131 0000 Integrated Multimedia and Peripheral Controller 1132 Mitel Corp. @@ -8945,26 +11980,76 @@ 1137 Cisco Systems Inc 0023 VIC 81 PCIe Upstream Port 0040 VIC PCIe Upstream Port + 1137 004f VIC 1280 Dual 40Gb Mezzanine + 1137 0084 VIC 1240 Dual 40Gb MLOM + 1137 0085 VIC 1225 Dual 10Gb SFP+ PCIe + 1137 00cd VIC 1285 Dual 40Gb QSFP+ PCIe + 1137 00ce VIC 1225T Dual 10GBaseT PCIe + 1137 012a VIC M4308 Dual 40Gb + 1137 012c VIC 1340 Dual 40Gb MLOM + 1137 012e VIC 1227 Dual 10Gb SFP+ PCIe + 1137 0137 VIC 1380 Dual 40Gb Mezzanine 0041 VIC PCIe Downstream Port 0042 VIC Management Controller 1137 0047 VIC P81E PCIe Management Controller + 1137 0085 VIC 1225 PCIe Management Controller + 1137 00cd VIC 1285 PCIe Management Controller + 1137 00ce VIC 1225T PCIe Management Controller + 1137 012e VIC 1227 PCIe Management Controller 0043 VIC Ethernet NIC 1137 0047 VIC P81E PCIe Ethernet NIC 1137 0048 VIC M81KR Mezzanine Ethernet NIC 1137 004f VIC 1280 Mezzanine Ethernet NIC 1137 0084 VIC 1240 MLOM Ethernet NIC 1137 0085 VIC 1225 PCIe Ethernet NIC + 1137 00cd VIC 1285 PCIe Ethernet NIC + 1137 00ce VIC 1225T PCIe Ethernet NIC + 1137 012a VIC M4308 Ethernet NIC + 1137 012c VIC 1340 MLOM Ethernet NIC + 1137 012e VIC 1227 PCIe Ethernet NIC + 1137 0137 VIC 1380 Mezzanine Ethernet NIC 0044 VIC Ethernet NIC Dynamic 1137 0047 VIC P81E PCIe Ethernet NIC Dynamic 1137 0048 VIC M81KR Mezzanine Ethernet NIC Dynamic 1137 004f VIC 1280 Mezzanine Ethernet NIC Dynamic 1137 0084 VIC 1240 MLOM Ethernet NIC Dynamic 1137 0085 VIC 1225 PCIe Ethernet NIC Dynamic + 1137 00cd VIC 1285 PCIe Ethernet NIC Dynamic + 1137 00ce VIC 1225T PCIe Ethernet NIC Dynamic + 1137 012a VIC M4308 Ethernet NIC Dynamic + 1137 012c VIC 1340 MLOM Ethernet NIC Dynamic + 1137 012e VIC 1227 PCIe Ethernet NIC Dynamic + 1137 0137 VIC 1380 Mezzanine Ethernet NIC Dynamic 0045 VIC FCoE HBA 1137 0047 VIC P81E PCIe FCoE HBA 1137 0048 VIC M81KR Mezzanine FCoE HBA 1137 004f VIC 1280 Mezzanine FCoE HBA + 1137 0084 VIC 1240 MLOM FCoE HBA + 1137 0085 VIC 1225 PCIe FCoE HBA + 1137 00cd VIC 1285 PCIe FCoE HBA + 1137 00ce VIC 1225T PCIe FCoE HBA + 1137 012a VIC M4308 FCoE HBA + 1137 012c VIC 1340 MLOM FCoE HBA + 1137 012e VIC 1227 PCIe FCoE HBA + 1137 0137 VIC 1380 Mezzanine FCoE HBA + 0046 VIC SCSI Controller + 1137 012a VIC M4308 SCSI Controller 004e VIC 82 PCIe Upstream Port + 0071 VIC SR-IOV VF + 007a VIC 1300 PCIe Upstream Port + 1137 012a VIC M4308 Dual 40Gb + 1137 012c VIC 1340 Dual 40Gb MLOM + 1137 0137 VIC 1380 Dual 40Gb Mezzanine + 00cf VIC Userspace NIC + 1137 004f VIC 1280 Mezzanine Userspace NIC + 1137 0084 VIC 1240 MLOM Userspace NIC + 1137 0085 VIC 1225 PCIe Userspace NIC + 1137 00cd VIC 1285 PCIe Userspace NIC + 1137 00ce VIC 1225T PCIe Userspace NIC + 1137 012a VIC M4308 Userspace NIC + 1137 012c VIC 1340 MLOM Userspace NIC + 1137 012e VIC 1227 PCIe Userspace NIC + 1137 0137 VIC 1380 Mezzanine Userspace NIC 1138 Ziatech Corporation 8905 8905 [STD 32 Bridge] 1139 Dynamic Pictures, Inc @@ -9352,6 +12437,7 @@ 0617 ToPIC100 PCI to Cardbus Bridge with ZV Support 0618 CPU to PCI and PCI to ISA bridge 0701 FIR Port Type-O + 0803 TC6371AF SD Host Controller 0804 TC6371AF SmartMedia Controller 0805 SD TypA Controller 0d01 FIR Port Type-DO @@ -9359,13 +12445,18 @@ 117a A-Trend Technology 117b L G Electronics, Inc. 117c ATTO Technology, Inc. - 002c SAS RAID Adapter + 002c ExpressSAS R380 + 002d ExpressSAS R348 0030 Ultra320 SCSI Host Adapter 117c 8013 ExpressPCI UL4D 117c 8014 ExpressPCI UL4S 117c 8027 ExpressPCI UL5D 117c 802f ExpressPCI UL5D Low Profile 0033 SAS Adapter + 0041 ExpressSAS R30F + 8013 ExpressPCI UL4D + 8014 ExpressPCI UL4S + 8027 ExpressPCI UL5D 117d Becton & Dickinson 117e T/R Systems 117f Integrated Circuit Systems @@ -9391,8 +12482,9 @@ 144d c005 X10 Laptop 144d c00c P30/P35 notebook 14ef 0220 PCD-RP-220S - 17aa 201c ThinkPad X60s + 17aa 201c ThinkPad X60/X60s 17aa 20c4 ThinkPad T61 + 17aa 20c6 ThinkPad R61 0477 RL5c477 0478 RL5c478 1014 0184 ThinkPad A30p @@ -9407,9 +12499,10 @@ 1028 014f Latitude X300 laptop 1028 0188 Inspiron 6000 laptop 1043 1237 A6J-Q008 + 1043 1757 M2400N laptop 144d c005 X10 Laptop 144d c00c P30/P35 notebook - 17aa 201e ThinkPad X60s + 17aa 201e ThinkPad X60/X60s 0554 R5C554 0575 R5C575 SD Bus Host Adapter 0576 R5C576 SD Bus Host Adapter @@ -9420,6 +12513,7 @@ 103c 30b5 Presario V3242AU 103c 30b7 Presario V6133CL 103c 30cc Pavilion dv6700 + 103c 30cf Pavilion dv9668eg Laptop 1043 1237 A6J-Q008 1043 1967 V6800V 144d c018 X20 IV @@ -9437,20 +12531,25 @@ 103c 30b7 Presario V6133CL 103c 30c1 Compaq 6910p 103c 30cc Pavilion dv6700 + 103c 30cf Pavilion dv9668eg Laptop 1043 1237 A6J-Q008 1043 1967 ASUS V6800V 10f7 8338 Panasonic CF-Y5 laptop 144d c018 X20 IV - 17aa 201d ThinkPad X60s + 17aa 201d ThinkPad X60/X60s 17aa 20c7 ThinkPad T61 + 17aa 20c8 ThinkPad W500 0832 R5C832 IEEE 1394 Controller 1025 0121 Aspire 5920G 1028 01d7 XPS M1210 1028 01f3 Inspiron 1420 + 1028 024d Latitude E4300 103c 30b5 Presario V3242AU 103c 30b7 Presario V6133CL 103c 30c1 Compaq 6910p 103c 30cc Pavilion dv6700 + 103c 30cf Pavilion dv9668eg Laptop + 17aa 20c7 ThinkPad R61 0841 R5C841 CardBus/SD/SDIO/MMC/MS/MSPro/xD/IEEE1394 0843 R5C843 MMC Host Controller 1025 0121 Aspire 5920G @@ -9467,6 +12566,7 @@ 103c 30b5 Presario V3242AU 103c 30b7 Presario V6133CL 103c 30cc Pavilion dv6700 + 103c 30cf Pavilion dv9668eg Laptop 1043 1967 V6800V 1180 0852 Pavilion 2410us 1324 10cf P7120 @@ -9487,7 +12587,6 @@ 1184 Forks Inc 1185 Dataworld International Ltd 1186 D-Link System Inc - 0100 DC21041 1002 DL10050 Sundance Ethernet 1186 1002 DFE-550TX/FX 1186 1012 DFE-580TX @@ -9499,33 +12598,23 @@ 1186 1301 DFE-530TX+ 10/100 Ethernet Adapter 1186 1303 DFE-528TX 10/100 Fast Ethernet PCI Adapter 1340 DFE-690TXD CardBus PC Card - 1405 DFE-520TX Fast Ethernet PCI Adapter 1540 DFE-680TX 1541 DFE-680TXD CardBus PC Card 1561 DRP-32TXD Cardbus PC Card 3300 DWL-510 / DWL-610 802.11b [Realtek RTL8180L] 1186 3300 DWL-610 Wireless Cardbus Adapter 1186 3301 DWL-510 Wireless PCI Adapter - 3a03 AirPro DWL-A650 Wireless Cardbus Adapter(rev.B) - 3a04 AirPro DWL-AB650 Multimode Wireless Cardbus Adapter - 3a05 AirPro DWL-AB520 Multimode Wireless PCI Adapter - 3a07 AirXpert DWL-AG650 Wireless Cardbus Adapter - 3a08 AirXpert DWL-AG520 Wireless PCI Adapter 3a10 AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B) 3a11 AirXpert DWL-AG520 Wireless PCI Adapter(rev.B) - 3a12 AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C) - 3a63 AirXpert DWL-AG660 Wireless Cardbus Adapter - 3a70 DWA-556 Xtreme N PCI Express Desktop Adapter - 3c00 D-link DWL-G650X - 3c09 AirPlus G DWL-G510 4000 DL2000-based Gigabit Ethernet 4001 DGE-550SX PCI-X Gigabit Ethernet Adapter + 4200 DFE-520TX Fast Ethernet PCI Adapter + 1186 1103 DFE-520TX Fast Ethernet PCI Adapter (rev. C1) 4300 DGE-528T Gigabit Ethernet Adapter + 1186 4300 DGE-528T PCI Gigabit Ethernet Adapter # rev. B1; RealTek RTL8168E. 1186 4b10 DGE-560T PCI Express (x1) Gigabit Ethernet Adapter 4302 DGE-530T Gigabit Ethernet Adapter (rev.C1) [Realtek RTL8169] -# There are at least 3 revisions of this adapter; 4800 is board revision A1 as far as I can tell, revision B1 is 4c00. - 4800 DGE-530T Gigabit Ethernet Adapter (rev 11) 4b00 DGE-560T PCI Express Gigabit Ethernet Adapter 4b01 DGE-530T Gigabit Ethernet Adapter (rev 11) 4b02 DGE-560SX PCI Express Gigabit Ethernet Adapter @@ -9636,6 +12725,7 @@ 2a01 88W8335 [Libertas] 802.11b/g Wireless 2a02 88W8361 [TopDog] 802.11n Wireless 07d1 3b02 DIR-615 rev. A1 Mini PCI Wireless Module + 1385 7c00 WN511T RangeMax Next 300 Mbps Wireless PC Card 1385 7c01 WN511T RangeMax Next 300 Mbps Wireless Notebook Adapter 1385 7e00 WN311T RangeMax Next 300 Mbps Wireless PCI Adapter 1799 801b F5D8011 v2 802.11n N1 Wireless Notebook Card @@ -9646,7 +12736,12 @@ 2a2b 88W8687 [TopDog] 802.11b/g Wireless 2a30 88W8687 [TopDog] 802.11b/g Wireless 2a40 88W8366 [TopDog] 802.11n Wireless + 2a41 88W8366 [TopDog] 802.11n Wireless + 2a42 88W8366 [TopDog] 802.11n Wireless 2a43 88W8366 [TopDog] 802.11n Wireless + 2a55 88W8864 [Avastar] 802.11ac Wireless + 2b36 88W8764 [Avastar] 802.11n Wireless + 2b38 88W8897 [AVASTAR] 802.11ac Wireless 4101 OLPC Cafe Controller Secure Digital Controller 4320 88E8001 Gigabit Ethernet Controller 1019 0f38 Marvell 88E8001 Gigabit Ethernet Controller (ECS) @@ -9716,6 +12811,7 @@ 4353 88E8039 PCI-E Fast Ethernet Controller 104d 902d VAIO VGN-NR120E 4354 88E8040 PCI-E Fast Ethernet Controller + 144d c06a R730 Laptop 144d c072 Notebook N150P 4355 88E8040T PCI-E Fast Ethernet Controller 1179 ff50 Satellite P305D-S8995E @@ -9778,6 +12874,7 @@ a0a0 0506 Marvell 88E8053 Gigabit Ethernet Controller (Aopen) 4363 88E8055 PCI-E Gigabit Ethernet Controller 4364 88E8056 PCI-E Gigabit Ethernet Controller + 1043 81f8 Motherboard 11ba 00ba 8056 Gigabit Ethernet Controller 4365 88E8070 based Ethernet Controller 4366 88EC036 PCI-E Gigabit Ethernet Controller @@ -9808,6 +12905,7 @@ 6042 88SX6042 PCI-X 4-Port SATA-II 6081 MV88SX6081 8-port SATA II PCI-X Controller 6101 88SE6101/6102 single-port PATA133 interface + 1043 82e0 P5K PRO Motherboard 6111 88SE6111 1-port PATA133(IDE) and 1-port SATA II Controllers 6121 88SE6121 SATA II / PATA Controller 6141 88SE614x SATA II PCI-E controller @@ -9827,6 +12925,8 @@ 16b8 434b Tempo SATA E4P 7810 MV78100 [Discovery Innovation] ARM SoC 7820 MV78200 [Discovery Innovation] ARM SoC + 7823 MV78230 [Armada XP] ARM SoC + 7846 88F6820 [Armada 385] ARM SoC f003 GT-64010 Primary Image Piranha Image Generator 11ac Canon Information Systems Research Aust. 11ad Lite-On Communications Inc @@ -9848,6 +12948,7 @@ 0002 V300PSC 0292 V292PBC [Am29030/40 Bridge] 0960 V96xPBC + 880a Deltacast Delta-HD-22 c960 V96DPC 11b1 Apricot Computers 11b2 Eastman Kodak @@ -9989,9 +13090,7 @@ # InPorte Home Internal 56k Modem/fax/answering machine/SMS Features 048f V.92 56k WinModem 0620 Lucent V.92 Data/Fax Modem - 1040 HDA softmodem 2600 StarPro26XX family (SP2601, SP2603, SP2612) DSP - 3026 HDA Modem 5400 OR3TP12 FPSC 5656 Venus Modem 5801 USB @@ -9999,6 +13098,7 @@ 5803 USS-344S USB Controller 5811 FW322/323 [TrueFire] 1394a Controller 103c 2a34 Pavilion a1677c + 103c 2a6f Asus IPIBL-LB Motherboard 103c 2a9e Pavilion p6310f 1043 8294 LSI FW322/323 IEEE 1394a FireWire Controller 8086 524c D865PERL mainboard @@ -10053,19 +13153,8 @@ 11d2 Intercom Inc. 11d3 Trancell Systems Inc 11d4 Analog Devices - 0078 AD1986HD sound chip 1535 Blackfin BF535 processor 1805 SM56 PCI modem - 1889 AD1889 sound chip - 194a AD1984A sound chip - 1981 AD1981HD sound chip - 1983 AD1983HD sound chip - 1984 AD1984HD sound chip - 17aa 20bb T61p Notebook - 1986 AD1986A sound chip - 11d4 1986 Lenovo N100 B9G - 198b AD1988B Sound Chip - 5340 AD1881 sound chip 11d5 Ikon Corporation 0115 10115 0117 10117 @@ -10142,6 +13231,9 @@ 7375 PM7375 [LASAR-155 ATM SAR] 7384 PM7384 [FREEDM - 84P672 Frm Engine & Datalink Mgr] 8000 PM8000 [SPC - SAS Protocol Controller] + 8032 ATTO Celerity FC8xEN + 117c 003b Celerity FC-82EN Fibre Channel Adapter + 117c 003c Celerity FC-84EN Fibre Channel Adapter 11f9 I-Cube Inc 11fa Kasan Electronics Company, Ltd. 11fb Datel Inc @@ -10231,9 +13323,11 @@ 1216 Purup Prepress A/S 1217 O2 Micro, Inc. 00f7 Firewire (IEEE 1394) + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 1179 ff50 Satellite P305D-S8995E 10f7 1394 OHCI Compliant Host Controller 11f7 OZ600 1394a-2000 Controller + 1028 04a3 Precision M4600 13f7 1394 OHCI Compliant Host Controller 6729 OZ6729 673a OZ6730 @@ -10256,8 +13350,10 @@ 1025 0035 TravelMate 660 7114 OZ711M1/MC1 4-in-1 MemoryCardBus Controller 7120 Integrated MMC/SD Controller + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 1179 ff50 Satellite P305D-S8995E 7130 Integrated MS/xD Controller + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 1179 ff50 Satellite P305D-S8995E 7134 OZ711MP1/MS1 MemoryCardBus Controller 7135 Cardbus bridge @@ -10272,8 +13368,15 @@ 7233 OZ711MP3/MS3 4-in-1 MemoryCardBus Controller 8120 Integrated MMC/SD Controller 8130 Integrated MS/MSPRO/xD Controller - 8321 Integrated MMC/SD controller + 8220 OZ600FJ1/OZ900FJ1 SD/MMC Card Reader Controller + 8221 OZ600FJ0/OZ900FJ0/OZ600FJS SD/MMC Card Reader Controller + 8320 OZ600RJ1/OZ900RJ1 SD/MMC Card Reader Controller + 1028 04a3 Precision M4600 + 8321 OZ600RJ0/OZ900RJ0/OZ600RJS SD/MMC Card Reader Controller + 8330 OZ600 MS/xD Controller + 1028 04a3 Precision M4600 8331 O2 Flash Memory Card + 8520 SD/MMC Card Reader Controller 1218 Hybricon Corp. 1219 First Virtual Corporation 121a 3Dfx Interactive, Inc. @@ -10395,9 +13498,15 @@ 0002 EasyConnect 8/64 0003 EasyIO 123e Simutech, Inc. -123f C-Cube Microsystems +# nee C-Cube Microsystems / acquired by Magnum Semiconductor +123f LSI Logic 00e4 MPEG - 8120 E4? + 8120 DVxplore Codec + 10de 01e1 NVTV PAL + 10de 01e2 NVTV NTSC + 10de 01e3 NVTV PAL + 10de 0248 NVTV NTSC + 10de 0249 NVTV PAL 11bd 0006 DV500 E4 11bd 000a DV500 E4 11bd 000f DV500 E4 @@ -10423,7 +13532,9 @@ 0800 C4 ISDN 0a00 A1 ISDN [Fritz] 1244 0a00 FRITZ!Card ISDN Controller - 0e00 Fritz!PCI v2.0 ISDN + 0e00 Fritz!Card PCI v2.0 ISDN + 0e80 Fritz!Card PCI v2.1 ISDN + 1244 0e00 PSB 3100F (AVM KAFKA) [Fritz!Card PCI v2.1] 1100 C2 ISDN 1200 T1 ISDN 2700 Fritz!Card DSL SL @@ -10464,7 +13575,8 @@ 5201 PCI-2000 1257 Vertex Networks, Inc. 1258 Gilbarco, Inc. -1259 Allied Telesyn International +# nee Allied Telesyn International +1259 Allied Telesis 2560 AT-2560 Fast Ethernet Adapter (i82557B) 2801 AT-2801FX (RTL-8139) a117 RTL81xx Fast Ethernet @@ -10504,6 +13616,7 @@ 125d 1989 ESS Modem 1998 ES1983S Maestro-3i PCI Audio Accelerator 1028 00b1 Latitude C600 + 1028 00e5 Latitude C810 1028 00e6 ES1983S Maestro-3i (Dell Inspiron 8100) 1999 ES1983S Maestro-3i PCI Modem Accelerator 199a ES1983S Maestro-3i PCI Audio Accelerator @@ -10523,6 +13636,12 @@ 14fe 0429 ES56-PI Data Fax Modem 125e Specialvideo Engineering SRL 125f Concurrent Technologies, Inc. +# 4 x serial ports, 2 x printer ports + 2071 CC PMC/232 +# 4 x serial ports, 2 x printer ports + 2084 CC PMC/23P +# 4 x serial ports, RS422 + 2091 CC PMC/422 1260 Intersil Corporation 3872 ISL3872 [Prism 3] 1468 0202 LAN-Express IEEE 802.11b Wireless LAN @@ -10588,8 +13707,10 @@ 0510 SM501 VoyagerGX Rev. B 0710 SM710 LynxEM 0712 SM712 LynxEM+ + 0718 SM718 LynxSE+ 0720 SM720 Lynx3DM 0730 SM731 Cougar3DR + 0750 SM750 0810 SM810 LynxE 0811 SM811 LynxE 0820 SM820 Lynx3D @@ -10601,13 +13722,13 @@ 0002 DirecPC 1274 Ensoniq 1171 ES1373 [AudioPCI] (also Creative Labs CT5803) - 1371 ES1371 [AudioPCI-97] + 1371 ES1371 / Creative Labs CT2518 [AudioPCI-97] 0e11 0024 AudioPCI on Motherboard Compaq Deskpro 0e11 b1a7 ES1371, ES1373 AudioPCI 1033 80ac ES1371, ES1373 AudioPCI 1042 1854 Tazer 107b 8054 Tabor2 - 1274 1371 Creative Sound Blaster AudioPCI64V, AudioPCI128 + 1274 1371 AudioPCI 64V/128 / Creative Sound Blaster CT4810 1274 8001 CT4751 board 1462 6470 ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A 1462 6560 ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10 @@ -10904,7 +14025,6 @@ 0001 AceNIC Gigabit Ethernet 1014 0104 Gigabit Ethernet-SX PCI Adapter 12ae 0001 Gigabit Ethernet-SX (Universal) - 1410 0104 Gigabit Ethernet-SX PCI Adapter 0002 AceNIC Gigabit Ethernet (Copper) 10a9 8002 Acenic Gigabit Ethernet 12ae 0002 Gigabit Ethernet-T (3C986-T) @@ -11064,6 +14184,7 @@ 8154 PI7C8154A/PI7C8154B/PI7C8154BI PCI-to-PCI Bridge e110 PI7C9X110 PCI Express to PCI bridge 1775 11cc CC11/CL11 CompactPCI Bridge + e111 PI7C9X111SL PCIe-to-PCI Reversible Bridge e130 PCI Express to PCI-XPI7C9X130 PCI-X Bridge 12d9 Aculab PLC 0002 PCI Prosody @@ -11103,6 +14224,7 @@ 122d 1002 AU8820 Vortex Digital Audio Processor 12eb 0001 AU8820 Vortex Digital Audio Processor 5053 3355 Montego + 50b2 1111 XLerate 0002 Vortex 2 104d 8049 AU8830 Vortex 3D Digital Audio Processor 104d 807b AU8830 Vortex 3D Digital Audio Processor @@ -11402,7 +14524,7 @@ 0040 QSC-200/300 0050 ESC-100D 0060 ESC-100M - 00f0 MPAC-100 Synchronous Serial Card (Zilog 85230) + 00f0 MPAC-100 Syncronous Serial Card (Zilog 85230) 0170 QSCLP-100 0180 DSCLP-100 0190 SSCLP-100 @@ -11435,6 +14557,8 @@ 0204 GPS170PCI GPS Receiver 0205 GPS170PEX GPS Receiver (PCI Express) 0206 GPS180PEX GPS Receiver (PCI Express) + 0207 GLN180PEX GPS/GLONASS receiver (PCI Express) + 0208 GPS180AMC GPS Receiver (PCI Express / MicroTCA / AdvancedMC) 0301 TCR510PCI IRIG Timecode Reader 0302 TCR167PCI IRIG Timecode Reader 0303 TCR511PCI IRIG Timecode Reader @@ -11541,20 +14665,9 @@ 1385 Netgear 006b WA301 802.11b Wireless PCI Adapter 4100 MA301 802.11b Wireless PCI Adapter - 4105 MA311 802.11b Wireless PCI Adapter - 4400 WAG511 802.11a/b/g Dual Band Wireless PC Card - 4600 WAG511 802.11a/b/g Dual Band Wireless PC Card 4601 WAG511 802.11a/b/g Dual Band Wireless PC Card - 4610 WAG511 802.11a/b/g Dual Band Wireless PC Card - 4a00 WAG311 802.11a/g Wireless PCI Adapter - 5200 GA511 Gigabit PC Card 620a GA620 Gigabit Ethernet 630a GA630 Gigabit Ethernet - 6d00 WPNT511 RangeMax 240 Mbps Wireless PC Card - 7b00 WN511B RangeMax Next 270 Mbps Wireless PC Card - 7c00 WN511T RangeMax Next 300 Mbps Wireless PC Card - f004 FA310TX - f312 FA312 REV-A1 Fast Ethernet PCI Adapter 1386 Video Domain Technologies 1387 Systran Corp 1388 Hitachi Information Technology Co Ltd @@ -11614,19 +14727,52 @@ 1396 Cipher Systems Inc 1397 Cologne Chip Designs GmbH 08b4 ISDN network Controller [HFC-4S] + 1397 08b4 HFC-4S [Cologne Chip HFC-4S Eval. Board] + 1397 b51a HFC-4S [Allo.com BRI card] 1397 b520 HFC-4S [IOB4ST] - 1397 b540 HFC-4S [Swyx 4xS0 SX2 QuadBri] - 1397 b550 HFC-4S [Junghanns quadBRI] - 1397 b556 HFC-4S [Junghanns DuoDBRI] + 1397 b540 HFC-4S [Swyx SX2 QuadBri] + 1397 b550 HFC-4S [Junghanns.NET quadBRI] + 1397 b556 HFC-4S [Junghanns.NET duoBRI] + 1397 b559 HFC-4S [Junghanns.NET duoBRI miniPCI] + 1397 b560 HFC-4S [BeroNet BN4S0] + 1397 b566 HFC-4S [BeroNet BN2S0] + 1397 b567 HFC-4S [BeroNet BN1S0 miniPCI] + 1397 b568 HFC-4S [BeroNet BN4S0 miniPCI] + 1397 b569 HFC-4S [BeroNet BN2S0 miniPCI] + 1397 b620 HFC-4S + 1397 b752 HFC-4S [Junghanns.NET quadBRI PCIe] + 1397 b761 HFC-4S [BeroNet BN2S0 PCIe] + 1397 b762 HFC-4S [BeroNet BN4S0 PCIe] + 1397 e884 HFC-4S [OpenVox B200P] 1397 e888 HFC-4S [OpenVox B200P / B400P] 16b8 ISDN network Controller [HFC-8S] - 1397 b562 HFC-8S [IOB8ST] + 1397 16b8 HFC-8S [Cologne Chip HFC-8S Eval. Board] + 1397 b521 HFC-8S [IOB4ST Recording] + 1397 b522 HFC-8S [IOB8ST] + 1397 b552 HFC-8S [Junghanns.NET octoBRI] + 1397 b55b HFC-8S [Junghanns.NET octoBRI] + 1397 b562 HFC-8S [BeroNet BN8S0] + 1397 b56b HFC-8S [BeroNet BN8S0+] + 1397 b622 HFC-8S + 1397 e998 HFC-8S [OpenVox B800P] 2bd0 ISDN network controller [HFC-PCI] 0675 1704 ISDN Adapter (PCI Bus, D, C) 0675 1708 ISDN Adapter (PCI Bus, D, C, ACPI) 1397 2bd0 ISDN Board e4bf 1000 CI1-1-Harp 30b1 ISDN network Controller [HFC-E1] + 1397 30b1 HFC-E1 [Cologne Chip HFC-E1 Eval. Board] + 1397 b523 HFC-E1 [IOB1E1] + 1397 b543 HFC-E1 [Swyx SX2 SinglePRI V2] + 1397 b544 HFC-E1 [Swyx SX2 DualPRI V2] + 1397 b553 HFC-E1 [Junghanns.NET singleE1] + 1397 b554 HFC-E1 [Junghanns.NET doubleE1] + 1397 b555 HFC-E1 [Junghanns.NET doubleE1 2.0] + 1397 b55a HFC-E1 [Junghanns.NET singleE1 miniPCI] + 1397 b563 HFC-E1 [beroNet BN1E1] + 1397 b564 HFC-E1 [beroNet BN2E1] + 1397 b565 HFC-E1 [beroNet BN2E1+] + 1397 b56a HFC-E1 [beroNet BN1E1 miniPCI] b700 ISDN network controller PrimuX S0 [HFC-PCI] f001 GSM Network Controller [HFC-4GSM] 1398 Clarion co. Ltd @@ -11846,10 +14992,12 @@ 1043 838e Virtuoso 66 (Xonar DS) 1043 8428 Virtuoso 100 (Xonar Xense) 1043 8467 CMI8786 (Xonar DG) + 1043 85f4 Virtuoso 100 (Xonar Essence STX II) 13f6 8782 PCI 2.0 HD Audio 13f6 ffff CMI8787-HG2PCI 14c3 1710 HiFier Fantasia 14c3 1711 HiFier Serenade + 14c3 1713 HiFier Serenade III 1a58 0910 Barracuda AC-1 415a 5431 X-Meridian 7.1 5431 017a X-Meridian 7.1 2G @@ -11858,7 +15006,6 @@ 7284 9781 CLARO halo 7284 9783 eCLARO 7284 9787 CLARO II - 9880 CM9880 13f7 Wildfire Communications 13f8 Ad Lib Multimedia Inc 13f9 NTT Advanced Technology Corp. @@ -11999,7 +15146,7 @@ 7168 PCI2S550 (Dual 16550 UART) 1409 0002 SER4036A3V (2x RS232 port) 1409 4027 SER4027A (1x RS232 port) - 1409 4037 SER4037A (2x RS232 port) + 1409 4037 SER4037A(L) [SUNIX SUN1889] (2x RS232 port) # Single DC-37 connector 1409 4056 SER4056A (4x RS232) 1409 5027 SER4027D @@ -12147,6 +15294,16 @@ 400c B404-BT Unified Wire Ethernet Controller 400d T480 Unified Wire Ethernet Controller 400e T440-LP-CR Unified Wire Ethernet Controller + 400f T440 [Amsterdam] Unified Wire Ethernet Controller + 4080 T480-4080 T480 Unified Wire Ethernet Controller + 4081 T440F-4081 T440-FCoE Unified Wire Ethernet Controller + 4082 T420-4082 Unified Wire Ethernet Controller + 4083 T420X-4083 Unified Wire Ethernet Controller + 4084 T440-4084 Unified Wire Ethernet Controller + 4085 T420-4085 SFP+ Unified Wire Ethernet Controller + 4086 T440-4086 10Gbase-T Unified Wire Ethernet Controller + 4087 T440T-4087 Unified Wire Ethernet Controller + 4088 T440-4088 Unified Wire Ethernet Controller 4401 T420-CR Unified Wire Ethernet Controller 4402 T422-CR Unified Wire Ethernet Controller 4403 T440-CR Unified Wire Ethernet Controller @@ -12161,6 +15318,16 @@ 440c B404-BT Unified Wire Ethernet Controller 440d T480 Unified Wire Ethernet Controller 440e T440-LP-CR Unified Wire Ethernet Controller + 440f T440 [Amsterdam] Unified Wire Ethernet Controller + 4480 T480-4080 T480 Unified Wire Ethernet Controller + 4481 T440F-4081 T440-FCoE Unified Wire Ethernet Controller + 4482 T420-4082 Unified Wire Ethernet Controller + 4483 T420X-4083 Unified Wire Ethernet Controller + 4484 T440-4084 Unified Wire Ethernet Controller + 4485 T420-4085 SFP+ Unified Wire Ethernet Controller + 4486 T440-4086 10Gbase-T Unified Wire Ethernet Controller + 4487 T440T-4087 Unified Wire Ethernet Controller + 4488 T440-4088 Unified Wire Ethernet Controller 4501 T420-CR Unified Wire Storage Controller 4502 T422-CR Unified Wire Storage Controller 4503 T440-CR Unified Wire Storage Controller @@ -12171,10 +15338,20 @@ 4508 T420-CX Unified Wire Storage Controller 4509 T420-BT Unified Wire Storage Controller 450a T404-BT Unified Wire Storage Controller - 450b B420-SR Unified Wire Ethernet Controller - 450c B404-BT Unified Wire Ethernet Controller + 450b B420-SR Unified Wire Storage Controller + 450c B404-BT Unified Wire Storage Controller 450d T480 Unified Wire Storage Controller 450e T440-LP-CR Unified Wire Storage Controller + 450f T440 [Amsterdam] Unified Wire Storage Controller + 4580 T480-4080 T480 Unified Wire Storage Controller + 4581 T440F-4081 T440-FCoE Unified Wire Storage Controller + 4582 T420-4082 Unified Wire Storage Controller + 4583 T420X-4083 Unified Wire Storage Controller + 4584 T440-4084 Unified Wire Storage Controller + 4585 T420-4085 SFP+ Unified Wire Storage Controller + 4586 T440-4086 10Gbase-T Unified Wire Storage Controller + 4587 T440T-4087 Unified Wire Storage Controller + 4588 T440-4088 Unified Wire Storage Controller 4601 T420-CR Unified Wire Storage Controller 4602 T422-CR Unified Wire Storage Controller 4603 T440-CR Unified Wire Storage Controller @@ -12185,10 +15362,20 @@ 4608 T420-CX Unified Wire Storage Controller 4609 T420-BT Unified Wire Storage Controller 460a T404-BT Unified Wire Storage Controller - 460b B420-SR Unified Wire Ethernet Controller - 460c B404-BT Unified Wire Ethernet Controller + 460b B420-SR Unified Wire Storage Controller + 460c B404-BT Unified Wire Storage Controller 460d T480 Unified Wire Storage Controller 460e T440-LP-CR Unified Wire Storage Controller + 460f T440 [Amsterdam] Unified Wire Storage Controller + 4680 T480-4080 T480 Unified Wire Storage Controller + 4681 T440F-4081 T440-FCoE Unified Wire Storage Controller + 4682 T420-4082 Unified Wire Storage Controller + 4683 T420X-4083 Unified Wire Storage Controller + 4684 T440-4084 Unified Wire Storage Controller + 4685 T420-4085 SFP+ Unified Wire Storage Controller + 4686 T440-4086 10Gbase-T Unified Wire Storage Controller + 4687 T440T-4087 Unified Wire Storage Controller + 4688 T440-4088 Unified Wire Storage Controller 4701 T420-CR Unified Wire Ethernet Controller 4702 T422-CR Unified Wire Ethernet Controller 4703 T440-CR Unified Wire Ethernet Controller @@ -12203,20 +15390,254 @@ 470c B404-BT Unified Wire Ethernet Controller 470d T480 Unified Wire Ethernet Controller 470e T440-LP-CR Unified Wire Ethernet Controller - 4801 T420-CR Unified Wire Ethernet Controller - 4802 T422-CR Unified Wire Ethernet Controller - 4803 T440-CR Unified Wire Ethernet Controller - 4804 T420-BCH Unified Wire Ethernet Controller - 4805 T440-BCH Unified Wire Ethernet Controller - 4806 T440-CH Unified Wire Ethernet Controller - 4807 T420-SO Unified Wire Ethernet Controller - 4808 T420-CX Unified Wire Ethernet Controller - 4809 T420-BT Unified Wire Ethernet Controller - 480a T404-BT Unified Wire Ethernet Controller - 480b B420-SR Unified Wire Ethernet Controller - 480c B404-BT Unified Wire Ethernet Controller - 480d T480 Unified Wire Ethernet Controller - 480e T440-LP-CR Unified Wire Ethernet Controller + 470f T440 [Amsterdam] Unified Wire Ethernet Controller + 4780 T480-4080 T480 Unified Wire Ethernet Controller + 4781 T440F-4081 T440-FCoE Unified Wire Ethernet Controller + 4782 T420-4082 Unified Wire Ethernet Controller + 4783 T420X-4083 Unified Wire Ethernet Controller + 4784 T440-4084 Unified Wire Ethernet Controller + 4785 T420-4085 SFP+ Unified Wire Ethernet Controller + 4786 T440-4086 10Gbase-T Unified Wire Ethernet Controller + 4787 T440T-4087 Unified Wire Ethernet Controller + 4788 T440-4088 Unified Wire Ethernet Controller + 4801 T420-CR Unified Wire Ethernet Controller [VF] + 4802 T422-CR Unified Wire Ethernet Controller [VF] + 4803 T440-CR Unified Wire Ethernet Controller [VF] + 4804 T420-BCH Unified Wire Ethernet Controller [VF] + 4805 T440-BCH Unified Wire Ethernet Controller [VF] + 4806 T440-CH Unified Wire Ethernet Controller [VF] + 4807 T420-SO Unified Wire Ethernet Controller [VF] + 4808 T420-CX Unified Wire Ethernet Controller [VF] + 4809 T420-BT Unified Wire Ethernet Controller [VF] + 480a T404-BT Unified Wire Ethernet Controller [VF] + 480b B420-SR Unified Wire Ethernet Controller [VF] + 480c B404-BT Unified Wire Ethernet Controller [VF] + 480d T480 Unified Wire Ethernet Controller [VF] + 480e T440-LP-CR Unified Wire Ethernet Controller [VF] + 480f T440 [Amsterdam] Unified Wire Ethernet Controller [VF] + 4880 T480-4080 T480 Unified Wire Ethernet Controller [VF] + 4881 T440F-4081 T440-FCoE Unified Wire Ethernet Controller [VF] + 4882 T420-4082 Unified Wire Ethernet Controller [VF] + 4883 T420X-4083 Unified Wire Ethernet Controller [VF] + 4884 T440-4084 Unified Wire Ethernet Controller [VF] + 4885 T420-4085 SFP+ Unified Wire Ethernet Controller [VF] + 4886 T440-4086 10Gbase-T Unified Wire Ethernet Controller [VF] + 4887 T440T-4087 Unified Wire Ethernet Controller [VF] + 4888 T440-4088 Unified Wire Ethernet Controller [VF] + 5001 T520-CR Unified Wire Ethernet Controller + 5002 T522-CR Unified Wire Ethernet Controller + 5003 T540-CR Unified Wire Ethernet Controller + 5004 T520-BCH Unified Wire Ethernet Controller + 5005 T540-BCH Unified Wire Ethernet Controller + 5006 T540-CH Unified Wire Ethernet Controller + 5007 T520-SO Unified Wire Ethernet Controller + 5008 T520-CX Unified Wire Ethernet Controller + 5009 T520-BT Unified Wire Ethernet Controller + 500a T504-BT Unified Wire Ethernet Controller + 500b B520-SR Unified Wire Ethernet Controller + 500c B504-BT Unified Wire Ethernet Controller + 500d T580-CR Unified Wire Ethernet Controller + 500e T540-LP-CR Unified Wire Ethernet Controller + 500f T540 [Amsterdam] Unified Wire Ethernet Controller + 5010 T580-LP-CR Unified Wire Ethernet Controller + 5011 T520-LL-CR Unified Wire Ethernet Controller + 5012 T560-CR Unified Wire Ethernet Controller + 5013 T580-CHR Unified Wire Ethernet Controller + 5014 T580-LP-SO-CR Unified Wire Ethernet Controller + 5015 T502-BT Unified Wire Ethernet Controller + 5016 T580-OCP-SO Unified Wire Ethernet Controller + 5017 T520-OCP-SO Unified Wire Ethernet Controller + 5080 T540-5080 Unified Wire Ethernet Controller + 5081 T540-5081 Unified Wire Ethernet Controller + 5082 T504-5082 Unified Wire Ethernet Controller + 5083 T540-5083 Unified Wire Ethernet Controller + 5084 T580-5084 Unified Wire Ethernet Controller + 5085 T580-5085 Unified Wire Ethernet Controller + 5086 T580-5086 Unified Wire Ethernet Controller + 5087 T580-5087 Unified Wire Ethernet Controller + 5088 T570-5088 Unified Wire Ethernet Controller + 5089 T520-5089 Unified Wire Ethernet Controller + 5090 T540-5090 Unified Wire Ethernet Controller + 5091 T522-5091 Unified Wire Ethernet Controller + 5092 T520-5092 Unified Wire Ethernet Controller + 5401 T520-CR Unified Wire Ethernet Controller + 5402 T522-CR Unified Wire Ethernet Controller + 5403 T540-CR Unified Wire Ethernet Controller + 5404 T520-BCH Unified Wire Ethernet Controller + 5405 T540-BCH Unified Wire Ethernet Controller + 5406 T540-CH Unified Wire Ethernet Controller + 5407 T520-SO Unified Wire Ethernet Controller + 5408 T520-CX Unified Wire Ethernet Controller + 5409 T520-BT Unified Wire Ethernet Controller + 540a T504-BT Unified Wire Ethernet Controller + 540b B520-SR Unified Wire Ethernet Controller + 540c B504-BT Unified Wire Ethernet Controller + 540d T580-CR Unified Wire Ethernet Controller + 540e T540-LP-CR Unified Wire Ethernet Controller + 540f T540 [Amsterdam] Unified Wire Ethernet Controller + 5410 T580-LP-CR Unified Wire Ethernet Controller + 5411 T520-LL-CR Unified Wire Ethernet Controller + 5412 T560-CR Unified Wire Ethernet Controller + 5413 T580-CHR Unified Wire Ethernet Controller + 5414 T580-LP-SO-CR Unified Wire Ethernet Controller + 5415 T502-BT Unified Wire Ethernet Controller + 5416 T580-OCP-SO Unified Wire Ethernet Controller + 5417 T520-OCP-SO Unified Wire Ethernet Controller + 5480 T540-5080 Unified Wire Ethernet Controller + 5481 T540-5081 Unified Wire Ethernet Controller + 5482 T504-5082 Unified Wire Ethernet Controller + 5483 T540-5083 Unified Wire Ethernet Controller + 5484 T580-5084 Unified Wire Ethernet Controller + 5485 T580-5085 Unified Wire Ethernet Controller + 5486 T580-5086 Unified Wire Ethernet Controller + 5487 T580-5087 Unified Wire Ethernet Controller + 5488 T570-5088 Unified Wire Ethernet Controller + 5489 T520-5089 Unified Wire Ethernet Controller + 5490 T540-5090 Unified Wire Ethernet Controller + 5491 T522-5091 Unified Wire Ethernet Controller + 5492 T520-5092 Unified Wire Ethernet Controller + 5501 T520-CR Unified Wire Storage Controller + 5502 T522-CR Unified Wire Storage Controller + 5503 T540-CR Unified Wire Storage Controller + 5504 T520-BCH Unified Wire Storage Controller + 5505 T540-BCH Unified Wire Storage Controller + 5506 T540-CH Unified Wire Storage Controller + 5507 T520-SO Unified Wire Storage Controller + 5508 T520-CX Unified Wire Storage Controller + 5509 T520-BT Unified Wire Storage Controller + 550a T504-BT Unified Wire Storage Controller + 550b B520-SR Unified Wire Storage Controller + 550c B504-BT Unified Wire Storage Controller + 550d T580-CR Unified Wire Storage Controller + 550e T540-LP-CR Unified Wire Storage Controller + 550f T540 [Amsterdam] Unified Wire Storage Controller + 5510 T580-LP-CR Unified Wire Storage Controller + 5511 T520-LL-CR Unified Wire Storage Controller + 5512 T560-CR Unified Wire Storage Controller + 5513 T580-CHR Unified Wire Storage Controller + 5514 T580-LP-SO-CR Unified Wire Storage Controller + 5515 T502-BT Unified Wire Storage Controller + 5516 T580-OCP-SO Unified Wire Storage Controller + 5517 T520-OCP-SO Unified Wire Storage Controller + 5580 T540-5080 Unified Wire Storage Controller + 5581 T540-5081 Unified Wire Storage Controller + 5582 T504-5082 Unified Wire Storage Controller + 5583 T540-5083 Unified Wire Storage Controller + 5584 T580-5084 Unified Wire Storage Controller + 5585 T580-5085 Unified Wire Storage Controller + 5586 T580-5086 Unified Wire Storage Controller + 5587 T580-5087 Unified Wire Storage Controller + 5588 T570-5088 Unified Wire Storage Controller + 5589 T520-5089 Unified Wire Storage Controller + 5590 T540-5090 Unified Wire Storage Controller + 5591 T522-5091 Unified Wire Storage Controller + 5592 T520-5092 Unified Wire Storage Controller + 5601 T520-CR Unified Wire Storage Controller + 5602 T522-CR Unified Wire Storage Controller + 5603 T540-CR Unified Wire Storage Controller + 5604 T520-BCH Unified Wire Storage Controller + 5605 T540-BCH Unified Wire Storage Controller + 5606 T540-CH Unified Wire Storage Controller + 5607 T520-SO Unified Wire Storage Controller + 5608 T520-CX Unified Wire Storage Controller + 5609 T520-BT Unified Wire Storage Controller + 560a T504-BT Unified Wire Storage Controller + 560b B520-SR Unified Wire Storage Controller + 560c B504-BT Unified Wire Storage Controller + 560d T580-CR Unified Wire Storage Controller + 560e T540-LP-CR Unified Wire Storage Controller + 560f T540 [Amsterdam] Unified Wire Storage Controller + 5610 T580-LP-CR Unified Wire Storage Controller + 5611 T520-LL-CR Unified Wire Storage Controller + 5612 T560-CR Unified Wire Storage Controller + 5613 T580-CHR Unified Wire Storage Controller + 5614 T580-LP-SO-CR Unified Wire Storage Controller + 5615 T502-BT Unified Wire Storage Controller + 5616 T580-OCP-SO Unified Wire Storage Controller + 5617 T520-OCP-SO Unified Wire Storage Controller + 5680 T540-5080 Unified Wire Storage Controller + 5681 T540-5081 Unified Wire Storage Controller + 5682 T504-5082 Unified Wire Storage Controller + 5683 T540-5083 Unified Wire Storage Controller + 5684 T580-5084 Unified Wire Storage Controller + 5685 T580-5085 Unified Wire Storage Controller + 5686 T580-5086 Unified Wire Storage Controller + 5687 T580-5087 Unified Wire Storage Controller + 5688 T570-5088 Unified Wire Storage Controller + 5689 T520-5089 Unified Wire Storage Controller + 5690 T540-5090 Unified Wire Storage Controller + 5691 T522-5091 Unified Wire Storage Controller + 5692 T520-5092 Unified Wire Storage Controller + 5701 T520-CR Unified Wire Ethernet Controller + 5702 T522-CR Unified Wire Ethernet Controller + 5703 T540-CR Unified Wire Ethernet Controller + 5704 T520-BCH Unified Wire Ethernet Controller + 5705 T540-BCH Unified Wire Ethernet Controller + 5706 T540-CH Unified Wire Ethernet Controller + 5707 T520-SO Unified Wire Ethernet Controller + 5708 T520-CX Unified Wire Ethernet Controller + 5709 T520-BT Unified Wire Ethernet Controller + 570a T504-BT Unified Wire Ethernet Controller + 570b B520-SR Unified Wire Ethernet Controller + 570c B504-BT Unified Wire Ethernet Controller + 570d T580-CR Unified Wire Ethernet Controller + 570e T540-LP-CR Unified Wire Ethernet Controller + 570f T540 [Amsterdam] Unified Wire Ethernet Controller + 5710 T580-LP-CR Unified Wire Ethernet Controller + 5711 T520-LL-CR Unified Wire Ethernet Controller + 5712 T560-CR Unified Wire Ethernet Controller + 5713 T580-CR Unified Wire Ethernet Controller + 5714 T580-LP-SO-CR Unified Wire Ethernet Controller + 5715 T502-BT Unified Wire Ethernet Controller + 5780 T540-5080 Unified Wire Ethernet Controller + 5781 T540-5081 Unified Wire Ethernet Controller + 5782 T504-5082 Unified Wire Ethernet Controller + 5783 T540-5083 Unified Wire Ethernet Controller + 5784 T580-5084 Unified Wire Ethernet Controller + 5785 T580-5085 Unified Wire Ethernet Controller + 5786 T580-5086 Unified Wire Ethernet Controller + 5787 T580-5087 Unified Wire Ethernet Controller + 5788 T570-5088 Unified Wire Ethernet Controller + 5789 T520-5089 Unified Wire Ethernet Controller + 5790 T540-5090 Unified Wire Ethernet Controller + 5791 T522-5091 Unified Wire Ethernet Controller + 5792 T520-5092 Unified Wire Ethernet Controller + 5801 T520-CR Unified Wire Ethernet Controller [VF] + 5802 T522-CR Unified Wire Ethernet Controller [VF] + 5803 T540-CR Unified Wire Ethernet Controller [VF] + 5804 T520-BCH Unified Wire Ethernet Controller [VF] + 5805 T540-BCH Unified Wire Ethernet Controller [VF] + 5806 T540-CH Unified Wire Ethernet Controller [VF] + 5807 T520-SO Unified Wire Ethernet Controller [VF] + 5808 T520-CX Unified Wire Ethernet Controller [VF] + 5809 T520-BT Unified Wire Ethernet Controller [VF] + 580a T504-BT Unified Wire Ethernet Controller [VF] + 580b B520-SR Unified Wire Ethernet Controller [VF] + 580c B504-BT Unified Wire Ethernet Controller [VF] + 580d T580-CR Unified Wire Ethernet Controller [VF] + 580e T540-LP-CR Unified Wire Ethernet Controller [VF] + 580f T540 [Amsterdam] Unified Wire Ethernet Controller [VF] + 5810 T580-LP-CR Unified Wire Ethernet Controller [VF] + 5811 T520-LL-CR Unified Wire Ethernet Controller [VF] + 5812 T560-CR Unified Wire Ethernet Controller [VF] + 5813 T580-CHR Unified Wire Ethernet Controller [VF] + 5814 T580-LP-SO-CR Unified Wire Ethernet Controller [VF] + 5815 T502-BT Unified Wire Ethernet Controller [VF] + 5816 T580-OCP-SO Unified Wire Ethernet Controller [VF] + 5817 T520-OCP-SO Unified Wire Ethernet Controller [VF] + 5880 T540-5080 Unified Wire Ethernet Controller [VF] + 5881 T540-5081 Unified Wire Ethernet Controller [VF] + 5882 T504-5082 Unified Wire Ethernet Controller [VF] + 5883 T540-5083 Unified Wire Ethernet Controller [VF] + 5884 T580-5084 Unified Wire Ethernet Controller [VF] + 5885 T580-5085 Unified Wire Ethernet Controller [VF] + 5886 T580-5086 Unified Wire Ethernet Controller [VF] + 5887 T580-5087 Unified Wire Ethernet Controller [VF] + 5888 T570-5088 Unified Wire Ethernet Controller [VF] + 5889 T520-5089 Unified Wire Ethernet Controller [VF] + 5890 T540-5090 Unified Wire Ethernet Controller [VF] + 5891 T522-5091 Unified Wire Ethernet Controller [VF] + 5892 T520-5092 Unified Wire Ethernet Controller [VF] a000 PE10K Unified Wire Ethernet Controller 1426 Storage Technology Corp. 1427 Better On-Line Solutions @@ -12284,8 +15705,18 @@ 144b Verint Systems Inc. 144c Catalina Research Inc 144d Samsung Electronics Co Ltd - c00c P35 laptop - c511 R20 Laptop + 1600 Apple PCIe SSD + a800 XP941 PCIe SSD + a820 NVMe SSD Controller 171X + 1028 1f95 Express Flash NVMe XS1715 SSD 400GB + 1028 1f96 Express Flash NVMe XS1715 SSD 800GB + 1028 1f97 Express Flash NVMe XS1715 SSD 1600GB + 1028 1fa4 Express Flash NVMe SM1715 3.2TB SFF + 1028 1fa6 Express Flash NVMe SM1715 3.2TB AIC + 1028 1fba Express Flash NVMe SM1715 800GB SFF + 1028 1fbb Express Flash NVMe SM1715 1.6TB SFF + 1028 1fbc Express Flash NVMe SM1715 1.6TB AIC + a821 NVMe SSD Controller 172X 144e OLITEC 144f Askey Computer Corp. 1450 Octave Communications Ind. @@ -12295,9 +15726,7 @@ 1455 Logic Plus Plus Inc 1456 Advanced Hardware Architectures 1457 Nuera Communications Inc -1458 Giga-byte Technology - 9001 GC-PTV-TAF Hybrid TV card - e911 GN-WIAG02 +1458 Gigabyte Technology Co., Ltd 1459 DOOIN Electronics 145a Escalate Networks Inc 145b PRAIM SRL @@ -12313,26 +15742,7 @@ a836 M115 DVB-T, PAL/SECAM/NTSC Tuner e836 M115S Hybrid Analog/DVB PAL/SECAM/NTSC Tuner f436 AVerTV Hybrid+FM -1462 Micro-Star International Co., Ltd. - 5501 nVidia NV15DDR [GeForce2 Ti] - 6819 Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G] - 6825 PCI Card wireless 11g [PC54G] - 6834 RaLink RT2500 802.11g [PC54G2] - 7125 MS-7125 [K8N Neo4 Platinum] - 7235 P965 Neo MS-7235 mainboard - 7242 K9AGM RS485 Motherboard - 7250 MS-7250 Motherboard [K9N Platinum SLI/non-SLI] - 7327 K9AGM2-FIH Motherboard - 7650 Hetis 865GV-E (MS-7065) - 8725 NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter - 9000 NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter - 9110 GeFORCE FX5200 - 9119 NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter - 9123 NVIDIA NV31 [GeForce FX 5600] FX5600-VTDR128 [MS-8912] - 9510 Radeon 9600XT - 9511 Radeon 9600XT - 9591 nVidia Corporation NV36 [GeForce FX 5700LE] - b834 Wireless 11g Turbo G PCI card [MSI PC60G] +1462 Micro-Star International Co., Ltd. [MSI] 1463 Fast Corporation 1464 Interactive Circuits & Systems Ltd 1465 GN NETTEST Telecom DIV. @@ -12340,7 +15750,11 @@ 1467 DIGICOM SPA 1468 AMBIT Microsystem Corp. 1469 Cleveland Motion Controls -146a IFR +# formerly IFR. +146a Aeroflex +# 1.5 GHz to 3.0 GHz x 1Hz + 3010 3010 RF Synthesizer + 3a11 3011A PXI RF Synthesizer 146b Parascan Technologies Ltd 146c Ruby Tech Corp. 1430 FE-1430TX Fast Ethernet PCI Adapter @@ -12377,7 +15791,7 @@ 1489 KYE Systems Corporation 148a OPTO 148b INNOMEDIALOGIC Inc. -148c C.P. Technology Co. Ltd +148c Tul Corporation / PowerColor 148d DIGICOM Systems, Inc. 1003 HCF 56k Data/Fax Modem 148e OSI Plus Corporation @@ -12398,7 +15812,8 @@ 21cc TCP460 CompactPCI 16 Channel Serial Interface RS232/RS422 21cd TCP461 CompactPCI 8 Channel Serial Interface RS232/RS422 3064 TPCI100 (2 Slot IndustryPack PCI Carrier) - 30c8 TPCI200 + 30c8 TPCI200 4 Slot IndustryPack PCI Carrier + 70c8 TPCE200 4 Slot IndustryPack PCIe Carrier 1499 EMTEC CO., Ltd 149a ANDOR Technology Ltd 149b SEIKO Instruments Inc @@ -12465,17 +15880,19 @@ 14be L3 Communications 14bf SPIDER Communications Inc. 14c0 COMPAL Electronics Inc +# now owned by CSP, Inc. 14c1 MYRICOM Inc. 0008 Myri-10G Dual-Protocol NIC 14c1 0008 10G-PCIE-8A 14c1 0009 10G-PCIE-8A (MSI-X firmware) 14c1 000a 10G-PCIE-8B - 14c1 000b 10G-PCIE-8B2 - 14c1 000c 10G-PCIE2-8B2 8043 Myrinet 2000 Scalable Cluster Interconnect 103c 1240 Myrinet M2L-PCI64/2-3.0 LANai 7.4 (HP OEM) 14c2 DTK Computer 14c3 MEDIATEK Corp. + 7630 MT7630e 802.11bgn Wireless Network Adapter +# MT7612E too? + 7662 MT7662E 802.11ac PCI Express Wireless Network Adapter 14c4 IWASAKI Information Systems Co Ltd 14c5 Automation Products AB 14c6 Data Race Inc @@ -12559,11 +15976,13 @@ 080f Sentry5 DDR/SDR RAM Controller 0811 Sentry5 External Interface Core 0816 BCM3302 Sentry5 MIPS32 CPU + 1570 720p FaceTime HD Camera 1600 NetXtreme BCM5752 Gigabit Ethernet PCI Express 1028 01c1 Precision 490 1028 01c2 Latitude D620 103c 3015 PCIe LAN on Motherboard 107b 5048 E4500 Onboard + 1259 2705 AT-2711FX 1601 NetXtreme BCM5752M Gigabit Ethernet PCI Express 1612 BCM70012 Video Decoder [Crystal HD] 1615 BCM70015 Video Decoder [Crystal HD] @@ -12579,6 +15998,7 @@ 1028 029c PowerEdge M710 BCM5709S Gigabit Ethernet 103c 171d NC382m Dual Port 1GbE Multifunction BL-c Adapter 103c 7056 NC382i Integrated Quad Port PCI Express Gigabit Server Adapter + 1259 2984 AT-2973SX 163b NetXtreme II BCM5716 Gigabit Ethernet 1028 028c PowerEdge R410 BCM5716 Gigabit Ethernet 1028 028d PowerEdge T410 BCM5716 Gigabit Ethernet @@ -12689,6 +16109,7 @@ 103c 7058 NC532i Dual Port 10GbE Multifunction BL-C Adapter 1653 NetXtreme BCM5705 Gigabit Ethernet 0e11 00e3 NC7761 Gigabit Server Adapter + 1734 1073 Primergy Econel 200 D2020 mainboard 1654 NetXtreme BCM5705_2 Gigabit Ethernet 0e11 00e3 NC7761 Gigabit Server Adapter 103c 3100 NC1020 ProLiant Gigabit Server Adapter 32 PCI @@ -12696,6 +16117,7 @@ 1655 NetXtreme BCM5717 Gigabit Ethernet PCIe 1656 NetXtreme BCM5718 Gigabit Ethernet PCIe 1657 NetXtreme BCM5719 Gigabit Ethernet PCIe + 103c 169d Ethernet 1Gb 4-port 331FLR Adapter 1659 NetXtreme BCM5721 Gigabit Ethernet PCI Express 1014 02c6 eServer xSeries server mainboard 1028 01e6 PowerEdge 860 @@ -12726,6 +16148,7 @@ 165f NetXtreme BCM5720 Gigabit Ethernet PCIe 1662 NetXtreme II BCM57712 10 Gigabit Ethernet 1663 NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function + 1665 NetXtreme BCM5717 Gigabit Ethernet PCIe 1668 NetXtreme BCM5714 Gigabit Ethernet 103c 7039 NC324i PCIe Dual Port Gigabit Server Adapter 1669 NetXtreme 5714S Gigabit Ethernet @@ -12777,6 +16200,8 @@ 1685 NetXtreme II BCM57500S Gigabit Ethernet 1686 NetXtreme BCM57766 Gigabit Ethernet PCIe 1687 NetXtreme BCM5762 Gigabit Ethernet PCIe + 1688 NetXtreme BCM5761 10/100/1000BASE-T Ethernet + 1259 2708 AT-2712 FX # The Broadcom 57800 device has two 1Gig ports and two 10Gig ports. The subsystem information can be used to differentiate. 168a NetXtreme II BCM57800 1/10 Gigabit Ethernet 1028 1f5c BCM57800 10-Gigabit Ethernet @@ -12785,6 +16210,16 @@ 1028 1f68 BCM57800 1-Gigabit Ethernet 168d NetXtreme II BCM57840 10/20 Gigabit Ethernet 168e NetXtreme II BCM57810 10 Gigabit Ethernet + 103c 1798 Flex-10 10Gb 2-port 530FLB Adapter [Meru] + 103c 17a5 HP Flex-10 10Gb 2-port 530M Adapter + 103c 18d3 HP Ethernet 10Gb 2-port 530T Adapter + 103c 1930 HP FlexFabric 10Gb 2-port 534FLR-SFP+ Adapter + 103c 1931 HP StoreFabric CN1100R Dual Port Converged Network Adapter + 103c 1932 HP FlexFabric 10Gb 2-port 534FLB Adapter + 103c 1933 HP FlexFabric 10Gb 2-port 534M Adapter + 103c 193a HP FlexFabric 10Gb 2-port 533FLR-T Adapter + 103c 3382 HP Ethernet 10Gb 2-port 530FLR-SFP+ Adapter + 103c 339d HP Ethernet 10Gb 2-port 530SFP+ Adapter 1690 NetXtreme BCM57760 Gigabit Ethernet PCIe 1691 NetLink BCM57788 Gigabit Ethernet PCIe 1028 04aa XPS 8300 @@ -12810,7 +16245,16 @@ 16a0 NetLink BCM5785 Fast Ethernet 16a1 BCM57840 NetXtreme II 10 Gigabit Ethernet 16a2 BCM57840 NetXtreme II 10/20-Gigabit Ethernet + 103c 1916 HP FlexFabric 20Gb 2-port 630FLB Adapter + 103c 1917 HP FlexFabric 20Gb 2-port 630M Adapter + 103c 2231 3820C 10/20Gb Converged Network Adapter + 103c 22fa FlexFabric 10Gb 2-port 536FLB Adapter + 16a3 NetXtreme BCM57786 Gigabit Ethernet PCIe 16a4 BCM57840 NetXtreme II Ethernet Multi Function + 103c 1916 HP NPAR 20Gb 2-port 630FLB Adapter + 103c 1917 HP NPAR 20Gb 2-port 630M Adapter + 103c 2231 3820C 10/20Gb Converged Network Adapter (NPAR 1.5) + 103c 22fa FlexFabric 10Gb 2-port 536FLB Adapter (NPAR 1.5) # The Broadcom 57800 device has two 1Gig ports and two 10Gig ports. The subsystem information can be used to differentiate. 16a5 NetXtreme II BCM57800 1/10 Gigabit Ethernet Multi Function 1028 1f5c NetXtreme II BCM57800 10-Gigabit Ethernet Multi Function @@ -12854,17 +16298,44 @@ 103c 703b NC373i Integrated Multifunction Gigabit Server Adapter 103c 703d NC373F PCI Express Multifunction Gigabit Server Adapter 16ad NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function + 103c 1916 HP FlexFabric 20Gb 2-port 630FLB Adapter + 103c 1917 HP FlexFabric 20Gb 2-port 630M Adapter + 103c 2231 3820C 10/20Gb Converged Network Adapter (SR-IOV VF) + 103c 22fa FlexFabric 10Gb 2-port 536FLB Adapter (SR-IOV VF) 16ae NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function + 103c 1798 HP NPAR 10Gb 2-port 530FLB Adapter + 103c 17a5 HP NPAR 10Gb 2-port 530M Adapter + 103c 18d3 HP NPAR 10Gb 2-port 530T Adapter + 103c 1930 HP NPAR 10Gb 2-port 534FLR-SFP+ Adapter + 103c 1931 HP NPAR CN1100R Dual Port Converged Network Adapter + 103c 1932 HP NPAR 10Gb 2-port 534FLB Adapter + 103c 1933 HP NPAR 10Gb 2-port 534M Adapter + 103c 193a HP NPAR 10Gb 2-port 533FLR-T Adapter + 103c 3382 HP NPAR 10Gb 2-port 530FLR-SFP+ Adapter + 103c 339d HP NPAR 10Gb 2-port 530SFP+ Adapter 16af NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function + 103c 1798 HP Flex-10 10Gb 2-port 530FLB Adapter + 103c 17a5 HP Flex-10 10Gb 2-port 530M Adapter + 103c 18d3 HP Ethernet 10Gb 2-port 530T Adapter + 103c 1930 HP FlexFabric 10Gb 2-port 534FLR-SFP+ Adapter + 103c 1931 HP StoreFabric CN1100R Dual Port Converged Network Adapter + 103c 1932 HP FlexFabric 10Gb 2-port 534FLB Adapter + 103c 1933 HP FlexFabric 10Gb 2-port 534M Adapter + 103c 193a HP FlexFabric 10Gb 2-port 533FLR-T Adapter + 103c 3382 HP Ethernet 10Gb 2-port 530FLR-SFP+ Adapter + 103c 339d HP Ethernet 10Gb 2-port 530SFP+ Adapter 16b0 NetXtreme BCM57761 Gigabit Ethernet PCIe 16b1 NetLink BCM57781 Gigabit Ethernet PCIe + 1849 96b1 Z77 Extreme4 motherboard 16b2 NetLink BCM57791 Gigabit Ethernet PCIe 16b3 NetXtreme BCM57786 Gigabit Ethernet PCIe 16b4 NetXtreme BCM57765 Gigabit Ethernet PCIe 16b5 NetLink BCM57785 Gigabit Ethernet PCIe 16b6 NetLink BCM57795 Gigabit Ethernet PCIe 16b7 NetXtreme BCM57782 Gigabit Ethernet PCIe - 16bc NetXtreme BCM57765 Memory Card Reader + 16bc BCM57765/57785 SDXC/MMC Card Reader + 16be BCM57765/57785 MS Card Reader + 16bf BCM57765/57785 xD-Picture Card Reader 16c6 NetXtreme BCM5702A3 Gigabit Ethernet 10b7 1100 3C1000B-T 10/100/1000 PCI 14e4 000c BCM5702 1000Base-T @@ -12878,6 +16349,7 @@ 14e4 0009 NetXtreme BCM5703 1000Base-T 14e4 000a NetXtreme BCM5703 1000Base-SX 16dd NetLink BCM5781 Gigabit Ethernet PCI Express + 16f3 NetXtreme BCM5727 Gigabit Ethernet PCIe 16f7 NetXtreme BCM5753 Gigabit Ethernet PCI Express 16fd NetXtreme BCM5753M Gigabit Ethernet PCI Express 103c 309f Compaq nx9420 Notebook @@ -12945,6 +16417,7 @@ 103c 1372 Broadcom 802.11a/b/g WLAN 103c 1373 Broadcom 802.11a/b/g WLAN 103c 30b5 Presario V3242AU + 106b 0089 AirPort Extreme 1371 103c Broadcom 802.11 Multiband-netwerkadapter(6715s) 4313 BCM4311 802.11a 4315 BCM4312 802.11b/g LP-PHY @@ -13007,7 +16480,7 @@ 185f 1220 TravelMate 290E WLAN Mini-PCI Card 4321 BCM4321 802.11a Wireless Network Controller 4322 BCM4322 802.11bgn Wireless Network Controller - 4324 BCM4306 802.11a/b/g + 4324 BCM4309 802.11abg Wireless Network Controller 1028 0001 Truemobile 1400 1028 0002 TrueMobile 1400 Dual Band WLAN PC Card 1028 0003 Truemobile 1450 MiniPCI @@ -13025,6 +16498,11 @@ 103c 1367 BCM4321 802.11a/b/g/n Wireless LAN Controller 103c 1368 BCM4321 802.11a/b/g/n Wireless LAN Controller 103c 1369 BCM4321 802.11a/b/g/n Wireless LAN Controller + 106b 0087 AirPort Extreme + 106b 0088 AirPort Extreme + 106b 008b AirPort Extreme + 106b 008c AirPort Extreme + 106b 0090 AirPort Extreme 14e4 4328 BCM4328 802.11a/b/g/n 1737 0066 WPC600N v1 802.11a/b/g/n Wireless-N CardBus Adapter 1737 0068 WEC600N v1 802.11a/b/g/n Wireless-N ExpressCard @@ -13035,27 +16513,55 @@ 432a BCM4321 802.11an Wireless Network Controller 432b BCM4322 802.11a/b/g/n Wireless LAN Controller 1028 000d Wireless 1510 Wireless-N WLAN Mini-Card + 106b 008d AirPort Extreme 106b 008e AirPort Extreme 432c BCM4322 802.11b/g/n 1799 d311 Dynex DX-NNBX 802.11n WLAN Cardbus Card 432d BCM4322 802.11an Wireless Network Controller 4331 BCM4331 802.11a/b/g/n 106b 00d6 AirPort Extreme + 106b 00e4 AirPort Extreme + 106b 00ef AirPort Extreme + 106b 00f4 AirPort Extreme + 106b 00f5 AirPort Extreme + 106b 010e AirPort Extreme + 106b 010f AirPort Extreme 4333 Serial (EDGE/GPRS modem part of Option GT Combo Edge) 4344 EDGE/GPRS data and 802.11b/g combo cardbus [GC89] + 4350 BCM43222 Wireless Network Adapter + 4351 BCM43222 802.11abgn Wireless Network Adapter 4353 BCM43224 802.11a/b/g/n 1028 000e Wireless 1520 Half-size Mini PCIe Card 103c 1509 WMIB-275N Half-size Mini PCIe Card + 106b 0093 AirPort Extreme + 106b 00d1 AirPort Extreme + 106b 00e9 AirPort Extreme 4357 BCM43225 802.11b/g/n 105b e021 T77H103.00 Wireless Half-size Mini PCIe Card 4358 BCM43227 802.11b/g/n 4359 BCM43228 802.11a/b/g/n 1028 0011 Wireless 1530 Half-size Mini PCIe Card 103c 182c BCM943228HM4L 802.11a/b/g/n 2x2 Wi-Fi Adapter + 4360 BCM4360 802.11ac Wireless Network Adapter 4365 BCM43142 802.11b/g/n 1028 0016 Wireless 1704 802.11n + BT 4.0 + 43a0 BCM4360 802.11ac Wireless Network Adapter + 43a1 BCM4360 802.11ac Wireless Network Adapter + 43a2 BCM4360 802.11ac Wireless Network Adapter + 43a9 BCM43217 802.11b/g/n + 43aa BCM43131 802.11b/g/n + 43b1 BCM4352 802.11ac Wireless Network Adapter + 43ba BCM43602 802.11ac Wireless LAN SoC + 43bb BCM43602 802.11ac Wireless LAN SoC + 43bc BCM43602 802.11ac Wireless LAN SoC + 43d3 BCM43567 802.11ac Wireless Network Adapter + 43d9 BCM43570 802.11ac Wireless Network Adapter + 43df BCM4354 802.11ac Wireless LAN SoC + 43e9 BCM4358 802.11ac Wireless LAN SoC + 43ec BCM4356 802.11ac Wireless Network Adapter 4401 BCM4401 100Base-T 1025 0035 TravelMate 660 + 1025 0064 Extensa 3000 series laptop 103c 08b0 tc1100 tablet 1043 80a8 A7V8X motherboard 4402 BCM4402 Integrated 10/100BaseT @@ -13081,13 +16587,13 @@ 4712 BCM47xx V.92 56k modem 4713 Sentry5 Ethernet Controller 4714 BCM47xx Sentry5 External Interface - 4715 Sentry5 USB Controller + 4715 BCM47xx Sentry5 USB / Ethernet Controller 4716 BCM47xx Sentry5 USB Host Controller 4717 BCM47xx Sentry5 USB Device Controller 4718 Sentry5 Crypto Accelerator 4719 BCM47xx/53xx RoboSwitch Core 4720 BCM4712 MIPS CPU - 4727 BCM4313 802.11b/g/n Wireless LAN Controller + 4727 BCM4313 802.11bgn Wireless Network Adapter 1028 0010 Inspiron M5010 / XPS 8300 5365 BCM5365P Sentry5 Host Bridge 5600 BCM5600 StrataSwitch 24+2 Ethernet Switch Controller @@ -13110,7 +16616,13 @@ 5840 BCM5840 Crypto Accelerator 5841 BCM5841 Crypto Accelerator 5850 BCM5850 Crypto Accelerator + 8602 BCM7400/BCM7405 Serial ATA Controller + a8d8 BCM43224/5 Wireless Network Adapter + aa52 BCM43602 802.11ac Wireless LAN SoC + b302 BCM56302 StrataXGS 24x1GE 2x10GE Switch Controller + b334 BCM56334 StrataXGS 24x1GE 4x10GE Switch Controller b800 BCM56800 StrataXGS 10GE Switch Controller + b842 BCM56842 Trident 10GE Switch Controller 14e5 Pixelfusion Ltd 14e6 SHINING Technology Inc 14e7 3CX @@ -13174,6 +16686,7 @@ 1054 HCF 56k Data/Fax/Voice Modem (Worldwide) 1055 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide) 1056 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) + 122d 4035 MDP3900V-W 1057 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) 1059 HCF 56k Data/Fax/Voice Modem (Worldwide) 1063 HCF 56k Data/Fax Modem @@ -13209,6 +16722,8 @@ 1815 HCF 56k Modem 0e11 0022 Grizzly 0e11 0042 Yogi +# Integrated in CX86111/CX86113 processors + 1830 CX861xx Integrated Host Bridge 2003 HSF 56k Data/Fax Modem 2004 HSF 56k Data/Fax/Voice Modem 2005 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem @@ -13263,8 +16778,6 @@ 2464 HSF 56k Data/Fax/Voice Modem (Mob SmartDAA) 2465 HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA) 2466 HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA) - 2bfa D110 HDAudio Soft Data Fax Modem with SmartCP - 1025 0009 Aspire 5622WLMi 2f00 HSF 56k HSFi Modem 13e0 8d84 IBM HSFi V.90 13e0 8d85 Compaq Stinger @@ -13277,16 +16790,15 @@ 2f30 SoftV92 SpeakerPhone SoftRing Modem with SmartSP 14f1 2014 Devolo MikroLink 56K Modem PCI 2f50 Conexant SoftK56 Data/Fax Modem - 5045 CX20549 (Venice) - 5047 High Definition Audio [Waikiki] - 5051 High Definition Audio (HERMOSA) 5b7a CX23418 Single-Chip MPEG-2 Encoder with Integrated Analog Video/Broadcast Audio Decoder 0070 7444 WinTV HVR-1600 + 107d 6f34 WinFast DVR3100 H 5854 3343 GoTView PCI DVD3 Hybrid 8200 CX25850 8234 RS8234 ATM SAR Controller [ServiceSAR Plus] 8800 CX23880/1/2/3 PCI Video and Audio Decoder 0070 2801 Hauppauge WinTV 28xxx (Roslyn) models + 0070 3400 WinTV 34604 0070 3401 Hauppauge WinTV 34xxx models 0070 6902 WinTV HVR-4000-HD 0070 7801 WinTV HVR-1800 MCE @@ -13297,6 +16809,7 @@ 0070 9600 WinTV 88x Video 0070 9802 WinTV-HVR1100 DVB-T/Hybrid (Low Profile) 1002 00f8 ATI TV Wonder Pro + 1002 00f9 ATI TV Wonder 1002 a101 HDTV Wonder 1043 4823 ASUS PVR-416 107d 6611 Winfast TV 2000XP Expert @@ -13364,6 +16877,7 @@ 0070 9402 WinTV-HVR1100 DVB-T/Hybrid 7063 5500 pcHDTV HD-5500 8811 CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port] + 0070 3400 WinTV 34604 0070 3401 Hauppauge WinTV 34xxx models 0070 6902 WinTV HVR-4000-HD 0070 9402 WinTV-HVR1100 DVB-T/Hybrid @@ -13375,11 +16889,20 @@ 18ac db00 DVICO FusionHDTV DVB-T1 5654 2388 GoTView PCI Hybrid Audio Capture Device 8852 CX23885 PCI Video and Audio Decoder - 0070 8010 Hauppauge WinTV HVR-1400 ExpressCard + 0070 8010 WinTV HVR-1400 ExpressCard + 0070 f038 WinTV HVR-5525 + 107d 6f22 WinFast PxTV1200 + 13c2 3013 TT-budget CT2-4500 CI 1461 c039 AVerTV Hybrid Express (A577) 153b 117e Cinergy T PCIe Dual 18ac db78 FusionHDTV DVB-T Dual Express + 4254 0950 S950 + 4254 0952 S952 + 4254 0982 T982 + 4254 9580 T9580 + 4254 980c T980C 8880 CX23887/8 PCIe Broadcast Audio and Video Decoder with 3D Comb + 0070 2259 WinTV HVR-1250 0070 c108 WinTV-HVR-4400-HD model 1278 5654 2389 GoTView X5 DVD Hybrid PCI-E 5654 2390 GoTView X5 3D HYBRID PCI-E @@ -13562,9 +17085,13 @@ 1541 MACHONE Communications 1542 Concurrent Computer Corporation 9260 RCIM-II Real-Time Clock & Interrupt Module + 9271 RCIM-III Real-Time Clock & Interrupt Module (PCIe) + 9272 Pulse Width Modulator Card + 9277 5 Volt Delta Sigma Converter Card + 9278 10 Volt Delta Sigma Converter Card + 9287 Analog Output Card 1543 SILICON Laboratories 3052 Intel 537 [Winmodem] - 3155 Motorola SM56 Speakerphone Modem 4c22 Si3036 MC'97 DAA 1544 DCM DATA Systems 1545 VISIONTEK @@ -13584,7 +17111,9 @@ 1553 CHICONY Electronics Co Ltd 1554 PROLINK Microsystems Corp 1555 GESYTEC GmBH -1556 PLD APPLICATIONS +1556 PLDA + 1100 PCI Express Core Reference Design + 110f PCI Express Core Reference Design Virtual Function 1557 MEDIASTAR Co Ltd 1558 CLEVO/KAPOK Computer 1559 SI LOGIC Ltd @@ -13714,10 +17243,13 @@ 0740 Virtual Machine Communication Interface 0770 USB2 EHCI Controller 0774 USB1.1 UHCI Controller + 0778 USB3 xHCI 0.96 Controller + 0779 USB3 xHCI 1.0 Controller 0790 PCI bridge 07a0 PCI Express Root Port 07b0 VMXNET3 Ethernet Controller 07c0 PVSCSI SCSI Controller + 07e0 SATA AHCI controller 0801 Virtual Machine Interface 15ad 0800 Hypervisor ROM Interface 1977 HD Audio Controller @@ -13729,13 +17261,25 @@ 0191 MT25408 [ConnectX IB Flash Recovery] 01f6 MT27500 Family [ConnectX-3 Flash Recovery] 01ff MT27600 Family [Connect-IB Flash Recovery] + 0209 MT27700 Family [ConnectX-4 Flash Recovery] + 020b MT27710 Family [ConnectX-4 Lx Flash Recovery] 1002 MT25400 Family [ConnectX-2 Virtual Function] 1003 MT27500 Family [ConnectX-3] - 1004 MT27500 Family [ConnectX-3 Virtual Function] + 103c 1777 InfiniBand FDR/EN 10/40Gb Dual Port 544FLR-QSFP Adapter (Rev Cx) + 103c 17c9 Infiniband QDR/Ethernet 10Gb 2-port 544i Adapter + 103c 18ce InfiniBand QDR/EN 10Gb Dual Port 544M Adapter + 103c 18cf InfiniBand FDR/EN 10/40Gb Dual Port 544M Adapter + 103c 18d6 InfiniBand FDR/EN 10/40Gb Dual Port 544QSFP Adapter + 1004 MT27500/MT27520 Family [ConnectX-3/ConnectX-3 Pro Virtual Function] 1005 MT27510 Family 1006 MT27511 Family - 1007 MT27520 Family - 1008 MT27521 Family + 1007 MT27520 Family [ConnectX-3 Pro] + 103c 22f3 InfiniBand FDR/Ethernet 10Gb/40Gb 2-port 544+QSFP Adapter + 103c 22f4 InfiniBand FDR/Ethernet 10Gb/40Gb 2-port 544+FLR-QSFP Adapter + 117c 0090 FastFrame NQ41 + 117c 0091 FastFrame NQ42 + 117c 0092 FastFrame NQ11 + 117c 0093 FastFrame NQ12 1009 MT27530 Family 100a MT27531 Family 100b MT27540 Family @@ -13746,10 +17290,12 @@ 1010 MT27561 Family 1011 MT27600 [Connect-IB] 1012 MT27600 Family [Connect-IB Virtual Function] - 1013 MT27620 Family - 1014 MT27621 Family - 1015 MT27630 Family - 1016 MT27631 Family + 1013 MT27700 Family [ConnectX-4] + 1014 MT27700 Family [ConnectX-4 Virtual Function] + 1015 MT27710 Family [ConnectX-4 Lx] + 1016 MT27710 Family [ConnectX-4 Lx Virtual Function] + 1017 MT27640 Family + 1018 MT27641 Family 5274 MT21108 InfiniBridge 5a44 MT23108 InfiniHost 5a45 MT23108 [Infinihost HCA Flash Recovery] @@ -13766,10 +17312,13 @@ 6372 MT25408 [ConnectX EN 10GigE 10GBaseT, PCIe 2.0 2.5GT/s] 6732 MT26418 [ConnectX VPI PCIe 2.0 5GT/s - IB DDR / 10GigE] 673c MT26428 [ConnectX VPI PCIe 2.0 5GT/s - IB QDR / 10GigE] + 103c 1782 4X QDR InfiniBand Mezzanine HCA for c-Class BladeSystem + 15b3 0021 HP InfiniBand 4X QDR CX-2 PCI-e G2 Dual Port HCA 6746 MT26438 [ConnectX VPI PCIe 2.0 5GT/s - IB QDR / 10GigE Virtualization+] 103c 1781 NC543i 1-port 4x QDR IB/Flex-10 10Gb Adapter 103c 3349 NC543i 2-port 4xQDR IB/10Gb Adapter 6750 MT26448 [ConnectX EN 10GigE, PCIe 2.0 5GT/s] + 15b3 0018 HP 10 GbE PCI-e G2 Dual-Port NIC (rev C1) 675a MT25408 [ConnectX EN 10GigE 10GBaseT, PCIe Gen2 5GT/s] 6764 MT26468 [ConnectX EN 10GigE, PCIe 2.0 5GT/s Virtualization+] 103c 3313 HP NC542m Dual Port Flex-10 10GbE BLc Adapter @@ -13812,8 +17361,10 @@ 15bc Agilent Technologies 0100 HPFC-5600 Tachyon DX2+ FC 0103 QX4 PCI Express quad 4-gigabit Fibre Channel controller - 0105 Celerity FC-42XS Fibre Channel Adapter + 0105 Celerity FC-44XS/FC-42XS/FC-41XS/FC-44ES/FC-42ES/FC-41ES 117c 0022 Celerity FC-42XS Fibre Channel Adapter + 117c 0025 Celerity FC-44ES Fibre Channel Adapter + 117c 0026 Celerity FC-42ES Fibre Channel Adapter 1100 E8001-66442 PCI Express CIC 2922 64 Bit, 133MHz PCI-X Exerciser & Protocol Checker 2928 64 Bit, 66MHz PCI Exerciser & Analyzer @@ -13839,6 +17390,7 @@ 15cd Dreamtech Co Ltd 15ce Genrad Inc 15cf Hilscher GmbH + 0000 CIFX 50E-DP(M/S) 15d1 Infineon Technologies AG 15d2 FIC (First International Computer Inc) 15d3 NDS Technologies Israel Ltd @@ -13924,10 +17476,14 @@ 0620 FarSync T2U (2 port X.21/V.35/V.24) 0640 FarSync T4U (4 port X.21/V.35/V.24) 1610 FarSync TE1 (T1,E1) + 1612 FarSync TE1 PCI Express (T1,E1) 2610 FarSync DSL-S1 (SHDSL) 3640 FarSync T4E (4-port X.21/V.35/V.24) 4620 FarSync T2Ue PCI Express (2-port X.21/V.35/V.24) 4640 FarSync T4Ue PCI Express (4-port X.21/V.35/V.24) + 5621 FarSync T2Ee PCI Express (2 port X.21/V.35/V.24) + 5641 FarSync T4Ee PCI Express (4 port X.21/V.35/V.24) + 6620 FarSync T2U-PMC PCI Express (2 port X.21/V.35/V.24) 161f Rioworks 1626 TDK Semiconductor Corp. 8410 RTL81xx Fast Ethernet @@ -13943,6 +17499,7 @@ 3052 SmartLink SmartPCI562 56K Modem 5449 SmartPCI561 Modem 1641 MKNet Corp. +1642 Bitland(ShenZhen) Information Technology Co., Ltd. 1657 Brocade Communications Systems, Inc. 0013 425/825/42B/82B 4Gbps/8Gbps PCIe dual port FC HBA 103c 1742 HP 82B 8Gbps dual port FC HBA @@ -13956,16 +17513,88 @@ 103c 1743 HP 81B 8Gbps single port FC HBA 1657 0014 415/815 4Gbps/8Gbps single port PCIe FC HBA 0021 804 8Gbps FC HBA for HP Bladesystem c-class - 0022 1867/1860: 16Gbps/10Gbps Fabric Adapter +# AnyIO Adapter + 0022 1860 16Gbps/10Gbps Fabric Adapter 1657 0022 10Gbps CNA - FCOE 1657 0023 10Gbps CNA - LL 1657 0024 16Gbps FC HBA +# Mezz card for IBM + 0023 1867/1869 16Gbps FC HBA # Same Device_ID used for 410 (1port) and 420 (2 port) HBAs. 0646 400 4Gbps PCIe FC HBA 165a Epix Inc c100 PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232] d200 PIXCI(R) D2X Digital Video Capture Board [custom QL5232] d300 PIXCI(R) D3X Digital Video Capture Board [custom QL5232] + eb01 PIXCI(R) EB1 PCI Camera Link Video Capture Board +# Gidel Reconfigurable Computing +165c Gidel Ltd. + 5361 PROCStarII60-1 + 5362 PROCStarII60-2 + 5364 PROCStarII60-4 + 5435 ProcSparkII + 5661 ProcE60 + 56e1 ProcE180 + 5911 ProcStarIII110-1 + 5912 ProcStarIII110-2 + 5913 ProcStarIII110-3 + 5914 ProcStarIII110-4 + 5921 ProcStarIII150-1 + 5922 ProcStarIII150-2 + 5923 ProcStarIII150-3 + 5924 ProcStarIII150-4 + 5931 ProcStarIII260-1 + 5932 ProcStarIII260-2 + 5933 ProcStarIII260-3 + 5934 ProcStarIII260-4 + 5941 ProcStarIII340-1 + 5942 ProcStarIII340-2 + 5943 ProcStarIII340-3 + 5944 ProcStarIII340-4 + 5a01 ProceIII80 + 5a11 ProceIII110 + 5a21 ProceIII150 + 5a31 ProceIII260 + 5a41 ProceIII340 + 5b51 ProceIV360 + 5b61 ProceIV530 + 5b71 ProceIV820 + 5c01 ProcStarIV80-1 + 5c02 ProcStarIV80-2 + 5c03 ProcStarIV80-3 + 5c04 ProcStarIV80-4 + 5c11 ProcStarIV110-1 + 5c12 ProcStarIV110-2 + 5c13 ProcStarIV110-3 + 5c14 ProcStarIV110-4 + 5c51 ProcStarIV360-1 + 5c52 ProcStarIV360-2 + 5c53 ProcStarIV360-3 + 5c54 ProcStarIV360-4 + 5c61 ProcStarIV530-1 + 5c62 ProcStarIV530-2 + 5c63 ProcStarIV530-3 + 5c64 ProcStarIV530-4 + 5c71 ProcStarIV820-1 + 5c72 ProcStarIV820-2 + 5c73 ProcStarIV820-3 + 5c74 ProcStarIV820-4 + 5d01 Proc10480 + 5d11 Proc104110 + 5f01 ProceV_A3 + 5f11 ProceV_A7 + 5f21 ProceV_AB + 5f31 ProceV_D5 + 5f41 ProceV_D8 + 6732 Proc6M + 6832 Proc12M + 7101 Proc10a_27 + 7111 Proc10a_48 + 7121 Proc10a_66 + 7141 Proc10a_115 + 7181 Proc10a_27S + 7191 Proc10a_48S + 71a1 Proc10a_66S 165d Hsing Tech. Enterprise Co., Ltd. 165f Linux Media Labs, LLC 1020 LMLM4 MPEG-4 encoder @@ -13998,7 +17627,8 @@ 1682 XFX Pine Group Inc. 1688 CastleNet Technology Inc. 1170 WLAN 802.11b card -168c Atheros Communications Inc. +# nee Atheros Communications, Inc. +168c Qualcomm Atheros 0007 AR5210 Wireless Network Adapter [AR5000 802.11a] 1737 0007 WPC54A Wireless PC Card 1b47 0100 Harmony 8450CN Wireless CardBus Module @@ -14006,11 +17636,13 @@ 8086 2501 PRO/Wireless 5000 LAN PCI Adapter Module 0011 AR5211 Wireless Network Adapter [AR5001A 802.11a] 0012 AR5211 Wireless Network Adapter [AR5001X 802.11ab] + 1186 3a03 AirPro DWL-A650 Wireless Cardbus Adapter (rev.B) + 1186 3a04 AirPro DWL-AB650 Multimode Wireless Cardbus Adapter + 1186 3a05 AirPro DWL-AB520 Multimode Wireless PCI Adapter 126c 8031 2201 Mobile Adapter 1385 4400 WAB501 802.11ab Wireless CardBus Card 1b47 aa00 8460 802.11ab Wireless CardBus Adapter -# AR5001G, AR5001X+, AR5002G, AR5002X, AR5004G, AR5004X chipsets - 0013 AR5212/AR5213 Wireless Network Adapter + 0013 AR5212/5213/2414 Wireless Network Adapter 0308 3402 AG-100 802.11ag Wireless Cardbus Adapter 0308 3405 G-102 v2 802.11g Wireless Cardbus Adapter 0308 3408 G-170S 802.11g Wireless CardBus Adapter @@ -14022,6 +17654,8 @@ 1154 034e Buffalo WLI-CB-AG108HP 802.11abg Cardbus Adapter 1186 3202 DWL-G650 (Rev B3,B5) Wireless cardbus adapter 1186 3203 AirPlus DWL-G520 Wireless PCI Adapter (rev. A) + 1186 3a07 AirXpert DWL-AG650 Wireless Cardbus Adapter + 1186 3a08 AirXpert DWL-AG520 Wireless PCI Adapter 1186 3a12 D-Link AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C) 1186 3a13 AirPlus DWL-G520 Wireless PCI Adapter (rev. B) 1186 3a14 AirPremier AG DWL-AG530 Wireless PCI Adapter (rev.A) @@ -14032,14 +17666,17 @@ 1186 3a93 Conceptronic C54I Wireless 801.11g PCI card 1186 3a94 Conceptronic C54C 802.11g Wireless Cardbus Adapter 1186 3ab0 Allnet ALL0281 Wireless PCI Card + 1385 4600 WAG511 802.11a/b/g Dual Band Wireless PC Card + 1385 4610 WAG511 802.11a/b/g Dual Band Wireless PC Card 1385 4900 WG311v1 802.11g Wireless PCI Adapter + 1385 4a00 WAG311 802.11a/g Wireless PCI Adapter 1385 4b00 WG511T 108 Mbps Wireless PC Card (rev.A/B) 1385 4d00 WG311T 108 Mbps Wireless PCI Adapter (rev.A2) 1385 4f00 WG511U Double 108 Mbps Wireless PC Card - 1385 5a00 WG311T 108 Mbps Wireless PCI Adapter (rev.A3) + 1385 5a00 WG311T (rev.A3 v1h3/v1h4) 108 Mbps Wireless PCI Adapter [AR2412] 1385 5b00 WG511T 108 Mbps Wireless PC Card (rev.C) 1385 5d00 WPN511 RangeMax Wireless PC Card - 1458 e911 Gigabyte GN-WIAG02 + 1458 e911 GN-WIAG02 1468 0403 U10H014 802.11g Cardbus Adapter 1468 0408 ThinkPad 11b/g Wireless LAN Mini PCI Adapter 14b7 0a10 8480-WD 802.11abg Cardbus Adapter @@ -14091,6 +17728,8 @@ 17f9 0008 DX-WGNBC 802.11bg Wireless CardBus Adapter 17f9 0018 DX-WGDTC 802.11bg Wireless PCI Adapter 001b AR5413/AR5414 Wireless Network Adapter [AR5006X(S) 802.11abg] +# Atheros AR5414 32-bit mini-PCI type IIIB + 0777 1107 UB5 802.11a Wireless Mini PCI Adapter 0777 3002 XR2 802.11g Wireless Mini PCI Adapter 0777 3005 XR5 802.11a Wireless Mini PCI Adapter 0777 3009 XR9 900MHz Wireless Mini PCI Adapter @@ -14112,7 +17751,7 @@ 001c AR242x / AR542x Wireless Network Adapter (PCI-Express) 0777 3006 SRX 802.11abg Wireless ExpressCard Adapter 103c 137a AR5BXB63 (Foxconn) 802.11bg Mini PCIe NIC - 106b 0086 AR5BXB6 802.11abg Wireless Mini PCIe Card + 106b 0086 AirPort Extreme 144f 7106 WLL3140 (Toshiba PA3501U-1MPC) 802.11bg Wireless Mini PCIe Card 144f 7128 WLL3141 (Toshiba PA3613U-1MPC) 802.11bg Wireless Mini PCIe Card 1468 0428 AR5BXB63 802.11bg NIC @@ -14150,17 +17789,21 @@ 187e 3411 NWD-370N 802.11n Wireless PCI Adapter 1976 2008 TEW-621PC 802.11bgn Wireless CardBus Adapter 0024 AR5418 Wireless Network Adapter [AR5008E 802.11(a)bgn] (PCI-Express) - 106b 0087 AR5BXB72 802.11abgn Mini PCIe Card [AR5008E-3NX] + 106b 0087 AirPort Extreme + 1186 3a70 DWA-556 Xtreme N PCI Express Desktop Adapter 0027 AR9160 Wireless Network Adapter [AR9001 802.11(a)bgn] 0777 4082 SR71-A 802.11abgn Wireless Mini PCI Adapter 0029 AR922X Wireless Network Adapter 0777 4005 SR71-15 802.11an Mini PCI Adapter 1186 3a7a DWA-552 802.11n Xtreme N Desktop Adapter (rev A2) + 1186 3a7d DWA-552 802.11n Xtreme N Desktop Adapter (rev A3) 002a AR928X Wireless Network Adapter (PCI-Express) 0777 4f05 SR71-X 802.11abgn Wireless ExpressCard Adapter [AR9280] 103c 3041 AR5BHB92-H 802.11abgn Wireless Half-size Mini PCIe Card [AR9280] + 103c 3042 AzureWave AW-NE773 802.11abgn Wireless Half-size Mini PCIe Card [AR9280] 105b e006 T77H053.00 802.11bgn Wireless Mini PCIe Card [AR9281] 105b e01f T77H047.31 802.11bgn Wireless Half-size Mini PCIe Card [AR9283] + 106b 008f AirPort Extreme 11ad 6600 WN6600A 802.11bgn Wireless Mini PCIe Card [AR9281] 144f 7141 WLL6080 802.11bgn Wireless Mini PCIe Card [AR9281] 168c 0203 DW1525 802.11abgn WLAN PCIe Card [AR9280] @@ -14174,6 +17817,8 @@ 103c 303f U98Z062.10 802.11bgn Wireless Half-size Mini PCIe Card 103c 3040 U98Z062.12 802.11bgn Wireless Half-size Mini PCIe Card 105b e017 T77H126.00 802.11bgn Wireless Half-size Mini PCIe Card + 105b e023 T77H121.04 802.11bgn Wireless Half-size Mini PCIe Card + 105b e025 T77H121.05 802.11bgn Wireless Half-size Mini PCIe Card 1113 e811 WN7811A (Toshiba PA3722U-1MPC) 802.11bgn Wireless Half-size Mini PCIe Card 185f 30af DNXA-95 802.11bgn Wireless Half-size Mini PCIe Card 1931 0023 Option GTM67x PCIe WiFi Adapter @@ -14184,22 +17829,36 @@ 002c AR2427 802.11bg Wireless Network Adapter (PCI-Express) 002d AR9227 Wireless Network Adapter 002e AR9287 Wireless Network Adapter (PCI-Express) - 0030 AR9300 Wireless LAN adaptor + 105b e034 T77H167.00 + 0030 AR93xx Wireless Network Adapter 103c 1627 AR9380/HB112 802.11abgn 3×3 Wi-Fi Adapter + 106b 009a AirPort Extreme + 1186 3a7e DWA-566 Wireless N 300 Dual Band PCIe Desktop Adapter 1a56 2000 Killer Wireless-N 1102 Half-size Mini PCIe Card [AR9382] 1a56 2001 Killer Wireless-N 1103 Half-size Mini PCIe Card [AR9380] 0032 AR9485 Wireless Network Adapter 103c 1838 AR9485/HB125 802.11bgn 1×1 Wi-Fi Adapter + 105b e044 Unex DHXA-225 0033 AR9580 Wireless Network Adapter 0034 AR9462 Wireless Network Adapter - 0036 AR9565 Wireless Network Adapter + 1a56 2003 Killer Wireless-N 1202 Half-size Mini PCIe Card + 0036 QCA9565 / AR9565 Wireless Network Adapter + 0037 AR9485 Wireless Network Adapter +# Also used as Gigabyte GC-WB150 on a PCIe-to-mini-PCIe converter + 1a3b 2100 AW-NB100H 802.11n Wireless Mini PCIe Card + 003c QCA986x/988x 802.11ac Wireless Network Adapter + 003e QCA6174 802.11ac Wireless Network Adapter + 1a56 1525 Killer N1525 Wireless-AC 0207 AR5210 Wireless Network Adapter [AR5000 802.11a] 1014 AR5212 802.11abg NIC 1014 058a ThinkPad 11a/b/g Wireless LAN Mini Express Adapter (AR5BXB6) 9013 AR5002X Wireless Network Adapter ff19 AR5006X Wireless Network Adapter + ff1b AR2425 Wireless Network Adapter [AR5007EG 802.11bg] ff1c AR5008 Wireless Network Adapter - ff1d AR5008 Wireless Network Adapter + ff1d AR922x Wireless Network Adapter +# Found in "AVM Fritz!Box FON WLAN 7270v3" + 168c ee1c AR9220-AC1A [AVM Fritz!Box FON WLAN 7270 v3] 1695 EPoX Computer Co., Ltd. 169c Netcell Corporation 0044 Revolution Storage Processing Card @@ -14220,6 +17879,7 @@ 16b4 Aspex Semiconductor Ltd 16b8 Sonnet Technologies, Inc. 16be Creatix Polymedia GmbH +16c3 Synopsys, Inc. 16c6 Micrel-Kendin 8695 Centaur KS8695 ARM processor 8842 KSZ8842-PMQL 2-Port Ethernet Switch @@ -14296,6 +17956,14 @@ 6302 XMC Module with user-configurable Virtex-6 FPGA, 365k logic cells, SFP front I/O 6303 XMC Module with user-configurable Virtex-6 FPGA, 240k logic cells, no front I/O 6304 XMC Module with user-configurable Virtex-6 FPGA, 365k logic cells, no front I/O + 7000 XMC-7K325F: User-configurable Kintex-7 FPGA, 325k logic cells plus SFP front I/O + 7001 XMC-7K410F: User-configurable Kintex-7 FPGA, 410k logic cells plus SFP front I/O + 7002 XMC-7K325AX: User-Configurable Kintex-7 FPGA, 325k logic cells with AXM Plug-In I/O + 7003 XMC-7K410AX: User-Configurable Kintex-7 FPGA, 410k logic cells with AXM Plug-In I/O + 7004 XMC-7K325CC: User-Configurable Kintex-7 FPGA, 325k logic cells, conduction-cooled + 7005 XMC-7K410CC: User-Configurable Kintex-7 FPGA, 410k logic cells, conduction-cooled + 7006 XMC-7A200: User-Configurable Artix-7 FPGA, 200k logic cells with Plug-In I/O + 7007 XMC-7A200CC: User-Configurable Conduction-Cooled Artix-7 FPGA, with 200k logic cells 16da Advantech Co., Ltd. 0011 INES GPIB-PCI 16df PIKA Technologies Inc. @@ -14314,6 +17982,9 @@ ab06 USR997901A 10/100 Cardbus NIC 16ed Sycron N. V. 1001 UMIO communication card +16f2 ETAS GmbH + 0200 I/O board + 16f2 0010 ES53xx I/O board 16f3 Jetway Information Co., Ltd. 16f4 Vweb Corp 8000 VW2010 @@ -14324,15 +17995,14 @@ 0100 NSP2000-SSL crypto accelerator 170c YottaYotta Inc. 1719 EZChip Technologies + 1000 NPA Access Network Processor Family # Seems to be a 2nd ID for Vitesse Semiconductor 1725 Vitesse Semiconductor 7174 VSC7174 PCI/PCI-X Serial ATA Host Bus Controller 172a Accelerated Encryption 13c8 AEP SureWare Runner 1000V3 +# nee Fujitsu Siemens Computers GmbH 1734 Fujitsu Technology Solutions - 1078 Amilo Pro v2010 - 1085 Celsius M450 - 1098 Amilo L 1310G 1735 Aten International Co. Ltd. 1737 Linksys 0029 WPG54G ver. 4 PCI Card @@ -14355,15 +18025,18 @@ 2020 XCode II Series 2100 XCode 2100 Series 1749 RLX Technologies -174b PC Partner Limited +174b PC Partner Limited / Sapphire Technology 174d WellX Telecom SA 175c AudioScience Inc 175e Sanera Systems, Inc. 1760 TEDIA spol. s r. o. + 0101 PCD-7004 Digital Bi-Directional Ports PCI Card + 0102 PCD-7104 Digital Input & Output PCI Card + 0303 PCD-7006C Digital Input & Output PCI Card 1771 InnoVISION Multimedia Ltd. # nee SBS Technologies 1775 GE Intelligent Platforms -177d Cavium Networks +177d Cavium, Inc. 0001 Nitrox XL N1 0003 Nitrox XL N1 Lite 0004 Octeon (and older) FIPS @@ -14380,6 +18053,58 @@ 0091 Octeon II CN68XX Network Processor 0092 Octeon II CN65XX Network Processor 0093 Octeon II CN61XX Network Processor + 0094 Octeon Fusion CNF71XX Cell processor + 0095 Octeon III CN78XX Network Processor + 0096 Octeon III CN70XX Network Processor + 9700 Octeon III CN73XX Network Processor + 9800 Octeon Fusion CNF75XX Processor + a001 THUNDERX MRML Bridge + a002 THUNDERX PCC Bridge + 177d a102 CN88XX PCC Bridge + a008 THUNDERX SMMU + 177d a108 CN88XX SMMU + a009 THUNDERX Generic Interrupt Controller + a00a THUNDERX GPIO Controller + a00b THUNDERX MPI / SPI Controller + a00c THUNDERX MIO-PTP Controller + a00d THUNDERX MIX Network Controller + a00e THUNDERX Reset Controller + a00f THUNDERX UART Controller + a010 THUNDERX eMMC/SD Controller + a011 THUNDERX MIO-BOOT Controller + a012 THUNDERX TWSI / I2C Controller + a013 THUNDERX CCPI (Multi-node connect) + a014 THUNDERX Voltage Regulator Module + a015 THUNDERX PCIe Switch Logic Interface + a016 THUNDERX Key Memory + a017 THUNDERX GTI (Global System Timers) + a018 THUNDERX Random Number Generator + a019 THUNDERX DFA + a01a THUNDERX Zip Coprocessor + a01b THUNDERX xHCI USB Controller + a01c THUNDERX AHCI SATA Controller + 177d a11c CN88XX AHCI SATA Controller + a01d THUNDERX RAID Coprocessor + a01e THUNDERX Network Interface Controller + a01f THUNDERX Traffic Network Switch + a020 THUNDERX PEM (PCI Express Interface) + a021 THUNDERX L2C (Level-2 Cache Controller) + a022 THUNDERX LMC (DRAM Controller) + a023 THUNDERX OCLA (On-Chip Logic Analyzer) + a024 THUNDERX OSM + a025 THUNDERX GSER (General Serializer/Deserializer) + a026 THUNDERX BGX (Common Ethernet Interface) + a027 THUNDERX IOBN + a029 THUNDERX NCSI (Network Controller Sideband Interface) + a02a THUNDERX SGP + a02b THUNDERX SMI / MDIO Controller + a02c THUNDERX DAP (Debug Access Port) + a02d THUNDERX PCIERC (PCIe Root Complex) + a02e THUNDERX L2C-TAD + a02f THUNDERX L2C-CBC + a030 THUNDERX L2C-MCI + a031 THUNDERX MIO-FUS (Fuse Access Controller) + a032 THUNDERX FUSF (Fuse Controller) 1787 Hightech Information System Ltd. 1789 Ennyah Technologies Corp. # also used by Struck Innovative Systeme for joint developments @@ -14396,13 +18121,24 @@ 0010 PCIe Counter Timer 0011 SIS1100-e single link 0012 SIS1100-e quad link -1797 Techwell Inc. + 0015 SIS8100 [Gigabit link, MicroTCA] +# nee Techwell, Inc. +1797 Intersil Techwell + 5864 TW5864 multimedia video controller 6801 TW6802 multimedia video card 6802 TW6802 multimedia other device 6810 TW6816 multimedia video controller 6811 TW6816 multimedia video controller 6812 TW6816 multimedia video controller 6813 TW6816 multimedia video controller +# port 5 of 8 + 6814 TW6816 multimedia video controller +# port 6 of 8 + 6815 TW6816 multimedia video controller +# port 7 of 8 + 6816 TW6816 multimedia video controller +# channel 8 of 8 + 6817 TW6816 multimedia video controller 1799 Belkin 6001 F5D6001 Wireless PCI Card [Realtek RTL8180] 6020 F5D6020 v3000 Wireless PCMCIA Card [Realtek RTL8180] @@ -14438,7 +18174,7 @@ 0017 StorSecure 300 GZIP Compression and AES Encryption Card 17c0 Wistron Corp. 17c2 Newisys, Inc. -17cb Airgo Networks Inc +17cb Airgo Networks, Inc. 0001 AGN100 802.11 a/b/g True MIMO Wireless Card 1385 5c00 WGM511 Pre-N 802.11g Wireless CardBus Adapter 1737 0045 WMP54GX v1 802.11g Wireless-G PCI Adapter with SRX @@ -14530,6 +18266,8 @@ 1468 0305 T60N871 802.11g Mini PCI Wireless Adapter 1737 0029 WPC54G v4 802.11g Wireless-G Notebook Adapter 17ff Benq Corporation +1800 Qualcore Logic Inc. + 1100 Nanospeed Trading Gateway 1803 ProdaSafe GmbH 1805 Euresys S.A. 1809 Lumanate, Inc. @@ -14594,6 +18332,7 @@ 0701 RT2760 Wireless 802.11n 1T/2R 1737 0074 WMP110 v2 802.11n RangePlus Wireless PCI Adapter 0781 RT2790 Wireless 802.11n 1T/2R PCIe + 1814 2790 RT2790 Wireless 802.11n 1T/2R PCIe 3060 RT3060 Wireless 802.11n 1T/1R 1186 3c04 DWA-525 Wireless N 150 Desktop Adapter (rev.A1) 3062 RT3062 Wireless 802.11n 2T/2R @@ -14601,14 +18340,22 @@ 13bd 1057 GN-WS32L-RH Half-size Mini PCIe Card 3091 RT3091 Wireless 802.11n 1T/2R PCIe 3092 RT3092 Wireless 802.11n 2T/2R PCIe - 3592 RT3592 Wireless 802.11abgn 1T/1R PCIe + 3290 RT3290 Wireless 802.11n 1T/1R PCIe + 103c 18ec Ralink RT3290LE 802.11bgn 1x1 Wi-Fi and Bluetooth 4.0 Combo Adapter + 3298 RT3290 Bluetooth + 103c 18ec Ralink RT3290LE 802.11bgn 1x1 Wi-Fi and Bluetooth 4.0 Combo Adapter + 3592 RT3592 Wireless 802.11abgn 2T/2R PCIe + 359f RT3592 PCIe Wireless Network Adapter 5360 RT5360 Wireless 802.11n 1T/1R 1186 3c05 DWA-525 Wireless N 150 Desktop Adapter (rev.A2) 20f4 703a TEW-703PI N150 Wireless PCI Adapter + 5362 RT5362 PCI 802.11n Wireless Network Adapter 5390 RT5390 Wireless 802.11n 1T/1R PCIe 103c 1636 U98Z077.00 Half-size Mini PCIe Card + 5392 RT5392 PCIe Wireless Network Adapter 539f RT5390 [802.11 b/g/n 1T1R G-band PCI Express Single Chip] 103c 1637 Pavilion DM1Z-3000 PCIe wireless card + 5592 RT5592 PCIe Wireless Network Adapter e932 RT2560F 802.11 b/g PCI 1815 Devolo AG 1820 InfiniCon Systems Inc. @@ -14653,14 +18400,15 @@ 0612 AD612 Data Acquisition Device 0614 MF614 Multifunction I/O Card 0622 AD622 Data Acquisition Device - 0624 MF624 Multifunction I/O Card + 0624 MF624 Multifunction I/O PCI Card 0625 MF625 3-phase Motor Driver + 0634 MF634 Multifunction I/O PCIe Card 186f WiNRADiO Communications 1876 L-3 Communications a101 VigraWATCH PCI a102 VigraWATCH PMC a103 Vigra I/O -187e ZyXEL Communication Corporation +187e ZyXEL Communications Corporation 3403 ZyAir G-110 802.11g 340e M-302 802.11g XtremeMIMO 1885 Avvida Systems Inc. @@ -14696,7 +18444,8 @@ db78 FusionHDTV DVB-T Dual Express 18b8 Ammasso b001 AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor -18bc Info-Tek Corp. +# formally Info-Tek Corp. +18bc GeCube Technologies, Inc. 18c3 Micronas Semiconductor Holding AG 0720 nGene PCI-Express Multimedia Controller 07ca 032e Hybrid M779 PCI-E @@ -14716,6 +18465,7 @@ 18d8 Dialogue Technology Corp. 18dd Artimi Inc 4c6f Artimi RTMI-100 UWB adapter +18df LeWiz Communications 18e6 MPL AG 0001 OSCI [Octal Serial Communication Interface] 18eb Advance Multimedia Internet Technology, Inc. @@ -14788,30 +18538,61 @@ 00e5 NT40E2-1 Network Adapter 1x40Gb # 4-Port Adapter for 1 GbE In-Line Bypass Applications 00f5 NT4E2-4T-BP Network Adapter 4x1Gb with Electrical Bypass + 0105 NT4E2-4-PTP Network Adapter 4x1Gb + 0115 NT20E2-PTP Network Adapter 2x10Gb + 0125 NT4E2-4-PTP Network Adapter 4x1Gb + 0135 NT20E2-PTP Network Adapter 2x10Gb + 0145 NT40E3-4-PTP Network Adapter 4x10Gb + 0155 NT100E3-1-PTP Network Adapter 1x100Gb + 0175 NT20E3-2-PTP Network Adapter 2x10Gb 18f6 NextIO 1000 [Nexsis] Switch Virtual P2P PCIe Bridge + 1001 [Texsis] Switch Virtual P2P PCIe Bridge 1050 [Nexsis] Switch Virtual P2P PCI Bridge + 1051 [Texsis] Switch Virtual P2P PCI Bridge 2000 [Nexsis] Switch Integrated Mgmt. Endpoint + 2001 [Texsis] Switch Integrated Mgmt. Endpoint 18f7 Commtech, Inc. - 0001 Fastcom ESCC-PCI-335 - 0002 Fastcom 422/4-PCI-335 - 0003 Fastcom 232/4-1M-PCI - 0004 Fastcom 422/2-PCI-335 - 0005 Fastcom IGESCC-PCI-ISO/1 - 000a Fastcom 232/4-PCI-335 - 000b Fastcom 232/8-PCI-335 Async 8-Port RS-232 Serial PCI Adapter - 000f Fastcom FSCC - 0010 Fastcom GSCC - 0011 Fastcom QSSB - 0014 SuperFSCC - 0015 SuperFSCC-104 - 0016 Fastcom FSCC-232 Sync/Async 2-Port RS-232 Serial PCI Adapter (F-Core) - 0017 SuperFSCC-104-NOUART - 0018 Fastcom SuperFSCC/4 Sync/Async 4-Port RS-422 Serial PCI Adapter with DMA (F-Core) - 0019 SuperFSCC with soft UARTs - 001a Fastcom SuperFSCC-104-LVDS Sync/Async 2-Port RS-644 Serial PC/104+ Adapter with DMA (F-Core) - 001b Fastcom FSCC/4 Sync/Async 4-Port RS-422 Serial PCI Adapter (F-Core) - 001c Fastcom SuperFSCC/4-LVDSSync/Async 4-Port RS-644 Serial PCI Adapter with DMA (F-Core) + 0001 ESCC-PCI-335 Serial PCI Adapter [Fastcom] + 0002 422/4-PCI-335 Serial PCI Adapter [Fastcom] + 0003 232/4-1M-PCI Serial PCI Adapter [Fastcom] + 0004 422/2-PCI-335 Serial PCI Adapter [Fastcom] + 0005 IGESCC-PCI-ISO/1 Serial PCI Adapter [Fastcom] + 000a 232/4-PCI-335 Serial PCI Adapter [Fastcom] + 000b 232/8-PCI-335 Serial PCI Adapter [Fastcom] + 000f FSCC Serial PCI Adapter [Fastcom] + 0010 GSCC Serial PCI Adapter [Fastcom] + 0011 QSSB Serial PCI Adapter [Fastcom] + 0014 SuperFSCC Serial PCI Adapter [Fastcom] + 0015 SuperFSCC-104-LVDS Serial PC/104+ Adapter [Fastcom] + 0016 FSCC-232 RS-232 Serial PCI Adapter [Fastcom] +# Software UARTs + 0017 SuperFSCC-104 Serial PC/104+ Adapter [Fastcom] +# Software UARTs + 0018 SuperFSCC/4 Serial PCI Adapter [Fastcom] +# Software UARTs + 0019 SuperFSCC Serial PCI Adapter [Fastcom] + 001a SuperFSCC-LVDS Serial PCI Adapter [Fastcom] +# Software UARTs + 001b FSCC/4 Serial PCI Adapter [Fastcom] +# RS-644 Only + 001c SuperFSCC/4-LVDS Serial PCI Adapter [Fastcom] +# Software UARTs + 001d FSCC Serial PCI Adapter [Fastcom] + 001e SuperFSCC/4 Serial PCIe Adapter [Fastcom] + 001f SuperFSCC/4 Serial cPCI Adapter [Fastcom] + 0020 422/4-PCIe Serial PCIe Adapter [Fastcom] + 0021 422/8-PCIe Serial PCIe Adapter [Fastcom] +# RS-644 Only + 0022 SuperFSCC/4-LVDS Serial PCIe Adapter [Fastcom] +# Software UARTs + 0023 SuperFSCC/4 Serial cPCI Adapter [Fastcom] +# RS-644 Only, Software UARTs + 0025 SuperFSCC/4-LVDS Serial PCI Adapter [Fastcom] +# RS-644 Only, Software UARTs + 0026 SuperFSCC-LVDS Serial PCI Adapter [Fastcom] +# Software UARTs + 0027 FSCC/4 Serial PCIe Adapter [Fastcom] 18fb Resilience Corporation 1904 Hangzhou Silan Microelectronics Co., Ltd. 2031 SC92031 PCI Fast Ethernet Adapter @@ -14822,6 +18603,8 @@ 0011 SH7757 PCIe End-Point [PBI] 0012 SH7757 PCIe-PCI Bridge [PPB] 0013 SH7757 PCIe Switch [PS] + 0014 uPD720201 USB 3.0 Host Controller + 0015 uPD720202 USB 3.0 Host Controller 1919 Soltek Computer Inc. 1923 Sangoma Technologies Corp. 0040 A200/Remora FXO/FXS Analog AFT card @@ -14859,40 +18642,63 @@ 1924 5201 SFN4112F-R1 1924 5202 SFN4112F-R2 0803 SFC9020 [Solarstorm] + 1014 0478 2-port 10GbE Low-Latency (R7) + 1014 0479 2-port 10GbE OpenOnload (R7) + 1014 04a7 Solarflare 10Gb Low-latency Dual-port HBA (R7) + 1014 04a8 Solarflare 10Gb Dual-port HBA (R7) + 103c 2132 Ethernet 10Gb 2-port 570FLR-SFP+ Adapter (R1) + 103c 2136 Ethernet 10Gb 2-port 570SFP+ Adapter (R7) 1924 1201 SFA6902F-R1 SFP+ AOE Adapter - 1924 6200 SFN5122F-R0 - 1924 6201 SFN5122F-R1 - 1924 6202 SFN5122F-R2 - 1924 6204 SFN5122F-R4 - 1924 6205 SFN5122F-R5 - 1924 6206 SFN5122F-R6 - 1924 6207 SFN5122F-R7 - 1924 6210 SFN5322F-R0 - 1924 6211 SFN5322F-R1 - 1924 6217 SFN5322F-R7 - 1924 6227 SFN6122F-R7 - 1924 6237 SFN6322F-R7 - 1924 6501 SFN5802K-R1 - 1924 6511 SFN5814H-R1 - 1924 6521 SFN5812H-R1 + 1924 6200 SFN5122F-R0 SFP+ Server Adapter + 1924 6201 SFN5122F-R1 SFP+ Server Adapter + 1924 6202 SFN5122F-R2 SFP+ Server Adapter + 1924 6204 SFN5122F-R4 SFP+ Server Adapter + 1924 6205 SFN5122F-R5 SFP+ Server Adapter + 1924 6206 SFN5122F-R6 SFP+ Server Adapter + 1924 6207 SFN5122F-R7 SFP+ Server Adapter + 1924 6210 SFN5322F-R0 SFP+ Precision Time Synchronization Server Adapter + 1924 6211 SFN5322F-R1 SFP+ Precision Time Synchronization Server Adapter + 1924 6217 SFN5322F-R7 SFP+ Precision Time Synchronization Server Adapter + 1924 6227 SFN6122F-R7 SFP+ Server Adapter + 1924 6237 SFN6322F-R7 SFP+ Precision Time Synchronization Server Adapter + 1924 6501 SFN5802K-R1 Mezzanine Adapter + 1924 6511 SFN5814H-R1 Mezzanine Adapter + 1924 6521 SFN5812H-R1 Mezzanine Adapter 1924 6562 SFN6832F-R2 SFP+ Mezzanine Adapter - 1924 6a05 SFN5112F-R5 - 1924 6a06 SFN5112F-R6 - 1924 7206 SFN5162F-R6 - 1924 7207 SFN5162F-R7 - 1924 7a06 SFN5152F-R6 - 1924 7a07 SFN5152F-R7 + 1924 6a05 SFN5112F-R5 SFP+ Server Adapter + 1924 6a06 SFN5112F-R6 SFP+ Server Adapter + 1924 7206 SFN5162F-R6 SFP+ Server Adapter + 1924 7207 SFN5162F-R7 SFP+ Server Adapter + 1924 7a06 SFN5152F-R6 SFP+ Server Adapter + 1924 7a07 SFN5152F-R7 SFP+ Server Adapter 0813 SFL9021 [Solarstorm] - 1924 6100 SFN5121T-R0 - 1924 6102 SFN5121T-R2 - 1924 6103 SFN5121T-R3 - 1924 6104 SFN5121T-R4 - 1924 6902 SFN5111T-R2 - 1924 6904 SFN5111T-R4 - 1924 7104 SFN5161T-R4 - 1924 7904 SFN5151T-R4 + 1924 6100 SFN5121T-R0 10GBASE-T Server Adapter + 1924 6102 SFN5121T-R2 10GBASE-T Server Adapter + 1924 6103 SFN5121T-R3 10GBASE-T Server Adapter + 1924 6104 SFN5121T-R4 10GBASE-T Server Adapter + 1924 6902 SFN5111T-R2 10GBASE-T Server Adapter + 1924 6904 SFN5111T-R4 10GBASE-T Server Adapter + 1924 7104 SFN5161T-R4 10GBASE-T Server Adapter + 1924 7904 SFN5151T-R4 10GBASE-T Server Adapter + 0903 SFC9120 + 1014 04cc SFN7122F-R2 2x10GbE SFP+ Flareon Ultra + 1924 8002 SFN7122F-R1 SFP+ Server Adapter + 1924 8003 SFN7x41Q-R1 Flareon Ultra 7000 Series 10/40G Adapter + 1924 8006 SFN7022F-R1 SFP+ Server Adapter + 1924 8007 SFN7322F-R2 Precision Time SFP+ Server Adapter + 1924 8009 SFN7x22F-R2 Flareon Ultra 7000 Series 10G Adapter + 1924 800a SFN7x02F-R2 Flareon 7000 Series 10G Adapter + 1924 800b SFN7x22F-R3 Flareon Ultra 7000 Series 10G Adapter + 1924 800c SFN7x22F-R3 Flareon Ultra 7000 Series 10G Adapter + 1924 800d SFN7x02F-R3 Flareon 7000 Series 10G Adapter + 0923 SFC9140 + 1924 800b SFN7x42Q-R1 Flareon Ultra 7000 Series 10/40G Adapter + 1924 800e SFN7x42Q-R2 Flareon Ultra 7000 Series 10/40G Adapter + 1924 800f SFN7xx4F-R1 Flareon Ultra 7000 Series 10G Adapter 1803 SFC9020 Virtual Function [Solarstorm] 1813 SFL9021 Virtual Function [Solarstorm] + 1903 SFC9120 Virtual Function + 1923 SFC9140 Virtual Function 6703 SFC4000 rev A iSCSI/Onload [Solarstorm] 10b8 0102 SMC10GPCIe-10BT (A2) [TigerCard] 10b8 0103 SMC10GPCIe-10BT (A3) [TigerCard] @@ -14920,6 +18726,8 @@ 0364 AHA364-PCIe 0367 AHA367-PCIe 0370 AHA370-PCIe + 3641 AHA3641 + 3642 AHA3642 1942 ClearSpeed Technology plc e511 Advance X620 accelerator card e521 Advance e620 accelerator card @@ -14971,10 +18779,14 @@ 0082 MPC8347E TBGA 0083 MPC8347 TBGA 0084 MPC8347E PBGA + 110a 4074 SIMATIC NET CP 1628 0085 MPC8347 PBGA + 110a 4046 SIMATIC NET CP 1623 0086 MPC8343E 0087 MPC8343 00b4 MPC8315E + 00b6 MPC8314E + 1a56 1101 Killer Xeno Pro Gigabit Ethernet Controller 00c2 MPC8379E 00c3 MPC8379 00c4 MPC8378E @@ -14999,10 +18811,22 @@ 0401 P4080 0408 P4040E 0409 P4040 + 0440 T4240 with security + 0441 T4240 without security + 0446 T4160 with security + 0447 T4160 without security + 0830 T2080 with security + 0831 T2080 without security + 0838 T2081 with security + 0839 T2081 without security 580c MPC5121e 7010 MPC8641 PCI Host Bridge 7011 MPC8641D PCI Host Bridge 7018 MPC8610 + c006 MPC8308 + 1a56 1201 Killer E2100 Gigabit Ethernet Controller +# PCIe interface for emulator + fc02 RedStone 1958 Faster Technology, LLC. 1959 PA Semi, Inc a000 PA6T Core @@ -15022,8 +18846,8 @@ 1966 Orad Hi-Tec Systems 1975 DVG64 family 1977 DVG128 family -# nee Attansic Technology Corp. -1969 Atheros Communications Inc. +# nee Atheros Communications, Inc. nee Attansic Technology Corp. +1969 Qualcomm Atheros 1026 AR8121/AR8113/AR8114 Gigabit or Fast Ethernet 1043 8304 P5KPL-CM Motherboard 1048 Attansic L1 Gigabit Ethernet @@ -15031,6 +18855,7 @@ 1062 AR8132 Fast Ethernet 1063 AR8131 Gigabit Ethernet 1458 e000 GA-G31M-ES2L Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 1066 Attansic L2c Gigabit Ethernet 1067 Attansic L1c Gigabit Ethernet 1073 AR8151 v1.0 Gigabit Ethernet @@ -15038,9 +18863,13 @@ 1090 AR8162 Fast Ethernet 1091 AR8161 Gigabit Ethernet 1043 1477 N56VZ + 10a0 QCA8172 Fast Ethernet + 10a1 QCA8171 Gigabit Ethernet 2048 Attansic L2 Fast Ethernet 2060 AR8152 v1.1 Fast Ethernet 2062 AR8152 v2.0 Fast Ethernet +# E2200, E2201, E2205 + e091 Killer E220x Gigabit Ethernet Controller 196a Sensory Networks Inc. 0101 NodalCore C-1000 Content Classification Accelerator 0102 NodalCore C-2000 Content Classification Accelerator @@ -15063,7 +18892,7 @@ 1043 8460 P8P67 Deluxe Motherboard 2363 JMB363 SATA/IDE Controller 1043 81e4 P5B [JMB363] - 1458 b000 GA-EP45-DS5 Motherboard + 1458 b000 Motherboard 1849 2363 Motherboard (one of many) 2364 JMB364 AHCI Controller 2365 JMB365 AHCI/IDE @@ -15121,15 +18950,19 @@ 103c 3340 NC552SFP 2-port 10Gb Server Adapter 103c 3341 NC552m 10Gb 2-port FlexFabric Converged Network Adapter 103c 3345 NC553m 10Gb 2-port FlexFabric Converged Network Adapter + 103c 337b NC554FLB 10Gb 2-port FlexFabric Converged Network Adapter 0712 OneConnect 10Gb iSCSI Initiator (be3) 0714 OneConnect 10Gb FCoE Initiator (be3) 103c 3315 NC553i 10Gb 2-port FlexFabric Converged Network Adapter + 103c 337b NC554FLB 10Gb 2-port FlexFabric Converged Network Adapter 19a8 DAQDATA GmbH 19ac Kasten Chase Applied Research 0001 ACA2400 Crypto Accelerator 19ae Progeny Systems Corporation 0520 4135 HFT Interface Controller 0521 Decimator +19ba ZyXEL Communications Corp. + 2330 ZyWALL Turbo Card 19c1 Exegy Inc. # nee NextNet Wireless 19d1 Motorola Expedience @@ -15161,6 +18994,7 @@ 1a08 Sierra semiconductor 0000 SC15064 1a0e DekTec Digital Video B.V. + 083f DTA-2111 VHF/UHF Modulator 1a17 Force10 Networks, Inc. 8002 PB-10GE-2P 10GbE Security Card 1a1d GFaI e.V. @@ -15168,6 +19002,8 @@ 1a1e 3Leaf Systems, Inc. 1a22 Ambric Inc. 1a29 Fortinet, Inc. + 4338 CP8 Content Processor ASIC + 4e36 NP6 Network Processor 1a2b Ascom AG 0000 GESP v1.2 0001 GESP v1.3 @@ -15175,19 +19011,44 @@ 0005 ETP v1.4 000a ETP-104 v1.1 000e DSLP-104 v1.1 +# nee Metalink Ltd. +1a30 Lantiq + 0680 MtW8171 [Hyperion II] + 0700 Wave300 PSB8224 [Hyperion III] + 0710 Wave300 PSB8231 [Hyperion III] 1a32 Quanta Microsystems, Inc 1a3b AzureWave 1112 AR9285 Wireless Network Adapter (PCI-Express) 1a41 Tilera Corp. 0001 TILE64 processor 0002 TILEPro processor - 0200 TILE-Gx36 processor + 0200 TILE-Gx processor + 0201 TILE-Gx Processor Virtual Function + 2000 TILE-Gx PCI Express Root Port 1a4a SLAC National Accelerator Lab PPA-REG 1000 MCOR Power Supply Controller 1010 AMC EVR - Stockholm Timing Board 2000 PGPCard - 4 Lane + 2001 PGPCard - 8 Lane Plus EVR 2010 PCI-Express EVR 1a51 Hectronic AB +1a55 Rohde & Schwarz DVS GmbH + 0010 SDStationOEM + 0011 SDStationOEM II + 0020 Centaurus + 0021 Centaurus II + 0022 Centaurus II LT + 0030 CLIPSTER-VPU 1.x (Hugo) + 0040 Hydra Cinema (JPEG) + 0050 CLIPSTER-VPU 2.x (DigiLab) + 0060 CLIPSTER-DCI 2.x (HydraX) + 0061 Atomix + 0062 Atomix LT + 0063 Atomix HDMI + 0064 Atomix STAN + 0065 Atomix HDMI STAN + 0070 RED Rocket + 0090 CinePlay 1a56 Bigfoot Networks, Inc. 1a57 Highly Reliable Systems 1a58 Razer USA Ltd. @@ -15201,12 +19062,15 @@ 1a76 Wavesat 1a77 Lightfleet Corporation 1a78 Virident Systems Inc. - 0031 Virident FlashMAX Drive + 0031 FlashMAX Drive 1a78 0034 FlashMAX PCIe SSD [rev 3] 1a78 0037 FlashMAX PCIe SSD [rev 3D] 1a78 0038 FlashMAX PCIe SSD [rev 4] 1a78 0039 FlashMAX PCIe SSD [rev 4D] 0040 FlashMAX II + 0041 FlashMAX II + 0042 FlashMAX II + 0050 FlashMAX III 1a84 Commex Technologies 0001 Vulcan SP HT6210 10-Gigabit Ethernet (rev 02) 1a88 MEN Mikro Elektronik @@ -15227,7 +19091,8 @@ 4005 Accelerated Virtual Video Adapter 4006 Memory Ballooning Controller 1ab9 Espia Srl -1acc Point of View B.V +1ac8 Aeroflex Gaisler +1acc Point of View BV 1ad7 Spectracom Corporation 8000 TSync-PCIe Time Code Processor 9100 TPRO-PCI-66U Timecode Reader/Generator @@ -15241,8 +19106,18 @@ 0a41 microEnable IV-FULL x1 0a44 microEnable IV-FULL x4 0e44 microEnable IV-GigE x4 +1ae9 Wilocity Ltd. + 0101 Wil6200 PCI Express Root Port + 0200 Wil6200 PCI Express Port + 0201 Wil6200 Wireless PCI Express Port + 0301 Wil6200 802.11ad Wireless Network Adapter + 0302 Wil6200 802.11ad Wireless Network Adapter + 0310 Wil6200 802.11ad Wireless Network Adapter +1aea Alcor Micro + 6601 AU6601 PCI-E Flash card reader controller 1aec Wolfson Microelectronics -1aed Fusion-io +# nee Fusion-io +1aed SanDisk 1003 ioDimm3 (v1.2) 1005 ioDimm3 1014 03c3 High IOPS SSD PCIe Adapter @@ -15256,6 +19131,9 @@ 1007 ioXtreme Pro 1008 ioXtreme-2 2001 ioDrive2 + 3001 ioMemory FHHL + 3002 ioMemory HHHL + 3003 ioMemory Mezzanine 1aee Caustic Graphics Inc. # nee Qumranet, Inc. 1af4 Red Hat, Inc @@ -15263,22 +19141,65 @@ 1001 Virtio block device 1002 Virtio memory balloon 1003 Virtio console + 1004 Virtio SCSI + 1005 Virtio RNG + 1009 Virtio filesystem + 1010 Virtio GPU + 1012 Virtio input device + 1110 Inter-VM shared memory + 1af4 1100 QEMU Virtual Machine 1af5 Netezza Corp. 1afa J & W Electronics Co., Ltd. 1b03 Magnum Semiconductor, Inc, 6100 DXT/DXTPro Multiformat Broadcast HD/SD Encoder/Decoder/Transcoder + 7000 D7 Multiformat Broadcast HD/SD Encoder/Decoder/Transcoder 1b08 MSC Vertriebs GmbH +1b0a Pegatron 1b13 Jaton Corp 1b1a K&F Computing Research Co. 0e70 GRAPE 1b21 ASMedia Technology Inc. 0611 ASM1061 SATA IDE Controller 0612 ASM1062 Serial ATA Controller + 1849 0612 Motherboard 1042 ASM1042 SuperSpeed USB Host Controller + 1043 8488 P8B WS Motherboard + 1849 1042 Motherboard 1080 ASM1083/1085 PCIe to PCI Bridge + 1849 1080 Motherboard + 1142 ASM1042A USB 3.0 Host Controller + 1242 ASM1142 USB 3.1 Host Controller +1b2c Opal-RT Technologies Inc. 1b36 Red Hat, Inc. + 0001 QEMU PCI-PCI bridge + 0002 QEMU PCI 16550A Adapter + 1af4 1100 QEMU Virtual Machine + 0003 QEMU PCI Dual-port 16550A Adapter + 1af4 1100 QEMU Virtual Machine + 0004 QEMU PCI Quad-port 16550A Adapter + 1af4 1100 QEMU Virtual Machine + 0005 QEMU PCI Test Device + 1af4 1100 QEMU Virtual Machine + 0100 QXL paravirtual graphic card + 1af4 1100 QEMU Virtual Machine 1b37 Signal Processing Devices Sweden AB + 0001 ADQ214 + 0003 ADQ114 + 0005 ADQ112 + 000e ADQ108 + 000f ADQDSP 0014 ADQ412 + 0015 ADQ212 + 001b SDR14 + 001c ADQ1600 + 001e ADQ208 + 001f DSU + 0020 ADQ14 + 2014 TX320 + 2019 S6000 +# now owned by HGST (a Western Digital subsidiary) +1b39 sTec, Inc. + 0001 S1120 PCIe Accelerator SSD 1b3a Westar Display Technologies 7589 HRED J2000 - JPEG 2000 Video Codec Device 1b3e Teradata Corp. @@ -15294,23 +19215,33 @@ 0640 88SE9128 SATA III 6Gb/s RAID Controller 9120 88SE9120 SATA 6Gb/s Controller 9123 88SE9123 PCIe SATA 6.0 Gb/s controller + dc93 600e DC-6xxe series SATA 6G controller 9125 88SE9125 PCIe SATA 6.0 Gb/s controller 9128 88SE9128 PCIe SATA 6 Gb/s RAID controller 9130 88SE9128 PCIe SATA 6 Gb/s RAID controller with HyperDuo 1043 8438 P8P67 Deluxe Motherboard 9172 88SE9172 SATA 6Gb/s Controller + 9178 88SE9170 PCIe SATA 6Gb/s Controller 917a 88SE9172 SATA III 6Gb/s RAID Controller + 9183 88SS9183 PCIe SSD Controller 9192 88SE9172 SATA III 6Gb/s RAID Controller - 91a0 88SE91A0 SATA 6Gb/s Controller - 91a4 88SE9128 IDE Controller + 91a0 88SE912x SATA 6Gb/s Controller [IDE mode] + 91a4 88SE912x IDE Controller + 9220 88SE9220 PCIe 2.0 x2 2-port SATA 6 Gb/s RAID Controller 9230 88SE9230 PCIe SATA 6Gb/s Controller + 9235 88SE9235 PCIe 2.0 x2 4-port SATA 6 Gb/s Controller + 9445 88SE9445 PCIe 2.0 x4 4-Port SAS/SATA 6 Gbps RAID Controller 9480 88SE9480 SAS/SATA 6Gb/s RAID controller + 9485 88SE9485 SAS/SATA 6Gb/s controller 1b55 NetUP Inc. + 18f6 Dual DVB Universal CI card 2a2c Dual DVB-S2-CI card e2e4 Dual DVB-T/C-CI RF card # 2xHDMI and 2xHD-SDI inputs e5f4 MPEG2 and H264 Encoder-Transcoder f1c4 Dual ASI-RX/TX-CI card +1b66 Deltacast + 0007 Delta-3G-elp-11 SDI I/O Board 1b6f Etron Technology, Inc. 7023 EJ168 USB 3.0 Host Controller 7052 EJ188/EJ198 USB 3.0 Host Controller @@ -15318,6 +19249,7 @@ 1000 FL1000G USB 3.0 Host Controller 1d5c 1000 Anker USB 3.0 Express Card 1009 FL1009 USB 3.0 Host Controller + 1100 FL1100 USB 3.0 Host Controller 1b74 OpenVox Communication Co. Ltd. 0115 D115P/D115E Single-port E1/T1 card d130 D130P/D130E Single-port E1/T1 card (3rd GEN) @@ -15327,11 +19259,24 @@ d430 D410/430 Quad-port E1/T1 card 1b85 OCZ Technology Group, Inc. 1041 RevoDrive 3 X2 PCI-Express SSD 240 GB (Marvell Controller) + 8788 RevoDrive Hybrid 1b96 Western Digital 1b9a XAVi Technologies Corp. 1bad ReFLEX CES 1bb0 SimpliVity Corporation 0002 OmniCube Accelerator OA-3000 + 0010 OmniCube Accelerator OA-3000-2 +1bb1 Seagate Technology PLC + 005d Nytro PCIe Flash Storage + 1bb1 6501 Nytro XP6500-8A1536 1.5TB +# 2TB Nytro PCIe controller + 1bb1 6502 Nytro XP6500-8A2048 +# 4TB Nytro PCIe controller + 1bb1 6503 Nytro XP6500-8A4096 +# 2GB DRAM variant of Nytro card + 1bb1 6511 Nytro XH6550-2GB DRAM +# 8GB variant of Nytro PCIe controller + 1bb1 6512 Nytro XH6550-8GB DRAM 1bb3 Bluecherry 4304 BC-04120A MPEG4 4 port video encoder / decoder 4309 BC-08240A MPEG4 4 port video encoder / decoder @@ -15346,24 +19291,88 @@ 1bbf Maxeler Technologies Ltd. 0003 MAX3 0004 MAX4 +1bd0 Astronics Corporation + 1001 Mx5 PMC/XMC Databus Interface Card + 1002 PM1553-5 (PC/104+ MIL-STD-1553 Interface Card) + 1004 AB3000 Series Rugged Computer + 1005 PE1000 (Multi-Protocol PCIe/104 Interface Card) + 1101 OmniBus II PCIe Multi-Protocol Interface Card + 1102 OmniBusBox II Multi-Protocol Interface Core + 1103 OmniBus II cPCIe/PXIe Multi-Protocol Interface Card +1bee IXXAT Automation GmbH + 0003 CAN-IB200/PCIe 1bf4 VTI Instruments Corporation + 0001 SentinelEX +1bfd EeeTOP +1c09 CSP, Inc. + 4254 10G-PCIE3-8D-2S + 4255 10G-PCIE3-8D-Q + 4256 10G-PCIE3-8D-2S 1c1c Symphony 0001 82C101 +1c28 Lite-On IT Corp. / Plextor + 0122 M6e PCI Express SSD [Marvell 88SS9183] 1c2c Fiberblaze + 000a Capture + 000f SmartNIC + 00a0 FBC4G Capture 4x1Gb + 00a1 FBC4XG Capture 4x10Gb + 00a2 FBC8XG Capture 8x10Gb + 00a3 FBC2XG Capture 2x10Gb + 00a4 FBC4XGG3 Capture 4x10Gb + 00a5 FBC2XLG Capture 2x40Gb + 00a6 FBC1CG Capture 1x100Gb # Used on V120 VME Crate Controller 1c32 Highland Technology, Inc. +1c33 Daktronics, Inc 1c3b Accensus, LLC 0200 Telas2 +# http://www.accensusllc.com/accensustelas2.html + 0300 Telas 2.V 1c44 Enmotus Inc 8000 8000 Storage IO Controller +# A Western Digital Subsidiary +1c58 HGST, Inc. + 0003 Ultrastar SN100 Series NVMe SSD +1c7e TTTech Computertechnik AG + 0200 zFAS Debug Port 1c7f Elektrobit Austria GmbH 5100 EB5100 1c8a TSF5 Corporation + 0001 Hunter PCI Express +1cb1 Collion UG & Co.KG +1cc5 Embedded Intelligence, Inc. + 0100 CAN-PCIe-02 +1cd2 SesKion GmbH + 0301 Simulyzer-RT CompactPCI Serial DIO-1 card +1ce4 Exablaze + 0001 ExaNIC X4 + 0002 ExaNIC X2 +1cf7 Subspace Dynamics +1d00 Pure Storage +# CEM Solutions Pvt. Ltd. +1d21 Allo +1d26 Kalray Inc. + 0040 Turbocard2 Accelerator + e004 AB01/EMB01 Development Board +1d40 Techman Electronics (Changshu) Co., Ltd. 1d44 DPT a400 PM2x24/PM3224 1d5c Fantasia Trading LLC +1d61 Technobox, Inc. +1d65 Imagine Communications Corp. + 04de Taurus/McKinley +1d6c Atomic Rules LLC + 1001 A5PL-E1 + 1002 A5PL-E7 + 1003 S5PEDS-AB + 1004 KC705-K325 + 1005 ZC706-Z045 + 1006 KCU105-KU040 + 1007 XUSP3S-VU095 [Jasper] + 4200 A5PL-E1-10GETI [10 GbE Ethernet Traffic Instrument] 1de1 Tekram Technology Co.,Ltd. - 0391 TRM-S1040 + 0391 TRM-S1040 [DC-315 / DC-395 series] 2020 DC-390 690c 690c dc29 DC290 @@ -15399,6 +19408,19 @@ 0000 3011 10-Giga TOE Dual Port SFP+/CX4 Low Profile SmartNIC 0000 3012 10-Giga TOE Dual Port CX4/SFP+ Low Profile SmartNIC 0000 3014 10-Giga TOE Dual Port CX4 Low Profile SmartNIC + 4010 TN4010 Clean SROM + 4020 TN9030 10GbE CX4 Ethernet Adapter + 4022 TN9310 10GbE SFP+ Ethernet Adapter + 1186 4d00 DXE-810S 10GbE SFP+ Ethernet Adapter + 1fc9 3015 Ethernet Adapter + 4024 TN9210 10GBase-T Ethernet Adapter + 4025 TN9510 10GBase-T/NBASE-T Ethernet Adapter + 1186 2900 DXE-810T 10GBase-T Ethernet Adapter + 1fc9 3015 Ethernet Adapter + 4026 TN9610 10GbE SFP+ Ethernet Adapter +1fcc StreamLabs + f416 MS416 + fb01 MH4LM 1fce Cognio Inc. 0001 Spectrum Analyzer PC Card (SAgE) 1fd4 SUNIX Co., Ltd. @@ -15413,8 +19435,6 @@ 20f4 TRENDnet 2116 ZyDAS Technology Corp. 21c3 21st Century Computer Corp. -# (Probably only the Mobile Phone Division) -22b8 Motorola, Inc. 2304 Colorgraphic Communications Corp. 2348 Racore 2010 8142 100VG/AnyLAN @@ -15422,12 +19442,13 @@ 270b Xantel Corporation 270f Chaintech Computer Co. Ltd 2711 AVID Technology Inc. -29b4 82q35 Express MEI Controller +2955 Connectix Virtual PC + 6e61 OHCI USB 1.1 controller 2a15 3D Vision(???) 3000 Hansol Electronics Inc. -3020 LSI SAS2 9211-8i -3080 LSI SAS2 9200-8e 3142 Post Impression Systems. +31ab Zonet + 1faa ZEW1602 802.11b/g Wireless Adapter 3388 Hint Corp 0013 HiNT HC4 PCI to ISDN bridge, Multimedia audio controller 0014 HiNT HC4 PCI to ISDN bridge, Network controller @@ -15463,6 +19484,10 @@ 3513 ARCOM Control Systems Ltd 37d9 ITD Firm ltd. 1138 SCHD-PH-8 Phase detector +# 12-ch Relay Actuator Card + 1140 VR-12-PCI +# multiport serial board + 1141 PCI-485(422) 3842 eVga.com. Corp. 38ef 4Links 3d3d 3DLabs @@ -15562,7 +19587,16 @@ 416c Aladdin Knowledge Systems 0100 AladdinCARD 0200 CPC +4254 DVBSky 4321 Tata Power Strategic Electronics Division +4348 WCH.CN + 2273 CH351 PCI Dual Serial Port Controller + 3253 CH352 PCI Dual Serial Port Controller + 3453 CH353 PCI Quad Serial Port Controller + 5053 CH352 PCI Serial and Parallel Port Controller + 7053 CH353 PCI Dual Serial and Parallel Ports Controller + 7073 CH356 PCI Quad Serial and Parallel Ports Controller + 7173 CH355 PCI Quad Serial Port Controller 434e CAST Navigation LLC 4444 Internext Compression Inc 0016 iTVC16 (CX23416) Video Decoder @@ -15740,7 +19774,6 @@ 5053 Voyetra Technologies 2010 Daytona Audio Adapter 50b2 TerraTec Electronic GmbH - 1111 Terratec XLerate 5136 S S Technologies 5143 Qualcomm Inc 5145 Ensoniq (Old) @@ -15750,7 +19783,7 @@ 0301 FlyDVB-T 5301 Alliance Semiconductor Corp. 0001 ProMotion aT3D -5333 S3 Inc. +5333 S3 Graphics Ltd. 0551 Plato/PX (system) 5631 86c325 [ViRGE] 8800 86c866 [Vision 866] @@ -15856,12 +19889,12 @@ 1179 0001 ViRGE/MX 8c02 ViRGE/MX+ 8c03 ViRGE/MX+MV - 8c10 86C270-294 Savage/MX-MV - 8c11 82C270-294 Savage/MX - 8c12 86C270-294 Savage/IX-MV + 8c10 86C270-294 [SavageMX-MV] + 8c11 82C270-294 [SavageMX] + 8c12 86C270-294 [SavageIX-MV] 1014 017f ThinkPad T20/T22 1179 0001 86C584 SuperSavage/IXC Toshiba - 8c13 86C270-294 Savage/IX + 8c13 86C270-294 [SavageIX] 1179 0001 Magnia Z310 8c22 SuperSavage MX/128 8c24 SuperSavage MX/64 @@ -15877,10 +19910,15 @@ 8d02 VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK) 8d03 VT8751 [ProSavageDDR P4M266] 8d04 VT8375 [ProSavage8 KM266/KL266] + 8e00 DeltaChrome + 8e26 ProSavage 8e40 2300E Graphics Processor - 8e48 Chrome S27 PCIE + 8e48 Matrix [Chrome S25 / S27] 5333 0130 Chrome S27 256M DDR2 - 9102 86C410 Savage 2000 + 9043 Chrome 430 GT + 9045 Chrome 430 ULP / 435 ULP / 440 GTX + 9060 Chrome 530 GT + 9102 86C410 [Savage 2000] 1092 5932 Viper II Z200 1092 5934 Viper II Z200 1092 5952 Viper II Z200 @@ -15908,8 +19946,12 @@ 5700 Netpower 584d AuzenTech Co., Ltd. 5851 Exacq Technologies + 8008 tDVR8008 8-port video capture card + 8016 tDVR8016 16-chan video capture card + 8032 tDVR8032 32-chan video capture card 5853 XenSource, Inc. 0001 Xen Platform Device + c000 Citrix XenServer PCI Device for Windows Update # Virtual device surfaced in guests to provide HID events. c110 Virtualized HID # Device surfaced in guests to provide 2d graphics capabilities @@ -15937,6 +19979,11 @@ 1022 4 photo couple 4 relay Card 1025 16 photo couple 16 relay Card 4000 WatchDog Card +6688 Zycoo Co., Ltd + 1200 CooVox TDM Analog Module + 1400 CooVOX TDM GSM Module + 1600 CooVOX TDM E1/T1 Module + 1800 CooVOX TDM BRI Module # nee Qumranet 6900 Red Hat, Inc. 7063 pcHDTV @@ -15944,6 +19991,9 @@ 3000 HD-3000 5500 HD5500 HDTV 7284 HT OMEGA Inc. +7401 EndRun Technologies + e100 PTP3100 PCIe PTP Slave Clock +7470 TP-LINK Technologies Co., Ltd. 7604 O.N. Electronic Co Ltd. 7bde MIDAC Corporation 7fed PowerTV @@ -15963,9 +20013,15 @@ 0043 Core Processor Secondary PCI Express Root Port 0044 Core Processor DRAM Controller 1025 0347 Aspire 7740G + 1025 0487 TravelMate 5742 + 144d c06a R730 Laptop + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 0045 Core Processor PCI Express x16 Root Port + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 0046 Core Processor Integrated Graphics Controller + 144d c06a R730 Laptop + 17c0 10d9 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 0047 Core Processor Secondary PCI Express Root Port 0048 Core Processor DRAM Controller @@ -16027,12 +20083,15 @@ 8086 5226 Centrino Advanced-N 6230 ABG 0100 2nd Generation Core Processor Family DRAM Controller 1028 04aa XPS 8300 - 1043 844d P8P67 Deluxe Motherboard + 1043 844d P8P67/P8H67 Series Motherboard 0101 Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port 1028 04b2 Vostro 3350 106b 00dc MacBookPro8,2 [Core i7, 15", 2011] 0102 2nd Generation Core Processor Family Integrated Graphics Controller + 1028 04aa XPS 8300 + 1043 0102 P8H67 Series Motherboard 0104 2nd Generation Core Processor Family DRAM Controller + 1028 04a3 Precision M4600 1028 04b2 Vostro 3350 1028 04da Vostro 3750 106b 00dc MacBookPro8,2 [Core i7, 15", 2011] @@ -16053,30 +20112,52 @@ 0126 2nd Generation Core Processor Family Integrated Graphics Controller 1028 04cc Vostro 3350 0150 Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller + 1043 84ca P8 series motherboard + 15d9 0624 X9SCM-F Motherboard + 1849 0150 Motherboard 0151 Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port 1043 1477 N56VZ + 1043 844d P8 series motherboard + 1043 84ca P8H77-I Motherboard + 8086 2010 Server Board S1200BTS 0152 Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller + 1043 84ca P8H77-I Motherboard + 0153 3rd Gen Core Processor Thermal Subsystem + 1043 1517 Zenbook Prime UX31A 0154 3rd Gen Core processor DRAM Controller + 1025 0813 Aspire R7-571 + 103c 17f6 ProBook 4540s 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A 0155 Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port + 8086 2010 Server Board S1200BTS 0156 3rd Gen Core processor Graphics Controller 0158 Xeon E3-1200 v2/Ivy Bridge DRAM Controller + 1043 844d P8 series motherboard + 8086 2010 Server Board S1200BTS 0159 Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port 015a Xeon E3-1200 v2/Ivy Bridge Graphics Controller 015c Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 015d Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port + 1043 844d P8 series motherboard 015e Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller 0162 Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller + 1043 84ca P8 series motherboard + 1849 0162 Motherboard 0166 3rd Gen Core processor Graphics Controller + 1043 1517 Zenbook Prime UX31A 1043 2103 N56VZ 016a Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller + 1043 844d P8B WS Motherboard 0172 Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller 0176 3rd Gen Core processor Graphics Controller 0309 80303 I/O Processor PCI-to-PCI Bridge 030d 80312 I/O Companion Chip PCI-to-PCI Bridge 0326 6700/6702PXH I/OxAPIC Interrupt Controller A + 103c 3208 ProLiant DL140 G2 1775 1100 CR11/VR11 Single Board Computer 0327 6700PXH I/OxAPIC Interrupt Controller B + 103c 3208 ProLiant DL140 G2 1775 1100 CR11/VR11 Single Board Computer 0329 6700PXH PCI Express-to-PCI Bridge A 032a 6700PXH PCI Express-to-PCI Bridge B @@ -16090,22 +20171,28 @@ 0336 80331 [Lindsay] I/O processor (ATU) 0340 41210 [Lanai] Serial to Parallel PCI Bridge (A-Segment Bridge) 0341 41210 [Lanai] Serial to Parallel PCI Bridge (B-Segment Bridge) - 0370 80333 Segment-A PCI Express-to-PCI Express Bridge + 0370 80333 Segment-A PCIe Express to PCI-X bridge 0371 80333 A-Bus IOAPIC - 0372 80333 Segment-B PCI Express-to-PCI Express Bridge + 0372 80333 Segment-B PCIe Express to PCI-X bridge 0373 80333 B-Bus IOAPIC 0374 80333 Address Translation Unit - 0402 Haswell Integrated Graphics Controller - 0406 Haswell Integrated Graphics Controller - 040a Haswell Integrated Graphics Controller - 0412 Haswell Integrated Graphics Controller - 0416 Haswell Integrated Graphics Controller - 041a Haswell Integrated Graphics Controller + 0402 Xeon E3-1200 v3/4th Gen Core Processor Integrated Graphics Controller + 0406 4th Gen Core Processor Integrated Graphics Controller + 040a Xeon E3-1200 v3 Processor Integrated Graphics Controller + 0412 Xeon E3-1200 v3/4th Gen Core Processor Integrated Graphics Controller + 0416 4th Gen Core Processor Integrated Graphics Controller + 17aa 220e ThinkPad T440p + 041a Xeon E3-1200 v3 Processor Integrated Graphics Controller + 041e 4th Generation Core Processor Family Integrated Graphics Controller + 0434 DH89XXCC Series QAT + 0435 DH895XCC Series QAT 0436 DH8900CC Null Device 0438 DH8900CC Series Gigabit Network Connection 043a DH8900CC Series Gigabit Fiber Network Connection 043c DH8900CC Series Gigabit Backplane Network Connection 0440 DH8900CC Series Gigabit SFP Network Connection + 0442 DH89XXCC Series QAT Virtual Function + 0443 DH895XCC Series QAT Virtual Function 0482 82375EB/SB PCI to EISA Bridge 0483 82424TX/ZX [Saturn] CPU to PCI bridge 0484 82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge @@ -16221,17 +20308,306 @@ 08af Centrino Wireless-N 100 8086 1015 Centrino Wireless-N 100 BGN 8086 1017 Centrino Wireless-N 100 BG + 08b1 Wireless 7260 +# Wilkins Peak 2 + 8086 4020 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 402a Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4060 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4062 Wireless-N 7260 +# Wilkins Peak 2 + 8086 406a Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4070 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4072 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4160 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4162 Wireless-N 7260 +# Wilkins Peak 2 + 8086 4170 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4420 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4460 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4462 Wireless-N 7260 +# Wilkins Peak 2 + 8086 446a Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4470 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4472 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4560 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4570 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 486e Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4870 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4a6c Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4a6e Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4a70 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4c60 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4c70 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 5070 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 5072 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 5170 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 5770 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c020 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c02a Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c060 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c062 Wireless-N 7260 +# Wilkins Peak 2 + 8086 c06a Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c070 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c072 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c160 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c162 Wireless-N 7260 +# Wilkins Peak 2 + 8086 c170 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c360 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c420 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c460 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c462 Wireless-N 7260 +# Wilkins Peak 2 + 8086 c470 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c472 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c560 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c570 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c760 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c770 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 cc60 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 cc70 Dual Band Wireless-AC 7260 + 08b2 Wireless 7260 +# Wilkins Peak 2 + 8086 4220 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4260 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4262 Wireless-N 7260 +# Wilkins Peak 2 + 8086 426a Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4270 Wireless-N 7260 +# Wilkins Peak 2 + 8086 4272 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 4360 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 4370 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c220 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c260 Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c262 Wireless-N 7260 +# Wilkins Peak 2 + 8086 c26a Dual Band Wireless-N 7260 +# Wilkins Peak 2 + 8086 c270 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c272 Dual Band Wireless-AC 7260 +# Wilkins Peak 2 + 8086 c370 Dual Band Wireless-AC 7260 + 08b3 Wireless 3160 +# Wilkins Peak 1 + 8086 0060 Dual Band Wireless-N 3160 +# Wilkins Peak 1 + 8086 0062 Wireless-N 3160 +# Wilkins Peak 1 + 8086 0070 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 0072 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 0170 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 0172 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 0260 Dual Band Wireless-N 3160 +# Wilkins Peak 1 + 8086 0470 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 0472 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 1070 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 1170 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 8060 Dual Band Wireless N-3160 +# Wilkins Peak 1 + 8086 8062 Wireless N-3160 +# Wilkins Peak 1 + 8086 8070 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8072 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8170 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8172 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8470 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8570 Dual Band Wireless AC 3160 + 08b4 Wireless 3160 +# Wilkins Peak 1 + 8086 0270 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 0272 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 0370 Dual Band Wireless-AC 3160 +# Wilkins Peak 1 + 8086 8260 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8270 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8272 Dual Band Wireless AC 3160 +# Wilkins Peak 1 + 8086 8370 Dual Band Wireless AC 3160 +# PowerVR SGX 545 + 08cf Atom Processor Z2760 Integrated Graphics Controller + 0953 PCIe Data Center SSD + 8086 3702 DC P3700 SSD + 8086 3703 DC P3700 SSD [2.5" SFF] + 8086 3704 DC P3500 SSD [Add-in Card] + 8086 3705 DC P3500 SSD [2.5" SFF] + 8086 3709 DC P3600 SSD [Add-in Card] + 8086 370a DC P3600 SSD [2.5" SFF] + 095a Wireless 7265 +# Stone Peak 2 AC + 8086 1010 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 5000 Dual Band Wireless-N 7265 +# Stone Peak 2 BGN + 8086 5002 Wireless-N 7265 +# Stone Peak 2 AGN + 8086 500a Dual Band Wireless-N 7265 +# Stone Peak 2 AC + 8086 5010 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 5012 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 5020 Dual Band Wireless-N 7265 +# Stone Peak 2 AGN + 8086 502a Dual Band Wireless-N 7265 +# Maple Peak AC + 8086 5090 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 5100 Dual Band Wireless-AC 7265 +# Stone Peak 2 BGN + 8086 5102 Wireless-N 7265 +# Stone Peak 2 AGN + 8086 510a Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 5110 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 5112 Dual Band Wireless-AC 7265 +# Maple Peak AC + 8086 5190 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 5400 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 5410 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 5412 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 5420 Dual Band Wireless-N 7265 +# Maple Peak AC + 8086 5490 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 5510 Dual Band Wireless-AC 7265 +# Maple Peak AC + 8086 5590 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 9000 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 900a Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9010 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9012 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9110 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9112 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9210 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9310 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 9400 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9410 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 9510 Dual Band Wireless-AC 7265 + 095b Wireless 7265 +# Stone Peak 2 AGN + 8086 5200 Dual Band Wireless-N 7265 +# Stone Peak 2 BGN + 8086 5202 Wireless-N 7265 +# Stone Peak 2 AGN + 8086 520a Dual Band Wireless-N 7265 +# Stone Peak 2 AC + 8086 5210 Dual Band Wireless-AC 7265 +# Stone Peak 2 AC + 8086 5212 Dual Band Wireless-AC 7265 +# Maple Peak AC + 8086 5290 Dual Band Wireless-AC 7265 +# Stone Peak 2 BGN + 8086 5302 Wireless-N 7265 +# Stone Peak 2 AC + 8086 5310 Dual Band Wireless-AC 7265 +# Stone Peak 2 AGN + 8086 9200 Dual Band Wireless-AC 7265 0960 80960RP (i960RP) Microprocessor/Bridge 0962 80960RM (i960RM) Bridge 0964 80960RP (i960RP) Microprocessor/Bridge 0a04 Haswell-ULT DRAM Controller + 17aa 2214 ThinkPad X240 0a06 Haswell-ULT Integrated Graphics Controller + 0a0c Haswell-ULT HD Audio Controller + 17aa 2214 ThinkPad X240 0a16 Haswell-ULT Integrated Graphics Controller + 17aa 2214 ThinkPad X240 0a22 Haswell-ULT Integrated Graphics Controller 0a26 Haswell-ULT Integrated Graphics Controller 0a2a Haswell-ULT Integrated Graphics Controller + 0a2e Haswell-ULT Integrated Graphics Controller 0be0 Atom Processor D2xxx/N2xxx Integrated Graphics Controller 0be1 Atom Processor D2xxx/N2xxx Integrated Graphics Controller + 105b 0d7c D270S/D250S Motherboard 0be2 Atom Processor D2xxx/N2xxx Integrated Graphics Controller 0be3 Atom Processor D2xxx/N2xxx Integrated Graphics Controller 0be4 Atom Processor D2xxx/N2xxx Integrated Graphics Controller @@ -16252,232 +20628,236 @@ 0bf3 Atom Processor D2xxx/N2xxx DRAM Controller 0bf4 Atom Processor D2xxx/N2xxx DRAM Controller 0bf5 Atom Processor D2xxx/N2xxx DRAM Controller + 105b 0d7c D270S/D250S Motherboard 0bf6 Atom Processor D2xxx/N2xxx DRAM Controller 0bf7 Atom Processor D2xxx/N2xxx DRAM Controller - 0c00 Haswell DRAM Controller - 0c01 Haswell PCI Express x16 Controller - 0c04 Haswell DRAM Controller - 0c05 Haswell PCI Express x8 Controller - 0c08 Haswell DRAM Controller - 0c09 Haswell PCI Express x4 Controller - 0c0c Haswell HD Audio Controller - 0c46 Centerton PCI Express Root Port 1 - 0c47 Centerton PCI Express Root Port 2 - 0c48 Centerton PCI Express Root Port 3 - 0c49 Centerton PCI Express Root Port 4 - 0c4e Centerton NTB Primary - 0c54 Centerton Internal Management - 0c59 Centerton SMBus 2.0 Controller 0 - 0c5a Centerton SMBus 2.0 Controller 1 - 0c5f Centerton UART - 0c60 Centerton Integrated Legacy Bus - 0c70 Centerton Internal Fabric - 0c71 Centerton Internal Fabric - 0c72 Centerton Internal Fabric - 0c73 Centerton Internal Fabric - 0c74 Centerton Internal Fabric - 0c75 Centerton Internal Fabric - 0c76 Centerton Internal Fabric - 0c77 Centerton Internal Fabric - 0c78 Centerton Internal Fabric - 0c79 Centerton Internal Fabric - 0c7a Centerton Internal Fabric - 0c7b Centerton Internal Fabric - 0c7c Centerton Internal Fabric - 0c7d Centerton Internal Fabric - 0c7e Centerton Internal Fabric - 0c7f Centerton Internal Fabric - 0e00 Ivytown DMI2 - 0e01 Ivytown PCI Express Root Port in DMI2 Mode - 0e04 Ivytown PCI Express Root Port 2a - 0e05 Ivytown PCI Express Root Port 2b - 0e06 Ivytown PCI Express Root Port 2c - 0e07 Ivytown PCI Express Root Port 2d - 0e08 Ivytown PCI Express Root Port 3a - 0e09 Ivytown PCI Express Root Port 3b - 0e0a Ivytown PCI Express Root Port 3c - 0e0b Ivytown PCI Express Root Port 3d - 0e1c Ivytown Debug and Error Injection Related Registers - 0e1d Ivytown R2PCIe - 0e1e Ivytown Semaphore and Scratchpad Configuration Registers - 0e1f Ivytown Semaphore and Scratchpad Configuration Registers - 0e20 Ivytown Crystal Beach DMA Channel 0 - 0e21 Ivytown Crystal Beach DMA Channel 1 - 0e22 Ivytown Crystal Beach DMA Channel 2 - 0e23 Ivytown Crystal Beach DMA Channel 3 - 0e24 Ivytown Crystal Beach DMA Channel 4 - 0e25 Ivytown Crystal Beach DMA Channel 5 - 0e26 Ivytown Crystal Beach DMA Channel 6 - 0e27 Ivytown Crystal Beach DMA Channel 7 - 0e28 Ivytown VTd/Memory Map/Misc - 0e29 Ivytown Memory Hotplug - 0e2a Ivytown IIO RAS - 0e2c Ivytown IOAPIC - 0e2e Ivytown CBDMA - 0e2f Ivytown CBDMA - 0e30 Ivytown Home Agent 0 - 0e32 Ivytown QPI Link 0 - 0e33 Ivytown QPI Link 1 - 0e34 Ivytown PCI Express Ring Performance Monitoring - 0e36 Ivytown QPI Ring Performance Ring Monitoring - 0e37 Ivytown QPI Ring Performance Ring Monitoring - 0e38 Ivytown Home Agent 1 - 0e3a Ivytown QPI Link 2 - 0e3e Ivytown QPI Ring Performance Ring Monitoring - 0e3f Ivytown QPI Ring Performance Ring Monitoring - 0e40 Ivytown QPI Link 2 - 0e41 Ivytown QPI Ring Registers - 0e43 Ivytown QPI Link Reut 2 - 0e44 Ivytown QPI Link Reut 2 - 0e60 Ivytown Home Agent 1 - 0e68 Ivytown Integrated Memory Controller 1 Target Address/Thermal Registers - 0e6a Ivytown Integrated Memory Controller 1 Channel Target Address Decoder Registers - 0e6b Ivytown Integrated Memory Controller 1 Channel Target Address Decoder Registers - 0e6c Ivytown Integrated Memory Controller 1 Channel Target Address Decoder Registers - 0e6d Ivytown Integrated Memory Controller 1 Channel Target Address Decoder Registers - 0e71 Ivytown Integrated Memory Controller 0 RAS Registers - 0e79 Ivytown Integrated Memory Controller 1 RAS Registers - 0e80 Ivytown QPI Link 0 - 0e81 Ivytown QPI Ring Registers - 0e83 Ivytown QPI Link Reut 0 - 0e84 Ivytown QPI Link Reut 0 - 0e90 Ivytown QPI Link 1 - 0e93 Ivytown QPI Link 1 - 0e94 Ivytown QPI Link Reut 1 - 0ea0 Ivytown Home Agent 0 - 0ea8 Ivytown Integrated Memory Controller 0 Target Address/Thermal Registers - 0eaa Ivytown Integrated Memory Controller 0 Channel Target Address Decoder Registers - 0eab Ivytown Integrated Memory Controller 0 Channel Target Address Decoder Registers - 0eac Ivytown Integrated Memory Controller 0 Channel Target Address Decoder Registers - 0ead Ivytown Integrated Memory Controller 0 Channel Target Address Decoder Registers - 0eb0 Ivytown Integrated Memory Controller 1 Channel 0-3 Thermal Control 0 - 0eb1 Ivytown Integrated Memory Controller 1 Channel 0-3 Thermal Control 1 - 0eb2 Ivytown Integrated Memory Controller 1 Channel 0-3 ERROR Registers 0 - 0eb3 Ivytown Integrated Memory Controller 1 Channel 0-3 ERROR Registers 1 - 0eb4 Ivytown Integrated Memory Controller 1 Channel 0-3 Thermal Control 2 - 0eb5 Ivytown Integrated Memory Controller 1 Channel 0-3 Thermal Control 3 - 0eb7 Ivytown Integrated Memory Controller 1 Channel 0-3 ERROR Registers 2 - 0ec0 Ivytown Power Control Unit 0 - 0ec1 Ivytown Power Control Unit 1 - 0ec2 Ivytown Power Control Unit 2 - 0ec3 Ivytown Power Control Unit 3 - 0ec4 Ivytown Power Control Unit 4 - 0ec8 Ivytown System Address Decoder - 0ec9 Ivytown Broadcast Registers - 0eca Ivytown Broadcast Registers - 0ed8 Ivytown DDRIO - 0ed9 Ivytown DDRIO - 0edc Ivytown DDRIO - 0edd Ivytown DDRIO - 0ede Ivytown DDRIO - 0edf Ivytown DDRIO - 0ee0 Ivytown Unicast Registers - 0ee1 Ivytown Unicast Registers - 0ee2 Ivytown Unicast Registers - 0ee3 Ivytown Unicast Registers - 0ee4 Ivytown Unicast Registers - 0ee5 Ivytown Unicast Registers - 0ee6 Ivytown Unicast Registers - 0ee7 Ivytown Unicast Registers - 0ee8 Ivytown Unicast Registers - 0ee9 Ivytown Unicast Registers - 0eea Ivytown Unicast Registers - 0eeb Ivytown Unicast Registers - 0eec Ivytown Unicast Registers - 0eed Ivytown Unicast Registers - 0eee Ivytown Unicast Registers - 0ef0 Ivytown Integrated Memory Controller 0 Channel 0-3 Thermal Control 0 - 0ef1 Ivytown Integrated Memory Controller 0 Channel 0-3 Thermal Control 1 - 0ef2 Ivytown Integrated Memory Controller 0 Channel 0-3 ERROR Registers 0 - 0ef3 Ivytown Integrated Memory Controller 0 Channel 0-3 ERROR Registers 2 - 0ef4 Ivytown Integrated Memory Controller 0 Channel 0-3 Thermal Control 2 - 0ef5 Ivytown Integrated Memory Controller 0 Channel 0-3 Thermal Control 3 - 0ef7 Ivytown Integrated Memory Controller 0 Channel 0-3 ERROR Registers 3 - 0ef8 Ivytown DDRIO - 0ef9 Ivytown DDRIO - 0efa Ivytown DDRIO - 0efb Ivytown DDRIO - 0efc Ivytown DDRIO - 0efd Ivytown DDRIO - 0f00 ValleyView SSA-CUnit - 0f01 ValleyView SSA-CUnit - 0f02 ValleyView SSA-CUnit - 0f03 ValleyView SSA-CUnit - 0f04 ValleyView High Definition Audio Controller - 0f05 ValleyView High Definition Audio Controller - 0f06 ValleyView LPIO1 DMA Controller - 0f07 ValleyView LPIO1 DMA Controller - 0f08 ValleyView LPIO1 PWM Controller - 0f09 ValleyView LPIO1 PWM Controller - 0f0a ValleyView LPIO1 HSUART Controller #1 - 0f0b ValleyView LPIO1 HSUART Controller #1 - 0f0c ValleyView LPIO1 HSUART Controller #2 - 0f0d ValleyView LPIO1 HSUART Controller #2 - 0f0e ValleyView LPIO1 SPI Controller - 0f0f ValleyView LPIO1 SPI Controller - 0f10 ValleyView LPIO1 Controller - 0f11 ValleyView LPIO1 Controller - 0f12 ValleyView SMBus Controller - 0f13 ValleyView SMBus Controller - 0f14 ValleyView SDIO Controller - 0f15 ValleyView SDIO Controller - 0f16 ValleyView SDIO Controller - 0f17 ValleyView SDIO Controller - 0f18 ValleyView SEC - 0f19 ValleyView SEC - 0f1a ValleyView SEC - 0f1b ValleyView SEC - 0f1c ValleyView Power Control Unit - 0f1d ValleyView Power Control Unit - 0f1e ValleyView Power Control Unit - 0f1f ValleyView Power Control Unit - 0f20 ValleyView 4-Port SATA Storage Controller - 0f21 ValleyView 4-Port SATA Storage Controller - 0f22 ValleyView 6-Port SATA AHCI Controller - 0f23 ValleyView 6-Port SATA AHCI Controller - 0f24 ValleyView SATA RAID Storage Controller - 0f25 ValleyView SATA RAID Storage Controller - 0f26 ValleyView 2-Port SATA Storage Controller - 0f27 ValleyView 2-Port SATA Storage Controller - 0f28 ValleyView LPE Audio Controller - 0f29 ValleyView LPE Audio Controller - 0f2a ValleyView LPE Audio Controller - 0f2b ValleyView LPE Audio Controller - 0f2e ValleyView SATA RAID Storage Controller - 0f2f ValleyView SATA RAID Storage Controller - 0f30 ValleyView Gen7 - 0f31 ValleyView Gen7 - 0f32 ValleyView Gen7 - 0f33 ValleyView Gen7 - 0f34 ValleyView USB Enhanced Host Controller - 0f35 ValleyView USB xHCI Host Controller - 0f36 ValleyView USB xHCI Host Controller - 0f37 ValleyView OTG - 0f38 ValleyView ISP - 0f39 ValleyView ISP - 0f3a ValleyView ISP - 0f3b ValleyView ISP - 0f3c ValleyView ISP - 0f3d ValleyView ISP - 0f3e ValleyView ISP - 0f3f ValleyView ISP - 0f40 ValleyView LPIO2 DMA Controller - 0f41 ValleyView LPIO2 I2C Controller #1 - 0f42 ValleyView LPIO2 I2C Controller #2 - 0f43 ValleyView LPIO2 I2C Controller #3 - 0f44 ValleyView LPIO2 I2C Controller #4 - 0f45 ValleyView LPIO2 I2C Controller #5 - 0f46 ValleyView LPIO2 I2C Controller #6 - 0f47 ValleyView LPIO2 I2C Controller #7 - 0f48 ValleyView PCI Express Root Port - 0f49 ValleyView PCI Express Root Port - 0f4a ValleyView PCI Express Root Port - 0f4b ValleyView PCI Express Root Port - 0f4c ValleyView PCI Express Root Port - 0f4d ValleyView PCI Express Root Port - 0f4e ValleyView PCI Express Root Port - 0f4f ValleyView PCI Express Root Port - 0f50 ValleyView MIPI-HSI Controller + 0c00 4th Gen Core Processor DRAM Controller + 0c01 Xeon E3-1200 v3/4th Gen Core Processor PCI Express x16 Controller + 0c04 Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 0c05 Xeon E3-1200 v3/4th Gen Core Processor PCI Express x8 Controller + 0c08 Xeon E3-1200 v3 Processor DRAM Controller + 0c09 Xeon E3-1200 v3/4th Gen Core Processor PCI Express x4 Controller + 0c0c Xeon E3-1200 v3/4th Gen Core Processor HD Audio Controller + 17aa 220e ThinkPad T440p + 0c46 Atom Processor S1200 PCI Express Root Port 1 + 0c47 Atom Processor S1200 PCI Express Root Port 2 + 0c48 Atom Processor S1200 PCI Express Root Port 3 + 0c49 Atom Processor S1200 PCI Express Root Port 4 + 0c4e Atom Processor S1200 NTB Primary + 0c50 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QuickData Technology Device + 0c51 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QuickData Technology Device + 0c52 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QuickData Technology Device + 0c53 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QuickData Technology Device + 0c54 Atom Processor S1200 Internal + 0c55 Atom Processor S1200 DFX 1 + 0c56 Atom Processor S1200 DFX 2 + 0c59 Atom Processor S1200 SMBus 2.0 Controller 0 + 0c5a Atom Processor S1200 SMBus 2.0 Controller 1 + 0c5b Atom Processor S1200 SMBus Controller 2 + 0c5c Atom Processor S1200 SMBus Controller 3 + 0c5d Atom Processor S1200 SMBus Controller 4 + 0c5e Atom Processor S1200 SMBus Controller 5 + 0c5f Atom Processor S1200 UART + 0c60 Atom Processor S1200 Integrated Legacy Bus + 0c70 Atom Processor S1200 Internal + 0c71 Atom Processor S1200 Internal + 0c72 Atom Processor S1200 Internal + 0c73 Atom Processor S1200 Internal + 0c74 Atom Processor S1200 Internal + 0c75 Atom Processor S1200 Internal + 0c76 Atom Processor S1200 Internal + 0c77 Atom Processor S1200 Internal + 0c78 Atom Processor S1200 Internal + 0c79 Atom Processor S1200 Internal + 0c7a Atom Processor S1200 Internal + 0c7b Atom Processor S1200 Internal + 0c7c Atom Processor S1200 Internal + 0c7d Atom Processor S1200 Internal + 0c7e Atom Processor S1200 Internal + 0c7f Atom Processor S1200 Internal + 0d00 Crystal Well DRAM Controller + 0d01 Crystal Well PCI Express x16 Controller + 0d04 Crystal Well DRAM Controller + 0d05 Crystal Well PCI Express x8 Controller + 0d09 Crystal Well PCI Express x4 Controller + 0d0c Crystal Well HD Audio Controller + 0d16 Crystal Well Integrated Graphics Controller + 0d26 Crystal Well Integrated Graphics Controller + 0d36 Crystal Well Integrated Graphics Controller + 0e00 Xeon E7 v2/Xeon E5 v2/Core i7 DMI2 + 0e01 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port in DMI2 Mode + 0e02 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 1a + 0e03 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 1b + 0e04 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 2a + 0e05 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 2b + 0e06 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 2c + 0e07 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 2d + 0e08 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 3a + 0e09 Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 3b + 0e0a Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 3c + 0e0b Xeon E7 v2/Xeon E5 v2/Core i7 PCI Express Root Port 3d + 0e10 Xeon E7 v2/Xeon E5 v2/Core i7 IIO Configuration Registers + 0e13 Xeon E7 v2/Xeon E5 v2/Core i7 IIO Configuration Registers + 0e17 Xeon E7 v2/Xeon E5 v2/Core i7 IIO Configuration Registers + 0e18 Xeon E7 v2/Xeon E5 v2/Core i7 IIO Configuration Registers + 0e1c Xeon E7 v2/Xeon E5 v2/Core i7 IIO Configuration Registers + 0e1d Xeon E7 v2/Xeon E5 v2/Core i7 R2PCIe + 0e1e Xeon E7 v2/Xeon E5 v2/Core i7 UBOX Registers + 0e1f Xeon E7 v2/Xeon E5 v2/Core i7 UBOX Registers + 0e20 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 0 + 0e21 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 1 + 0e22 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 2 + 0e23 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 3 + 0e24 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 4 + 0e25 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 5 + 0e26 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 6 + 0e27 Xeon E7 v2/Xeon E5 v2/Core i7 Crystal Beach DMA Channel 7 + 0e28 Xeon E7 v2/Xeon E5 v2/Core i7 VTd/Memory Map/Misc + 0e29 Xeon E7 v2/Xeon E5 v2/Core i7 Memory Hotplug + 0e2a Xeon E7 v2/Xeon E5 v2/Core i7 IIO RAS + 0e2c Xeon E7 v2/Xeon E5 v2/Core i7 IOAPIC + 0e2e Xeon E7 v2/Xeon E5 v2/Core i7 CBDMA + 0e2f Xeon E7 v2/Xeon E5 v2/Core i7 CBDMA + 0e30 Xeon E7 v2/Xeon E5 v2/Core i7 Home Agent 0 + 0e32 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link 0 + 0e33 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link 1 + 0e34 Xeon E7 v2/Xeon E5 v2/Core i7 R2PCIe + 0e36 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Performance Ring Monitoring + 0e37 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Performance Ring Monitoring + 0e38 Xeon E7 v2/Xeon E5 v2/Core i7 Home Agent 1 + 0e3a Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link 2 + 0e3e Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Performance Ring Monitoring + 0e3f Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Performance Ring Monitoring + 0e40 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link 2 + 0e41 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Registers + 0e43 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Reut 2 + 0e44 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Reut 2 + 0e45 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Agent Register + 0e47 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Agent Register + 0e60 Xeon E7 v2/Xeon E5 v2/Core i7 Home Agent 1 + 0e68 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Target Address/Thermal Registers + 0e6a Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder Registers + 0e6b Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder Registers + 0e6c Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder Registers + 0e6d Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder Registers + 0e71 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 RAS Registers + 0e74 Xeon E7 v2/Xeon E5 v2/Core i7 R2PCIe + 0e75 Xeon E7 v2/Xeon E5 v2/Core i7 R2PCIe + 0e77 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Registers + 0e79 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 RAS Registers + 0e7d Xeon E7 v2/Xeon E5 v2/Core i7 UBOX Registers + 0e7f Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Registers + 0e80 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link 0 + 0e81 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Registers + 0e83 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Reut 0 + 0e84 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Reut 0 + 0e85 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Agent Register + 0e87 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Registers + 0e90 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link 1 + 0e93 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link 1 + 0e94 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Reut 1 + 0e95 Xeon E7 v2/Xeon E5 v2/Core i7 QPI Link Agent Register + 0ea0 Xeon E7 v2/Xeon E5 v2/Core i7 Home Agent 0 + 0ea8 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Target Address/Thermal Registers + 0eaa Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder Registers + 0eab Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder Registers + 0eac Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder Registers + 0ead Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder Registers + 0eae Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO Registers + 0eaf Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO Registers + 0eb0 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 Thermal Control 0 + 0eb1 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 Thermal Control 1 + 0eb2 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 ERROR Registers 0 + 0eb3 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 ERROR Registers 1 + 0eb4 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 Thermal Control 2 + 0eb5 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 Thermal Control 3 + 0eb6 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 ERROR Registers 2 + 0eb7 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 1 Channel 0-3 ERROR Registers 3 + 0ebc Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO Registers + 0ebe Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO Registers + 0ebf Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO Registers + 0ec0 Xeon E7 v2/Xeon E5 v2/Core i7 Power Control Unit 0 + 0ec1 Xeon E7 v2/Xeon E5 v2/Core i7 Power Control Unit 1 + 0ec2 Xeon E7 v2/Xeon E5 v2/Core i7 Power Control Unit 2 + 0ec3 Xeon E7 v2/Xeon E5 v2/Core i7 Power Control Unit 3 + 0ec4 Xeon E7 v2/Xeon E5 v2/Core i7 Power Control Unit 4 + 0ec8 Xeon E7 v2/Xeon E5 v2/Core i7 System Address Decoder + 0ec9 Xeon E7 v2/Xeon E5 v2/Core i7 Broadcast Registers + 0eca Xeon E7 v2/Xeon E5 v2/Core i7 Broadcast Registers + 0ed8 Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0ed9 Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0edc Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0edd Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0ede Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0edf Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0ee0 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee1 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee2 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee3 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee4 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee5 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee6 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee7 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee8 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ee9 Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0eea Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0eeb Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0eec Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0eed Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0eee Xeon E7 v2/Xeon E5 v2/Core i7 Unicast Registers + 0ef0 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 Thermal Control 0 + 0ef1 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 Thermal Control 1 + 0ef2 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 ERROR Registers 0 + 0ef3 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 ERROR Registers 1 + 0ef4 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 Thermal Control 2 + 0ef5 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 Thermal Control 3 + 0ef6 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 ERROR Registers 2 + 0ef7 Xeon E7 v2/Xeon E5 v2/Core i7 Integrated Memory Controller 0 Channel 0-3 ERROR Registers 3 + 0ef8 Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0ef9 Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0efa Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0efb Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0efc Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0efd Xeon E7 v2/Xeon E5 v2/Core i7 DDRIO + 0f00 Atom Processor Z36xxx/Z37xxx Series SoC Transaction Register + 0f04 Atom Processor Z36xxx/Z37xxx Series High Definition Audio Controller + 0f06 Atom Processor Z36xxx/Z37xxx Series LPIO1 DMA Controller + 0f08 Atom Processor Z36xxx/Z37xxx Series LPIO1 PWM Controller + 0f09 Atom Processor Z36xxx/Z37xxx Series LPIO1 PWM Controller + 0f0a Atom Processor Z36xxx/Z37xxx Series LPIO1 HSUART Controller #1 + 0f0c Atom Processor Z36xxx/Z37xxx Series LPIO1 HSUART Controller #2 + 0f0e Atom Processor Z36xxx/Z37xxx Series LPIO1 SPI Controller + 0f12 Atom Processor E3800 Series SMBus Controller + 0f14 Atom Processor Z36xxx/Z37xxx Series SDIO Controller + 0f15 Atom Processor Z36xxx/Z37xxx Series SDIO Controller + 0f16 Atom Processor Z36xxx/Z37xxx Series SDIO Controller + 0f18 Atom Processor Z36xxx/Z37xxx Series Trusted Execution Engine + 0f1c Atom Processor Z36xxx/Z37xxx Series Power Control Unit + 0f20 Atom Processor E3800 Series SATA IDE Controller + 0f21 Atom Processor E3800 Series SATA IDE Controller + 0f22 Atom Processor E3800 Series SATA AHCI Controller + 0f23 Atom Processor E3800 Series SATA AHCI Controller + 0f28 Atom Processor Z36xxx/Z37xxx Series LPE Audio Controller + 0f31 Atom Processor Z36xxx/Z37xxx Series Graphics & Display + 0f34 Atom Processor Z36xxx/Z37xxx Series USB EHCI + 0f35 Atom Processor Z36xxx/Z37xxx Series USB xHCI + 0f37 Atom Processor Z36xxx/Z37xxx Series OTG USB Device + 0f38 Atom Processor Z36xxx/Z37xxx Series Camera ISP + 0f40 Atom Processor Z36xxx/Z37xxx Series LPIO2 DMA Controller + 0f41 Atom Processor Z36xxx/Z37xxx Series LPIO2 I2C Controller #1 + 0f42 Atom Processor Z36xxx/Z37xxx Series LPIO2 I2C Controller #2 + 0f43 Atom Processor Z36xxx/Z37xxx Series LPIO2 I2C Controller #3 + 0f44 Atom Processor Z36xxx/Z37xxx Series LPIO2 I2C Controller #4 + 0f45 Atom Processor Z36xxx/Z37xxx Series LPIO2 I2C Controller #5 + 0f46 Atom Processor Z36xxx/Z37xxx Series LPIO2 I2C Controller #6 + 0f47 Atom Processor Z36xxx/Z37xxx Series LPIO2 I2C Controller #7 + 0f48 Atom Processor E3800 Series PCI Express Root Port 1 + 0f4a Atom Processor E3800 Series PCI Express Root Port 2 + 0f4c Atom Processor E3800 Series PCI Express Root Port 3 + 0f4e Atom Processor E3800 Series PCI Express Root Port 4 + 0f50 Atom Processor E3800 Series eMMC 4.5 Controller 1000 82542 Gigabit Ethernet Controller (Fiber) 0e11 b0df NC6132 Gigabit Ethernet Adapter (1000-SX) 0e11 b0e0 NC6133 Gigabit Ethernet Adapter (1000-LX) @@ -16528,6 +20908,7 @@ 1028 0134 PowerEdge 600SC 1028 0151 Optiplex GX270 107b 8920 PRO/1000 MT Desktop Adapter + 1af4 1100 QEMU Virtual Machine 8086 001e PRO/1000 MT Desktop Adapter 8086 002e PRO/1000 MT Desktop Adapter 8086 1376 PRO/1000 GT Desktop Adapter @@ -16591,6 +20972,7 @@ 1179 0001 PRO/1000 MT Mobile Connection 8086 101e PRO/1000 MT Mobile Connection 1026 82545GM Gigabit Ethernet Controller + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 8086 1000 PRO/1000 MT Server Connection 8086 1001 PRO/1000 MT Server Adapter @@ -16649,7 +21031,7 @@ 8086 a11f PRO/10GbE LR Server Adapter 1049 82566MM Gigabit Network Connection 103c 30c1 Compaq 6910p - 17aa 20b9 ThinkPad T61 + 17aa 20b9 ThinkPad T61/R61 104a 82566DM Gigabit Network Connection 104b 82566DC Gigabit Network Connection 104c 82562V 10/100 Network Connection @@ -16675,6 +21057,7 @@ 103c 704e Dual Port 1000Base-T (PCIe) [AD337A] 1775 1100 CR11/VR11 Single Board Computer 1775 6003 Telum GE-QT + 18df 1214 2x 1GbE, PCIe x1, dual Intel 82571EB chips 8086 005e PRO/1000 PT Dual Port Server Connection 8086 105e PRO/1000 PT Dual Port Network Connection 8086 10d5 82571PT Gigabit PT Quad Port Server ExpressModule @@ -16768,10 +21151,12 @@ 108f Active Management Technology - SOL 1091 PRO/100 VM Network Connection 1092 PRO/100 VE Network Connection + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 1093 PRO/100 VM Network Connection 1094 PRO/100 VE Network Connection 1095 PRO/100 VE Network Connection 1096 80003ES2LAN Gigabit Ethernet Controller (Copper) + 15d9 1096 Motherboard 15d9 8680 X7DVL-E-O motherboard 8086 3476 Intel S5000PSLSATA Server Board 1097 631xESB/632xESB DPT LAN Controller (Fiber) @@ -16781,7 +21166,7 @@ 109a 82573L Gigabit Ethernet Controller 1179 ff10 PRO/1000 PL 17aa 2001 ThinkPad T60 - 17aa 207e ThinkPad X60s + 17aa 207e ThinkPad X60/X60s 8086 109a PRO/1000 PL Network Connection 8086 309c Desktop Board D945GTP 8086 30a5 Desktop Board D975XBX @@ -16858,9 +21243,15 @@ 10cd 82567LF-2 Gigabit Network Connection 10ce 82567V-2 Gigabit Network Connection 10d3 82574L Gigabit Network Connection + 103c 1785 NC112i 1-port Ethernet Server Adapter 103c 3250 NC112T PCI Express single Port Gigabit Server Adapter + 1043 8369 Motherboard + 1093 76e9 PCIe-8233 Ethernet Adapter 10a9 8029 Prism XL Single Port Gigabit Ethernet + 15d9 060a X7SPA-H/X7SPA-HF Motherboard + 15d9 060d C7SIM-Q Motherboard 8086 0001 Gigabit CT2 Desktop Adapter + 8086 357a Server Board S1200BTS 8086 a01f Gigabit CT Desktop Adapter e4bf 50c1 PC1-GROOVE e4bf 50c2 PC2-LIMBO @@ -16903,6 +21294,7 @@ 10ed 82599 Ethernet Controller Virtual Function 10ef 82578DM Gigabit Network Connection 1028 02da OptiPlex 980 + 15d9 060d C7SIM-Q Motherboard 10f0 82578DC Gigabit Network Connection 10f1 82598EB 10-Gigabit AF Dual Port Network Connection 8086 a20f 10-Gigabit AF DA Dual Port Server Adapter @@ -16912,30 +21304,35 @@ 8086 a06f 10-Gigabit XF LR Server Adapter 10f5 82567LM Gigabit Network Connection 10f6 82574L Gigabit Network Connection - 10f7 82599EB 10-Gigabit KX4 Network Connection + 10f7 10 Gigabit BR KX4 Dual Port Network Connection 108e 7b12 Sun Dual 10GbE PCIe 2.0 FEM 8086 000d Ethernet Mezzanine Adapter X520-KX4-2 - 10f8 82599EB 10 Gigabit Dual Port Backplane Connection + 10f8 82599 10 Gigabit Dual Port Backplane Connection 1028 1f63 10GbE 2P X520k bNDC 103c 17d2 Ethernet 10Gb 2-port 560M Adapter 103c 18d0 Ethernet 10Gb 2-port 560FLB Adapter 8086 000c Ethernet X520 10GbE Dual Port KX4-KR Mezz - 10f9 82599EB 10 Gigabit CX4 Dual Port Network Connection - 10fb 82599EB 10-Gigabit SFI/SFP+ Network Connection + 10f9 82599 10 Gigabit Dual Port Network Connection + 10fb 82599ES 10-Gigabit SFI/SFP+ Network Connection 1028 1f72 Ethernet 10G 4P X520/I350 rNDC 103c 17d0 Ethernet 10Gb 2-port 560FLR-SFP+ Adapter 103c 17d2 Ethernet 10Gb 2-port 560M Adapter 103c 17d3 Ethernet 10Gb 2-port 560SFP+ Adapter + 103c 211b Ethernet 10Gb 1-port P560FLR-SFP+ Adapter + 103c 2147 Ethernet 10Gb 1-port 561i Adapter + 103c 2159 Ethernet 10Gb 2-port 562i Adapter 108e 7b11 Ethernet Server Adapter X520-2 1734 11a9 10 Gigabit Dual Port Network Connection + 17aa 1071 ThinkServer X520-2 AnyFabric 8086 0002 Ethernet Server Adapter X520-DA2 8086 0003 Ethernet Server Adapter X520-2 8086 0006 Ethernet Server Adapter X520-1 + 8086 0008 Ethernet OCP Server Adapter X520-2 8086 000a Ethernet Server Adapter X520-1 8086 000c Ethernet Server Adapter X520-2 8086 7a11 Ethernet Server Adapter X520-2 8086 7a12 Ethernet Server Adapter X520-2 - 10fc 82599EB 10-Gigabit XAUI/BX4 Network Connection + 10fc 82599 10 Gigabit Dual Port Network Connection 10fe 82552 10/100 Network Connection 1107 PRO/1000 MF Server Adapter (LX) 1130 82815 815 Chipset Host Bridge and Memory Controller Hub @@ -16959,6 +21356,7 @@ 172a 0000 AEP SSL Accelerator 1209 8255xER/82551IT Fast Ethernet Controller 140b 0610 PMC610 quad Ethernet board + 1af4 1100 QEMU Virtual Machine 4c53 1050 CT7 mainboard 4c53 1051 CE7 mainboard 4c53 1070 PC6 mainboard @@ -17041,6 +21439,7 @@ 1668 1100 EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem) 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 + 1af4 1100 QEMU Virtual Machine 4c53 1080 CT8 mainboard 4c53 10e0 PSL09 PrPMC 8086 0001 EtherExpress PRO/100B (TX) @@ -17158,9 +21557,11 @@ 1462 82870P2 P64H2 Hot Plug Controller 1501 82567V-3 Gigabit Network Connection 1502 82579LM Gigabit Network Connection + 1028 04a3 Precision M4600 + 8086 357a Server Board S1200BTS 1503 82579V Gigabit Network Connection 1043 849c P8P67 Deluxe Motherboard - 1507 82599EB 10 Gigabit Network Connection + 1507 Ethernet Express Module X520-P2 1508 82598EB Gigabit BX Network Connection 150a 82576NS Gigabit Network Connection 150b 82598EB 10-Gigabit AT2 Server Adapter @@ -17177,7 +21578,7 @@ 150f 82580 Gigabit Fiber Network Connection 1510 82580 Gigabit Backplane Connection 1511 82580 Gigabit SFP Connection - 1514 82599EB 10 Gigabit KX4 Network Connection + 1514 Ethernet X520 10GbE Dual Port KX4 Mezz 8086 000b Ethernet X520 10GbE Dual Port KX4 Mezz 1515 X540 Ethernet Controller Virtual Function 1516 82580 Gigabit Network Connection @@ -17186,18 +21587,29 @@ 1517 82599ES 10 Gigabit Network Connection 1137 006a UCS CNA M61KR-I Intel Converged Network Adapter 1518 82576NS SerDes Gigabit Network Connection - 151c 82599EB 10 Gigabit TN Network Connection + 151c 82599 10 Gigabit TN Network Connection 108e 7b13 Dual 10GBASE-T LP 1520 I350 Ethernet Controller Virtual Function 1521 I350 Gigabit Network Connection - 1028 1f60 Intel GbE 4P I350crNDC - 1028 1f62 Intel GbE 2P I350crNDC + 1028 0602 Gigabit 2P I350-t LOM + 1028 1f60 Gigabit 4P I350-t rNDC + 1028 1f62 Gigabit 4P X540/I350 rNDC + 1028 ff9a Gigabit 4P X710/I350 rNDC + 103c 17d1 Ethernet 1Gb 4-port 366FLR Adapter + 103c 2003 Ethernet 1Gb 2-port 367i Adapter + 103c 2226 Ethernet 1Gb 1-port 364i Adapter 103c 337f Ethernet 1Gb 2-port 361i Adapter 103c 3380 Ethernet 1Gb 4-port 366i Adapter - 103c 339e Ethernet 1Gb 2-port 361T Adapter [Wharton Stony Lake] + 103c 339e Ethernet 1Gb 2-port 361T Adapter + 103c 8157 Ethernet 1Gb 4-port 366T Adapter 108e 7b16 Quad Port GbE PCIe 2.0 ExpressModule, UTP 108e 7b18 Quad Port GbE PCIe 2.0 Low Profile Adapter, UTP + 1093 7648 PCIe-8237R Ethernet Adapter + 1093 7649 PCIe-8236 Ethernet Adapter + 1093 76b1 PCIe-8237R-S Ethernet Adapter + 1093 775b PCIe-8237 Ethernet Adapter 10a9 802a UV2-BaseIO dual-port GbE + 17aa 1074 ThinkServer I350-T4 AnyFabric 8086 0001 Ethernet Server Adapter I350-T4 8086 0002 Ethernet Server Adapter I350-T2 8086 00a1 Ethernet Server Adapter I350-T4 @@ -17210,12 +21622,17 @@ 8086 0002 Ethernet Server Adapter I350-T2 8086 0003 Ethernet Server Adapter I350-F4 8086 0004 Ethernet Server Adapter I350-F2 + 8086 0005 Ethernet Server Adapter I350-F1 + 8086 00a2 Ethernet Server Adapter I350-T2 8086 00a3 Ethernet Server Adapter I350-F4 8086 00a4 Ethernet Server Adapter I350-F2 1523 I350 Gigabit Backplane Connection - 103c 1784 Ethernet 1Gb 2-port 361FLB Adapter [Badger Flat] + 1028 0060 Gigabit 2P I350 LOM + 1028 1f9b Gigabit 4P I350-t bNDC + 103c 1784 Ethernet 1Gb 2-port 361FLB Adapter 103c 18d1 Ethernet 1Gb 2-port 361FLB Adapter - 103c 339f Ethernet 1Gb 4-port 366M Adapter [Vaca Key] + 103c 1989 Ethernet 1Gb 2-port 363i Adapter + 103c 339f Ethernet 1Gb 4-port 366M Adapter 8086 1f52 1GbE 4P I350 Mezz 1524 I350 Gigabit Connection 1525 82567V-4 Gigabit Network Connection @@ -17226,28 +21643,39 @@ 8086 0001 Ethernet Server Adapter I340-F4 8086 0002 Ethernet Server Adapter I340-F4 1528 Ethernet Controller 10-Gigabit X540-AT2 + 1028 1f61 Ethernet 10G 4P X540/I350 rNDC 103c 192d 561FLR-T 2-port 10Gb Ethernet Adapter + 103c 2004 Ethernet 10Gb 2-port 561i Adapter + 103c 211a Ethernet 10Gb 2-port 561T Adapter + 108e 4853 Ethernet Controller 10-Gigabit X540-AT2 108e 7b14 Sun Dual Port 10 GbE PCIe 2.0 ExpressModule, Base-T 108e 7b15 Sun Dual Port 10 GbE PCIe 2.0 Low Profile Adapter, Base-T 1137 00bf Ethernet Converged Network Adapter X540-T2 + 17aa 1073 ThinkServer X540-T2 AnyFabric 8086 0001 Ethernet Converged Network Adapter X540-T2 8086 0002 Ethernet Converged Network Adapter X540-T1 8086 001a Ethernet Converged Network Adapter X540-T2 8086 00a2 Ethernet Converged Network Adapter X540-T1 8086 1f61 Ethernet 10G 4P X540/I350 rNDC 8086 5003 Ethernet 10G 2P X540-t Adapter - 1529 82599 10 Gigabit Dual Port Backplane Connection with FCoE - 152a 82599 10 Gigabit Dual port Network Connection with FCoE + 8086 5004 Ethernet 10G 2P X540-t Adapter + 1529 82599 10 Gigabit Dual Port Network Connection with FCoE + 152a 82599 10 Gigabit Dual Port Backplane Connection with FCoE 1533 I210 Gigabit Network Connection - 103c 0003 Ethernet Server Adapter I210-T1 + 103c 0003 Ethernet I210-T1 GbE NIC + 1093 7706 Compact Vision System Ethernet Adapter + 10a9 802c UV300 BaseIO single-port GbE + 10a9 802d UV3000 BaseIO GbE Network + 17aa 1100 ThinkServer Ethernet Server Adapter 8086 0001 Ethernet Server Adapter I210-T1 8086 0002 Ethernet Server Adapter I210-T1 - 1534 I210 Gigabit Network Connection 1536 I210 Gigabit Fiber Network Connection 1537 I210 Gigabit Backplane Connection 1538 I210 Gigabit Network Connection 1539 I211 Gigabit Network Connection 153a Ethernet Connection I217-LM + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p 153b Ethernet Connection I217-V 1547 DSL3510 Thunderbolt Port [Cactus Ridge] 1549 DSL3510 Thunderbolt Controller [Cactus Ridge] @@ -17255,9 +21683,155 @@ 8086 011a Ethernet Converged Network Adapter X520-4 8086 011b Ethernet Converged Network Adapter X520-4 8086 011c Ethernet Converged Network Adapter X520-4 - 154d 82599EB 10-Gigabit SFP+ Network Connection + 154c XL710/X710 Virtual Function + 154d Ethernet 10G 2P X520 Adapter 8086 7b11 10GbE 2P X520 Adapter - 1560 Ethernet Controller X540-AT1 + 1557 82599 10 Gigabit Network Connection + 8086 0001 Ethernet OCP Server Adapter X520-1 + 1558 Ethernet Converged Network Adapter X520-Q1 + 8086 011a Ethernet Converged Network Adapter X520-Q1 + 8086 011b Ethernet Converged Network Adapter X520-Q1 + 1559 Ethernet Connection I218-V + 155a Ethernet Connection I218-LM + 17aa 2214 ThinkPad X240 + 155c Ethernet Server Bypass Adapter + 8086 0001 Ethernet Server Bypass Adapter X540-T2 + 155d Ethernet Server Bypass Adapter + 8086 0001 Ethernet Server Bypass Adapter X520-SR2 + 8086 0002 Ethernet Server Bypass Adapter X520-LR2 + 1560 Ethernet Controller X540 + 156f Ethernet Connection I219-LM + 1570 Ethernet Connection I219-V + 1571 XL710/X710 Virtual Function + 1572 Ethernet Controller X710 for 10GbE SFP+ + 1028 1f99 Ethernet 10G 4P X710/I350 rNDC + 103c 22fc HP Ethernet 10Gb 2-port 562FLR-SFP+ Adapter + 103c 22fd HP Ethernet 10Gb 2-port 562SFP+ Adapter + 1137 0000 Ethernet Converged NIC X710-4 + 1137 013b Ethernet Converged NIC X710-4 + 17aa 0000 ThinkServer X710 AnyFabric for 10GbE SFP+ + 17aa 4001 ThinkServer X710-4 AnyFabric for 10GbE SFP+ + 17aa 4002 ThinkServer X710-2 AnyFabric for 10GbE SFP+ + 8086 0000 Ethernet Converged Network Adapter X710 + 8086 0001 Ethernet Converged Network Adapter X710-4 + 8086 0002 Ethernet Converged Network Adapter X710-4 + 8086 0004 Ethernet Converged Network Adapter X710-4 + 8086 0005 Ethernet 10G 4P X710 Adapter + 8086 0006 Ethernet 10G 2P X710 Adapter + 8086 0007 Ethernet Converged Network Adapter X710-2 + 8086 0008 Ethernet Converged Network Adapter X710-2 + 8086 0009 Ethernet Controller X710 for 10GbE SFP+ + 8086 000a Ethernet Controller X710 for 10GbE SFP+ + 8086 000d Ethernet Controller X710 for 10GbE SFP+ + 8086 4005 Ethernet Controller XL710 for 10 Gigabit SFP+ + 8086 4006 Ethernet Controller X710 for 10GbE SFP+ + 157b I210 Gigabit Network Connection + 157c I210 Gigabit Backplane Connection + 1580 Ethernet Controller XL710 for 40GbE backplane + 1581 Ethernet Controller X710 for 10GbE backplane + 1028 1f98 Ethernet 10G 4P X710-k bNDC + 1583 Ethernet Controller XL710 for 40GbE QSFP+ + 1028 0000 Ethernet 40G 2P XL710 QSFP+ rNDC + 1028 1f9f Ethernet 40G 2P XL710 QSFP+ rNDC + 108e 0000 Oracle 10 Gb and 40 Gb Ethernet Adapter + 108e 7b1b Oracle 10 Gb and 40 Gb Ethernet Adapter + 1137 0000 Ethernet Converged NIC XL710-Q2 + 1137 013c Ethernet Converged NIC XL710-Q2 + 8086 0000 Ethernet Converged Network Adapter XL710-Q2 + 8086 0001 Ethernet Converged Network Adapter XL710-Q2 + 8086 0002 Ethernet Converged Network Adapter XL710-Q2 + 8086 0003 Ethernet I/O Module XL710-Q2 + 8086 0006 Ethernet Converged Network Adapter XL710-Q2 + 1584 Ethernet Controller XL710 for 40GbE QSFP+ + 8086 0000 Ethernet Converged Network Adapter XL710-Q1 + 8086 0001 Ethernet Converged Network Adapter XL710-Q1 + 8086 0002 Ethernet Converged Network Adapter XL710-Q1 + 8086 0003 Ethernet I/O Module XL710-Q1 + 1585 Ethernet Controller X710 for 10GbE QSFP+ + 1586 Ethernet Controller X710 for 10GBASE-T + 108e 0000 Ethernet Controller X710 for 10GBASE-T + 108e 4857 Ethernet Controller X710 for 10GBASE-T + 1587 Ethernet Controller XL710 for 20GbE backplane + 103c 0000 HP Flex-20 20Gb 2-port 660FLB Adapter + 103c 22fe HP Flex-20 20Gb 2-port 660FLB Adapter + 103c 22ff HP Flex-20 20Gb 2-port 660M Adapter + 1588 Ethernet Controller XL710 for 20GbE backplane + 103c 0000 HP Flex-20 20Gb 2-port 660M Adapter + 103c 22ff HP Flex-20 20Gb 2-port 660M Adapter + 1589 Ethernet Controller X710/X557-AT 10GBASE-T + 8086 0000 Ethernet Converged Network Adapter X710-T + 8086 0001 Ethernet Converged Network Adapter X710-T4 + 8086 0002 Ethernet Converged Network Adapter X710-T4 + 15a0 Ethernet Connection (2) I218-LM + 15a1 Ethernet Connection (2) I218-V + 15a2 Ethernet Connection (3) I218-LM + 15a3 Ethernet Connection (3) I218-V + 15a4 Ethernet Switch FM10000 Host Interface + 15a5 Ethernet Switch FM10000 Host Virtual Interface + 15a8 Ethernet Connection X552 Virtual Function + 15aa Ethernet Connection X552 10 GbE Backplane + 15ab Ethernet Connection X552 10 GbE Backplane + 15ac Ethernet Connection X552 10 GbE SFP+ + 15ad Ethernet Connection X552/X557-AT 10GBASE-T + 15b7 Ethernet Connection (2) I219-LM + 15b8 Ethernet Connection (2) I219-V + 1600 Broadwell-U Host Bridge -OPI + 1601 Broadwell-U PCI Express x16 Controller + 1602 Broadwell-U Integrated Graphics + 1603 Broadwell-U Camarillo Device + 1604 Broadwell-U Host Bridge -OPI + 1605 Broadwell-U PCI Express x8 Controller + 1606 Broadwell-U Integrated Graphics + 1607 Broadwell-U CHAPS Device + 1608 Broadwell-U Host Bridge -OPI + 1609 Broadwell-U x4 PCIe + 160a Broadwell-U Integrated Graphics + 160b Broadwell-U Integrated Graphics + 160c Broadwell-U Audio Controller + 160d Broadwell-U Integrated Graphics + 160e Broadwell-U Integrated Graphics + 160f Broadwell-U SoftSKU + 1610 Broadwell-U Host Bridge - DMI + 1612 Broadwell-U Integrated Graphics + 1614 Broadwell-U Host Bridge - DMI + 1616 Broadwell-U Integrated Graphics + 103c 2216 ZBook 15u G2 Mobile Workstation + 1618 Broadwell-U Host Bridge - DMI + 161a Broadwell-U Integrated Graphics + 161b Broadwell-U Integrated Graphics + 161d Broadwell-U Integrated Graphics + 161e Broadwell-U Integrated Graphics + 1622 Broadwell-U Integrated Graphics + 1626 Broadwell-U Integrated Graphics + 162a Broadwell-U Integrated Graphics + 162b Broadwell-U Integrated Graphics + 162d Broadwell-U Integrated Graphics + 162e Broadwell-U Integrated Graphics + 1632 Broadwell-U Integrated Graphics + 1636 Broadwell-U Integrated Graphics + 163a Broadwell-U Integrated Graphics + 163b Broadwell-U Integrated Graphics + 163d Broadwell-U Integrated Graphics + 163e Broadwell-U Integrated Graphics + 1900 Sky Lake Host Bridge/DRAM Registers + 1901 Sky Lake PCIe Controller (x16) + 1904 Sky Lake Host Bridge/DRAM Registers + 1905 Sky Lake PCIe Controller (x8) + 1908 Sky Lake Host Bridge/DRAM Registers + 1909 Sky Lake PCIe Controller (x4) + 190c Sky Lake Host Bridge/DRAM Registers + 190f Sky Lake Host Bridge/DRAM Registers + 1910 Sky Lake Host Bridge/DRAM Registers + 1911 Sky Lake Gaussian Mixture Model + 1912 Sky Lake Integrated Graphics + 1916 Sky Lake Integrated Graphics + 1918 Sky Lake Host Bridge/DRAM Registers + 1919 Sky Lake Imaging Unit + 191e Sky Lake Integrated Graphics + 191f Sky Lake Host Bridge/DRAM Registers + 1926 Sky Lake Integrated Graphics + 1932 Sky Lake Integrated Graphics + 193b Sky Lake Integrated Graphics 1960 80960RP (i960RP) Microprocessor 101e 0431 MegaRAID 431 RAID Controller 101e 0438 MegaRAID 438 Ultra2 LVD RAID Controller @@ -17290,6 +21864,7 @@ 1a24 82840 840 [Carmel] Chipset PCI Bridge (Hub B) 1a30 82845 845 [Brookdale] Chipset Host Bridge 1028 010e Optiplex GX240 + 147b 0505 BL7 motherboard 15d9 3280 Supermicro P4SBE Mainboard 1a31 82845 845 [Brookdale] Chipset AGP Bridge 1a38 5000 Series Chipset DMA Engine @@ -17305,68 +21880,86 @@ 1c01 6 Series/C200 Series Chipset Family 4 port SATA IDE Controller 1c02 6 Series/C200 Series Chipset Family SATA AHCI Controller 1028 04aa XPS 8300 - 1043 844d P8P67 Deluxe Motherboard + 1043 844d P8 series motherboard + 8086 7270 Server Board S1200BTS 1c03 6 Series/C200 Series Chipset Family 6 port SATA AHCI Controller + 1028 04a3 Precision M4600 1028 04b2 Vostro 3350 1028 04da Vostro 3750 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c04 6 Series/C200 Series Chipset Family SATA RAID Controller + 103c 3118 Smart Array B110i SATA RAID Controller 1c05 6 Series/C200 Series Chipset Family SATA RAID Controller 1c08 6 Series/C200 Series Chipset Family 2 port SATA IDE Controller 1c09 6 Series/C200 Series Chipset Family 2 port SATA IDE Controller 1c10 6 Series/C200 Series Chipset Family PCI Express Root Port 1 + 1028 04aa XPS 8300 1028 04da Vostro 3750 - 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] + 1043 844d P8 series motherboard + 8086 7270 Server Board S1200BTS / Apple MacBook Pro 8,1/8,2 1c12 6 Series/C200 Series Chipset Family PCI Express Root Port 2 + 1028 04aa XPS 8300 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c14 6 Series/C200 Series Chipset Family PCI Express Root Port 3 1028 04da Vostro 3750 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c16 6 Series/C200 Series Chipset Family PCI Express Root Port 4 + 1028 04aa XPS 8300 1c18 6 Series/C200 Series Chipset Family PCI Express Root Port 5 1028 04da Vostro 3750 + 8086 7270 Server Board S1200BTS 1c1a 6 Series/C200 Series Chipset Family PCI Express Root Port 6 1028 04da Vostro 3750 + 1043 844d P8 series motherboard 1c1c 6 Series/C200 Series Chipset Family PCI Express Root Port 7 1c1e 6 Series/C200 Series Chipset Family PCI Express Root Port 8 + 1043 844d P8 series motherboard 1c20 6 Series/C200 Series Chipset Family High Definition Audio Controller 1028 0490 Alienware M17x R3 + 1028 04a3 Precision M4600 1028 04aa XPS 8300 1028 04b2 Vostro 3350 1028 04da Vostro 3750 1043 8418 P8P67 Deluxe Motherboard + 1043 841b P8H67 Series Motherboard +# Realtek ALC888 audio codec + 8086 2008 DQ67SW board 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c22 6 Series/C200 Series Chipset Family SMBus Controller + 1028 04a3 Precision M4600 1028 04aa XPS 8300 1028 04b2 Vostro 3350 1028 04da Vostro 3750 - 1043 844d P8P67 Deluxe Motherboard - 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] + 1043 844d P8 series motherboard + 8086 7270 Server Board S1200BTS / Apple MacBook Pro 8,1/8,2 1c24 6 Series/C200 Series Chipset Family Thermal Management Controller 1c25 6 Series/C200 Series Chipset Family DMI to PCI Bridge 1c26 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #1 + 1028 04a3 Precision M4600 1028 04aa XPS 8300 1028 04b2 Vostro 3350 1028 04da Vostro 3750 - 1043 844d P8P67 Deluxe Motherboard - 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] + 1043 844d P8 series motherboard + 8086 7270 Server Board S1200BTS / Apple MacBook Pro 8,1/8,2 1c27 6 Series/C200 Series Chipset Family USB Universal Host Controller #1 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c2c 6 Series/C200 Series Chipset Family USB Universal Host Controller #5 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c2d 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #2 + 1028 04a3 Precision M4600 1028 04aa XPS 8300 1028 04b2 Vostro 3350 1028 04da Vostro 3750 - 1043 844d P8P67 Deluxe Motherboard - 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] + 1043 844d P8 series motherboard + 8086 7270 Server Board S1200BTS / Apple MacBook Pro 8,1/8,2 1c33 6 Series/C200 Series Chipset Family LAN Controller 1c35 6 Series/C200 Series Chipset Family VECI Controller 1c3a 6 Series/C200 Series Chipset Family MEI Controller #1 + 1028 04a3 Precision M4600 1028 04aa XPS 8300 1028 04b2 Vostro 3350 1028 04da Vostro 3750 - 1043 844d P8P67 Deluxe Motherboard + 1043 844d P8 series motherboard 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c3b 6 Series/C200 Series Chipset Family MEI Controller #2 1c3c 6 Series/C200 Series Chipset Family IDE-r Controller @@ -17385,6 +21978,7 @@ 8086 7270 Apple MacBookPro8,2 [Core i7, 15", 2011] 1c4a H67 Express Chipset Family LPC Controller 1028 04aa XPS 8300 + 1043 844d P8H67 Series Motherboard 1c4b HM67 Express Chipset Family LPC Controller 1028 04b2 Vostro 3350 1028 04da Vostro 3750 @@ -17392,13 +21986,16 @@ 1c4d QS67 Express Chipset Family LPC Controller 1c4e Q67 Express Chipset Family LPC Controller 1c4f QM67 Express Chipset Family LPC Controller + 1028 04a3 Precision M4600 1c50 B65 Express Chipset Family LPC Controller 1c51 6 Series/C200 Series Chipset Family LPC Controller 1c52 C202 Chipset Family LPC Controller + 8086 7270 Server Board S1200BTS 1c53 6 Series/C200 Series Chipset Family LPC Controller 1c54 C204 Chipset Family LPC Controller 1c55 6 Series/C200 Series Chipset Family LPC Controller 1c56 C206 Chipset Family LPC Controller + 1043 844d P8B WS Motherboard 1c57 6 Series/C200 Series Chipset Family LPC Controller 1c58 Upgraded B65 Express Chipset Family LPC Controller 1c59 Upgraded HM67 Express Chipset Family LPC Controller @@ -17475,8 +22072,11 @@ 1e00 7 Series/C210 Series Chipset Family 4-port SATA Controller [IDE mode] 1e01 7 Series Chipset Family 4-port SATA Controller [IDE mode] 1e02 7 Series/C210 Series Chipset Family 6-port SATA Controller [AHCI mode] + 1043 84ca P8 series motherboard + 1849 1e02 Motherboard 1e03 7 Series Chipset Family 6-port SATA Controller [AHCI mode] 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A 1e04 7 Series/C210 Series Chipset Family SATA Controller [RAID mode] 1e05 7 Series Chipset SATA Controller [RAID mode] 1e06 7 Series/C210 Series Chipset Family SATA Controller [RAID mode] @@ -17486,30 +22086,60 @@ 1e0e 7 Series/C210 Series Chipset Family SATA Controller [RAID mode] 1e10 7 Series/C210 Series Chipset Family PCI Express Root Port 1 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A + 1043 84ca P8H77-I Motherboard + 1849 1e10 Motherboard 1e12 7 Series/C210 Series Chipset Family PCI Express Root Port 2 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A 1e14 7 Series/C210 Series Chipset Family PCI Express Root Port 3 1e16 7 Series/C210 Series Chipset Family PCI Express Root Port 4 1043 1477 N56VZ + 1849 1618 Z77 Extreme4 motherboard 1e18 7 Series/C210 Series Chipset Family PCI Express Root Port 5 + 1043 84ca P8H77-I Motherboard + 1849 1e18 Motherboard 1e1a 7 Series/C210 Series Chipset Family PCI Express Root Port 6 + 1849 1e1a Motherboard 1e1c 7 Series/C210 Series Chipset Family PCI Express Root Port 7 1e1e 7 Series/C210 Series Chipset Family PCI Express Root Port 8 + 1849 1e1e Motherboard 1e20 7 Series/C210 Series Chipset Family High Definition Audio Controller 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A + 1043 8415 P8H77-I Motherboard + 1043 8445 ASUS P8Z77-V LX Motherboard + 1849 1898 Z77 Extreme4 motherboard 1e22 7 Series/C210 Series Chipset Family SMBus Controller 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A + 1043 84ca P8 series motherboard + 1849 1e22 Motherboard 1e24 7 Series/C210 Series Chipset Family Thermal Management Controller + 1043 1517 Zenbook Prime UX31A 1e25 7 Series/C210 Series Chipset Family DMI to PCI Bridge 1e26 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A + 1043 84ca P8 series motherboard + 1849 1e26 Motherboard 1e2d 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A + 1043 84ca P8 series motherboard + 1849 1e2d Motherboard 1e31 7 Series/C210 Series Chipset Family USB xHCI Host Controller + 103c 17ab ProBook 6570b 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A + 1043 84ca P8 series motherboard + 1849 1e31 Motherboard 1e33 7 Series/C210 Series Chipset Family LAN Controller 1e3a 7 Series/C210 Series Chipset Family MEI Controller #1 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A + 1043 84ca P8 series motherboard + 1849 1e3a Motherboard 1e3b 7 Series/C210 Series Chipset Family MEI Controller #2 1e3c 7 Series/C210 Series Chipset Family IDE-r Controller 1e3d 7 Series/C210 Series Chipset Family KT Controller @@ -17517,12 +22147,15 @@ 1e42 7 Series Chipset Family LPC Controller 1e43 7 Series Chipset Family LPC Controller 1e44 Z77 Express Chipset LPC Controller + 1043 84ca P8 series motherboard + 1849 1e44 Motherboard 1e45 7 Series Chipset Family LPC Controller 1e46 Z75 Express Chipset LPC Controller 1e47 Q77 Express Chipset LPC Controller 1e48 Q75 Express Chipset LPC Controller 1e49 B75 Express Chipset LPC Controller 1e4a H77 Express Chipset LPC Controller + 1043 84ca P8H77-I Motherboard 1e4b 7 Series Chipset Family LPC Controller 1e4c 7 Series Chipset Family LPC Controller 1e4d 7 Series Chipset Family LPC Controller @@ -17539,12 +22172,110 @@ 1e58 UM77 Express Chipset LPC Controller 1e59 HM76 Express Chipset LPC Controller 1043 1477 N56VZ + 1043 1517 Zenbook Prime UX31A 1e5a 7 Series Chipset Family LPC Controller 1e5b UM77 Express Chipset LPC Controller 1e5c 7 Series Chipset Family LPC Controller 1e5d HM75 Express Chipset LPC Controller 1e5e 7 Series Chipset Family LPC Controller 1e5f 7 Series Chipset Family LPC Controller + 1f00 Atom processor C2000 SoC Transaction Router + 1f01 Atom processor C2000 SoC Transaction Router + 1f02 Atom processor C2000 SoC Transaction Router + 1f03 Atom processor C2000 SoC Transaction Router + 1f04 Atom processor C2000 SoC Transaction Router + 1f05 Atom processor C2000 SoC Transaction Router + 1f06 Atom processor C2000 SoC Transaction Router + 1f07 Atom processor C2000 SoC Transaction Router + 1f08 Atom processor C2000 SoC Transaction Router + 1f09 Atom processor C2000 SoC Transaction Router + 1f0a Atom processor C2000 SoC Transaction Router + 1f0b Atom processor C2000 SoC Transaction Router + 1f0c Atom processor C2000 SoC Transaction Router + 1f0d Atom processor C2000 SoC Transaction Router + 1f0e Atom processor C2000 SoC Transaction Router + 1f0f Atom processor C2000 SoC Transaction Router + 1f10 Atom processor C2000 PCIe Root Port 1 + 1f11 Atom processor C2000 PCIe Root Port 2 + 1f12 Atom processor C2000 PCIe Root Port 3 + 1f13 Atom processor C2000 PCIe Root Port 4 + 1f14 Atom processor C2000 RAS + 1f15 Atom processor C2000 SMBus 2.0 + 1f16 Atom processor C2000 RCEC + 1f18 Atom processor C2000 QAT + 1f19 Atom processor C2000 QAT + 1f20 Atom processor C2000 4-Port IDE SATA2 Controller + 1f21 Atom processor C2000 4-Port IDE SATA2 Controller + 1f22 Atom processor C2000 AHCI SATA2 Controller + 1f23 Atom processor C2000 AHCI SATA2 Controller + 1f24 Atom processor C2000 RAID SATA2 Controller + 1f25 Atom processor C2000 RAID SATA2 Controller + 1f26 Atom processor C2000 RAID SATA2 Controller + 1f27 Atom processor C2000 RAID SATA2 Controller + 1f2c Atom processor C2000 USB Enhanced Host Controller + 1f2e Atom processor C2000 RAID SATA2 Controller + 1f2f Atom processor C2000 RAID SATA2 Controller + 1f30 Atom processor C2000 2-Port IDE SATA3 Controller + 1f31 Atom processor C2000 2-Port IDE SATA3 Controller + 1f32 Atom processor C2000 AHCI SATA3 Controller + 1f33 Atom processor C2000 AHCI SATA3 Controller + 1f34 Atom processor C2000 RAID SATA3 Controller + 1f35 Atom processor C2000 RAID SATA3 Controller + 1f36 Atom processor C2000 RAID SATA3 Controller + 1f37 Atom processor C2000 RAID SATA3 Controller + 1f38 Atom processor C2000 PCU + 1f39 Atom processor C2000 PCU + 1f3a Atom processor C2000 PCU + 1f3b Atom processor C2000 PCU + 1f3c Atom processor C2000 PCU SMBus + 1f3e Atom processor C2000 RAID SATA3 Controller + 1f3f Atom processor C2000 RAID SATA3 Controller + 1f40 Ethernet Connection I354 1.0 GbE Backplane + 1028 05f1 Ethernet Connection I354 1.0 GbE Backplane + 1f41 Ethernet Connection I354 + 1f42 Atom processor C2000 GbE + 1f44 Atom processor C2000 GbE Virtual Function + 1f45 Ethernet Connection I354 2.5 GbE Backplane + 2014 Sky Lake-E Ubox Registers + 2015 Sky Lake-E Ubox Registers + 2016 Sky Lake-E Ubox Registers + 2018 Sky Lake-E M2PCI Registers + 201a Sky Lake-E Non-Transparent Bridge Registers + 201c Sky Lake-E Non-Transparent Bridge Registers + 2021 Sky Lake-E CBDMA Registers + 2024 Sky Lake-E MM/Vt-d Configuration Registers + 2030 Sky Lake-E PCI Express Root Port 1A + 2031 Sky Lake-E PCI Express Root Port 1B + 2032 Sky Lake-E PCI Express Root Port 1C + 2033 Sky Lake-E PCI Express Root Port 1D + 2035 Sky Lake-E RAS Configuration Registers + 204c Sky Lake-E M3KTI Registers + 204d Sky Lake-E M3KTI Registers + 204e Sky Lake-E M3KTI Registers + 2054 Sky Lake-E CHA Registers + 2055 Sky Lake-E CHA Registers + 2056 Sky Lake-E CHA Registers + 2057 Sky Lake-E CHA Registers + 2068 Sky Lake-E DDRIO Registers + 2069 Sky Lake-E DDRIO Registers + 206a Sky Lake-E IOxAPIC Configuration Registers + 206e Sky Lake-E DDRIO Registers + 206f Sky Lake-E DDRIO Registers + 2078 Sky Lake-E PCU Registers + 207a Sky Lake-E PCU Registers + 2080 Sky Lake-E PCU Registers + 2081 Sky Lake-E PCU Registers + 2082 Sky Lake-E PCU Registers + 2083 Sky Lake-E PCU Registers + 2084 Sky Lake-E PCU Registers + 2085 Sky Lake-E PCU Registers + 2086 Sky Lake-E PCU Registers + 208d Sky Lake-E CHA Registers + 208e Sky Lake-E CHA Registers + 2250 Xeon Phi coprocessor 5100 series + 225c Xeon Phi coprocessor SE10/7120 series + 225d Xeon Phi coprocessor 3120 series + 225e Xeon Phi coprocessor 31S1 2310 DH89xxCC LPC Controller 2323 DH89xxCC 4 Port SATA AHCI Controller 2330 DH89xxCC SMBus Controller @@ -17563,6 +22294,26 @@ 2360 DH89xxCC Watchdog Timer 2364 DH89xxCC MEI 0 2365 DH89xxCC MEI 1 + 2390 DH895XCC Series LPC Controller + 23a1 DH895XCC Series 2-Port SATA Controller [IDE Mode] + 23a3 DH895XCC Series 4-Port SATA Controller [AHCI Mode] + 23a6 DH895XCC Series 2-Port SATA Controller [IDE Mode] + 23b0 DH895XCC Series SMBus Controller + 23b1 DH895XCC Series CHAP Counter + 23b2 DH895XCC Series Thermal Management Controller + 23b4 DH895XCC Series USB2 Enhanced Host Controller #1 + 23b5 DH895XCC Series USB2 Enhanced Host Controller #1 + 23c2 DH895XCC Series PCI Express Root Port #1 + 23c3 DH895XCC Series PCI Express Root Port #1 + 23c4 DH895XCC Series PCI Express Root Port #2 + 23c5 DH895XCC Series PCI Express Root Port #2 + 23c6 CDH895XCC Series PCI Express Root Port #3 + 23c7 DH895XCC Series PCI Express Root Port #3 + 23c8 DH895XCC Series PCI Express Root Port #4 + 23c9 DH895XCC Series PCI Express Root Port #4 + 23e0 DH895XCC Series Watchdog Timer + 23e4 DH895XCC Series MEI Controller #1 + 23e5 DH895XCC Series MEI Controller #2 2410 82801AA ISA Bridge (LPC) 2411 82801AA IDE Controller 2412 82801AA USB Controller @@ -17575,6 +22326,7 @@ 11d4 0048 SoundMAX Integrated Digital Audio 11d4 5340 SoundMAX Integrated Digital Audio 1734 1025 Activy 3xx + 1af4 1100 QEMU Virtual Machine 2416 82801AA AC'97 Modem Controller 2418 82801AA PCI Bridge 2420 82801AB ISA Bridge (LPC) @@ -17588,7 +22340,7 @@ 2428 82801AB PCI Bridge 2440 82801BA ISA Bridge (LPC) 8086 5744 S845WD1-E - 2442 82801BA/BAM USB Controller #1 + 2442 82801BA/BAM UHCI USB 1.1 Controller #1 1014 01c6 Netvista A40/A40p 1025 1016 Travelmate 612 TX 1028 00c7 Dimension 8100 @@ -17597,6 +22349,7 @@ 103c 126f e-pc 40 1043 8027 TUSL2-C Mainboard 104d 80df Vaio PCG-FX403 + 147b 0505 BL7 motherboard 147b 0507 TH7II-RAID 8086 4532 D815EEA2 mainboard 8086 4557 D815EGEW Mainboard @@ -17610,12 +22363,13 @@ 103c 126f e-pc 40 1043 8027 TUSL2-C Mainboard 104d 80df Vaio PCG-FX403 + 147b 0505 BL7 motherboard 147b 0507 TH7II-RAID 15d9 3280 Supermicro P4SBE Mainboard 8086 4532 D815EEA2 mainboard 8086 4557 D815EGEW Mainboard 8086 5744 S845WD1-E mainboard - 2444 82801BA/BAM USB Controller #1 + 2444 82801BA/BAM UHCI USB 1.1 Controller #2 1025 1016 Travelmate 612 TX 1028 00c7 Dimension 8100 1028 00d8 Precision 530 @@ -17623,6 +22377,7 @@ 103c 126f e-pc 40 1043 8027 TUSL2-C Mainboard 104d 80df Vaio PCG-FX403 + 147b 0505 BL7 motherboard 147b 0507 TH7II-RAID 8086 4532 D815EEA2 mainboard 8086 5744 S845WD1-E mainboard @@ -17635,6 +22390,7 @@ 103c 126f e-pc 40 104d 80df Vaio PCG-FX403 1462 3370 STAC9721 AC + 147b 0505 BL7 motherboard 147b 0507 TH7II-RAID 8086 4557 D815EGEW Mainboard 2446 82801BA/BAM AC'97 Modem Controller @@ -17648,10 +22404,17 @@ 103c 30a3 Compaq nw8440 103c 30c1 Compaq 6910p 104d 902d VAIO VGN-NR120E + 105b 0d7c D270S/D250S Motherboard + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 144d c00c P30 notebook + 144d c06a R730 Laptop 144d c072 Notebook N150P + 1458 5000 GA-D525TUD 1734 1055 Amilo M1420 - 17aa 20ae ThinkPad T61 + 17aa 20ae ThinkPad T61/R61 + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] + 8086 544b Desktop Board D425KT e4bf cc47 CCG-RUMBA 2449 82801BA/BAM/CA/CAM Ethernet Controller 0e11 0012 EtherExpress PRO/100 VM @@ -17675,6 +22438,7 @@ 1179 ff01 PRO/100 VE Network Connection 1186 7801 EtherExpress PRO/100 VE 144d 2602 HomePNA 1M CNR + 1af4 1100 QEMU Virtual Machine 8086 3010 EtherExpress PRO/100 VE 8086 3011 EtherExpress PRO/100 VM 8086 3012 82562EH based Phoneline @@ -17694,6 +22458,7 @@ 1028 010e Optiplex GX240 103c 126f e-pc 40 1043 8027 TUSL2-C Mainboard + 147b 0505 BL7 motherboard 147b 0507 TH7II-RAID 15d9 3280 Supermicro P4SBE Mainboard 8086 4532 D815EEA2 mainboard @@ -17706,9 +22471,18 @@ 1028 0211 Optiplex 755 1028 02da OptiPlex 980 103c 2a3b Pavilion A1512X + 103c 2a6f Asus IPIBL-LB Motherboard + 103c 31fe ProLiant DL140 G3 103c 330b ProLiant ML150 G6 Server - 1458 5000 GA-EP45-DS5 Motherboard +# same ID possibly also on other ASUS boards + 1043 8277 P5K PRO Motherboard + 1043 844d P8 series motherboard + 1458 5000 Motherboard + 1462 7418 Wind PC MS-7418 + 15d9 060d C7SIM-Q Motherboard + 15d9 9680 X7DBN Motherboard 1775 11cc CC11/CL11 + 8086 7270 Server Board S1200BTS 2450 82801E ISA Bridge (LPC) 2452 82801E USB Controller 2453 82801E SMBus Controller @@ -17779,6 +22553,7 @@ 1014 0267 NetVista A30p 1014 052d ThinkPad 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 0126 Optiplex GX260 1028 0163 Latitude D505 1028 018d Inspiron 700m/710m @@ -17804,6 +22579,7 @@ 1014 0267 NetVista A30p 1014 052d ThinkPad 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 0126 Optiplex GX260 1028 014f Latitude X300 1028 018d Inspiron 700m/710m @@ -17825,6 +22601,7 @@ 1014 0267 NetVista A30p 1014 052d ThinkPad 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 0126 Optiplex GX260 1028 0163 Latitude D505 1028 018d Inspiron 700m/710m @@ -17846,9 +22623,10 @@ 24c5 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller 0e11 00b8 Analog Devices Inc. codec [SoundMAX] 1014 0267 NetVista A30p - 1014 0537 ThinkPad T41 + 1014 0537 ThinkPad T4x Series 1014 055f Thinkpad R50e model 1634 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 0139 Latitude D400 1028 014f Latitude X300 1028 0152 Latitude D500 @@ -17858,7 +22636,7 @@ 103c 088c NC8000 laptop 103c 0890 NC6000 laptop 103c 08b0 tc1100 tablet - 1043 1713 M6800N + 1043 1713 M2400N/M6800N laptop 1043 80b0 P4B533 1071 8160 MIM2000 1179 0201 Toshiba Tecra M1 @@ -17870,15 +22648,17 @@ 1734 1055 Amilo M1420 8086 24c5 Dell Dimension 2400 24c6 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller - 1014 0524 ThinkPad T41 + 1014 0524 ThinkPad T4x Series 1014 0525 ThinkPad 1014 0559 ThinkPad R50e 1025 003c Aspire 2001WLCi (Compal CL50 motherboard) implementation 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 0196 Inspiron 5160 103c 088c NC8000 laptop 103c 0890 NC6000 laptop 103c 08b0 tc1100 tablet + 1043 1716 M2400N laptop 1043 1826 M6800N 1071 8160 MIM2000 134d 4c21 Latitude D500 @@ -17890,6 +22670,7 @@ 1014 0267 NetVista A30p 1014 052d ThinkPad 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 0126 Optiplex GX260 1028 0163 Latitude D505 1028 018d Inspiron 700m/710m @@ -17911,6 +22692,7 @@ 24ca 82801DBM (ICH4-M) IDE Controller 1014 052d ThinkPad 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 014f Latitude X300 1028 0163 Latitude D505 1028 018d Inspiron 700m/710m @@ -17941,6 +22723,7 @@ 1014 0267 NetVista A30p 1014 052e ThinkPad 1025 005a TravelMate 290 + 1025 0064 Extensa 3000 series laptop: Intel 82801DBM (ICH4-M) 1028 011d Latitude D600 1028 0126 Optiplex GX260 1028 0139 Latitude D400 @@ -17961,15 +22744,18 @@ 1509 1968 Averatec 5110H 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) 1734 1055 Amilo M1420 + 1af4 1100 QEMU Virtual Machine 4c53 1090 Cx9 / Vx9 mainboard 8086 24c2 Latitude X300 e4bf 0cc9 CC9-SAMBA e4bf 0cd2 CD2-BEBOP 24d0 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge 24d1 82801EB (ICH5) SATA Controller + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 1028 019a PowerEdge SC1425 103c 12bc d530 CMT (DG746A) + 103c 3208 ProLiant DL140 G2 1043 80a6 P4P800 series motherboard 1458 24d1 GA-8IPE1000 Pro2 motherboard (865PE) 1462 7280 865PE Neo2 (MS-6728) @@ -17983,6 +22769,7 @@ 24d2 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 1014 02dd eServer xSeries server mainboard 1014 02ed eServer xSeries server mainboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 1028 016c PowerEdge 1850 onboard UHCI 1028 016d PowerEdge 2850 onboard UHCI @@ -17991,6 +22778,7 @@ 1028 019a PowerEdge SC1425 103c 006a NX9500 103c 12bc d530 CMT (DG746A) + 103c 3208 ProLiant DL140 G2 1043 80a6 P4P800/P5P800 series motherboard 1458 24d2 GA-8IPE1000/8KNXP motherboard 1462 7280 865PE Neo2 (MS-6728) @@ -18005,8 +22793,10 @@ 1014 02dd eServer xSeries server mainboard 1014 02ed eServer xSeries server mainboard 1028 0156 Precision 360 + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 103c 12bc d330 uT + 103c 3208 ProLiant DL140 G2 1043 80a6 P4P800/P5P800 series motherboard 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) 1462 7280 865PE Neo2 (MS-6728) @@ -18021,6 +22811,7 @@ 24d4 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 1014 02dd eServer xSeries server mainboard 1014 02ed eServer xSeries server mainboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 1028 016c PowerEdge 1850 onboard UHCI 1028 016d PowerEdge 2850 onboard UHCI @@ -18029,6 +22820,7 @@ 1028 019a PowerEdge SC1425 103c 006a NX9500 103c 12bc d530 CMT (DG746A) + 103c 3208 ProLiant DL140 G2 1043 80a6 P4P800/P5P800 series motherboard 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) 1462 7280 865PE Neo2 (MS-6728) @@ -18042,6 +22834,7 @@ 8086 524c D865PERL mainboard 24d5 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller 100a 147b Abit IS7-E motherboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 103c 006a NX9500 103c 12bc d330 uT @@ -18059,6 +22852,7 @@ 103c 006a NX9500 24d7 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 1014 02ed xSeries server mainboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 1028 016c PowerEdge 1850 onboard UHCI 1028 016d PowerEdge 2850 onboard UHCI @@ -18080,6 +22874,7 @@ 24db 82801EB/ER (ICH5/ICH5R) IDE Controller 1014 02dd eServer xSeries server mainboard 1014 02ed eServer xSeries server mainboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 1028 016c PowerEdge 1850 IDE Controller 1028 016d PowerEdge 2850 IDE Controller @@ -18104,6 +22899,7 @@ 24dd 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller 1014 02dd eServer xSeries server mainboard 1014 02ed eServer xSeries server mainboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 1028 016c PowerEdge 1850 onboard EHCI 1028 016d PowerEdge 2850 onboard EHCI @@ -18112,6 +22908,7 @@ 1028 019a PowerEdge SC1425 103c 006a NX9500 103c 12bc d530 CMT (DG746A) + 103c 3208 ProLiant DL140 G2 1043 80a6 P4P800/P5P800 series motherboard 1458 5006 GA-8IPE1000 Pro2 motherboard (865PE) 1462 7280 865PE Neo2 (MS-6728) @@ -18122,6 +22919,7 @@ 8086 524c D865PERL mainboard 24de 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 1014 02ed xSeries server mainboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 1043 80a6 P4P800/P5P800 series motherboard 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) @@ -18135,6 +22933,15 @@ 8086 4c43 Desktop Board D865GLC 8086 524c D865PERL mainboard 24df 82801ER (ICH5R) SATA Controller + 1028 0168 Precision Workstation 670 Mainboard + 24f0 Omni-Path HFI Silicon 100 Series [discrete] + 24f1 Omni-Path HFI Silicon 100 Series [integrated] + 24f3 Wireless 8260 +# Snow Field Peak AC + 8086 0010 Dual Band Wireless-AC 8260 + 24f4 Wireless 8260 +# Snow Field Peak AC + 8086 0030 Dual Band Wireless-AC 8260 2500 82820 820 (Camino) Chipset Host Bridge (MCH) 1028 0095 Precision Workstation 220 Chipset 1043 801c P3C-2000 system chipset @@ -18246,18 +23053,21 @@ e4bf 58b1 XB1 25a1 6300ESB LPC Interface Controller 25a2 6300ESB PATA Storage Controller + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 10d0 V5D Single Board Computer IDE 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 4c53 10b0 CL9 mainboard 4c53 10e0 PSL09 PrPMC 25a3 6300ESB SATA Storage Controller + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 4c53 10b0 CL9 mainboard 4c53 10d0 Telum ASLP10 Processor AMC 4c53 10e0 PSL09 PrPMC 25a4 6300ESB SMBus Controller + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 10d0 V5D Single Board Computer 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 @@ -18270,6 +23080,7 @@ 4c53 10b0 CL9 mainboard 25a7 6300ESB AC'97 Modem Controller 25a9 6300ESB USB Universal Host Controller + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 10d0 V5D Single Board Computer USB 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 @@ -18277,19 +23088,23 @@ 4c53 10d0 Telum ASLP10 Processor AMC 4c53 10e0 PSL09 PrPMC 25aa 6300ESB USB Universal Host Controller + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 4c53 10b0 CL9 mainboard 4c53 10d0 Telum ASLP10 Processor AMC 4c53 10e0 PSL09 PrPMC 25ab 6300ESB Watchdog Timer + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 10d0 V5D Single Board Computer 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 + 1af4 1100 QEMU Virtual Machine 4c53 10b0 CL9 mainboard 4c53 10d0 Telum ASLP10 Processor AMC 4c53 10e0 PSL09 PrPMC 25ac 6300ESB I/O Advanced Programmable Interrupt Controller + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 10d0 V5D Single Board Computer 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 @@ -18297,6 +23112,7 @@ 4c53 10d0 Telum ASLP10 Processor AMC 4c53 10e0 PSL09 PrPMC 25ad 6300ESB USB2 Enhanced Host Controller + 1734 1073 Primergy Econel 200 D2020 mainboard 1775 10d0 V5D Single Board Computer USB 2.0 1775 1100 CR11/VR11 Single Board Computer 1775 ce90 CE9 @@ -18313,7 +23129,8 @@ 25d4 5000V Chipset Memory Controller Hub 15d9 8680 X7DVL-E-O motherboard 25d8 5000P Chipset Memory Controller Hub - 8086 3476 Intel S5000PSLSATA Server Board + 15d9 9680 X7DBN Motherboard + 8086 3476 S5000PSLSATA Server Board 25e2 5000 Series Chipset PCI Express x4 Port 2 25e3 5000 Series Chipset PCI Express x4 Port 3 25e4 5000 Series Chipset PCI Express x4 Port 4 @@ -18322,20 +23139,30 @@ 25e7 5000 Series Chipset PCI Express x4 Port 7 25f0 5000 Series Chipset FSB Registers 1028 01bb PowerEdge 1955 FSB Registers + 103c 31fd ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard - 8086 3476 Intel S5000PSLSATA Server Board + 15d9 9680 X7DBN Motherboard + 8086 3476 S5000PSLSATA Server Board 25f1 5000 Series Chipset Reserved Registers + 103c 31fd ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard - 8086 3476 Intel S5000PSLSATA Server Board + 15d9 9680 X7DBN Motherboard + 8086 3476 S5000PSLSATA Server Board 25f3 5000 Series Chipset Reserved Registers + 103c 31fd ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard - 8086 3476 Intel S5000PSLSATA Server Board + 15d9 9680 X7DBN Motherboard + 8086 3476 S5000PSLSATA Server Board 25f5 5000 Series Chipset FBD Registers + 103c 31fd ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard - 8086 3476 Intel S5000PSLSATA Server Board + 15d9 9680 X7DBN Motherboard + 8086 3476 S5000PSLSATA Server Board 25f6 5000 Series Chipset FBD Registers + 103c 31fd ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard - 8086 3476 Intel S5000PSLSATA Server Board + 15d9 9680 X7DBN Motherboard + 8086 3476 S5000PSLSATA Server Board 25f7 5000 Series Chipset PCI Express x8 Port 2-3 25f8 5000 Series Chipset PCI Express x8 Port 4-5 25f9 5000 Series Chipset PCI Express x8 Port 6-7 @@ -18491,6 +23318,7 @@ 1043 1173 Asus A6VC 1043 814e P5GD1-VW Mainboard 1462 7028 915P/G Neo2 + 1af4 1100 QEMU Virtual Machine 266a 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller 1028 0177 Dimension 8400 1028 0179 Optiplex GX280 @@ -18532,11 +23360,15 @@ e4bf 0cd3 CD3-JIVE e4bf 58b1 XB1 2670 631xESB/632xESB/3100 Chipset LPC Interface Controller + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 Intel S5000PSLSATA Server Board 2680 631xESB/632xESB/3100 Chipset SATA IDE Controller 2681 631xESB/632xESB SATA AHCI Controller + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 Intel S5000PSLSATA Server Board 2682 631xESB/632xESB SATA RAID Controller 103c 31fe Adaptec Serial ATA HostRAID @@ -18544,16 +23376,22 @@ 2688 631xESB/632xESB/3100 Chipset UHCI USB Controller #1 1028 01bb PowerEdge 1955 onboard USB 1028 01f0 PowerEdge R900 onboard USB + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 Intel S5000PSLSATA Server Board 2689 631xESB/632xESB/3100 Chipset UHCI USB Controller #2 1028 01bb PowerEdge 1955 onboard USB 1028 01f0 PowerEdge R900 onboard USB + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 Intel S5000PSLSATA Server Board 268a 631xESB/632xESB/3100 Chipset UHCI USB Controller #3 1028 01f0 PowerEdge R900 onboard USB + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 Intel S5000PSLSATA Server Board 268b 631xESB/632xESB/3100 Chipset UHCI USB Controller #4 1028 01f0 PowerEdge R900 onboard USB @@ -18562,29 +23400,40 @@ 268c 631xESB/632xESB/3100 Chipset EHCI USB2 Controller 1028 01bb PowerEdge 1955 onboard USB 1028 01f0 PowerEdge R900 onboard USB + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 Intel S5000PSLSATA Server Board 2690 631xESB/632xESB/3100 Chipset PCI Express Root Port 1 + 103c 31fe ProLiant DL140 G3 + 15d9 9680 X7DBN Motherboard 2692 631xESB/632xESB/3100 Chipset PCI Express Root Port 2 + 103c 31fe ProLiant DL140 G3 2694 631xESB/632xESB/3100 Chipset PCI Express Root Port 3 2696 631xESB/632xESB/3100 Chipset PCI Express Root Port 4 2698 631xESB/632xESB AC '97 Audio Controller 2699 631xESB/632xESB AC '97 Modem Controller 269a 631xESB/632xESB High Definition Audio Controller 269b 631xESB/632xESB/3100 Chipset SMBus Controller + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 8086 3476 Intel S5000PSLSATA Server Board 269e 631xESB/632xESB IDE Controller + 103c 31fe ProLiant DL140 G3 15d9 8680 X7DVL-E-O motherboard + 15d9 9680 X7DBN Motherboard 2770 82945G/GZ/P/PL Memory Controller Hub 1028 01ad OptiPlex GX620 103c 2a3b Pavilion A1512X 1043 817a P5LD2-VM Mainboard 107b 5048 E4500 + 1462 7418 Wind PC MS-7418 8086 544e DeskTop Board D945GTP 2771 82945G/GZ/P/PL PCI Express Root Port 2772 82945G/GZ Integrated Graphics Controller 103c 2a3b Pavilion A1512X + 1462 7418 Wind PC MS-7418 8086 544e DeskTop Board D945GTP 8086 d605 Intel Desktop Board D945GCCR 2774 82955X Memory Controller Hub @@ -18614,19 +23463,21 @@ 103c 30a1 NC2400 103c 30a3 Compaq nw8440 1043 1237 A6J-Q008 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 17aa 2015 ThinkPad T60 - 17aa 2017 ThinkPad T60/R60 series + 17aa 2017 ThinkPad R60/T60/X60 series 27a1 Mobile 945GM/PM/GMS, 943/940GML and 945GT Express PCI Express Root Port 103c 309f Compaq nx9420 Notebook 103c 30a3 Compaq nw8440 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 27a2 Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller 103c 30a1 NC2400 - 17aa 201a ThinkPad T60/R60 series + 17aa 201a ThinkPad R60/T60/X60 series 9902 1584 CCE MPL-D10H120F 27a6 Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller 103c 30a1 NC2400 1775 11cc CC11/CL11 integrated graphics (secondary) - 17aa 201a ThinkPad T60/R60 series + 17aa 201a ThinkPad R60/T60/X60 series 27ac Mobile 945GSE Express Memory Controller Hub 1775 11cc CC11/CL11 27ad Mobile 945GSE Express PCI Express Root Port @@ -18639,6 +23490,7 @@ 1028 01e6 PowerEdge 860 1043 8179 P5KPL-VM Motherboard 107b 5048 E4500 + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 8086 544e DeskTop Board D945GTP 27b9 82801GBM (ICH7-M) LPC Interface Bridge @@ -18646,11 +23498,15 @@ 103c 309f Compaq nx9420 Notebook 103c 30a1 NC2400 103c 30a3 Compaq nw8440 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 10f7 8338 Panasonic CF-Y5 laptop - 17aa 2009 ThinkPad T60/R60 series + 17aa 2009 ThinkPad R60/T60/X60 series 27bc NM10 Family LPC Controller + 105b 0d7c D270S/D250S Motherboard 144d c072 Notebook N150P + 1458 5001 GA-D525TUD 8086 4f4d DeskTop Board D510MO + 8086 544b Desktop Board D425KT 27bd 82801GHM (ICH7-M DH) LPC Interface Bridge 1025 006c 9814 WKMI 27c0 NM10/ICH7 Family SATA Controller [IDE mode] @@ -18661,12 +23517,16 @@ 107b 5048 E4500 1462 2310 MSI Hetis 945 1462 7236 945P Neo3-F Rev. 2.2 motherboard + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 + 8086 544b Desktop Board D425KT 8086 544e DeskTop Board D945GTP 27c1 NM10/ICH7 Family SATA Controller [AHCI mode] 1028 01df PowerEdge SC440 103c 2a3b Pavilion A1512X + 105b 0d7c D270S/D250S Motherboard 144d c072 Notebook N150P + 1458 b005 GA-D525TUD 1775 11cc CC11/CL11 8086 4f4d DeskTop Board D510MO 8086 5842 DeskTop Board D975XBX @@ -18676,11 +23536,12 @@ 27c4 82801GBM/GHM (ICH7-M Family) SATA Controller [IDE mode] 1025 006c 9814 WKMI 1028 01d7 XPS M1210 - 17aa 200e Thinkpad T60 model 2007 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] + 17aa 200e ThinkPad T60 27c5 82801GBM/GHM (ICH7-M Family) SATA Controller [AHCI mode] 103c 309f Compaq nx9420 Notebook 103c 30a3 Compaq nw8440 - 17aa 200d ThinkPad T60/R60 series + 17aa 200d ThinkPad R60/T60/X60 series 27c6 82801GHM (ICH7-M DH) SATA Controller [RAID mode] 27c8 NM10/ICH7 Family USB UHCI Controller #1 1025 006c 9814 WKMI @@ -18694,11 +23555,16 @@ 103c 30a3 Compaq nw8440 1043 1237 A6J-Q008 1043 8179 P5KPL-VM,P5LD2-VM Mainboard + 105b 0d7c D270S/D250S Motherboard + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 107b 5048 E4500 144d c072 Notebook N150P + 1458 5004 GA-D525TUD + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 - 17aa 200a ThinkPad T60/R60 series + 17aa 200a ThinkPad R60/T60/X60 series 8086 4f4d DeskTop Board D510MO + 8086 544b Desktop Board D425KT 8086 544e DeskTop Board D945GTP 27c9 NM10/ICH7 Family USB UHCI Controller #2 1025 006c 9814 WKMI @@ -18712,11 +23578,16 @@ 103c 30a3 Compaq nw8440 1043 1237 A6J-Q008 1043 8179 P5KPL-VM,P5LD2-VM Mainboard + 105b 0d7c D270S/D250S Motherboard + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 107b 5048 E4500 144d c072 Notebook N150P + 1458 5004 GA-D525TUD + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 - 17aa 200a ThinkPad T60/R60 series + 17aa 200a ThinkPad R60/T60/X60 series 8086 4f4d DeskTop Board D510MO + 8086 544b Desktop Board D425KT 8086 544e DeskTop Board D945GTP 27ca NM10/ICH7 Family USB UHCI Controller #3 1025 006c 9814 WKMI @@ -18730,10 +23601,14 @@ 103c 30a3 Compaq nw8440 1043 1237 A6J-Q008 1043 8179 P5KPL-VM,P5LD2-VM Mainboard + 105b 0d7c D270S/D250S Motherboard + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 107b 5048 E4500 144d c072 Notebook N150P + 1458 5004 GA-D525TUD + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 - 17aa 200a ThinkPad T60/R60 series + 17aa 200a ThinkPad R60/T60/X60 series 8086 4f4d DeskTop Board D510MO 8086 544e DeskTop Board D945GTP 27cb NM10/ICH7 Family USB UHCI Controller #4 @@ -18747,10 +23622,14 @@ 103c 30a3 Compaq nw8440 1043 1237 A6J-Q008 1043 8179 P5KPL-VM,P5LD2-VM Mainboard + 105b 0d7c D270S/D250S Motherboard + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 107b 5048 E4500 144d c072 Notebook N150P + 1458 5004 GA-D525TUD + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 - 17aa 200a ThinkPad T60/R60 series + 17aa 200a ThinkPad R60/T60/X60 series 8086 4f4d DeskTop Board D510MO 8086 544e DeskTop Board D945GTP 27cc NM10/ICH7 Family USB2 EHCI Controller @@ -18765,28 +23644,46 @@ 103c 30a3 Compaq nw8440 1043 1237 A6J-Q008 1043 8179 P5KPL-VM,P5LD2-VM Mainboard + 105b 0d7c D270S/D250S Motherboard + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 144d c072 Notebook N150P + 1458 5006 GA-D525TUD + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 - 17aa 200b ThinkPad T60/R60 series + 17aa 200b ThinkPad R60/T60/X60 series 8086 4f4d DeskTop Board D510MO + 8086 544b Desktop Board D425KT 8086 544e DeskTop Board D945GTP 27d0 NM10/ICH7 Family PCI Express Port 1 103c 309f Compaq nx9420 Notebook 103c 30a3 Compaq nw8440 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 144d c072 Notebook N150P + 1458 5001 GA-D525TUD + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 + 8086 544b Desktop Board D425KT 27d2 NM10/ICH7 Family PCI Express Port 2 103c 309f Compaq nx9420 Notebook 103c 30a3 Compaq nw8440 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 144d c072 Notebook N150P + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 + 8086 544b Desktop Board D425KT 27d4 NM10/ICH7 Family PCI Express Port 3 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 144d c072 Notebook N150P + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 + 8086 544b Desktop Board D425KT 27d6 NM10/ICH7 Family PCI Express Port 4 103c 30a3 Compaq nw8440 + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 144d c072 Notebook N150P + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 + 8086 544b Desktop Board D425KT 27d8 NM10/ICH7 Family High Definition Audio Controller 1025 006c 9814 WKMI 1028 01d7 XPS M1210 @@ -18799,16 +23696,20 @@ 1043 817f P5LD2-VM Mainboard (Realtek ALC 882 codec) 1043 8290 P5KPL-VM Motherboard 1043 82ea P5KPL-CM Motherboard + 105b 0d7c D270S/D250S Motherboard + 1071 8207 Medion MIM 2240 Notebook PC [MD98100] 107b 5048 E4500 10f7 8338 Panasonic CF-Y5 laptop 1179 ff10 Toshiba Satellite A100-796 audio (Realtek ALC861) 1179 ff31 AC97 Data Fax SoftModem with SmartCP 1447 1043 Asus A8JP (Analog Devices AD1986A) 144d c072 Notebook N150P + 1458 a002 GA-D525TUD (Realtek ALC887) 1458 a102 GA-8I945PG-RH Mainboard + 1462 7418 Wind PC MS-7418 152d 0753 Softmodem 1734 10ad Conexant softmodem SmartCP - 17aa 2010 ThinkPad T60/R60 series + 17aa 2010 ThinkPad R60/T60/X60 series 17aa 3802 Lenovo 3000 C200 audio [Realtek ALC861VD] 8086 1112 DeskTop Board D945GTP 8086 27d8 DeskTop Board D945GTP @@ -18822,12 +23723,16 @@ 1028 01e6 PowerEdge 860 103c 2a3b Pavilion A1512X 1043 8179 P5KPL-VM Motherboard + 105b 0d7c D270S/D250S Motherboard + 1071 8209 Medion MIM 2240 Notebook PC [MD98100] 10f7 8338 Panasonic CF-Y5 laptop 144d c072 Notebook N150P - 1458 5001 GA-8I945PG-RH Mainboard + 1458 5001 GA-8I945PG-RH/GA-D525TUD Mainboard + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 - 17aa 200f ThinkPad T60/R60 series + 17aa 200f ThinkPad R60/T60/X60 series 8086 4f4d DeskTop Board D510MO + 8086 544b Desktop Board D425KT 8086 544e DeskTop Board D945GTP 8086 5842 DeskTop Board D975XBX 27dc NM10/ICH7 Family LAN Controller @@ -18849,19 +23754,19 @@ 1043 8179 P5KPL-VM Motherboard 107b 5048 E4500 10f7 8338 Panasonic CF-Y5 laptop + 1462 7418 Wind PC MS-7418 1775 11cc CC11/CL11 - 17aa 200c ThinkPad T60/R60 series + 17aa 200c ThinkPad R60/T60/X60 series 8086 544e DeskTop Board D945GTP 27e0 82801GR/GH/GHM (ICH7 Family) PCI Express Port 5 1775 11cc CC11/CL11 27e2 82801GR/GH/GHM (ICH7 Family) PCI Express Port 6 1775 11cc CC11/CL11 - 2802 82GL40 [Cantiga] High Definition Audio HDMI Service 2810 82801HB/HR (ICH8/R) LPC Interface Controller 1043 81ec P5B 2811 82801HEM (ICH8M-E) LPC Interface Controller 103c 30c1 Compaq 6910p - 17aa 20b6 T61 + 17aa 20b6 ThinkPad T61/R61 e4bf cc47 CCG-RUMBA 2812 82801HH (ICH8DH) LPC Interface Controller 2814 82801HO (ICH8DO) LPC Interface Controller @@ -18873,18 +23778,23 @@ 103c 30d9 Presario C700 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] 2820 82801H (ICH8 Family) 4 port SATA Controller [IDE mode] 1028 01da OptiPlex 745 1462 7235 P965 Neo MS-7235 mainboard 2821 82801HR/HO/HH (ICH8R/DO/DH) 6 port SATA Controller [AHCI mode] - 2822 82801 SATA Controller [RAID mode] + 2822 SATA Controller [RAID mode] 1028 020d Inspiron 530 + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard + 2823 C610/X99 series chipset sSATA Controller [RAID mode] 2824 82801HB (ICH8) 4 port SATA Controller [AHCI mode] 1043 81ec P5B 2825 82801HR/HO/HH (ICH8R/DO/DH) 2 port SATA Controller [IDE mode] 1028 01da OptiPlex 745 1462 7235 P965 Neo MS-7235 mainboard 2826 C600/X79 series chipset SATA RAID Controller + 2827 C610/X99 series chipset sSATA Controller [RAID mode] 2828 82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [IDE mode] 1028 01f3 Inspiron 1420 103c 30c0 Compaq 6710b @@ -18897,7 +23807,8 @@ 103c 30d9 Presario C700 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E - 17aa 20a7 ThinkPad T61 + 17aa 20a7 ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 282a 82801 Mobile SATA Controller [RAID mode] 1028 040b Latitude E6510 @@ -18914,7 +23825,8 @@ 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E 1462 7235 P965 Neo MS-7235 mainboard - 17aa 20aa ThinkPad T61 + 17aa 20aa ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2831 82801H (ICH8 Family) USB UHCI Controller #2 1025 0121 Aspire 5920G @@ -18928,7 +23840,8 @@ 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E 1462 7235 P965 Neo MS-7235 mainboard - 17aa 20aa ThinkPad T61 + 17aa 20aa ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2832 82801H (ICH8 Family) USB UHCI Controller #3 1025 0121 Aspire 5920G @@ -18941,7 +23854,8 @@ 1043 81ec P5B 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E - 17aa 20aa ThinkPad T61 + 17aa 20aa ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2833 82801H (ICH8 Family) USB UHCI Controller #4 1043 81ec P5B @@ -18956,7 +23870,8 @@ 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E 1462 7235 P965 Neo MS-7235 mainboard - 17aa 20aa ThinkPad T61 + 17aa 20aa ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2835 82801H (ICH8 Family) USB UHCI Controller #5 1025 0121 Acer Aspire 5920G @@ -18968,7 +23883,8 @@ 1043 81ec P5B 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E - 17aa 20aa ThinkPad T60 + 17aa 20aa Thinkpad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2836 82801H (ICH8 Family) USB2 EHCI Controller #1 1025 0121 Aspire 5920G @@ -18982,7 +23898,8 @@ 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E 1462 7235 P965 Neo MS-7235 mainboard - 17aa 20ab ThinkPad T61 + 17aa 20ab ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 283a 82801H (ICH8 Family) USB2 EHCI Controller #2 1025 0121 Acer Aspire 5920G @@ -18994,7 +23911,8 @@ 1043 81ec P5B 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E - 17aa 20ab ThinkPad T61 + 17aa 20ab ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 283e 82801H (ICH8 Family) SMBus Controller 1025 0121 Aspire 5920G @@ -19006,26 +23924,32 @@ 104d 9008 Vaio VGN-SZ79SN_C 104d 902d VAIO VGN-NR120E 1462 7235 P965 Neo MS-7235 mainboard - 17aa 20a9 ThinkPad T61 + 17aa 20a9 ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 283f 82801H (ICH8 Family) PCI Express Port 1 1028 01da OptiPlex 745 103c 30c1 Compaq 6910p 104d 902d VAIO VGN-NR120E - 17aa 20ad ThinkPad T61 + 17aa 20ad ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] 2841 82801H (ICH8 Family) PCI Express Port 2 103c 30c1 Compaq 6910p 104d 902d VAIO VGN-NR120E - 17aa 20ad ThinkPad T61 + 17aa 20ad ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] 2843 82801H (ICH8 Family) PCI Express Port 3 104d 902d VAIO VGN-NR120E - 17aa 20ad ThinkPad T61 + 17aa 20ad ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] 2845 82801H (ICH8 Family) PCI Express Port 4 - 17aa 20ad ThinkPad T61 + 17aa 20ad ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] 2847 82801H (ICH8 Family) PCI Express Port 5 1028 01da OptiPlex 745 103c 30c1 Compaq 6910p - 17aa 20ad ThinkPad T61 + 17aa 20ad ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] 2849 82801H (ICH8 Family) PCI Express Port 6 284b 82801H (ICH8 Family) HD Audio Controller 1025 011f Realtek ALC268 audio codec @@ -19047,7 +23971,8 @@ 104d 9016 Sony VAIO VGN-AR51M 104d 902d VAIO VGN-NR120E 14f1 5051 Presario C700 - 17aa 20ac ThinkPad T61 + 17aa 20ac ThinkPad T61/R61 + 17c0 4088 Medion WIM 2210 Notebook PC [MD96850] 8384 7616 Dell Vostro 1400 e4bf cc47 CCG-RUMBA 284f 82801H (ICH8 Family) Thermal Reporting Device @@ -19060,19 +23985,23 @@ 103c 30d9 Presario C700 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E - 17aa 20a6 ThinkPad T61 + 17aa 20a6 ThinkPad T61/R61 + 17c0 4083 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2912 82801IH (ICH9DH) LPC Interface Controller 2914 82801IO (ICH9DO) LPC Interface Controller 1028 0211 Optiplex 755 2916 82801IR (ICH9R) LPC Interface Controller 1028 020d Inspiron 530 + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 8086 5044 Desktop Board DP35DP 2917 ICH9M-E LPC Interface Controller e4bf cc4d CCM-BOOGIE 2918 82801IB (ICH9) LPC Interface Controller 1028 0236 PowerEdge R610 82801IB (ICH9) LPC Interface Controller 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 2919 ICH9M LPC Interface Controller 2920 82801IR/IO/IH (ICH9R/DO/DH) 4 port SATA Controller [IDE mode] 1028 020d Inspiron 530 @@ -19080,12 +24009,15 @@ 1028 0210 PowerEdge T300 onboard SATA Controller 1028 0211 Optiplex 755 1028 023c PowerEdge R200 onboard SATA Controller + 1043 8277 P5K PRO Motherboard 2921 82801IB (ICH9) 2 port SATA Controller [IDE mode] 1028 0235 PowerEdge R710 SATA IDE Controller 1028 0236 PowerEdge R610 SATA IDE Controller 1028 0237 PowerEdge T610 SATA IDE Controller 1462 7360 G33/P35 Neo 2922 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA Controller [AHCI mode] + 1043 8277 P5K PRO Motherboard + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP 2923 82801IB (ICH9) 4 port SATA Controller [AHCI mode] 2925 82801IR/IO (ICH9R/DO) SATA Controller [RAID mode] @@ -19096,6 +24028,7 @@ 1028 020f PowerEdge R300 onboard SATA Controller 1028 0210 PowerEdge T300 onboard SATA Controller 1028 0211 Optiplex 755 + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo 2928 82801IBM/IEM (ICH9M/ICH9M-E) 2 port SATA Controller [IDE mode] 2929 82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller [AHCI mode] @@ -19107,8 +24040,11 @@ 2930 82801I (ICH9 Family) SMBus Controller 1028 020d Inspiron 530 1028 0211 Optiplex 755 + 103c 2a6f Asus IPIBL-LB Motherboard 103c 3628 dv6-1190en + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE 2932 82801I (ICH9 Family) Thermal Subsystem @@ -19125,7 +24061,10 @@ 1028 0287 PowerEdge M610 onboard UHCI 1028 029c PowerEdge M710 USB UHCI Controller 1028 2011 Optiplex 755 + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE 2935 82801I (ICH9 Family) USB UHCI Controller #2 @@ -19139,7 +24078,10 @@ 1028 023c PowerEdge R200 onboard UHCI 1028 0287 PowerEdge M610 onboard UHCI 1028 029c PowerEdge M710 USB UHCI Controller + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE 2936 82801I (ICH9 Family) USB UHCI Controller #3 @@ -19151,7 +24093,10 @@ 1028 023c PowerEdge R200 onboard UHCI 1028 0287 PowerEdge M610 onboard UHCI 1028 029c PowerEdge M710 USB UHCI Controller + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE 2937 82801I (ICH9 Family) USB UHCI Controller #4 @@ -19163,7 +24108,10 @@ 1028 0287 PowerEdge M610 onboard UHCI 1028 029c PowerEdge M710 USB UHCI Controller 1028 2011 Optiplex 755 + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 2937 Optiplex 755 8086 2942 828011 (ICH9 Family ) USB UHCI Controller 8086 5044 Desktop Board DP35DP @@ -19176,7 +24124,10 @@ 1028 0237 PowerEdge T610 USB UHCI Controller 1028 0287 PowerEdge M610 onboard UHCI 1028 029c PowerEdge M710 USB UHCI Controller + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 2938 Optiplex 755 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE @@ -19184,7 +24135,10 @@ 1028 020d Inspiron 530 1028 0210 PowerEdge T300 onboard UHCI 1028 0237 PowerEdge T610 USB UHCI Controller + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE 293a 82801I (ICH9 Family) USB2 EHCI Controller #1 @@ -19198,7 +24152,10 @@ 1028 023c PowerEdge R200 onboard EHCI 1028 0287 PowerEdge M610 onboard EHCI 1028 029c PowerEdge M710 USB EHCI Controller + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE 293c 82801I (ICH9 Family) USB2 EHCI Controller #2 @@ -19209,32 +24166,46 @@ 1028 0237 PowerEdge T610 USB EHCI Controller 1028 0287 PowerEdge M610 onboard EHCI 1028 029c PowerEdge M710 USB EHCI Controller + 103c 2a6f Asus IPIBL-LB Motherboard + 1043 8277 P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 293c Optiplex 755 8086 5044 Desktop Board DP35DP e4bf cc4d CCM-BOOGIE 293e 82801I (ICH9 Family) HD Audio Controller 1028 020d Inspiron 530 1028 0211 Optiplex 755 + 103c 2a6f Asus IPIBL-LB Motherboard 103c 3628 dv6-1190en + 1043 829f P5K PRO Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 293e Optiplex 755 8086 2940 Optiplex 755 e4bf cc4d CCM-BOOGIE 2940 82801I (ICH9 Family) PCI Express Port 1 1028 020d Inspiron 530 1028 0211 Optiplex 755 + 103c 2a6f Asus IPIBL-LB Motherboard +# same ID possibly also on other ASUS boards + 1043 8277 P5K PRO Motherboard 8086 2940 Optiplex 755 2942 82801I (ICH9 Family) PCI Express Port 2 1028 020d Inspiron 530 2944 82801I (ICH9 Family) PCI Express Port 3 1028 020d Inspiron 530 + 103c 2a6f Asus IPIBL-LB Motherboard 2946 82801I (ICH9 Family) PCI Express Port 4 1028 020d Inspiron 530 2948 82801I (ICH9 Family) PCI Express Port 5 1028 020d Inspiron 530 +# same ID possibly also on other ASUS boards + 1043 8277 P5K PRO Motherboard 294a 82801I (ICH9 Family) PCI Express Port 6 1028 020d Inspiron 530 +# same ID possibly also on other ASUS boards + 1043 8277 P5K PRO Motherboard 294c 82566DC-2 Gigabit Network Connection 17aa 302e 82566DM-2 Gigabit Network Connection 2970 82946GZ/PL/GL Memory Controller Hub @@ -19287,11 +24258,17 @@ 1028 0211 OptiPlex 755 29c0 82G33/G31/P35/P31 Express DRAM Controller 1028 020d Inspiron 530 + 103c 2a6f Asus IPIBL-LB Motherboard +# same ID possibly also on other ASUS boards + 1043 8276 P5K PRO Motherboard 1043 82b0 P5KPL-VM Motherboard 1462 7360 G33/P35 Neo + 1af4 1100 QEMU Virtual Machine 8086 5044 Desktop Board DP35DP 29c1 82G33/G31/P35/P31 Express PCI Express Root Port 1028 020d Inspiron 530 +# same ID possibly also on other ASUS boards + 1043 8276 P5K PRO Motherboard 29c2 82G33/G31 Express Integrated Graphics Controller 1028 020d Inspiron 530 1043 82b0 P5KPL-VM Motherboard @@ -19336,7 +24313,8 @@ 104d 9005 Vaio VGN-FZ260E 104d 902d VAIO VGN-NR120E 17aa 20b1 ThinkPad T61 - 17aa 20b3 T61 + 17aa 20b3 ThinkPad T61/R61 + 17c0 4082 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2a01 Mobile PM965/GM965/GL960 PCI Express Root Port 2a02 Mobile GM965/GL960 Integrated Graphics Controller (primary) @@ -19345,14 +24323,16 @@ 103c 30c0 Compaq 6710b 103c 30d9 Presario C700 104d 902d VAIO VGN-NR120E - 17aa 20b5 T61 + 17aa 20b5 ThinkPad T61/R61 + 17c0 4082 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2a03 Mobile GM965/GL960 Integrated Graphics Controller (secondary) - 1028 01f3 Dell Inspiron 1420 + 1028 01f3 Inspiron 1420 103c 30c0 Compaq 6710b 103c 30d9 Presario C700 104d 902d VAIO VGN-NR120E - 17aa 20b5 T61 + 17aa 20b5 ThinkPad T61/R61 + 17c0 4082 Medion WIM 2210 Notebook PC [MD96850] e4bf cc47 CCG-RUMBA 2a04 Mobile PM965/GM965 MEI Controller 103c 30c1 Compaq 6910p @@ -19511,9 +24491,9 @@ 2cf3 Xeon C5500/C3500 Integrated Memory Controller Channel 2 Thermal Control 2d01 Core Processor QuickPath Architecture System Address Decoder 2d10 Core Processor QPI Link 0 - 2d11 Core Processor QPI Physical 0 - 2d12 Core Processor Reserved - 2d13 Core Processor Reserved + 2d11 1st Generation Core i3/5/7 Processor QPI Physical 0 + 2d12 1st Generation Core i3/5/7 Processor Reserved + 2d13 1st Generation Core i3/5/7 Processor Reserved 2d81 Xeon 5600 Series QuickPath Architecture System Address Decoder 2d90 Xeon 5600 Series QPI Link 0 2d91 Xeon 5600 Series QPI Physical 0 @@ -19548,12 +24528,14 @@ 2e10 4 Series Chipset DRAM Controller 2e11 4 Series Chipset PCI Express Root Port 2e12 4 Series Chipset Integrated Graphics Controller + 17aa 3048 ThinkCentre M6258 2e13 4 Series Chipset Integrated Graphics Controller 2e14 4 Series Chipset HECI Controller 2e15 4 Series Chipset HECI Controller 2e16 4 Series Chipset PT IDER Controller 2e17 4 Series Chipset Serial KT Controller 2e20 4 Series Chipset DRAM Controller + 1028 0283 Dell Vostro 220 1043 82d3 P5Q Deluxe Motherboard 1458 5000 GA-EP45-DS5/GA-EG45M-DS2H Motherboard 2e21 4 Series Chipset PCI Express Root Port @@ -19615,6 +24597,170 @@ 2e94 4 Series Chipset HECI Controller 2e95 4 Series Chipset HECI Controller 2e96 4 Series Chipset PT IDER Controller + 2f00 Xeon E7 v3/Xeon E5 v3/Core i7 DMI2 + 2f01 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 0 + 2f02 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 1 + 2f03 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 1 + 2f04 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 2 + 2f05 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 2 + 2f06 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 2 + 2f07 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 2 + 2f08 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 3 + 2f09 Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 3 + 2f0a Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 3 + 2f0b Xeon E7 v3/Xeon E5 v3/Core i7 PCI Express Root Port 3 + 2f10 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f11 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f12 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f13 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f14 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f15 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f16 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f17 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f18 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f19 Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f1a Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f1b Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f1c Xeon E7 v3/Xeon E5 v3/Core i7 IIO Debug + 2f1d Xeon E7 v3/Xeon E5 v3/Core i7 PCIe Ring Interface + 2f1e Xeon E7 v3/Xeon E5 v3/Core i7 Scratchpad & Semaphore Registers + 2f1f Xeon E7 v3/Xeon E5 v3/Core i7 Scratchpad & Semaphore Registers + 2f20 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 0 + 2f21 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 1 + 2f22 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 2 + 2f23 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 3 + 2f24 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 4 + 2f25 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 5 + 2f26 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 6 + 2f27 Xeon E7 v3/Xeon E5 v3/Core i7 DMA Channel 7 + 2f28 Xeon E7 v3/Xeon E5 v3/Core i7 Address Map, VTd_Misc, System Management + 2f29 Xeon E7 v3/Xeon E5 v3/Core i7 Hot Plug + 2f2a Xeon E7 v3/Xeon E5 v3/Core i7 RAS, Control Status and Global Errors + 2f2c Xeon E7 v3/Xeon E5 v3/Core i7 I/O APIC + 2f2e Xeon E7 v3/Xeon E5 v3/Core i7 RAID 5/6 + 2f2f Xeon E7 v3/Xeon E5 v3/Core i7 RAID 5/6 + 2f30 Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 0 + 2f32 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 + 2f33 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 1 + 2f34 Xeon E7 v3/Xeon E5 v3/Core i7 PCIe Ring Interface + 2f36 Xeon E7 v3/Xeon E5 v3/Core i7 R3 QPI Link 0 & 1 Monitoring + 2f37 Xeon E7 v3/Xeon E5 v3/Core i7 R3 QPI Link 0 & 1 Monitoring + 2f38 Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 1 + 2f39 Xeon E7 v3/Xeon E5 v3/Core i7 I/O Performance Monitoring + 2f3a Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 2 + 2f3e Xeon E7 v3/Xeon E5 v3/Core i7 R3 QPI Link 2 Monitoring + 2f3f Xeon E7 v3/Xeon E5 v3/Core i7 R3 QPI Link 2 Monitoring + 2f40 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 2 + 2f41 Xeon E7 v3/Xeon E5 v3/Core i7 R3 QPI Link 2 Monitoring + 2f43 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 2 + 2f45 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 2 Debug + 2f46 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 2 Debug + 2f47 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 2 Debug + 2f60 Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 1 + 2f68 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Target Address, Thermal & RAS Registers + 2f6a Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder + 2f6b Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder + 2f6c Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder + 2f6d Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel Target Address Decoder + 2f6e Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Channel 2/3 Broadcast + 2f6f Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Global Broadcast + 2f70 Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 0 Debug + 2f71 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Target Address, Thermal & RAS Registers + 2f76 Xeon E7 v3/Xeon E5 v3/Core i7 E3 QPI Link Debug + 2f78 Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 1 Debug + 2f79 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Target Address, Thermal & RAS Registers + 2f7d Xeon E7 v3/Xeon E5 v3/Core i7 Scratchpad & Semaphore Registers + 2f7e Xeon E7 v3/Xeon E5 v3/Core i7 E3 QPI Link Debug + 2f80 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 + 2f81 Xeon E7 v3/Xeon E5 v3/Core i7 R3 QPI Link 0 & 1 Monitoring + 2f83 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 + 2f85 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 Debug + 2f86 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 Debug + 2f87 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 0 Debug + 2f88 Xeon E7 v3/Xeon E5 v3/Core i7 VCU + 2f8a Xeon E7 v3/Xeon E5 v3/Core i7 VCU + 2f90 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 1 + 2f93 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 1 + 2f95 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 1 Debug + 2f96 Xeon E7 v3/Xeon E5 v3/Core i7 QPI Link 1 Debug + 2f98 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2f99 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2f9a Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2f9c Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2fa0 Xeon E7 v3/Xeon E5 v3/Core i7 Home Agent 0 + 2fa8 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Target Address, Thermal & RAS Registers + 2faa Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder + 2fab Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder + 2fac Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder + 2fad Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel Target Address Decoder + 2fae Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Channel 0/1 Broadcast + 2faf Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO Global Broadcast + 2fb0 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 0 Thermal Control + 2fb1 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 1 Thermal Control + 2fb2 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 0 ERROR Registers + 2fb3 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 1 ERROR Registers + 2fb4 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 2 Thermal Control + 2fb5 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 3 Thermal Control + 2fb6 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 2 ERROR Registers + 2fb7 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 0 Channel 3 ERROR Registers + 2fb8 Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 2 & 3 + 2fb9 Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 2 & 3 + 2fba Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 2 & 3 + 2fbb Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 2 & 3 + 2fbc Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 0 & 1 + 2fbd Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 0 & 1 + 2fbe Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 0 & 1 + 2fbf Xeon E7 v3/Xeon E5 v3/Core i7 DDRIO (VMSE) 0 & 1 + 2fc0 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2fc1 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2fc2 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2fc3 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2fc4 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2fc5 Xeon E7 v3/Xeon E5 v3/Core i7 Power Control Unit + 2fd0 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 0 Thermal Control + 2fd1 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 1 Thermal Control + 2fd2 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 0 ERROR Registers + 2fd3 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 1 ERROR Registers + 2fd4 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 2 Thermal Control + 2fd5 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 3 Thermal Control + 2fd6 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 2 ERROR Registers + 2fd7 Xeon E7 v3/Xeon E5 v3/Core i7 Integrated Memory Controller 1 Channel 3 ERROR Registers + 2fe0 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe1 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe2 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe3 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe4 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe5 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe6 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe7 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe8 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fe9 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fea Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2feb Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fec Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fed Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fee Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2fef Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff0 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff1 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff2 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff3 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff4 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff5 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff6 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff7 Xeon E7 v3/Xeon E5 v3/Core i7 Unicast Registers + 2ff8 Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent + 2ff9 Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent + 2ffa Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent + 2ffb Xeon E7 v3/Xeon E5 v3/Core i7 Buffered Ring Agent + 2ffc Xeon E7 v3/Xeon E5 v3/Core i7 System Address Decoder & Broadcast Registers + 2ffd Xeon E7 v3/Xeon E5 v3/Core i7 System Address Decoder & Broadcast Registers + 2ffe Xeon E7 v3/Xeon E5 v3/Core i7 System Address Decoder & Broadcast Registers + 3165 Wireless 3165 +# Stone Peak 1x1 + 8086 4010 Dual Band Wireless AC 3165 +# Stone Peak 1x1 + 8086 4210 Dual Band Wireless AC 3165 3200 GD31244 PCI-X SATA HBA 1775 c200 C2K onboard SATA host bus adapter 3310 IOP348 I/O Processor @@ -19691,16 +24837,23 @@ 3433 5520/5500/X58 Chipset QuickData Technology Device 3438 7500/5520/5500/X58 I/O Hub Throttle Registers 3500 6311ESB/6321ESB PCI Express Upstream Port + 103c 31fe ProLiant DL140 G3 + 15d9 9680 X7DBN Motherboard 3501 6310ESB PCI Express Upstream Port 3504 6311ESB/6321ESB I/OxAPIC Interrupt Controller 3505 6310ESB I/OxAPIC Interrupt Controller 350c 6311ESB/6321ESB PCI Express to PCI-X Bridge + 103c 31fe ProLiant DL140 G3 + 15d9 9680 X7DBN Motherboard 350d 6310ESB PCI Express to PCI-X Bridge 3510 6311ESB/6321ESB PCI Express Downstream Port E1 + 103c 31fe ProLiant DL140 G3 + 15d9 9680 X7DBN Motherboard 3511 6310ESB PCI Express Downstream Port E1 3514 6311ESB/6321ESB PCI Express Downstream Port E2 3515 6310ESB PCI Express Downstream Port E2 3518 6311ESB/6321ESB PCI Express Downstream Port E3 + 15d9 9680 X7DBN Motherboard 3519 6310ESB PCI Express Downstream Port E3 3575 82830M/MG/MP Host Bridge 0e11 0030 Evo N600c @@ -19712,6 +24865,7 @@ 3578 82830M/MG/MP Host Bridge 3580 82852/82855 GM/GME/PM/GMV Processor to I/O Controller 1014 055c ThinkPad R50e + 1025 0064 Extensa 3000 series laptop 1028 0139 Latitude D400 1028 014f Latitude X300 1028 0152 Latitude D500 @@ -19744,6 +24898,7 @@ e4bf 0cd2 CD2-BEBOP 3584 82852/82855 GM/GME/PM/GMV Processor to I/O Controller 1014 055d ThinkPad R50e + 1025 0064 Extensa 3000 series laptop 1028 0139 Latitude D400 1028 014f Latitude X300 1028 0152 Latitude D500 @@ -19758,6 +24913,7 @@ 4c53 10e0 PSL09 PrPMC 3585 82852/82855 GM/GME/PM/GMV Processor to I/O Controller 1014 055e ThinkPad R50e + 1025 0064 Extensa 3000 series laptop 1028 0139 Latitude D400 1028 014f Latitude X300 1028 0152 Latitude D500 @@ -19782,10 +24938,14 @@ 4c53 10d0 Telum ASLP10 Processor AMC 3591 E7525/E7520 Error Reporting Registers 1014 02dd eServer xSeries server mainboard + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 + 103c 3208 ProLiant DL140 G2 4c53 10d0 Telum ASLP10 Processor AMC 3592 E7320 Memory Controller Hub + 1734 1073 Primergy Econel 200 D2020 mainboard 3593 E7320 Error Reporting Registers + 1734 1073 Primergy Econel 200 D2020 mainboard 3594 E7520 DMA Controller 1775 1100 CR11/VR11 Single Board Computer 4c53 10d0 Telum ASLP10 Processor AMC @@ -19802,6 +24962,7 @@ 359b E7525/E7520/E7320 Extended Configuration Registers 1014 02dd eServer xSeries server mainboard 359e E7525 Memory Controller Hub + 1028 0168 Precision Workstation 670 Mainboard 1028 0169 Precision 470 35b0 3100 Chipset Memory I/O Controller Hub 35b1 3100 DRAM Controller Error Reporting Registers @@ -19921,19 +25082,19 @@ 1028 028d PowerEdge T410 USB UHCI Controller 103c 330b ProLiant G6 series 1043 82d4 P5Q Deluxe Motherboard - 1458 5004 GA-EP45-DS5/GA-EG45M-DS2H Motherboard + 1458 5004 Motherboard 3a38 82801JI (ICH10 Family) USB UHCI Controller #5 1028 028c PowerEdge R410 USB UHCI Controller 1028 028d PowerEdge T410 USB UHCI Controller 103c 330b ProLiant ML150 G6 Server 1043 82d4 P5Q Deluxe Motherboard - 1458 5004 GA-EP45-DS5/GA-EG45M-DS2H Motherboard + 1458 5004 Motherboard 3a39 82801JI (ICH10 Family) USB UHCI Controller #6 1028 028c PowerEdge R410 USB UHCI Controller 1028 028d PowerEdge T410 USB UHCI Controller 103c 330b ProLiant ML150 G6 Server 1043 82d4 P5Q Deluxe Motherboard - 1458 5004 GA-EP45-DS5/GA-EG45M-DS2H Motherboard + 1458 5004 Motherboard 3a3a 82801JI (ICH10 Family) USB2 EHCI Controller #1 1028 028c PowerEdge R410 USB EHCI Controller 1028 028d PowerEdge T410 USB EHCI Controller @@ -19945,7 +25106,7 @@ 1028 028d PowerEdge T410 USB EHCI Controller 103c 330b ProLiant G6 series 1043 82d4 P5Q Deluxe Motherboard - 1458 5006 GA-EP45-DS5 Motherboard + 1458 5006 Motherboard 3a3e 82801JI (ICH10 Family) HD Audio Controller 1043 8311 P5Q Deluxe Motherboard 1458 a002 GA-EP45-UD3R Motherboard @@ -20006,8 +25167,11 @@ 3b08 5 Series Chipset LPC Interface Controller 3b09 Mobile 5 Series Chipset LPC Interface Controller 1025 0347 Aspire 7740G + 144d c06a R730 Laptop + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b0a 5 Series Chipset LPC Interface Controller 1028 02da OptiPlex 980 + 15d9 060d C7SIM-Q Motherboard 3b0b Mobile 5 Series Chipset LPC Interface Controller 3b0c 5 Series Chipset LPC Interface Controller 3b0d 5 Series/3400 Series Chipset LPC Interface Controller @@ -20033,14 +25197,22 @@ 3b21 5 Series/3400 Series Chipset 2 port SATA IDE Controller 3b22 5 Series/3400 Series Chipset 6 port SATA AHCI Controller 1028 02da OptiPlex 980 + 15d9 060d C7SIM-Q Motherboard 3b23 5 Series/3400 Series Chipset 4 port SATA AHCI Controller 3b25 5 Series/3400 Series Chipset SATA RAID Controller + 103c 3118 HP Smart Array B110i SATA RAID Controller 3b26 5 Series/3400 Series Chipset 2 port SATA IDE Controller 3b28 5 Series/3400 Series Chipset 4 port SATA IDE Controller + 144d c06a R730 Laptop + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b29 5 Series/3400 Series Chipset 4 port SATA AHCI Controller 1025 0347 Aspire 7740G + 144d c06a R730 Laptop + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b2c 5 Series/3400 Series Chipset SATA RAID Controller 3b2d 5 Series/3400 Series Chipset 2 port SATA IDE Controller + 144d c06a R730 Laptop + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 3b2e 5 Series/3400 Series Chipset 4 port SATA IDE Controller e4bf 50c1 PC1-GROOVE @@ -20051,13 +25223,21 @@ 1025 0347 Aspire 7740G 1028 02da OptiPlex 980 1028 040b Latitude E6510 + 144d c06a R730 Laptop + 15d9 060d C7SIM-Q Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 3b32 5 Series/3400 Series Chipset Thermal Subsystem 1025 0347 Aspire 7740G + 144d c06a R730 Laptop + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b34 5 Series/3400 Series Chipset USB2 Enhanced Host Controller 1025 0347 Aspire 7740G 1028 02da OptiPlex 980 1028 040b Latitude E6510 + 144d c06a R730 Laptop + 15d9 060d C7SIM-Q Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 3b36 5 Series/3400 Series Chipset USB Universal Host Controller 3b37 5 Series/3400 Series Chipset USB Universal Host Controller @@ -20069,6 +25249,9 @@ 1025 0347 Aspire 7740G 1028 02da OptiPlex 980 1028 040b Latitude E6510 + 144d c06a R730 Laptop + 15d9 060d C7SIM-Q Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 3b3e 5 Series/3400 Series Chipset USB Universal Host Controller 3b3f 5 Series/3400 Series Chipset USB Universal Host Controller @@ -20077,14 +25260,23 @@ 3b42 5 Series/3400 Series Chipset PCI Express Root Port 1 1028 02da OptiPlex 980 1028 040b Latitude E6510 + 144d c06a R730 Laptop + 15d9 060d C7SIM-Q Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b44 5 Series/3400 Series Chipset PCI Express Root Port 2 1028 040b Latitude E6510 + 15d9 060d C7SIM-Q Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b46 5 Series/3400 Series Chipset PCI Express Root Port 3 1028 040b Latitude E6510 + 144d c06a R730 Laptop + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b48 5 Series/3400 Series Chipset PCI Express Root Port 4 1028 040b Latitude E6510 + 144d c06a R730 Laptop 3b4a 5 Series/3400 Series Chipset PCI Express Root Port 5 1028 02da OptiPlex 980 + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] 3b4c 5 Series/3400 Series Chipset PCI Express Root Port 6 3b4e 5 Series/3400 Series Chipset PCI Express Root Port 7 3b50 5 Series/3400 Series Chipset PCI Express Root Port 8 @@ -20093,10 +25285,15 @@ 1025 0347 Aspire 7740G 1028 02da OptiPlex 980 1028 040b Latitude E6510 + 144d c06a R730 Laptop + 15d9 060d C7SIM-Q Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 3b57 5 Series/3400 Series Chipset High Definition Audio 3b64 5 Series/3400 Series Chipset HECI Controller 1025 0347 Aspire 7740G + 15d9 060d C7SIM-Q Motherboard + 17c0 10d2 Medion Akoya E7214 Notebook PC [MD98410] e4bf 50c1 PC1-GROOVE 3b65 5 Series/3400 Series Chipset HECI Controller 3b66 5 Series/3400 Series Chipset PT IDER Controller @@ -20213,6 +25410,7 @@ 4220 PRO/Wireless 2200BG [Calexico2] Network Connection 103c 0934 Compaq nw8240/nx8220 103c 12f6 nc6120/nx8220/nw8240 + 8086 2701 WM3B2200BG Mini-PCI Card 8086 2712 IBM ThinkPad R50e 8086 2721 Dell B130 laptop integrated WLAN 8086 2722 Dell Latitude D600 @@ -20220,7 +25418,7 @@ 4222 PRO/Wireless 3945ABG [Golan] Network Connection 103c 135c PRO/Wireless 3945ABG [Golan] Network Connection 8086 1000 PRO/Wireless 3945ABG Network Connection - 8086 1001 PRO/Wireless 3945ABG Network Connection + 8086 1001 WM3945ABG MOW2 8086 1005 PRO/Wireless 3945BG Network Connection 8086 1034 PRO/Wireless 3945BG Network Connection 8086 1044 PRO/Wireless 3945BG Network Connection @@ -20233,7 +25431,7 @@ 1351 103c Compaq NC6220 4224 PRO/Wireless 2915ABG [Calexico2] Network Connection 4227 PRO/Wireless 3945ABG [Golan] Network Connection - 8086 1011 ThinkPad R60e/X60s + 8086 1011 ThinkPad T60/R60e/X60s 8086 1014 PRO/Wireless 3945BG Network Connection 4229 PRO/Wireless 4965 AG or AGN [Kedron] Network Connection 8086 1100 Vaio VGN-SZ79SN_C @@ -20345,10 +25543,12 @@ 504a EP80579 Reserved 504b EP80579 Reserved 504c EP80579 Integrated Processor with QuickAssist TDM - 5200 EtherExpress PRO/100 Intelligent Server - 5201 EtherExpress PRO/100 Intelligent Server + 5200 EtherExpress PRO/100 Intelligent Server PCI Bridge + 5201 EtherExpress PRO/100 Intelligent Server Fast Ethernet Controller 8086 0001 EtherExpress PRO/100 Server Ethernet Adapter 530d 80310 (IOP) IO Processor + 5845 QEMU NVM Express Controller + 1af4 1100 QEMU Virtual Machine 65c0 5100 Chipset Memory Controller Hub 65e2 5100 Chipset PCI Express x4 Port 2 65e3 5100 Chipset PCI Express x4 Port 3 @@ -20369,12 +25569,173 @@ 65f9 5100 Chipset PCI Express x8 Port 6-7 65fa 5100 Chipset PCI Express x16 Port 4-7 65ff 5100 Chipset DMA Engine + 6f00 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DMI2 + 6f01 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 0 + 6f02 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 1 + 6f03 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 1 + 6f04 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 2 + 6f05 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 2 + 6f06 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 2 + 6f07 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 2 + 6f08 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 3 + 6f09 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 3 + 6f0a Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 3 + 6f0b Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI Express Root Port 3 + 6f10 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f11 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f12 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f13 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f14 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f15 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f16 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f17 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f18 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f19 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f1a Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f1b Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f1c Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Debug + 6f1d Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R2PCIe Agent + 6f1e Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Ubox + 6f1f Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Ubox + 6f20 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 0 + 6f21 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 1 + 6f22 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 2 + 6f23 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 3 + 6f24 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 4 + 6f25 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 5 + 6f26 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 6 + 6f27 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Crystal Beach DMA Channel 7 + 6f28 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Map/VTd_Misc/System Management + 6f29 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO Hot Plug + 6f2a Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IIO RAS/Control Status/Global Errors + 6f2c Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D I/O APIC + 6f30 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Home Agent 0 + 6f32 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 0 + 6f33 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 1 + 6f34 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R2PCIe Agent + 6f36 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link 0/1 + 6f37 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link 0/1 + 6f38 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Home Agent 1 + 6f39 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D IO Performance Monitoring + 6f3a Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 2 + 6f3e Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link 2 + 6f3f Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link 2 + 6f40 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 2 + 6f41 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link 2 + 6f43 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 2 + 6f45 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 2 Debug + 6f46 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 2 Debug + 6f47 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 2 Debug + 6f60 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Home Agent 1 + 6f68 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Target Address/Thermal/RAS + 6f6a Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Channel Target Address Decoder + 6f6b Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Channel Target Address Decoder + 6f6c Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Channel Target Address Decoder + 6f6d Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Channel Target Address Decoder + 6f6e Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 2/3 Broadcast + 6f6f Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Global Broadcast + 6f70 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Home Agent 0 Debug + 6f71 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Target Address/Thermal/RAS + 6f76 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link Debug + 6f78 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Home Agent 1 Debug + 6f79 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Target Address/Thermal/RAS + 6f7d Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Ubox + 6f7e Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link Debug + 6f80 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 0 + 6f81 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D R3 QPI Link 0/1 + 6f83 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 0 + 6f85 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 0 Debug + 6f86 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 0 Debug + 6f87 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 0 Debug + 6f88 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6f8a Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6f90 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 1 + 6f93 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 1 + 6f95 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 1 Debug + 6f96 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D QPI Link 1 Debug + 6f98 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6f99 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6f9a Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6f9c Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fa0 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Home Agent 0 + 6fa8 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Target Address/Thermal/RAS + 6faa Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel Target Address Decoder + 6fab Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel Target Address Decoder + 6fac Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel Target Address Decoder + 6fad Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel Target Address Decoder + 6fae Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 0/1 Broadcast + 6faf Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Global Broadcast + 6fb0 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 0 Thermal Control + 6fb1 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 1 Thermal Control + 6fb2 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 0 Error + 6fb3 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 1 Error + 6fb4 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 2 Thermal Control + 6fb5 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 3 Thermal Control + 6fb6 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 2 Error + 6fb7 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 0 - Channel 3 Error + 6fb8 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 2/3 Interface + 6fb9 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 2/3 Interface + 6fba Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 2/3 Interface + 6fbb Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 2/3 Interface + 6fbc Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 0/1 Interface + 6fbd Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 0/1 Interface + 6fbe Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 0/1 Interface + 6fbf Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DDRIO Channel 0/1 Interface + 6fc0 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc1 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc2 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc3 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc4 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc5 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc6 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc7 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc8 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fc9 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fca Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fcb Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fcc Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fcd Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fce Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fcf Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Power Control Unit + 6fd0 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 0 Thermal Control + 6fd1 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 1 Thermal Control + 6fd2 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 0 Error + 6fd3 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 1 Error + 6fd4 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 2 Thermal Control + 6fd5 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 3 Thermal Control + 6fd6 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 2 Error + 6fd7 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Memory Controller 1 - Channel 3 Error + 6fe0 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe1 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe2 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe3 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe4 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe5 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe6 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe7 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe8 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fe9 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fea Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6feb Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fec Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fed Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fee Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6fef Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ff0 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ff1 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ff8 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ff9 Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ffa Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ffb Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ffc Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ffd Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent + 6ffe Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D Caching Agent 7000 82371SB PIIX3 ISA [Natoma/Triton II] 1af4 1100 Qemu virtual machine 7010 82371SB PIIX3 IDE [Natoma/Triton II] 1af4 1100 Qemu virtual machine 7020 82371SB PIIX3 USB [Natoma/Triton II] - 1af4 1100 Qemu virtual machine + 1af4 1100 QEMU Virtual Machine 7030 430VX - 82437VX TVX [Triton VX] 7050 Intercast Video Capture Card 7051 PB 642365-003 (Business Video Conferencing Card) @@ -20385,6 +25746,7 @@ 15ad 1976 Virtual Machine Chipset 7112 82371AB/EB/MB PIIX4 USB 15ad 1976 Virtual Machine Chipset + 1af4 1100 QEMU Virtual Machine 7113 82371AB/EB/MB PIIX4 ACPI 15ad 1976 Virtual Machine Chipset 1af4 1100 Qemu virtual machine @@ -20518,80 +25880,196 @@ 8817 Platform Controller Hub EG20T I2C Controller 8818 Platform Controller Hub EG20T Controller Area Network (CAN) Controller 8819 Platform Controller Hub EG20T IEEE 1588 Hardware Assist - 8c00 Lynx Point 4-port SATA Controller 1 [IDE mode] - 8c01 Lynx Point 4-port SATA Controller 1 [IDE mode] - 8c02 Lynx Point 6-port SATA Controller 1 [AHCI mode] - 8c03 Lynx Point 6-port SATA Controller 1 [AHCI mode] - 8c04 Lynx Point SATA Controller 1 [RAID mode] - 8c05 Lynx Point SATA Controller 1 [RAID mode] - 8c06 Lynx Point SATA Controller 1 [RAID mode] - 8c07 Lynx Point SATA Controller 1 [RAID mode] - 8c08 Lynx Point 2-port SATA Controller 2 [IDE mode] - 8c09 Lynx Point 2-port SATA Controller 2 [IDE mode] - 8c0e Lynx Point SATA Controller 1 [RAID mode] - 8c0f Lynx Point SATA Controller 1 [RAID mode] - 8c10 Lynx Point PCI Express Root Port #1 - 8c11 Lynx Point PCI Express Root Port #1 - 8c12 Lynx Point PCI Express Root Port #2 - 8c13 Lynx Point PCI Express Root Port #2 - 8c14 Lynx Point PCI Express Root Port #3 - 8c15 Lynx Point PCI Express Root Port #3 - 8c16 Lynx Point PCI Express Root Port #4 - 8c17 Lynx Point PCI Express Root Port #4 - 8c18 Lynx Point PCI Express Root Port #5 - 8c19 Lynx Point PCI Express Root Port #5 - 8c1a Lynx Point PCI Express Root Port #6 - 8c1b Lynx Point PCI Express Root Port #6 - 8c1c Lynx Point PCI Express Root Port #7 - 8c1d Lynx Point PCI Express Root Port #7 - 8c1e Lynx Point PCI Express Root Port #8 - 8c1f Lynx Point PCI Express Root Port #8 - 8c20 Lynx Point High Definition Audio Controller - 8c21 Lynx Point High Definition Audio Controller - 8c22 Lynx Point SMBus Controller - 8c23 Lynx Point CHAP Counters - 8c24 Lynx Point Thermal Management Controller - 8c26 Lynx Point USB Enhanced Host Controller #1 - 8c2d Lynx Point USB Enhanced Host Controller #2 - 8c31 Lynx Point USB xHCI Host Controller - 8c33 Lynx Point LAN Controller - 8c34 Lynx Point NAND Controller - 8c3a Lynx Point MEI Controller #1 - 8c3b Lynx Point MEI Controller #2 - 8c3c Lynx Point IDE-r Controller - 8c3d Lynx Point KT Controller - 8c40 Lynx Point LPC Controller - 8c41 Lynx Point LPC Controller - 8c42 Lynx Point LPC Controller - 8c43 Lynx Point LPC Controller - 8c44 Lynx Point LPC Controller - 8c45 Lynx Point LPC Controller - 8c46 Lynx Point LPC Controller - 8c47 Lynx Point LPC Controller - 8c48 Lynx Point LPC Controller - 8c49 Lynx Point LPC Controller - 8c4a Lynx Point LPC Controller - 8c4b Lynx Point LPC Controller - 8c4c Lynx Point LPC Controller - 8c4d Lynx Point LPC Controller - 8c4e Lynx Point LPC Controller - 8c4f Lynx Point LPC Controller - 8c50 Lynx Point LPC Controller - 8c51 Lynx Point LPC Controller - 8c52 Lynx Point LPC Controller - 8c53 Lynx Point LPC Controller - 8c54 Lynx Point LPC Controller - 8c55 Lynx Point LPC Controller - 8c56 Lynx Point LPC Controller - 8c57 Lynx Point LPC Controller - 8c58 Lynx Point LPC Controller - 8c59 Lynx Point LPC Controller - 8c5a Lynx Point LPC Controller - 8c5b Lynx Point LPC Controller - 8c5c Lynx Point LPC Controller - 8c5d Lynx Point LPC Controller - 8c5e Lynx Point LPC Controller - 8c5f Lynx Point LPC Controller + 8c00 8 Series/C220 Series Chipset Family 4-port SATA Controller 1 [IDE mode] + 8c01 8 Series Chipset Family 4-port SATA Controller 1 [IDE mode] - Mobile + 8c02 8 Series/C220 Series Chipset Family 6-port SATA Controller 1 [AHCI mode] + 8c03 8 Series/C220 Series Chipset Family 6-port SATA Controller 1 [AHCI mode] + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c04 8 Series/C220 Series Chipset Family SATA Controller 1 [RAID mode] + 8c05 8 Series/C220 Series Chipset Family SATA Controller 1 [RAID mode] + 8c06 8 Series/C220 Series Chipset Family SATA Controller 1 [RAID mode] + 8c07 8 Series/C220 Series Chipset Family SATA Controller 1 [RAID mode] + 8c08 8 Series/C220 Series Chipset Family 2-port SATA Controller 2 [IDE mode] + 8c09 8 Series/C220 Series Chipset Family 2-port SATA Controller 2 [IDE mode] + 8c0e 8 Series/C220 Series Chipset Family SATA Controller 1 [RAID mode] + 8c0f 8 Series/C220 Series Chipset Family SATA Controller 1 [RAID mode] + 8c10 8 Series/C220 Series Chipset Family PCI Express Root Port #1 + 17aa 220e ThinkPad T440p + 8c11 8 Series/C220 Series Chipset Family PCI Express Root Port #1 + 8c12 8 Series/C220 Series Chipset Family PCI Express Root Port #2 + 17aa 220e ThinkPad T440p + 8c13 8 Series/C220 Series Chipset Family PCI Express Root Port #2 + 8c14 8 Series/C220 Series Chipset Family PCI Express Root Port #3 + 8c15 8 Series/C220 Series Chipset Family PCI Express Root Port #3 + 8c16 8 Series/C220 Series Chipset Family PCI Express Root Port #4 + 8c17 8 Series/C220 Series Chipset Family PCI Express Root Port #4 + 8c18 8 Series/C220 Series Chipset Family PCI Express Root Port #5 + 8c19 8 Series/C220 Series Chipset Family PCI Express Root Port #5 + 8c1a 8 Series/C220 Series Chipset Family PCI Express Root Port #6 + 8c1b 8 Series/C220 Series Chipset Family PCI Express Root Port #6 + 8c1c 8 Series/C220 Series Chipset Family PCI Express Root Port #7 + 8c1d 8 Series/C220 Series Chipset Family PCI Express Root Port #7 + 8c1e 8 Series/C220 Series Chipset Family PCI Express Root Port #8 + 8c1f 8 Series/C220 Series Chipset Family PCI Express Root Port #8 + 8c20 8 Series/C220 Series Chipset High Definition Audio Controller + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c21 8 Series/C220 Series Chipset High Definition Audio Controller + 8c22 8 Series/C220 Series Chipset Family SMBus Controller + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c23 8 Series Chipset Family CHAP Counters + 8c24 8 Series Chipset Family Thermal Management Controller + 8c26 8 Series/C220 Series Chipset Family USB EHCI #1 + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c2d 8 Series/C220 Series Chipset Family USB EHCI #2 + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c31 8 Series/C220 Series Chipset Family USB xHCI + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c33 8 Series/C220 Series Chipset Family LAN Controller + 8c34 8 Series/C220 Series Chipset Family NAND Controller + 8c3a 8 Series/C220 Series Chipset Family MEI Controller #1 + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c3b 8 Series/C220 Series Chipset Family MEI Controller #2 + 8c3c 8 Series/C220 Series Chipset Family IDE-r Controller + 8c3d 8 Series/C220 Series Chipset Family KT Controller + 8c40 8 Series/C220 Series Chipset Family LPC Controller + 8c41 8 Series Chipset Family Mobile Super SKU LPC Controller + 8c42 8 Series/C220 Series Chipset Family Desktop Super SKU LPC Controller + 8c43 8 Series/C220 Series Chipset Family LPC Controller + 8c44 Z87 Express LPC Controller + 8c45 8 Series/C220 Series Chipset Family LPC Controller + 8c46 Z85 Express LPC Controller + 8c47 8 Series/C220 Series Chipset Family LPC Controller + 8c48 8 Series/C220 Series Chipset Family LPC Controller + 8c49 HM86 Express LPC Controller + 8c4a H87 Express LPC Controller + 8c4b HM87 Express LPC Controller + 8c4c Q85 Express LPC Controller + 8c4d 8 Series/C220 Series Chipset Family LPC Controller + 8c4e Q87 Express LPC Controller + 8c4f QM87 Express LPC Controller + 103c 1909 ZBook 15 + 17aa 220e ThinkPad T440p + 8c50 B85 Express LPC Controller + 8c51 8 Series/C220 Series Chipset Family LPC Controller + 8c52 C222 Series Chipset Family Server Essential SKU LPC Controller + 8c53 8 Series/C220 Series Chipset Family LPC Controller + 8c54 C224 Series Chipset Family Server Standard SKU LPC Controller + 8c55 8 Series/C220 Series Chipset Family LPC Controller + 8c56 C226 Series Chipset Family Server Advanced SKU LPC Controller + 8c57 8 Series/C220 Series Chipset Family LPC Controller + 8c58 8 Series/C220 Series Chipset Family WS SKU LPC Controller + 8c59 8 Series/C220 Series Chipset Family LPC Controller + 8c5a 8 Series/C220 Series Chipset Family LPC Controller + 8c5b 8 Series/C220 Series Chipset Family LPC Controller + 8c5c C220 Series Chipset Family H81 Express LPC Controller + 8c5d 8 Series/C220 Series Chipset Family LPC Controller + 8c5e 8 Series/C220 Series Chipset Family LPC Controller + 8c5f 8 Series/C220 Series Chipset Family LPC Controller + 8c80 9 Series Chipset Family SATA Controller [IDE Mode] + 8c81 9 Series Chipset Family SATA Controller [IDE Mode] + 8c82 9 Series Chipset Family SATA Controller [AHCI Mode] + 8c83 9 Series Chipset Family SATA Controller [AHCI Mode] + 8c84 9 Series Chipset Family SATA Controller [RAID Mode] + 8c85 9 Series Chipset Family SATA Controller [RAID Mode] + 8c86 9 Series Chipset Family SATA Controller [RAID Mode] + 8c87 9 Series Chipset Family SATA Controller [RAID Mode] + 8c88 9 Series Chipset Family SATA Controller [IDE Mode] + 8c89 9 Series Chipset Family SATA Controller [IDE Mode] + 8c8e 9 Series Chipset Family SATA Controller [RAID Mode] + 8c8f 9 Series Chipset Family SATA Controller [RAID Mode] + 8c90 9 Series Chipset Family PCI Express Root Port 1 + 8c92 9 Series Chipset Family PCI Express Root Port 2 + 8c94 9 Series Chipset Family PCI Express Root Port 3 + 8c96 9 Series Chipset Family PCI Express Root Port 4 + 8c98 9 Series Chipset Family PCI Express Root Port 5 + 8c9a 9 Series Chipset Family PCI Express Root Port 6 + 8c9c 9 Series Chipset Family PCI Express Root Port 7 + 8c9e 9 Series Chipset Family PCI Express Root Port 8 + 8ca0 9 Series Chipset Family HD Audio Controller + 8ca2 9 Series Chipset Family SMBus Controller + 8ca4 9 Series Chipset Family Thermal Controller + 8ca6 9 Series Chipset Family USB EHCI Controller #1 + 8cad 9 Series Chipset Family USB EHCI Controller #2 + 8cb1 9 Series Chipset Family USB xHCI Controller + 8cb3 9 Series Chipset Family LAN Controller + 8cba 9 Series Chipset Family ME Interface #1 + 8cbb 9 Series Chipset Family ME Interface #2 + 8cbc 9 Series Chipset Family IDE-R Controller + 8cbd 9 Series Chipset Family KT Controller + 8cc1 9 Series Chipset Family LPC Controller + 8cc2 9 Series Chipset Family LPC Controller + 8cc3 9 Series Chipset Family HM97 LPC Controller + 8cc4 9 Series Chipset Family Z97 LPC Controller + 8cc6 9 Series Chipset Family H97 Controller + 8d00 C610/X99 series chipset 4-port SATA Controller [IDE mode] + 8d02 C610/X99 series chipset 6-Port SATA Controller [AHCI mode] + 8d04 C610/X99 series chipset SATA Controller [RAID mode] + 8d06 C610/X99 series chipset SATA Controller [RAID mode] + 17aa 1031 ThinkServer RAID 110i + 8d08 C610/X99 series chipset 2-port SATA Controller [IDE mode] + 8d0e C610/X99 series chipset SATA Controller [RAID mode] + 8d10 C610/X99 series chipset PCI Express Root Port #1 + 8d11 C610/X99 series chipset PCI Express Root Port #1 + 8d12 C610/X99 series chipset PCI Express Root Port #2 + 8d13 C610/X99 series chipset PCI Express Root Port #2 + 8d14 C610/X99 series chipset PCI Express Root Port #3 + 8d15 C610/X99 series chipset PCI Express Root Port #3 + 8d16 C610/X99 series chipset PCI Express Root Port #4 + 8d17 C610/X99 series chipset PCI Express Root Port #4 + 8d18 C610/X99 series chipset PCI Express Root Port #5 + 8d19 C610/X99 series chipset PCI Express Root Port #5 + 8d1a C610/X99 series chipset PCI Express Root Port #6 + 8d1b C610/X99 series chipset PCI Express Root Port #6 + 8d1c C610/X99 series chipset PCI Express Root Port #7 + 8d1d C610/X99 series chipset PCI Express Root Port #7 + 8d1e C610/X99 series chipset PCI Express Root Port #8 + 8d1f C610/X99 series chipset PCI Express Root Port #8 + 8d20 C610/X99 series chipset HD Audio Controller + 8d21 C610/X99 series chipset HD Audio Controller + 8d22 C610/X99 series chipset SMBus Controller + 8d24 C610/X99 series chipset Thermal Subsystem + 8d26 C610/X99 series chipset USB Enhanced Host Controller #1 + 8d2d C610/X99 series chipset USB Enhanced Host Controller #2 + 8d31 C610/X99 series chipset USB xHCI Host Controller + 8d33 C610/X99 series chipset LAN Controller + 8d34 C610/X99 series chipset NAND Controller + 8d3a C610/X99 series chipset MEI Controller #1 + 8d3b C610/X99 series chipset MEI Controller #2 + 8d3c C610/X99 series chipset IDE-r Controller + 8d3d C610/X99 series chipset KT Controller + 8d40 C610/X99 series chipset LPC Controller + 8d41 C610/X99 series chipset LPC Controller + 8d42 C610/X99 series chipset LPC Controller + 8d43 C610/X99 series chipset LPC Controller + 8d44 C610/X99 series chipset LPC Controller + 8d45 C610/X99 series chipset LPC Controller + 8d46 C610/X99 series chipset LPC Controller + 8d47 C610/X99 series chipset LPC Controller + 8d48 C610/X99 series chipset LPC Controller + 8d49 C610/X99 series chipset LPC Controller + 8d4a C610/X99 series chipset LPC Controller + 8d4b C610/X99 series chipset LPC Controller + 8d4c C610/X99 series chipset LPC Controller + 8d4d C610/X99 series chipset LPC Controller + 8d4e C610/X99 series chipset LPC Controller + 8d4f C610/X99 series chipset LPC Controller + 8d60 C610/X99 series chipset sSATA Controller [IDE mode] + 8d62 C610/X99 series chipset sSATA Controller [AHCI mode] + 8d64 C610/X99 series chipset sSATA Controller [RAID mode] + 8d66 C610/X99 series chipset sSATA Controller [RAID mode] + 8d68 C610/X99 series chipset sSATA Controller [IDE mode] + 8d6e C610/X99 series chipset sSATA Controller [RAID mode] + 8d7c C610/X99 series chipset SPSR + 8d7d C610/X99 series chipset MS SMBus 0 + 8d7e C610/X99 series chipset MS SMBus 1 + 8d7f C610/X99 series chipset MS SMBus 2 9000 IXP2000 Family Network Processor 9001 IXP2400 Network Processor 9002 IXP2300 Network Processor @@ -20600,66 +26078,117 @@ 9622 Integrated RAID 9641 Integrated RAID 96a1 Integrated RAID - 9c00 Lynx Point-LP SATA Controller 1 [IDE mode] - 9c01 Lynx Point-LP SATA Controller 1 [IDE mode] - 9c02 Lynx Point-LP SATA Controller 1 [AHCI mode] - 9c03 Lynx Point-LP SATA Controller 1 [AHCI mode] - 9c04 Lynx Point-LP SATA Controller 1 [RAID mode] - 9c05 Lynx Point-LP SATA Controller 1 [RAID mode] - 9c06 Lynx Point-LP SATA Controller 1 [RAID mode] - 9c07 Lynx Point-LP SATA Controller 1 [RAID mode] - 9c08 Lynx Point-LP SATA Controller 2 [IDE mode] - 9c09 Lynx Point-LP SATA Controller 2 [IDE mode] - 9c0a LynxPoint-LP SATA Controller [Reserved] - 9c0b LynxPoint-LP SATA Controller [Reserved] - 9c0c LynxPoint-LP SATA Controller [Reserved] - 9c0d LynxPoint-LP SATA Controller [Reserved] - 9c0e Lynx Point-LP SATA Controller 1 [RAID mode] - 9c0f Lynx Point-LP SATA Controller 1 [RAID mode] - 9c10 Lynx Point-LP PCI Express Root Port 1 - 9c11 Lynx Point-LP PCI Express Root Port 1 - 9c12 Lynx Point-LP PCI Express Root Port 2 - 9c13 Lynx Point-LP PCI Express Root Port 2 - 9c14 Lynx Point-LP PCI Express Root Port 3 - 9c15 Lynx Point-LP PCI Express Root Port 3 - 9c16 Lynx Point-LP PCI Express Root Port 4 - 9c17 Lynx Point-LP PCI Express Root Port 4 - 9c18 Lynx Point-LP PCI Express Root Port 5 - 9c19 Lynx Point-LP PCI Express Root Port 5 - 9c1a Lynx Point-LP PCI Express Root Port 6 - 9c1b Lynx Point-LP PCI Express Root Port 6 - 9c20 Lynx Point-LP HD Audio Controller - 9c21 Lynx Point-LP HD Audio Controller - 9c22 Lynx Point-LP SMBus Controller - 9c23 Lynx Point-LP CHAP Counters - 9c24 Lynx Point-LP Thermal - 9c26 Lynx Point-LP USB EHCI #1 - 9c31 Lynx Point-LP USB xHCI HC - 9c35 Lynx Point-LP SDIO Controller - 9c36 Lynx Point-LP Audio DSP Controller - 9c3a Lynx Point-LP HECI #0 - 9c3b Lynx Point-LP HECI #1 - 9c3c Lynx Point-LP HECI IDER - 9c3d Lynx Point-LP HECI KT - 9c40 Lynx Point-LP LPC Controller - 9c41 Lynx Point-LP LPC Controller - 9c42 Lynx Point-LP LPC Controller - 9c43 Lynx Point-LP LPC Controller - 9c44 Lynx Point-LP LPC Controller - 9c45 Lynx Point-LP LPC Controller - 9c46 Lynx Point-LP LPC Controller - 9c47 Lynx Point-LP LPC Controller - 9c60 Lynx Point-LP Low Power Sub-System DMA - 9c61 Lynx Point-LP I2C Controller #0 - 9c62 Lynx Point-LP I2C Controller #1 - 9c63 Lynx Point-LP UART Controller #0 - 9c64 Lynx Point-LP UART Controller #1 - 9c65 Lynx Point-LP SPI Controller #0 - 9c66 Lynx Point-LP SPI Controller #1 + 9c00 8 Series SATA Controller 1 [IDE mode] + 9c01 8 Series SATA Controller 1 [IDE mode] + 9c02 8 Series SATA Controller 1 [AHCI mode] + 9c03 8 Series SATA Controller 1 [AHCI mode] + 17aa 2214 ThinkPad X240 + 9c04 8 Series SATA Controller 1 [RAID mode] + 9c05 8 Series SATA Controller 1 [RAID mode] + 9c06 8 Series SATA Controller 1 [RAID mode] + 9c07 8 Series SATA Controller 1 [RAID mode] + 9c08 8 Series SATA Controller 2 [IDE mode] + 9c09 8 Series SATA Controller 2 [IDE mode] + 9c0a 8 Series SATA Controller [Reserved] + 9c0b 8 Series SATA Controller [Reserved] + 9c0c 8 Series SATA Controller [Reserved] + 9c0d 8 Series SATA Controller [Reserved] + 9c0e 8 Series SATA Controller 1 [RAID mode] + 9c0f 8 Series SATA Controller 1 [RAID mode] + 9c10 8 Series PCI Express Root Port 1 + 9c11 8 Series PCI Express Root Port 1 + 9c12 8 Series PCI Express Root Port 2 + 9c13 8 Series PCI Express Root Port 2 + 9c14 8 Series PCI Express Root Port 3 + 9c15 8 Series PCI Express Root Port 3 + 9c16 8 Series PCI Express Root Port 4 + 9c17 8 Series PCI Express Root Port 4 + 9c18 8 Series PCI Express Root Port 5 + 9c19 8 Series PCI Express Root Port 5 + 9c1a 8 Series PCI Express Root Port 6 + 9c1b 8 Series PCI Express Root Port 6 + 9c1c 8 Series PCI Express Root Port 7 + 9c1d 8 Series PCI Express Root Port 7 + 9c1e 8 Series PCI Express Root Port 8 + 9c1f 8 Series PCI Express Root Port 8 + 9c20 8 Series HD Audio Controller + 17aa 2214 ThinkPad X240 + 9c21 8 Series HD Audio Controller + 9c22 8 Series SMBus Controller + 17aa 2214 ThinkPad X240 + 9c23 8 Series CHAP Counters + 9c24 8 Series Thermal + 9c26 8 Series USB EHCI #1 + 17aa 2214 ThinkPad X240 + 9c2d 8 Series USB EHCI #2 + 9c31 8 Series USB xHCI HC + 17aa 2214 ThinkPad X240 + 9c35 8 Series SDIO Controller + 9c36 8 Series Audio DSP Controller + 9c3a 8 Series HECI #0 + 17aa 2214 ThinkPad X240 + 9c3b 8 Series HECI #1 + 9c3c 8 Series HECI IDER + 9c3d 8 Series HECI KT + 9c40 8 Series LPC Controller + 9c41 8 Series LPC Controller + 9c42 8 Series LPC Controller + 9c43 8 Series LPC Controller + 17aa 2214 ThinkPad X240 + 9c44 8 Series LPC Controller + 9c45 8 Series LPC Controller + 9c46 8 Series LPC Controller + 9c47 8 Series LPC Controller + 9c60 8 Series Low Power Sub-System DMA + 9c61 8 Series I2C Controller #0 + 9c62 8 Series I2C Controller #1 + 9c63 8 Series UART Controller #0 + 9c64 8 Series UART Controller #1 + 9c65 8 Series SPI Controller #0 + 9c66 8 Series SPI Controller #1 + 9c83 Wildcat Point-LP SATA Controller [AHCI Mode] + 9c85 Wildcat Point-LP SATA Controller [RAID Mode] + 9c87 Wildcat Point-LP SATA Controller [RAID Mode] + 9c8f Wildcat Point-LP SATA Controller [RAID Mode] + 9c90 Wildcat Point-LP PCI Express Root Port #1 + 9c92 Wildcat Point-LP PCI Express Root Port #2 + 9c94 Wildcat Point-LP PCI Express Root Port #3 + 9c96 Wildcat Point-LP PCI Express Root Port #4 + 9c98 Wildcat Point-LP PCI Express Root Port #5 + 9c9a Wildcat Point-LP PCI Express Root Port #6 + 9ca0 Wildcat Point-LP High Definition Audio Controller + 9ca2 Wildcat Point-LP SMBus Controller + 9ca4 Wildcat Point-LP Thermal Management Controller + 9ca6 Wildcat Point-LP USB EHCI Controller + 9cb1 Wildcat Point-LP USB xHCI Controller + 9cb5 Wildcat Point-LP Secure Digital IO Controller + 9cb6 Wildcat Point-LP Smart Sound Technology Controller + 9cba Wildcat Point-LP MEI Controller #1 + 9cbb Wildcat Point-LP MEI Controller #2 + 9cbc Wildcat Point-LP IDE-r Controller + 9cbd Wildcat Point-LP KT Controller + 9cc1 Wildcat Point-LP LPC Controller + 9cc2 Wildcat Point-LP LPC Controller + 9cc3 Wildcat Point-LP LPC Controller + 9cc5 Wildcat Point-LP LPC Controller + 9cc6 Wildcat Point-LP LPC Controller + 9cc7 Wildcat Point-LP LPC Controller + 9cc9 Wildcat Point-LP LPC Controller + 9ce0 Wildcat Point-LP Serial IO DMA Controller + 9ce1 Wildcat Point-LP Serial IO I2C Controller #0 + 9ce2 Wildcat Point-LP Serial IO I2C Controller #1 + 9ce3 Wildcat Point-LP Serial IO UART Controller #0 + 9ce4 Wildcat Point-LP Serial IO UART Controller #1 + 9ce5 Wildcat Point-LP Serial IO GSPI Controller #0 + 9ce6 Wildcat Point-LP Serial IO GSPI Controller #1 a000 Atom Processor D4xx/D5xx/N4xx/N5xx DMI Bridge + 1458 5000 GA-D525TUD 8086 4f4d DeskTop Board D510MO + 8086 544b Desktop Board D425KT a001 Atom Processor D4xx/D5xx/N4xx/N5xx Integrated Graphics Controller + 1458 d000 GA-D525TUD 8086 4f4d DeskTop Board D510MO + 8086 544b Desktop Board D425KT a002 Atom Processor D4xx/D5xx/N4xx/N5xx Integrated Graphics Controller a003 Atom Processor D4xx/D5xx/N4xx/N5xx CHAPS counter a010 Atom Processor D4xx/D5xx/N4xx/N5xx DMI Bridge @@ -20669,7 +26198,136 @@ a012 Atom Processor D4xx/D5xx/N4xx/N5xx Integrated Graphics Controller 144d c072 Notebook N150P a013 Atom Processor D4xx/D5xx/N4xx/N5xx CHAPS counter + a103 Sunrise Point-H SATA Controller [AHCI mode] + a105 Sunrise Point-H SATA Controller [RAID mode] + a107 Sunrise Point-H SATA Controller [RAID mode] + a10f Sunrise Point-H SATA Controller [RAID mode] + a110 Sunrise Point-H PCI Express Root Port #1 + a111 Sunrise Point-H PCI Express Root Port #2 + a112 Sunrise Point-H PCI Express Root Port #3 + a113 Sunrise Point-H PCI Express Root Port #4 + a114 Sunrise Point-H PCI Express Root Port #5 + a115 Sunrise Point-H PCI Express Root Port #6 + a116 Sunrise Point-H PCI Express Root Port #7 + a117 Sunrise Point-H PCI Express Root Port #8 + a118 Sunrise Point-H PCI Express Root Port #9 + a119 Sunrise Point-H PCI Express Root Port #10 + a11a Sunrise Point-H PCI Express Root Port #11 + a11b Sunrise Point-H PCI Express Root Port #12 + a11c Sunrise Point-H PCI Express Root Port #13 + a11d Sunrise Point-H PCI Express Root Port #14 + a11e Sunrise Point-H PCI Express Root Port #15 + a11f Sunrise Point-H PCI Express Root Port #16 + a120 Sunrise Point-H P2SB + a121 Sunrise Point-H PMC + a122 Sunrise Point-H cAVS + a123 Sunrise Point-H SMBus + a124 Sunrise Point-H SPI Controller + a125 Sunrise Point-H Gigabit Ethernet Controller + a126 Sunrise Point-H Northpeak + a127 Sunrise Point-H LPSS UART #0 + a128 Sunrise Point-H LPSS UART #1 + a129 Sunrise Point-H LPSS SPI #0 + a12a Sunrise Point-H LPSS SPI #1 + a12f Sunrise Point-H USB 3.0 xHCI Controller + a130 Sunrise Point-H USB Device Controller (OTG) + a131 Sunrise Point-H Thermal subsystem + a133 Sunrise Point-H Northpeak ACPI Function + a135 Sunrise Point-H Integrated Sensor Hub + a13a Sunrise Point-H CSME HECI #1 + a13b Sunrise Point-H CSME HECI #2 + a13c Sunrise Point-H CSME IDE Redirection + a13d Sunrise Point-H KT Redirection + a13e Sunrise Point-H CSME HECI #3 + a140 Sunrise Point-H LPC Controller + a141 Sunrise Point-H LPC Controller + a142 Sunrise Point-H LPC Controller + a143 Sunrise Point-H LPC Controller + a144 Sunrise Point-H LPC Controller + a145 Sunrise Point-H LPC Controller + a146 Sunrise Point-H LPC Controller + a147 Sunrise Point-H LPC Controller + a148 Sunrise Point-H LPC Controller + a149 Sunrise Point-H LPC Controller + a14a Sunrise Point-H LPC Controller + a14b Sunrise Point-H LPC Controller + a14c Sunrise Point-H LPC Controller + a14d Sunrise Point-H LPC Controller + a14e Sunrise Point-H LPC Controller + a14f Sunrise Point-H LPC Controller + a150 Sunrise Point-H LPC Controller + a151 Sunrise Point-H LPC Controller + a152 Sunrise Point-H LPC Controller + a153 Sunrise Point-H LPC Controller + a154 Sunrise Point-H LPC Controller + a155 Sunrise Point-H LPC Controller + a156 Sunrise Point-H LPC Controller + a157 Sunrise Point-H LPC Controller + a158 Sunrise Point-H LPC Controller + a159 Sunrise Point-H LPC Controller + a15a Sunrise Point-H LPC Controller + a15b Sunrise Point-H LPC Controller + a15c Sunrise Point-H LPC Controller + a15d Sunrise Point-H LPC Controller + a15e Sunrise Point-H LPC Controller + a15f Sunrise Point-H LPC Controller + a160 Sunrise Point-H LPSS I2C Controller #0 + a161 Sunrise Point-H LPSS I2C Controller #1 + a166 Sunrise Point-H LPSS UART Controller #2 + a167 Sunrise Point-H PCI Root Port #17 + a168 Sunrise Point-H PCI Root Port #18 + a169 Sunrise Point-H PCI Root Port #19 + a16a Sunrise Point-H PCI Root Port #20 + a170 Sunrise Point-H HD Audio + a182 Lewisburg SATA Controller [AHCI mode] + a190 Lewisburg PCI Express Root Port #1 + a191 Lewisburg PCI Express Root Port #2 + a192 Lewisburg PCI Express Root Port #3 + a193 Lewisburg PCI Express Root Port #4 + a194 Lewisburg PCI Express Root Port #5 + a195 Lewisburg PCI Express Root Port #6 + a196 Lewisburg PCI Express Root Port #7 + a197 Lewisburg PCI Express Root Port #8 + a198 Lewisburg PCI Express Root Port #9 + a199 Lewisburg PCI Express Root Port #10 + a19a Lewisburg PCI Express Root Port #11 + a19b Lewisburg PCI Express Root Port #12 + a19c Lewisburg PCI Express Root Port #13 + a19d Lewisburg PCI Express Root Port #14 + a19e Lewisburg PCI Express Root Port #15 + a19f Lewisburg PCI Express Root Port #16 + a1a0 Lewisburg P2SB + a1a1 Lewisburg PMC + a1a2 Lewisburg cAVS + a1a3 Lewisburg SMBus + a1a4 Lewisburg SPI Controller + a1af Lewisburg USB 3.0 xHCI Controller + a1ba Lewisburg CSME: HECI #1 + a1bb Lewisburg CSME: HECI #2 + a1bc Lewisburg CSME: IDE-r + a1bd Lewisburg CSME: KT Controller + a1be Lewisburg CSME: HECI #3 + a1c1 Lewisburg LPC Controller + a1c2 Lewisburg LPC Controller + a1c3 Lewisburg LPC Controller + a1c4 Lewisburg LPC Controller + a1c5 Lewisburg LPC Controller + a1c6 Lewisburg LPC Controller + a1c7 Lewisburg LPC Controller + a1d2 Lewisburg SSATA Controller [AHCI mode] + a1e7 Lewisburg PCI Express Root Port #17 + a1e8 Lewisburg PCI Express Root Port #18 + a1e9 Lewisburg PCI Express Root Port #19 + a1ea Lewisburg PCI Express Root Port #20 + a1f0 Lewisburg MROM 0 + a1f1 Lewisburg MROM 1 + a1f8 Lewisburg IE: HECI #1 + a1f9 Lewisburg IE: HECI #2 + a1fa Lewisburg IE: IDE-r + a1fb Lewisburg IE: KT Controller + a1fc Lewisburg IE: HECI #3 a620 6400/6402 Advanced Memory Buffer (AMB) + abc0 Omni-Path Fabric Switch Silicon 100 Series b152 21152 PCI-to-PCI Bridge 8086 b152 21152 PCI-to-PCI Bridge # observed, and documented in Intel revision note; new mask of 1011:0026 @@ -20684,6 +26342,7 @@ d130 Core Processor DMI d131 Core Processor DMI 1028 02da OptiPlex 980 + 15d9 060d C7SIM-Q Motherboard d132 Core Processor DMI 1028 040b Latitude E6510 d133 Core Processor DMI @@ -20694,6 +26353,7 @@ d138 Core Processor PCI Express Root Port 1 1028 02da OptiPlex 980 1028 040b Latitude E6510 + 15d9 060d C7SIM-Q Motherboard d139 Core Processor PCI Express Root Port 2 d13a Core Processor PCI Express Root Port 3 d13b Core Processor PCI Express Root Port 4 @@ -20708,16 +26368,6 @@ cafe VirtualBox Guest Service 8322 Sodick America Corp. 8384 SigmaTel - 7618 High Definition Audio Codec - 7634 9250 HD Audio Codec - 7662 High Definition Audio Codec - 104d 1e00 High Definition Audio Codec [STAC9872AK] - 7664 High Definition Audio Codec - 7670 9770 High Definition Audio - 7672 9772 High Definition Audio - 7682 IDT High Definition Audio Codec - 7690 9200 HD Audio Codec - 1028 01c1 Precision 490 8401 TRENDware International Inc. 8686 ScaleMP 1010 vSMPowered system controller [vSMP CTL] @@ -20740,8 +26390,8 @@ 3860 AHA-2930CU 3b78 AHA-4844W/4844UW 5075 AIC-755x - 5078 AIC-7850 - 9004 7850 AHA-2904/Integrated AIC-7850 + 5078 AIC-7850T/7856T [AVA-2902/4/6 / AHA-2910] + 9004 7850 AIC-7850T/7856T [AVA-290x / AHA-2910] 5175 AIC-755x 5178 AIC-7851 5275 AIC-755x @@ -20790,7 +26440,7 @@ 9004 8020 ANA62022 2-port 64 bit 10/100 9004 8028 ANA69011A/TX 64 bit 10/100 7078 AHA-294x / AIC-7870 - 7178 AHA-2940/2940W / AIC-7871 + 7178 AIC-7870P/7871 [AHA-2940/W/S76] 7278 AHA-3940/3940W / AIC-7872 7378 AHA-3985 / AIC-7873 7478 AHA-2944/2944W / AIC-7874 @@ -20829,7 +26479,7 @@ 7897 AIC-789x 8078 AIC-7880U 9004 7880 AIC-7880P Ultra/Ultra Wide SCSI Chipset - 8178 AHA-2940U/UW/D / AIC-7881U + 8178 AIC-7870P/7881U [AHA-2940U/UW/D/S76] 9004 7881 AHA-2940UW SCSI Host Adapter 8278 AHA-3940U/UW/UWD / AIC-7882U 8378 AHA-3940U/UW / AIC-7883U @@ -20842,12 +26492,13 @@ 9004 7888 AHA-2930UW SCSI Controller 8b78 ABA-1030 ec78 AHA-4944W/UW +# acquired by PMC-Sierra 9005 Adaptec 0010 AHA-2940U2/U2W 9005 2180 AHA-2940U2 SCSI Controller 9005 8100 AHA-2940U2B SCSI Controller 9005 a100 AHA-2940U2B SCSI Controller - 9005 a180 AHA-2940U2W SCSI Controller + 9005 a180 AIC-3860Q [AHA-2940U2W/GE] SCSI Controller 9005 e100 AHA-2950U2B SCSI Controller 0011 AHA-2930U2 0013 78902 @@ -20915,7 +26566,7 @@ 1028 0287 PowerEdge Expandable RAID Controller 320/DC 1028 0291 CERC SATA RAID 2 PCI SATA 6ch (DellCorsair) 103c 3227 AAR-2610SA - 108e 0286 STK RAID INT + 108e 0286 Sun StorageTek SAS RAID HBA, Internal 108e 0287 STK RAID EXT 108e 7aac STK RAID REM 108e 7aae STK RAID EX @@ -21088,7 +26739,11 @@ 801f AIC-7902 U320 1734 1011 PRIMERGY RX300 onboard SCSI 8080 ASC-29320A U320 w/HostRAID + 8081 PMC-Sierra PM8001 SAS HBA [Series 6H] + 8088 PMC-Sierra PM8018 SAS HBA [Series 7H] + 8089 PMC-Sierra PM8019 SAS encryption HBA [Series 7He] 808f AIC-7901 U320 w/HostRAID + 1028 0168 Precision Workstation 670 Mainboard 8090 ASC-39320 U320 w/HostRAID 8091 ASC-39320D U320 w/HostRAID 8092 ASC-29320 U320 w/HostRAID @@ -21107,11 +26762,15 @@ 919a Gigapixel Corp 9412 Holtek 6565 6565 +9413 Softlogic Co., Ltd. + 6010 SOLO6010 MPEG-4 Video encoder/decoder + 6110 SOLO6110 H.264 Video encoder/decoder 9618 JusonTech Corporation 0001 JusonTech Gigabit Ethernet Controller 9699 Omni Media Technology Inc 6565 6565 -9710 NetMos Technology +# nee Netmos Technology +9710 MosChip Semiconductor Technology Ltd. 9250 PCI-to-PCI bridge [MCS9250] 9805 PCI 1 port parallel adapter 9815 PCI 9815 Multi-I/O Controller @@ -21136,8 +26795,10 @@ 9904 4-Port PCIe Serial Adapter # 2-port Serial 1-port Parallel Adaptor 9912 PCIe 9912 Multi-I/O Controller - 9922 PCIe 9922 Multi-I/O Controller + 9922 MCS9922 PCIe Multi-I/O Controller 9990 MCS9990 PCIe to 4‐Port USB 2.0 Host Controller +# Subsystem ID on a 3c985B-SX network card +9850 3Com (wrong ID) 9902 Stargen Inc. 0001 SG2010 PCI over Starfabric Bridge 0002 SG2010 PCI to Starfabric Gateway @@ -21151,6 +26812,22 @@ a304 Sony a727 3Com Corporation 0013 3CRPAG175 Wireless PC Card 6803 3CRDAG675B Wireless 11a/b/g Adapter +aa00 iTuner +aa01 iTuner +aa02 iTuner +aa03 iTuner +aa04 iTuner +aa05 iTuner +aa06 iTuner +aa07 iTuner +aa08 iTuner +aa09 iTuner +aa0a iTuner +aa0b iTuner +aa0c iTuner +aa0d iTuner +aa0e iTuner +aa0f iTuner aa42 Scitex Digital Video aa55 Ncomputing X300 PCI-Engine aaaa Adnaco Technology Inc. @@ -21175,6 +26852,29 @@ b1d9 ATCOM Technology co., LTD. # Pinnacle should be 11bd, but they got it wrong several times --mj bd11 Pinnacle Systems, Inc. (Wrong ID) bdbd Blackmagic Design + a106 Multibridge Extreme + a117 Intensity Pro + a11a DeckLink HD Extreme 2 + a11b DeckLink SDI/Duo/Quad + a11c DeckLink HD Extreme 3 + a11d DeckLink Studio + a11e DeckLink Optical Fibre + a120 Decklink Studio 2 + a121 DeckLink HD Extreme 3D/3D+ + a124 Intensity Extreme + a126 Intensity Shuttle + a127 UltraStudio Express + a129 UltraStudio Mini Monitor + a12a UltraStudio Mini Recorder + a12d UltraStudio 4K + a12e DeckLink 4K Extreme + a12f DeckLink Mini Monitor + a130 DeckLink Mini Recorder + a132 UltraStudio 4K + a136 DeckLink 4K Extreme 12G + a137 DeckLink Studio 4K + a138 Decklink SDI 4K + a139 Intensity Pro 4K c001 TSI Telsys c0a9 Micron/Crucial Technology c0de Motorola @@ -21184,6 +26884,7 @@ cace CACE Technologies, Inc. 0001 TurboCap Port A 0002 TurboCap Port B 0023 AirPcap N +caed Canny Edge cafe Chrysalis-ITS 0003 Luna K3 Hardware Security Module 0006 Luna PCI-e 3000 Hardware Security Module @@ -21205,7 +26906,9 @@ d161 Digium, Inc. 1205 Wildcard TE205P/TE207P dual-span T1/E1/J1 card 5.0V (u1) 1220 Wildcard TE220 dual-span T1/E1/J1 card 3.3V (PCI-Express) (5th gen) 1405 Wildcard TE405P/TE407P quad-span T1/E1/J1 card 5.0V (u1) + 1410 Wildcard TE410P quad-span T1/E1/J1 card 3.3V (5th Gen) 1420 Wildcard TE420 quad-span T1/E1/J1 card 3.3V (PCI-Express) (5th gen) + 1820 Wildcard TE820 octal-span T1/E1/J1 card 3.3V (PCI-Express) 2400 Wildcard TDM2400P 24-port analog card 3400 Wildcard TC400P transcoder base card 8000 Wildcard TE121 single-span T1/E1/J1 card (PCI-Express) @@ -21217,27 +26920,71 @@ d161 Digium, Inc. 8006 Wildcard AEX410 4-port analog card (PCI-Express) 8007 Hx8 Series 8-port Base Card 8008 Hx8 Series 8-port Base Card (PCI-Express) + 800a Wildcard TE133 single-span T1/E1/J1 card (PCI Express) + 800b Wildcard TE134 single-span T1/E1/J1 card + 800c Wildcard A8A 8-port analog card + 800d Wildcard A8B 8-port analog card (PCI-Express) + 800e Wildcard TE235/TE435 quad-span T1/E1/J1 card (PCI-Express) + 800f Wildcard A4A 4-port analog card + 8010 Wildcard A4B 4-port analog card (PCI-Express) + 8013 Wildcard TE236/TE436 quad-span T1/E1/J1 card b410 Wildcard B410 quad-BRI card d4d4 Dy4 Systems Inc 0601 PCI Mezzanine Card d531 I+ME ACTIA GmbH d84d Exsys dada Datapath Limited + 0133 VisionRGB-X2 + 0139 VisionRGB-E1 + 0144 VisionSD8 + 0150 VisionRGB-E2 + 0151 VisionSD4+1 + 0159 VisionAV + 0161 DGC161 + 0165 DGC165 + 0167 DGC167 + 0168 DGC168 + 1139 VisionRGB-E1S + 1150 VisionRGB-E2S + 1151 VisionSD4+1S + 1153 VisionDVI-DL + 1154 VisionSDI2 db10 Diablo Technologies dcba Dynamic Engineering - 0046 PCIeAlteraCycloneIV + 0046 PCIe Altera Cyclone IV # VPX format Receiver Controller Board 0047 VPX-RCB # PMC Format FPGA design with 8 high speed UART channels 0048 PMC-Biserial-III-BAE9 + 004e PC104p-Biserial-III-NVY5 + 004f PC104p-Biserial-III-NVY6 + 0052 PCIeBiSerialDb37 BA22 LVDS IO dd01 Digital Devices GmbH - 0003 Octopus LE DVB adapter + 0003 Octopus DVB Adapter + dd01 0001 Octopus DVB adapter + dd01 0002 Octopus LE DVB adapter + dd01 0003 Octopus OEM + dd01 0004 Octopus V3 DVB adapter + dd01 0010 Octopus Mini + dd01 0020 Cine S2 V6 DVB adapter + dd01 0021 Cine S2 V6.5 DVB adapter + dd01 0030 Cine CT V6.1 DVB adapter + dd01 db03 Mystique SaTiX-S2 V3 DVB adapter + 0006 Cine V7 + 0007 Max + dd01 0023 Max S8 4/8 + 0011 Octopus CI DVB Adapter + dd01 0040 Octopus CI + dd01 0041 Octopus CI Single + 0201 Resi DVB-C Modulator + dd01 0001 Resi DVB-C Modulator dead Indigita Corporation deaf Middle Digital Inc. 9050 PC Weasel Virtual VGA 9051 PC Weasel Serial Port 9052 PC Weasel Watchdog Timer -deda SoftHard Technology Ltd. +# formerly SoftHard Technology Ltd. +deda XIMEA e000 Winbond e000 W89C940 e159 Tiger Jet Network Inc. @@ -21260,6 +27007,7 @@ e4bf EKF Elektronik GmbH 53c1 SC1-ALLEGRO cc47 CCG-RUMBA cc4d CCM-BOOGIE +e4e4 Xorcom e55e Essence Technology, Inc. ea01 Eagle Technology 000a PCI-773 Temperature Card @@ -21325,7 +27073,11 @@ eace Endace Measurement Systems, Ltd 820f DAG 8.2X 10G Ethernet (2nd bus) 8400 DAG 8.4I Infiniband x4 SDR 8500 DAG 8.5I Infiniband x4 DDR + 9200 DAG 9.2SX2 10G Ethernet 920e DAG 9.2X2 10G Ethernet + a120 DAG 10X2-P 10G Ethernet + a12e DAG 10X2-S 10G Ethernet + a140 DAG 10X4-P 10G Ethernet ec80 Belkin Corporation ec00 F5D6000 ecc0 Echo Digital Audio Corporation @@ -21342,6 +27094,7 @@ f1d0 AJA Video c0ff Kona/Xena 2 cafe Kona SD cfee Xena LS/SD-22-DA/SD-DA + daff KONA LHi dcaf Kona HD dfee Xena HD-DA efac Xena SD-MM/SD-22-MM @@ -21359,7 +27112,6 @@ feda Broadcom Inc a10e BCM4230 iLine10 HomePNA 2.0 fede Fedetec Inc. 0003 TABIC PCI v3 -ffee FNK Tech fffd XenSource, Inc. 0101 PCI Event Channel Controller # Used in some old VMWare products before they got a real ID assigned @@ -21390,8 +27142,12 @@ C 01 Mass storage controller 06 SATA controller 00 Vendor specific 01 AHCI 1.0 + 02 Serial Storage Bus 07 Serial Attached SCSI controller + 01 Serial Storage Bus 08 Non-Volatile memory controller + 01 NVMHCI + 02 NVM Express 80 Mass storage controller C 02 Network controller 00 Ethernet controller @@ -21401,6 +27157,8 @@ C 02 Network controller 04 ISDN controller 05 WorldFip controller 06 PICMG controller + 07 Infiniband controller + 08 Fabric controller 80 Network controller C 03 Display controller 00 VGA compatible controller @@ -21478,6 +27236,7 @@ C 08 Generic system peripheral 00 8254 01 ISA Timer 02 EISA Timers + 03 HPET 03 RTC 00 Generic 01 ISA RTC @@ -21550,4 +27309,8 @@ C 11 Signal processing controller 10 Communication synchronizer 20 Signal processing management 80 Signal processing controller +C 12 Processing accelerators + 00 Processing accelerators +C 13 Non-Essential Instrumentation +C 40 Coprocessor C ff Unassigned class diff --git a/share/mk/bsd.lib.mk b/share/mk/bsd.lib.mk index b8159de..dc2e230 100644 --- a/share/mk/bsd.lib.mk +++ b/share/mk/bsd.lib.mk @@ -171,7 +171,7 @@ _LIBS= lib${LIB_PRIVATE}${LIB}.a lib${LIB_PRIVATE}${LIB}.a: ${OBJS} ${STATICOBJS} @${ECHO} building static ${LIB} library @rm -f ${.TARGET} - ${AR} ${ARFLAGS} ${.TARGET} `NM='${NM}' lorder ${OBJS} ${STATICOBJS} | tsort -q` ${ARADD} + ${AR} ${ARFLAGS} ${.TARGET} `NM='${NM}' NMFLAGS='${NMFLAGS}' lorder ${OBJS} ${STATICOBJS} | tsort -q` ${ARADD} ${RANLIB} ${RANLIBFLAGS} ${.TARGET} .endif @@ -185,7 +185,7 @@ NOPATH_FILES+= ${POBJS} lib${LIB_PRIVATE}${LIB}_p.a: ${POBJS} @${ECHO} building profiled ${LIB} library @rm -f ${.TARGET} - ${AR} ${ARFLAGS} ${.TARGET} `NM='${NM}' lorder ${POBJS} | tsort -q` ${ARADD} + ${AR} ${ARFLAGS} ${.TARGET} `NM='${NM}' NMFLAGS='${NMFLAGS}' lorder ${POBJS} | tsort -q` ${ARADD} ${RANLIB} ${RANLIBFLAGS} ${.TARGET} .endif @@ -250,7 +250,7 @@ ${SHLIB_NAME_FULL}: ${SOBJS} .endif ${_LD} ${LDFLAGS} ${SSP_CFLAGS} ${SOLINKOPTS} \ -o ${.TARGET} -Wl,-soname,${SONAME} \ - `NM='${NM}' lorder ${SOBJS} | tsort -q` ${LDADD} + `NM='${NM}' NMFLAGS='${NMFLAGS}' lorder ${SOBJS} | tsort -q` ${LDADD} .if ${MK_CTF} != "no" ${CTFMERGE} ${CTFFLAGS} -o ${.TARGET} ${SOBJS} .endif diff --git a/share/mk/src.opts.mk b/share/mk/src.opts.mk index ba8f48f..a5e78a3 100644 --- a/share/mk/src.opts.mk +++ b/share/mk/src.opts.mk @@ -80,7 +80,7 @@ __DEFAULT_YES_OPTIONS = \ DYNAMICROOT \ ED_CRYPTO \ EE \ - ELFTOOLCHAIN_TOOLS \ + ELFTOOLCHAIN_BOOTSTRAP \ EXAMPLES \ FDT \ FILE \ @@ -156,7 +156,6 @@ __DEFAULT_YES_OPTIONS = \ SOURCELESS_UCODE \ SVNLITE \ SYSCONS \ - SYSINSTALL \ TALK \ TCP_WRAPPERS \ TCSH \ @@ -330,6 +329,7 @@ MK_GROFF:= no .if ${MK_CROSS_COMPILER} == "no" MK_BINUTILS_BOOTSTRAP:= no MK_CLANG_BOOTSTRAP:= no +MK_ELFTOOLCHAIN_BOOTSTRAP:= no MK_GCC_BOOTSTRAP:= no .endif diff --git a/share/mk/sys.mk b/share/mk/sys.mk index d23d1d7..99e0337 100644 --- a/share/mk/sys.mk +++ b/share/mk/sys.mk @@ -167,6 +167,7 @@ MAKE ?= make .if !defined(%POSIX) NM ?= nm +NMFLAGS ?= OBJC ?= cc OBJCFLAGS ?= ${OBJCINCLUDES} ${CFLAGS} -Wno-import diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c index 1e64fc8..41dea8b 100644 --- a/sys/amd64/amd64/pmap.c +++ b/sys/amd64/amd64/pmap.c @@ -390,6 +390,8 @@ static struct md_page *pv_table; */ pt_entry_t *CMAP1 = 0; caddr_t CADDR1 = 0; +static vm_offset_t qframe = 0; +static struct mtx qframe_mtx; static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */ @@ -1031,7 +1033,7 @@ pmap_init(void) struct pmap_preinit_mapping *ppim; vm_page_t mpte; vm_size_t s; - int i, pv_npg; + int error, i, pv_npg; /* * Initialize the vm page array entries for the kernel pmap's @@ -1112,6 +1114,12 @@ pmap_init(void) printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i, ppim->pa, ppim->va, ppim->sz, ppim->mode); } + + mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN); + error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK, + (vmem_addr_t *)&qframe); + if (error != 0) + panic("qframe allocation failed"); } static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, @@ -7019,13 +7027,27 @@ pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, vm_offset_t pmap_quick_enter_page(vm_page_t m) { + vm_paddr_t paddr; - return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); + paddr = VM_PAGE_TO_PHYS(m); + if (paddr < dmaplimit) + return (PHYS_TO_DMAP(paddr)); + mtx_lock_spin(&qframe_mtx); + KASSERT(*vtopte(qframe) == 0, ("qframe busy")); + pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A | + X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0)); + return (qframe); } void pmap_quick_remove_page(vm_offset_t addr) { + + if (addr != qframe) + return; + pte_store(vtopte(qframe), 0); + invlpg(qframe); + mtx_unlock_spin(&qframe_mtx); } #include "opt_ddb.h" diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 0b589ed..fea0581 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -904,6 +904,7 @@ set_cpufuncs() cputype == CPU_ID_CORTEXA9R1 || cputype == CPU_ID_CORTEXA9R2 || cputype == CPU_ID_CORTEXA9R3 || + cputype == CPU_ID_CORTEXA9R4 || cputype == CPU_ID_CORTEXA12R0 || cputype == CPU_ID_CORTEXA15R0 || cputype == CPU_ID_CORTEXA15R1 || diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c index 75bf08c..be1393b1 100644 --- a/sys/arm/arm/identcpu.c +++ b/sys/arm/arm/identcpu.c @@ -185,6 +185,8 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEXA, "Cortex A9-r3", generic_steppings }, + { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEXA, "Cortex A9-r4", + generic_steppings }, { CPU_ID_CORTEXA12R0, CPU_CLASS_CORTEXA, "Cortex A12-r0", generic_steppings }, { CPU_ID_CORTEXA15R0, CPU_CLASS_CORTEXA, "Cortex A15-r0", diff --git a/sys/arm/arm/pmap-v6-new.c b/sys/arm/arm/pmap-v6-new.c index b18648f..864e05c 100644 --- a/sys/arm/arm/pmap-v6-new.c +++ b/sys/arm/arm/pmap-v6-new.c @@ -1166,10 +1166,9 @@ pmap_init_qpages(void) pc = pcpu_find(i); pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); if (pc->pc_qmap_addr == 0) - panic("pmap_init_qpages: unable to allocate KVA"); + panic("%s: unable to allocate KVA", __func__); } } - SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL); /* @@ -5728,18 +5727,17 @@ pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], vm_offset_t pmap_quick_enter_page(vm_page_t m) { - pt2_entry_t *pte; - vm_offset_t qmap_addr; + pt2_entry_t *pte2p; + vm_offset_t qmap_addr; critical_enter(); - qmap_addr = PCPU_GET(qmap_addr); - pte = pt2map_entry(qmap_addr); + pte2p = pt2map_entry(qmap_addr); - KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy")); + KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__)); - pte2_store(pte, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), - PTE2_AP_KRW, pmap_page_get_memattr(m))); + pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW, + pmap_page_get_memattr(m))); tlb_flush_local(qmap_addr); return (qmap_addr); @@ -5748,16 +5746,16 @@ pmap_quick_enter_page(vm_page_t m) void pmap_quick_remove_page(vm_offset_t addr) { - pt2_entry_t *pte; + pt2_entry_t *pte2p; vm_offset_t qmap_addr; qmap_addr = PCPU_GET(qmap_addr); - pte = pt2map_entry(qmap_addr); + pte2p = pt2map_entry(qmap_addr); - KASSERT(addr == qmap_addr, ("pmap_quick_remove_page: invalid address")); - KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use")); + KASSERT(addr == qmap_addr, ("%s: invalid address", __func__)); + KASSERT(pte2_load(pte2p) != 0, ("%s: PTE2 not in use", __func__)); - pte2_clear(pte); + pte2_clear(pte2p); critical_exit(); } diff --git a/sys/arm/arm/stdatomic.c b/sys/arm/arm/stdatomic.c index 211f26a..3c0b997 100644 --- a/sys/arm/arm/stdatomic.c +++ b/sys/arm/arm/stdatomic.c @@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$"); #include <sys/types.h> #include <machine/acle-compat.h> +#include <machine/atomic.h> #include <machine/cpufunc.h> #include <machine/sysarch.h> @@ -67,19 +68,12 @@ do_sync(void) __asm volatile ("" : : : "memory"); } -#elif __ARM_ARCH >= 7 -static inline void -do_sync(void) -{ - - __asm volatile ("dmb" : : : "memory"); -} #elif __ARM_ARCH >= 6 static inline void do_sync(void) { - __asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory"); + dmb(); } #endif diff --git a/sys/arm/broadcom/bcm2835/bcm2835_systimer.c b/sys/arm/broadcom/bcm2835/bcm2835_systimer.c index 93bf676..731c7d0 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_systimer.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_systimer.c @@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$"); #define BCM2835_NUM_TIMERS 4 #define DEFAULT_TIMER 3 +#define DEFAULT_TIMER_NAME "BCM2835-3" #define DEFAULT_FREQUENCY 1000000 #define MIN_PERIOD 5LLU @@ -101,7 +102,7 @@ static struct bcm_systimer_softc *bcm_systimer_sc = NULL; static unsigned bcm_systimer_tc_get_timecount(struct timecounter *); static struct timecounter bcm_systimer_tc = { - .tc_name = "BCM2835 Timecounter", + .tc_name = DEFAULT_TIMER_NAME, .tc_get_timecount = bcm_systimer_tc_get_timecount, .tc_poll_pps = NULL, .tc_counter_mask = ~0u, @@ -238,8 +239,7 @@ bcm_systimer_attach(device_t dev) sc->st[DEFAULT_TIMER].index = DEFAULT_TIMER; sc->st[DEFAULT_TIMER].enabled = 0; - sc->st[DEFAULT_TIMER].et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO); - sprintf(sc->st[DEFAULT_TIMER].et.et_name, "BCM2835 Event Timer %d", DEFAULT_TIMER); + sc->st[DEFAULT_TIMER].et.et_name = DEFAULT_TIMER_NAME; sc->st[DEFAULT_TIMER].et.et_flags = ET_FLAGS_ONESHOT; sc->st[DEFAULT_TIMER].et.et_quality = 1000; sc->st[DEFAULT_TIMER].et.et_frequency = sc->sysclk_freq; diff --git a/sys/arm/conf/BEAGLEBONE b/sys/arm/conf/BEAGLEBONE index a0ca1b6..12b8290 100644 --- a/sys/arm/conf/BEAGLEBONE +++ b/sys/arm/conf/BEAGLEBONE @@ -26,7 +26,7 @@ ident BEAGLEBONE include "std.armv6" include "../ti/am335x/std.am335x" -makeoptions MODULES_EXTRA="dtb/am335x" +makeoptions MODULES_EXTRA="dtb/am335x am335x_dmtpps" # DTrace support options KDTRACE_HOOKS # Kernel DTrace hooks @@ -77,6 +77,7 @@ device ti_i2c device am335x_pmic # AM335x Power Management IC (TPC65217) device am335x_rtc # RTC support (power management only) +#define am335x_dmtpps # Pulse Per Second capture driver # Console and misc device uart diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 9358703..a300ddf 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -133,6 +133,7 @@ #define CPU_ID_CORTEXA9R1 0x411fc090 #define CPU_ID_CORTEXA9R2 0x412fc090 #define CPU_ID_CORTEXA9R3 0x413fc090 +#define CPU_ID_CORTEXA9R4 0x414fc090 #define CPU_ID_CORTEXA12R0 0x410fc0d0 #define CPU_ID_CORTEXA15R0 0x410fc0f0 #define CPU_ID_CORTEXA15R1 0x411fc0f0 diff --git a/sys/arm/ti/am335x/am335x_dmtpps.c b/sys/arm/ti/am335x/am335x_dmtpps.c new file mode 100644 index 0000000..08b4104 --- /dev/null +++ b/sys/arm/ti/am335x/am335x_dmtpps.c @@ -0,0 +1,549 @@ +/*- + * Copyright (c) 2015 Ian lepore <ian@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * AM335x PPS driver using DMTimer capture. + * + * Note that this PPS driver does not use an interrupt. Instead it uses the + * hardware's ability to latch the timer's count register in response to a + * signal on an IO pin. Each of timers 4-7 have an associated pin, and this + * code allows any one of those to be used. + * + * The timecounter routines in kern_tc.c call the pps poll routine periodically + * to see if a new counter value has been latched. When a new value has been + * latched, the only processing done in the poll routine is to capture the + * current set of timecounter timehands (done with pps_capture()) and the + * latched value from the timer. The remaining work (done by pps_event() while + * holding a mutex) is scheduled to be done later in a non-interrupt context. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/conf.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/malloc.h> +#include <sys/rman.h> +#include <sys/taskqueue.h> +#include <sys/timepps.h> +#include <sys/timetc.h> +#include <machine/bus.h> + +#include <dev/ofw/openfirm.h> +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <arm/ti/ti_prcm.h> +#include <arm/ti/ti_hwmods.h> +#include <arm/ti/ti_pinmux.h> +#include <arm/ti/am335x/am335x_scm_padconf.h> + +#include "am335x_dmtreg.h" + +#define PPS_CDEV_NAME "dmtpps" + +struct dmtpps_softc { + device_t dev; + int mem_rid; + struct resource * mem_res; + int tmr_num; /* N from hwmod str "timerN" */ + char tmr_name[12]; /* "DMTimerN" */ + uint32_t tclr; /* Cached TCLR register. */ + struct timecounter tc; + int pps_curmode; /* Edge mode now set in hw. */ + struct task pps_task; /* For pps_event handling. */ + struct cdev * pps_cdev; + struct pps_state pps_state; + struct mtx pps_mtx; +}; + +static int dmtpps_tmr_num; /* Set by probe() */ + +/* List of compatible strings for FDT tree */ +static struct ofw_compat_data compat_data[] = { + {"ti,am335x-timer", 1}, + {"ti,am335x-timer-1ms", 1}, + {NULL, 0}, +}; + +/* + * A table relating pad names to the hardware timer number they can be mux'd to. + */ +struct padinfo { + char * ballname; + int tmr_num; +}; +static struct padinfo dmtpps_padinfo[] = { + {"GPMC_ADVn_ALE", 4}, + {"I2C0_SDA", 4}, + {"MII1_TX_EN", 4}, + {"XDMA_EVENT_INTR0", 4}, + {"GPMC_BEn0_CLE", 5}, + {"MDC", 5}, + {"MMC0_DAT3", 5}, + {"UART1_RTSn", 5}, + {"GPMC_WEn", 6}, + {"MDIO", 6}, + {"MMC0_DAT2", 6}, + {"UART1_CTSn", 6}, + {"GPMC_OEn_REn", 7}, + {"I2C0_SCL", 7}, + {"UART0_CTSn", 7}, + {"XDMA_EVENT_INTR1", 7}, + {NULL, 0} +}; + +/* + * This is either brilliantly user-friendly, or utterly lame... + * + * The am335x chip is used on the popular Beaglebone boards. Those boards have + * pins for all four capture-capable timers available on the P8 header. Allow + * users to configure the input pin by giving the name of the header pin. + */ +struct nicknames { + const char * nick; + const char * name; +}; +static struct nicknames dmtpps_pin_nicks[] = { + {"P8-7", "GPMC_ADVn_ALE"}, + {"P8-9", "GPMC_BEn0_CLE"}, + {"P8-10", "GPMC_WEn"}, + {"P8-8", "GPMC_OEn_REn",}, + {NULL, NULL} +}; + +#define DMTIMER_READ4(sc, reg) bus_read_4((sc)->mem_res, (reg)) +#define DMTIMER_WRITE4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val)) + +/* + * Translate a short friendly case-insensitive name to its canonical name. + */ +static const char * +dmtpps_translate_nickname(const char *nick) +{ + struct nicknames *nn; + + for (nn = dmtpps_pin_nicks; nn->nick != NULL; nn++) + if (strcasecmp(nick, nn->nick) == 0) + return nn->name; + return (nick); +} + +/* + * See if our tunable is set to the name of the input pin. If not, that's NOT + * an error, return 0. If so, try to configure that pin as a timer capture + * input pin, and if that works, then we have our timer unit number and if it + * fails that IS an error, return -1. + */ +static int +dmtpps_find_tmr_num_by_tunable() +{ + struct padinfo *pi; + char iname[20]; + char muxmode[12]; + const char * ballname; + int err; + + if (!TUNABLE_STR_FETCH("hw.am335x_dmtpps.input", iname, sizeof(iname))) + return (0); + ballname = dmtpps_translate_nickname(iname); + for (pi = dmtpps_padinfo; pi->ballname != NULL; pi++) { + if (strcmp(ballname, pi->ballname) != 0) + continue; + snprintf(muxmode, sizeof(muxmode), "timer%d", pi->tmr_num); + err = ti_pinmux_padconf_set(pi->ballname, muxmode, + PADCONF_INPUT); + if (err != 0) { + printf("am335x_dmtpps: unable to configure capture pin " + "for %s to input mode\n", muxmode); + return (-1); + } else if (bootverbose) { + printf("am335x_dmtpps: configured pin %s as input " + "for %s\n", iname, muxmode); + } + return (pi->tmr_num); + } + + /* Invalid name in the tunable, that's an error. */ + printf("am335x_dmtpps: unknown pin name '%s'\n", iname); + return (-1); +} + +/* + * Ask the pinmux driver whether any pin has been configured as a TIMER4..TIMER7 + * input pin. If so, return the timer number, if not return 0. + */ +static int +dmtpps_find_tmr_num_by_padconf() +{ + int err; + unsigned int padstate; + const char * padmux; + struct padinfo *pi; + char muxmode[12]; + + for (pi = dmtpps_padinfo; pi->ballname != NULL; pi++) { + err = ti_pinmux_padconf_get(pi->ballname, &padmux, &padstate); + snprintf(muxmode, sizeof(muxmode), "timer%d", pi->tmr_num); + if (err == 0 && (padstate & RXACTIVE) != 0 && + strcmp(muxmode, padmux) == 0) + return (pi->tmr_num); + } + /* Nothing found, not an error. */ + return (0); +} + +/* + * Figure out which hardware timer number to use based on input pin + * configuration. This is done just once, the first time probe() runs. + */ +static int +dmtpps_find_tmr_num() +{ + int tmr_num; + + if ((tmr_num = dmtpps_find_tmr_num_by_tunable()) == 0) + tmr_num = dmtpps_find_tmr_num_by_padconf(); + + if (tmr_num <= 0) { + printf("am335x_dmtpps: PPS driver not enabled: unable to find " + "or configure a capture input pin\n"); + tmr_num = -1; /* Must return non-zero to prevent re-probing. */ + } + return (tmr_num); +} + +static void +dmtpps_set_hw_capture(struct dmtpps_softc *sc, bool force_off) +{ + int newmode; + + if (force_off) + newmode = 0; + else + newmode = sc->pps_state.ppsparam.mode & PPS_CAPTUREASSERT; + + if (newmode == sc->pps_curmode) + return; + sc->pps_curmode = newmode; + + if (newmode == PPS_CAPTUREASSERT) + sc->tclr |= DMT_TCLR_CAPTRAN_LOHI; + else + sc->tclr &= ~DMT_TCLR_CAPTRAN_MASK; + DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr); +} + +static unsigned +dmtpps_get_timecount(struct timecounter *tc) +{ + struct dmtpps_softc *sc; + + sc = tc->tc_priv; + + return (DMTIMER_READ4(sc, DMT_TCRR)); +} + +static void +dmtpps_poll(struct timecounter *tc) +{ + struct dmtpps_softc *sc; + + sc = tc->tc_priv; + + /* + * If a new value has been latched we've got a PPS event. Capture the + * timecounter data, then override the capcount field (pps_capture() + * populates it from the current DMT_TCRR register) with the latched + * value from the TCAR1 register. + * + * There is no locking here, by design. pps_capture() writes into an + * area of struct pps_state which is read only by pps_event(). The + * synchronization of access to that area is temporal rather than + * interlock based... we write in this routine and trigger the task that + * will read the data, so no simultaneous access can occur. + * + * Note that we don't have the TCAR interrupt enabled, but the hardware + * still provides the status bits in the "RAW" status register even when + * they're masked from generating an irq. However, when clearing the + * TCAR status to re-arm the capture for the next second, we have to + * write to the IRQ status register, not the RAW register. Quirky. + */ + if (DMTIMER_READ4(sc, DMT_IRQSTATUS_RAW) & DMT_IRQ_TCAR) { + pps_capture(&sc->pps_state); + sc->pps_state.capcount = DMTIMER_READ4(sc, DMT_TCAR1); + DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_TCAR); + taskqueue_enqueue_fast(taskqueue_fast, &sc->pps_task); + } +} + +static void +dmtpps_event(void *arg, int pending) +{ + struct dmtpps_softc *sc; + + sc = arg; + + /* This is the task function that gets enqueued by poll_pps. Once the + * time has been captured by the timecounter polling code which runs in + * primary interrupt context, the remaining (more expensive) work to + * process the event is done later in a threaded context. + * + * Here there is an interlock that protects the event data in struct + * pps_state. That data can be accessed at any time from userland via + * ioctl() calls so we must ensure that there is no read access to + * partially updated data while pps_event() does its work. + */ + mtx_lock(&sc->pps_mtx); + pps_event(&sc->pps_state, PPS_CAPTUREASSERT); + mtx_unlock(&sc->pps_mtx); +} + +static int +dmtpps_open(struct cdev *dev, int flags, int fmt, + struct thread *td) +{ + struct dmtpps_softc *sc; + + sc = dev->si_drv1; + + /* + * Begin polling for pps and enable capture in the hardware whenever the + * device is open. Doing this stuff again is harmless if this isn't the + * first open. + */ + sc->tc.tc_poll_pps = dmtpps_poll; + dmtpps_set_hw_capture(sc, false); + + return 0; +} + +static int +dmtpps_close(struct cdev *dev, int flags, int fmt, + struct thread *td) +{ + struct dmtpps_softc *sc; + + sc = dev->si_drv1; + + /* + * Stop polling and disable capture on last close. Use the force-off + * flag to override the configured mode and turn off the hardware. + */ + sc->tc.tc_poll_pps = NULL; + dmtpps_set_hw_capture(sc, true); + + return 0; +} + +static int +dmtpps_ioctl(struct cdev *dev, u_long cmd, caddr_t data, + int flags, struct thread *td) +{ + struct dmtpps_softc *sc; + int err; + + sc = dev->si_drv1; + + /* Let the kernel do the heavy lifting for ioctl. */ + mtx_lock(&sc->pps_mtx); + err = pps_ioctl(cmd, data, &sc->pps_state); + mtx_unlock(&sc->pps_mtx); + if (err != 0) + return (err); + + /* + * The capture mode could have changed, set the hardware to whatever + * mode is now current. Effectively a no-op if nothing changed. + */ + dmtpps_set_hw_capture(sc, false); + + return (err); +} + +static struct cdevsw dmtpps_cdevsw = { + .d_version = D_VERSION, + .d_open = dmtpps_open, + .d_close = dmtpps_close, + .d_ioctl = dmtpps_ioctl, + .d_name = PPS_CDEV_NAME, +}; + +static int +dmtpps_probe(device_t dev) +{ + char strbuf[64]; + int tmr_num; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + /* + * If we haven't chosen which hardware timer to use yet, go do that now. + * We need to know that to decide whether to return success for this + * hardware timer instance or not. + */ + if (dmtpps_tmr_num == 0) + dmtpps_tmr_num = dmtpps_find_tmr_num(); + + /* + * Figure out which hardware timer is being probed and see if it matches + * the configured timer number determined earlier. + */ + tmr_num = ti_hwmods_get_unit(dev, "timer"); + if (dmtpps_tmr_num != tmr_num) + return (ENXIO); + + snprintf(strbuf, sizeof(strbuf), "AM335x PPS-Capture DMTimer%d", + tmr_num); + device_set_desc_copy(dev, strbuf); + + return(BUS_PROBE_DEFAULT); +} + +static int +dmtpps_attach(device_t dev) +{ + struct dmtpps_softc *sc; + clk_ident_t timer_id; + int err, sysclk_freq; + + sc = device_get_softc(dev); + sc->dev = dev; + + /* Get the base clock frequency. */ + err = ti_prcm_clk_get_source_freq(SYS_CLK, &sysclk_freq); + + /* Enable clocks and power on the device. */ + if ((timer_id = ti_hwmods_get_clock(dev)) == INVALID_CLK_IDENT) + return (ENXIO); + if ((err = ti_prcm_clk_set_source(timer_id, SYSCLK_CLK)) != 0) + return (err); + if ((err = ti_prcm_clk_enable(timer_id)) != 0) + return (err); + + /* Request the memory resources. */ + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &sc->mem_rid, RF_ACTIVE); + if (sc->mem_res == NULL) { + return (ENXIO); + } + + /* Figure out which hardware timer this is and set the name string. */ + sc->tmr_num = ti_hwmods_get_unit(dev, "timer"); + snprintf(sc->tmr_name, sizeof(sc->tmr_name), "DMTimer%d", sc->tmr_num); + + /* Set up timecounter hardware, start it. */ + DMTIMER_WRITE4(sc, DMT_TSICR, DMT_TSICR_RESET); + while (DMTIMER_READ4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET) + continue; + + sc->tclr |= DMT_TCLR_START | DMT_TCLR_AUTOLOAD; + DMTIMER_WRITE4(sc, DMT_TLDR, 0); + DMTIMER_WRITE4(sc, DMT_TCRR, 0); + DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr); + + /* Register the timecounter. */ + sc->tc.tc_name = sc->tmr_name; + sc->tc.tc_get_timecount = dmtpps_get_timecount; + sc->tc.tc_counter_mask = ~0u; + sc->tc.tc_frequency = sysclk_freq; + sc->tc.tc_quality = 1000; + sc->tc.tc_priv = sc; + + tc_init(&sc->tc); + + /* + * Indicate our PPS capabilities. Have the kernel init its part of the + * pps_state struct and add its capabilities. + * + * While the hardware has a mode to capture each edge, it's not clear we + * can use it that way, because there's only a single interrupt/status + * bit to say something was captured, but not which edge it was. For + * now, just say we can only capture assert events (the positive-going + * edge of the pulse). + */ + mtx_init(&sc->pps_mtx, "dmtpps", NULL, MTX_DEF); + sc->pps_state.ppscap = PPS_CAPTUREASSERT; + sc->pps_state.driver_abi = PPS_ABI_VERSION; + sc->pps_state.driver_mtx = &sc->pps_mtx; + pps_init_abi(&sc->pps_state); + + /* + * Init the task that does deferred pps_event() processing after + * the polling routine has captured a pps pulse time. + */ + TASK_INIT(&sc->pps_task, 0, dmtpps_event, sc); + + /* Create the PPS cdev. */ + sc->pps_cdev = make_dev(&dmtpps_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, + PPS_CDEV_NAME); + sc->pps_cdev->si_drv1 = sc; + + if (bootverbose) + device_printf(sc->dev, "Using %s for PPS device /dev/%s\n", + sc->tmr_name, PPS_CDEV_NAME); + + return (0); +} + +static int +dmtpps_detach(device_t dev) +{ + + /* + * There is no way to remove a timecounter once it has been registered, + * even if it's not in use, so we can never detach. If we were + * dynamically loaded as a module this will prevent unloading. + */ + return (EBUSY); +} + +static device_method_t dmtpps_methods[] = { + DEVMETHOD(device_probe, dmtpps_probe), + DEVMETHOD(device_attach, dmtpps_attach), + DEVMETHOD(device_detach, dmtpps_detach), + { 0, 0 } +}; + +static driver_t dmtpps_driver = { + "am335x_dmtpps", + dmtpps_methods, + sizeof(struct dmtpps_softc), +}; + +static devclass_t dmtpps_devclass; + +DRIVER_MODULE(am335x_dmtpps, simplebus, dmtpps_driver, dmtpps_devclass, 0, 0); +MODULE_DEPEND(am335x_dmtpps, am335x_prcm, 1, 1, 1); + diff --git a/sys/arm/ti/am335x/files.am335x b/sys/arm/ti/am335x/files.am335x index 7293fd0..d0193e8 100644 --- a/sys/arm/ti/am335x/files.am335x +++ b/sys/arm/ti/am335x/files.am335x @@ -3,6 +3,7 @@ arm/ti/aintc.c standard arm/ti/am335x/am335x_dmtimer.c standard +arm/ti/am335x/am335x_dmtpps.c optional am335x_dmtpps arm/ti/am335x/am335x_gpio.c optional gpio arm/ti/am335x/am335x_lcd.c optional sc | vt arm/ti/am335x/am335x_lcd_syscons.c optional sc diff --git a/sys/arm/versatile/sp804.c b/sys/arm/versatile/sp804.c index a69c018..de05700 100644 --- a/sys/arm/versatile/sp804.c +++ b/sys/arm/versatile/sp804.c @@ -244,7 +244,7 @@ sp804_timer_attach(device_t dev) * Timer 1, timecounter */ sc->tc.tc_frequency = sc->sysclk_freq; - sc->tc.tc_name = "SP804 Time Counter"; + sc->tc.tc_name = "SP804-1"; sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount; sc->tc.tc_poll_pps = NULL; sc->tc.tc_counter_mask = ~0u; @@ -263,9 +263,7 @@ sp804_timer_attach(device_t dev) * Timer 2, event timer */ sc->et_enabled = 0; - sc->et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO); - sprintf(sc->et.et_name, "SP804 Event Timer %d", - device_get_unit(dev)); + sc->et.et_name = "SP804-2"; sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; sc->et.et_quality = 1000; sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR; diff --git a/sys/arm64/arm64/bus_machdep.c b/sys/arm64/arm64/bus_machdep.c index 25a675e..f6df4a1 100644 --- a/sys/arm64/arm64/bus_machdep.c +++ b/sys/arm64/arm64/bus_machdep.c @@ -49,6 +49,15 @@ void generic_bs_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, void generic_bs_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); +void generic_bs_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, + bus_size_t); +void generic_bs_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, + bus_size_t); +void generic_bs_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, + bus_size_t); +void generic_bs_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, + bus_size_t); + void generic_bs_w_1(void *, bus_space_handle_t, bus_size_t, uint8_t); void generic_bs_w_2(void *, bus_space_handle_t, bus_size_t, uint16_t); void generic_bs_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t); @@ -63,6 +72,15 @@ void generic_bs_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, void generic_bs_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, bus_size_t); +void generic_bs_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, + bus_size_t); +void generic_bs_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, + bus_size_t); +void generic_bs_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, + bus_size_t); +void generic_bs_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, + bus_size_t); + static int generic_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) @@ -126,6 +144,12 @@ struct bus_space memmap_bus = { .bs_rm_4 = generic_bs_rm_4, .bs_rm_8 = generic_bs_rm_8, + /* read region */ + .bs_rr_1 = generic_bs_rr_1, + .bs_rr_2 = generic_bs_rr_2, + .bs_rr_4 = generic_bs_rr_4, + .bs_rr_8 = generic_bs_rr_8, + /* write single */ .bs_w_1 = generic_bs_w_1, .bs_w_2 = generic_bs_w_2, @@ -139,10 +163,10 @@ struct bus_space memmap_bus = { .bs_wm_8 = generic_bs_wm_8, /* write region */ - .bs_wr_1 = NULL, - .bs_wr_2 = NULL, - .bs_wr_4 = NULL, - .bs_wr_8 = NULL, + .bs_wr_1 = generic_bs_wr_1, + .bs_wr_2 = generic_bs_wr_2, + .bs_wr_4 = generic_bs_wr_4, + .bs_wr_8 = generic_bs_wr_8, /* set multiple */ .bs_sm_1 = NULL, diff --git a/sys/arm64/arm64/bus_space_asm.S b/sys/arm64/arm64/bus_space_asm.S index 20d4128..d919bd5 100644 --- a/sys/arm64/arm64/bus_space_asm.S +++ b/sys/arm64/arm64/bus_space_asm.S @@ -133,6 +133,90 @@ ENTRY(generic_bs_rm_8) 2: ret END(generic_bs_rm_8) +ENTRY(generic_bs_rr_1) + /* Is there is anything to read. */ + cbz x4, 2f + + /* Calculate the device address. */ + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Read the data. */ +1: ldrb w1, [x0], #1 + strb w1, [x3], #1 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_rr_1) + +ENTRY(generic_bs_rr_2) + /* Is there is anything to read. */ + cbz x4, 2f + + /* Calculate the device address. */ + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Read the data. */ +1: ldrh w1, [x0], #2 + strh w1, [x3], #2 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_rr_2) + +ENTRY(generic_bs_rr_4) + /* Is there is anything to read. */ + cbz x4, 2f + + /* Calculate the device address. */ + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Read the data. */ +1: ldr w1, [x0], #4 + str w1, [x3], #4 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_rr_4) + +ENTRY(generic_bs_rr_8) + /* Is there is anything to read. */ + cbz x4, 2f + + /* Calculate the device address. */ + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Read the data. */ +1: ldr x1, [x0], #8 + str x1, [x3], #8 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_rr_8) + ENTRY(generic_bs_w_1) strb w3, [x1, x2] @@ -233,3 +317,83 @@ ENTRY(generic_bs_wm_8) 2: ret END(generic_bs_wm_8) + +ENTRY(generic_bs_wr_1) + /* Is there is anything to write. */ + cbz x4, 2f + + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Write the data */ +1: ldrb w1, [x3], #1 + strb w1, [x0], #1 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_wr_1) + +ENTRY(generic_bs_wr_2) + /* Is there is anything to write. */ + cbz x4, 2f + + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Write the data */ +1: ldrh w1, [x3], #2 + strh w1, [x0], #2 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_wr_2) + +ENTRY(generic_bs_wr_4) + /* Is there is anything to write. */ + cbz x4, 2f + + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Write the data */ +1: ldr w1, [x3], #4 + str w1, [x0], #4 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_wr_4) + +ENTRY(generic_bs_wr_8) + /* Is there is anything to write. */ + cbz x4, 2f + + add x0, x1, x2 + /* + * x0 = The device address. + * x3 = The kernel address. + * x4 = Count + */ + + /* Write the data */ +1: ldr x1, [x3], #8 + str x1, [x0], #8 + subs x4, x4, #1 + b.ne 1b + +2: ret +END(generic_bs_wr_8) diff --git a/sys/arm64/arm64/exception.S b/sys/arm64/arm64/exception.S index 4f457da..b05941f 100644 --- a/sys/arm64/arm64/exception.S +++ b/sys/arm64/arm64/exception.S @@ -104,7 +104,7 @@ __FBSDID("$FreeBSD$"); /* Read the current thread flags */ 1: ldr x1, [x18, #PC_CURTHREAD] /* Load curthread */ - ldr x2, [x1, #TD_FLAGS]! /* TODO: No need for the ! but clang fails without it */ + ldr x2, [x1, #TD_FLAGS] /* Check if we have either bits set */ mov x3, #((TDF_ASTPENDING|TDF_NEEDRESCHED) >> 8) diff --git a/sys/arm64/arm64/trap.c b/sys/arm64/arm64/trap.c index 41e92a6..fa9aaa8 100644 --- a/sys/arm64/arm64/trap.c +++ b/sys/arm64/arm64/trap.c @@ -229,6 +229,21 @@ data_abort(struct trapframe *frame, uint64_t esr, int lower) userret(td, frame); } +static void +print_registers(struct trapframe *frame) +{ + u_int reg; + + for (reg = 0; reg < 31; reg++) { + printf(" %sx%d: %16lx\n", (reg < 10) ? " " : "", reg, + frame->tf_x[reg]); + } + printf(" sp: %16lx\n", frame->tf_sp); + printf(" lr: %16lx\n", frame->tf_lr); + printf(" elr: %16lx\n", frame->tf_elr); + printf("spsr: %16lx\n", frame->tf_spsr); +} + void do_el1h_sync(struct trapframe *frame) { @@ -265,6 +280,7 @@ do_el1h_sync(struct trapframe *frame) switch(exception) { case EXCP_FP_SIMD: case EXCP_TRAP_FP: + print_registers(frame); panic("VFP exception in the kernel"); case EXCP_DATA_ABORT: data_abort(frame, esr, 0); @@ -286,11 +302,30 @@ do_el1h_sync(struct trapframe *frame) #endif break; default: + print_registers(frame); panic("Unknown kernel exception %x esr_el1 %lx\n", exception, esr); } } +/* + * We get EXCP_UNKNOWN from QEMU when executing zeroed memory. For now turn + * this into a SIGILL. + */ +static void +el0_excp_unknown(struct trapframe *frame) +{ + struct thread *td; + uint64_t far; + + td = curthread; + far = READ_SPECIALREG(far_el1); + printf("el0 EXCP_UNKNOWN exception\n"); + print_registers(frame); + call_trapsignal(td, SIGILL, ILL_ILLTRP, (void *)far); + userret(td, frame); +} + void do_el0_sync(struct trapframe *frame) { @@ -332,7 +367,11 @@ do_el0_sync(struct trapframe *frame) case EXCP_DATA_ABORT: data_abort(frame, esr, 1); break; + case EXCP_UNKNOWN: + el0_excp_unknown(frame); + break; default: + print_registers(frame); panic("Unknown userland exception %x esr_el1 %lx\n", exception, esr); } diff --git a/sys/boot/kshim/bsd_kernel.h b/sys/boot/kshim/bsd_kernel.h index 0e40fb0..aba8131 100644 --- a/sys/boot/kshim/bsd_kernel.h +++ b/sys/boot/kshim/bsd_kernel.h @@ -43,7 +43,8 @@ #define M_USBDEV 0 #define USB_PROC_MAX 3 #define USB_BUS_GIANT_PROC(bus) (usb_process + 2) -#define USB_BUS_NON_GIANT_PROC(bus) (usb_process + 2) +#define USB_BUS_NON_GIANT_BULK_PROC(bus) (usb_process + 2) +#define USB_BUS_NON_GIANT_ISOC_PROC(bus) (usb_process + 2) #define USB_BUS_EXPLORE_PROC(bus) (usb_process + 0) #define USB_BUS_CONTROL_XFER_PROC(bus) (usb_process + 1) #define SYSCTL_DECL(...) diff --git a/sys/boot/uboot/fdt/uboot_fdt.c b/sys/boot/uboot/fdt/uboot_fdt.c index 86f46e9..6b646f6 100644 --- a/sys/boot/uboot/fdt/uboot_fdt.c +++ b/sys/boot/uboot/fdt/uboot_fdt.c @@ -69,10 +69,11 @@ fdt_platform_load_dtb(void) } /* - * If the U-boot environment contains a variable giving the name of a - * file, use it if we can load and validate it. + * Try to get FDT filename first from loader env and then from u-boot env */ - s = ub_env_get("fdtfile"); + s = getenv("fdt_file"); + if (s == NULL) + s = ub_env_get("fdtfile"); if (s == NULL) s = ub_env_get("fdt_file"); if (s != NULL && *s != '\0') { diff --git a/sys/cam/ctl/README.ctl.txt b/sys/cam/ctl/README.ctl.txt index a6de201..d4dc938 100644 --- a/sys/cam/ctl/README.ctl.txt +++ b/sys/cam/ctl/README.ctl.txt @@ -366,16 +366,6 @@ This is a CTL frontend port that is also a CAM SIM. The idea is that this frontend allows for using CTL without any target-capable hardware. So any LUNs you create in CTL are visible via this port. - -ctl_frontend_internal.c -ctl_frontend_internal.h: ------------------------ - -This is a frontend port written for Copan to do some system-specific tasks -that required sending commands into CTL from inside the kernel. This isn't -entirely relevant to FreeBSD in general, but can perhaps be repurposed or -removed later. - ctl_ha.h: -------- diff --git a/sys/cam/ctl/ctl.c b/sys/cam/ctl/ctl.c index bdf5e6a..9141fc8 100644 --- a/sys/cam/ctl/ctl.c +++ b/sys/cam/ctl/ctl.c @@ -72,7 +72,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_util.h> #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_ioctl.h> @@ -383,18 +382,7 @@ static int ctl_init(void); void ctl_shutdown(void); static int ctl_open(struct cdev *dev, int flags, int fmt, struct thread *td); static int ctl_close(struct cdev *dev, int flags, int fmt, struct thread *td); -static void ctl_ioctl_online(void *arg); -static void ctl_ioctl_offline(void *arg); -static int ctl_ioctl_lun_enable(void *arg, int lun_id); -static int ctl_ioctl_lun_disable(void *arg, int lun_id); -static int ctl_ioctl_do_datamove(struct ctl_scsiio *ctsio); static int ctl_serialize_other_sc_cmd(struct ctl_scsiio *ctsio); -static int ctl_ioctl_submit_wait(union ctl_io *io); -static void ctl_ioctl_datamove(union ctl_io *io); -static void ctl_ioctl_done(union ctl_io *io); -static void ctl_ioctl_hard_startstop_callback(void *arg, - struct cfi_metatask *metatask); -static void ctl_ioctl_bbrread_callback(void *arg,struct cfi_metatask *metatask); static int ctl_ioctl_fill_ooa(struct ctl_lun *lun, uint32_t *cur_fill_num, struct ctl_ooa *ooa_hdr, struct ctl_ooa_entry *kern_entries); @@ -529,11 +517,6 @@ static moduledata_t ctl_moduledata = { DECLARE_MODULE(ctl, ctl_moduledata, SI_SUB_CONFIGURE, SI_ORDER_THIRD); MODULE_VERSION(ctl, 1); -static struct ctl_frontend ioctl_frontend = -{ - .name = "ioctl", -}; - #ifdef notyet static void ctl_isc_handler_finish_xfer(struct ctl_softc *ctl_softc, @@ -1064,7 +1047,6 @@ ctl_init(void) { struct ctl_softc *softc; void *other_pool; - struct ctl_port *port; int i, error, retval; //int isc_retval; @@ -1189,32 +1171,6 @@ ctl_init(void) return (error); } - /* - * Initialize the ioctl front end. - */ - ctl_frontend_register(&ioctl_frontend); - port = &softc->ioctl_info.port; - port->frontend = &ioctl_frontend; - sprintf(softc->ioctl_info.port_name, "ioctl"); - port->port_type = CTL_PORT_IOCTL; - port->num_requested_ctl_io = 100; - port->port_name = softc->ioctl_info.port_name; - port->port_online = ctl_ioctl_online; - port->port_offline = ctl_ioctl_offline; - port->onoff_arg = &softc->ioctl_info; - port->lun_enable = ctl_ioctl_lun_enable; - port->lun_disable = ctl_ioctl_lun_disable; - port->targ_lun_arg = &softc->ioctl_info; - port->fe_datamove = ctl_ioctl_datamove; - port->fe_done = ctl_ioctl_done; - port->max_targets = 15; - port->max_target_id = 15; - - if (ctl_port_register(&softc->ioctl_info.port) != 0) { - printf("ctl: ioctl front end registration failed, will " - "continue anyway\n"); - } - SYSCTL_ADD_PROC(&softc->sysctl_ctx,SYSCTL_CHILDREN(softc->sysctl_tree), OID_AUTO, "ha_state", CTLTYPE_INT | CTLFLAG_RWTUN, softc, 0, ctl_ha_state_sysctl, "I", "HA state for this head"); @@ -1238,9 +1194,6 @@ ctl_shutdown(void) softc = (struct ctl_softc *)control_softc; - if (ctl_port_deregister(&softc->ioctl_info.port) != 0) - printf("ctl: ioctl front end deregistration failed\n"); - mtx_lock(&softc->ctl_lock); /* @@ -1253,8 +1206,6 @@ ctl_shutdown(void) mtx_unlock(&softc->ctl_lock); - ctl_frontend_deregister(&ioctl_frontend); - #if 0 ctl_shutdown_thread(softc->work_thread); mtx_destroy(&softc->queue_lock); @@ -1426,26 +1377,6 @@ ctl_port_list(struct ctl_port_entry *entries, int num_entries_alloced, return (retval); } -static void -ctl_ioctl_online(void *arg) -{ - struct ctl_ioctl_info *ioctl_info; - - ioctl_info = (struct ctl_ioctl_info *)arg; - - ioctl_info->flags |= CTL_IOCTL_FLAG_ENABLED; -} - -static void -ctl_ioctl_offline(void *arg) -{ - struct ctl_ioctl_info *ioctl_info; - - ioctl_info = (struct ctl_ioctl_info *)arg; - - ioctl_info->flags &= ~CTL_IOCTL_FLAG_ENABLED; -} - /* * Remove an initiator by port number and initiator ID. * Returns 0 for success, -1 for failure. @@ -1641,181 +1572,6 @@ ctl_create_iid(struct ctl_port *port, int iid, uint8_t *buf) } } -static int -ctl_ioctl_lun_enable(void *arg, int lun_id) -{ - return (0); -} - -static int -ctl_ioctl_lun_disable(void *arg, int lun_id) -{ - return (0); -} - -/* - * Data movement routine for the CTL ioctl frontend port. - */ -static int -ctl_ioctl_do_datamove(struct ctl_scsiio *ctsio) -{ - struct ctl_sg_entry *ext_sglist, *kern_sglist; - struct ctl_sg_entry ext_entry, kern_entry; - int ext_sglen, ext_sg_entries, kern_sg_entries; - int ext_sg_start, ext_offset; - int len_to_copy, len_copied; - int kern_watermark, ext_watermark; - int ext_sglist_malloced; - int i, j; - - ext_sglist_malloced = 0; - ext_sg_start = 0; - ext_offset = 0; - - CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove\n")); - - /* - * If this flag is set, fake the data transfer. - */ - if (ctsio->io_hdr.flags & CTL_FLAG_NO_DATAMOVE) { - ctsio->ext_data_filled = ctsio->ext_data_len; - goto bailout; - } - - /* - * To simplify things here, if we have a single buffer, stick it in - * a S/G entry and just make it a single entry S/G list. - */ - if (ctsio->io_hdr.flags & CTL_FLAG_EDPTR_SGLIST) { - int len_seen; - - ext_sglen = ctsio->ext_sg_entries * sizeof(*ext_sglist); - - ext_sglist = (struct ctl_sg_entry *)malloc(ext_sglen, M_CTL, - M_WAITOK); - ext_sglist_malloced = 1; - if (copyin(ctsio->ext_data_ptr, ext_sglist, - ext_sglen) != 0) { - ctl_set_internal_failure(ctsio, - /*sks_valid*/ 0, - /*retry_count*/ 0); - goto bailout; - } - ext_sg_entries = ctsio->ext_sg_entries; - len_seen = 0; - for (i = 0; i < ext_sg_entries; i++) { - if ((len_seen + ext_sglist[i].len) >= - ctsio->ext_data_filled) { - ext_sg_start = i; - ext_offset = ctsio->ext_data_filled - len_seen; - break; - } - len_seen += ext_sglist[i].len; - } - } else { - ext_sglist = &ext_entry; - ext_sglist->addr = ctsio->ext_data_ptr; - ext_sglist->len = ctsio->ext_data_len; - ext_sg_entries = 1; - ext_sg_start = 0; - ext_offset = ctsio->ext_data_filled; - } - - if (ctsio->kern_sg_entries > 0) { - kern_sglist = (struct ctl_sg_entry *)ctsio->kern_data_ptr; - kern_sg_entries = ctsio->kern_sg_entries; - } else { - kern_sglist = &kern_entry; - kern_sglist->addr = ctsio->kern_data_ptr; - kern_sglist->len = ctsio->kern_data_len; - kern_sg_entries = 1; - } - - - kern_watermark = 0; - ext_watermark = ext_offset; - len_copied = 0; - for (i = ext_sg_start, j = 0; - i < ext_sg_entries && j < kern_sg_entries;) { - uint8_t *ext_ptr, *kern_ptr; - - len_to_copy = MIN(ext_sglist[i].len - ext_watermark, - kern_sglist[j].len - kern_watermark); - - ext_ptr = (uint8_t *)ext_sglist[i].addr; - ext_ptr = ext_ptr + ext_watermark; - if (ctsio->io_hdr.flags & CTL_FLAG_BUS_ADDR) { - /* - * XXX KDM fix this! - */ - panic("need to implement bus address support"); -#if 0 - kern_ptr = bus_to_virt(kern_sglist[j].addr); -#endif - } else - kern_ptr = (uint8_t *)kern_sglist[j].addr; - kern_ptr = kern_ptr + kern_watermark; - - kern_watermark += len_to_copy; - ext_watermark += len_to_copy; - - if ((ctsio->io_hdr.flags & CTL_FLAG_DATA_MASK) == - CTL_FLAG_DATA_IN) { - CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: copying %d " - "bytes to user\n", len_to_copy)); - CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: from %p " - "to %p\n", kern_ptr, ext_ptr)); - if (copyout(kern_ptr, ext_ptr, len_to_copy) != 0) { - ctl_set_internal_failure(ctsio, - /*sks_valid*/ 0, - /*retry_count*/ 0); - goto bailout; - } - } else { - CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: copying %d " - "bytes from user\n", len_to_copy)); - CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: from %p " - "to %p\n", ext_ptr, kern_ptr)); - if (copyin(ext_ptr, kern_ptr, len_to_copy)!= 0){ - ctl_set_internal_failure(ctsio, - /*sks_valid*/ 0, - /*retry_count*/0); - goto bailout; - } - } - - len_copied += len_to_copy; - - if (ext_sglist[i].len == ext_watermark) { - i++; - ext_watermark = 0; - } - - if (kern_sglist[j].len == kern_watermark) { - j++; - kern_watermark = 0; - } - } - - ctsio->ext_data_filled += len_copied; - - CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: ext_sg_entries: %d, " - "kern_sg_entries: %d\n", ext_sg_entries, - kern_sg_entries)); - CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: ext_data_len = %d, " - "kern_data_len = %d\n", ctsio->ext_data_len, - ctsio->kern_data_len)); - - - /* XXX KDM set residual?? */ -bailout: - - if (ext_sglist_malloced != 0) - free(ext_sglist, M_CTL); - - return (CTL_RETVAL_COMPLETE); -} - /* * Serialize a command that went down the "wrong" side, and so was sent to * this controller for execution. The logic is a little different than the @@ -1982,149 +1738,6 @@ ctl_serialize_other_sc_cmd(struct ctl_scsiio *ctsio) return (retval); } -static int -ctl_ioctl_submit_wait(union ctl_io *io) -{ - struct ctl_fe_ioctl_params params; - ctl_fe_ioctl_state last_state; - int done, retval; - - retval = 0; - - bzero(¶ms, sizeof(params)); - - mtx_init(¶ms.ioctl_mtx, "ctliocmtx", NULL, MTX_DEF); - cv_init(¶ms.sem, "ctlioccv"); - params.state = CTL_IOCTL_INPROG; - last_state = params.state; - - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr = ¶ms; - - CTL_DEBUG_PRINT(("ctl_ioctl_submit_wait\n")); - - /* This shouldn't happen */ - if ((retval = ctl_queue(io)) != CTL_RETVAL_COMPLETE) - return (retval); - - done = 0; - - do { - mtx_lock(¶ms.ioctl_mtx); - /* - * Check the state here, and don't sleep if the state has - * already changed (i.e. wakeup has already occured, but we - * weren't waiting yet). - */ - if (params.state == last_state) { - /* XXX KDM cv_wait_sig instead? */ - cv_wait(¶ms.sem, ¶ms.ioctl_mtx); - } - last_state = params.state; - - switch (params.state) { - case CTL_IOCTL_INPROG: - /* Why did we wake up? */ - /* XXX KDM error here? */ - mtx_unlock(¶ms.ioctl_mtx); - break; - case CTL_IOCTL_DATAMOVE: - CTL_DEBUG_PRINT(("got CTL_IOCTL_DATAMOVE\n")); - - /* - * change last_state back to INPROG to avoid - * deadlock on subsequent data moves. - */ - params.state = last_state = CTL_IOCTL_INPROG; - - mtx_unlock(¶ms.ioctl_mtx); - ctl_ioctl_do_datamove(&io->scsiio); - /* - * Note that in some cases, most notably writes, - * this will queue the I/O and call us back later. - * In other cases, generally reads, this routine - * will immediately call back and wake us up, - * probably using our own context. - */ - io->scsiio.be_move_done(io); - break; - case CTL_IOCTL_DONE: - mtx_unlock(¶ms.ioctl_mtx); - CTL_DEBUG_PRINT(("got CTL_IOCTL_DONE\n")); - done = 1; - break; - default: - mtx_unlock(¶ms.ioctl_mtx); - /* XXX KDM error here? */ - break; - } - } while (done == 0); - - mtx_destroy(¶ms.ioctl_mtx); - cv_destroy(¶ms.sem); - - return (CTL_RETVAL_COMPLETE); -} - -static void -ctl_ioctl_datamove(union ctl_io *io) -{ - struct ctl_fe_ioctl_params *params; - - params = (struct ctl_fe_ioctl_params *) - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; - - mtx_lock(¶ms->ioctl_mtx); - params->state = CTL_IOCTL_DATAMOVE; - cv_broadcast(¶ms->sem); - mtx_unlock(¶ms->ioctl_mtx); -} - -static void -ctl_ioctl_done(union ctl_io *io) -{ - struct ctl_fe_ioctl_params *params; - - params = (struct ctl_fe_ioctl_params *) - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; - - mtx_lock(¶ms->ioctl_mtx); - params->state = CTL_IOCTL_DONE; - cv_broadcast(¶ms->sem); - mtx_unlock(¶ms->ioctl_mtx); -} - -static void -ctl_ioctl_hard_startstop_callback(void *arg, struct cfi_metatask *metatask) -{ - struct ctl_fe_ioctl_startstop_info *sd_info; - - sd_info = (struct ctl_fe_ioctl_startstop_info *)arg; - - sd_info->hs_info.status = metatask->status; - sd_info->hs_info.total_luns = metatask->taskinfo.startstop.total_luns; - sd_info->hs_info.luns_complete = - metatask->taskinfo.startstop.luns_complete; - sd_info->hs_info.luns_failed = metatask->taskinfo.startstop.luns_failed; - - cv_broadcast(&sd_info->sem); -} - -static void -ctl_ioctl_bbrread_callback(void *arg, struct cfi_metatask *metatask) -{ - struct ctl_fe_ioctl_bbrread_info *fe_bbr_info; - - fe_bbr_info = (struct ctl_fe_ioctl_bbrread_info *)arg; - - mtx_lock(fe_bbr_info->lock); - fe_bbr_info->bbr_info->status = metatask->status; - fe_bbr_info->bbr_info->bbr_status = metatask->taskinfo.bbrread.status; - fe_bbr_info->wakeup_done = 1; - mtx_unlock(fe_bbr_info->lock); - - cv_broadcast(&fe_bbr_info->sem); -} - /* * Returns 0 for success, errno for failure. */ @@ -2367,57 +1980,9 @@ ctl_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flag, retval = 0; switch (cmd) { - case CTL_IO: { - union ctl_io *io; - void *pool_tmp; - - /* - * If we haven't been "enabled", don't allow any SCSI I/O - * to this FETD. - */ - if ((softc->ioctl_info.flags & CTL_IOCTL_FLAG_ENABLED) == 0) { - retval = EPERM; - break; - } - - io = ctl_alloc_io(softc->ioctl_info.port.ctl_pool_ref); - - /* - * Need to save the pool reference so it doesn't get - * spammed by the user's ctl_io. - */ - pool_tmp = io->io_hdr.pool; - memcpy(io, (void *)addr, sizeof(*io)); - io->io_hdr.pool = pool_tmp; - - /* - * No status yet, so make sure the status is set properly. - */ - io->io_hdr.status = CTL_STATUS_NONE; - - /* - * The user sets the initiator ID, target and LUN IDs. - */ - io->io_hdr.nexus.targ_port = softc->ioctl_info.port.targ_port; - io->io_hdr.flags |= CTL_FLAG_USER_REQ; - if ((io->io_hdr.io_type == CTL_IO_SCSI) - && (io->scsiio.tag_type != CTL_TAG_UNTAGGED)) - io->scsiio.tag_num = softc->ioctl_info.cur_tag_num++; - - retval = ctl_ioctl_submit_wait(io); - - if (retval != 0) { - ctl_free_io(io); - break; - } - - memcpy((void *)addr, io, sizeof(*io)); - - /* return this to our pool */ - ctl_free_io(io); - + case CTL_IO: + retval = ctl_ioctl_io(dev, cmd, addr, flag, td); break; - } case CTL_ENABLE_PORT: case CTL_DISABLE_PORT: case CTL_SET_PORT_WWNS: { @@ -2724,103 +2289,6 @@ ctl_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flag, break; } - case CTL_HARD_START: - case CTL_HARD_STOP: { - struct ctl_fe_ioctl_startstop_info ss_info; - struct cfi_metatask *metatask; - struct mtx hs_mtx; - - mtx_init(&hs_mtx, "HS Mutex", NULL, MTX_DEF); - - cv_init(&ss_info.sem, "hard start/stop cv" ); - - metatask = cfi_alloc_metatask(/*can_wait*/ 1); - if (metatask == NULL) { - retval = ENOMEM; - mtx_destroy(&hs_mtx); - break; - } - - if (cmd == CTL_HARD_START) - metatask->tasktype = CFI_TASK_STARTUP; - else - metatask->tasktype = CFI_TASK_SHUTDOWN; - - metatask->callback = ctl_ioctl_hard_startstop_callback; - metatask->callback_arg = &ss_info; - - cfi_action(metatask); - - /* Wait for the callback */ - mtx_lock(&hs_mtx); - cv_wait_sig(&ss_info.sem, &hs_mtx); - mtx_unlock(&hs_mtx); - - /* - * All information has been copied from the metatask by the - * time cv_broadcast() is called, so we free the metatask here. - */ - cfi_free_metatask(metatask); - - memcpy((void *)addr, &ss_info.hs_info, sizeof(ss_info.hs_info)); - - mtx_destroy(&hs_mtx); - break; - } - case CTL_BBRREAD: { - struct ctl_bbrread_info *bbr_info; - struct ctl_fe_ioctl_bbrread_info fe_bbr_info; - struct mtx bbr_mtx; - struct cfi_metatask *metatask; - - bbr_info = (struct ctl_bbrread_info *)addr; - - bzero(&fe_bbr_info, sizeof(fe_bbr_info)); - - bzero(&bbr_mtx, sizeof(bbr_mtx)); - mtx_init(&bbr_mtx, "BBR Mutex", NULL, MTX_DEF); - - fe_bbr_info.bbr_info = bbr_info; - fe_bbr_info.lock = &bbr_mtx; - - cv_init(&fe_bbr_info.sem, "BBR read cv"); - metatask = cfi_alloc_metatask(/*can_wait*/ 1); - - if (metatask == NULL) { - mtx_destroy(&bbr_mtx); - cv_destroy(&fe_bbr_info.sem); - retval = ENOMEM; - break; - } - metatask->tasktype = CFI_TASK_BBRREAD; - metatask->callback = ctl_ioctl_bbrread_callback; - metatask->callback_arg = &fe_bbr_info; - metatask->taskinfo.bbrread.lun_num = bbr_info->lun_num; - metatask->taskinfo.bbrread.lba = bbr_info->lba; - metatask->taskinfo.bbrread.len = bbr_info->len; - - cfi_action(metatask); - - mtx_lock(&bbr_mtx); - while (fe_bbr_info.wakeup_done == 0) - cv_wait_sig(&fe_bbr_info.sem, &bbr_mtx); - mtx_unlock(&bbr_mtx); - - bbr_info->status = metatask->status; - bbr_info->bbr_status = metatask->taskinfo.bbrread.status; - bbr_info->scsi_status = metatask->taskinfo.bbrread.scsi_status; - memcpy(&bbr_info->sense_data, - &metatask->taskinfo.bbrread.sense_data, - MIN(sizeof(bbr_info->sense_data), - sizeof(metatask->taskinfo.bbrread.sense_data))); - - cfi_free_metatask(metatask); - - mtx_destroy(&bbr_mtx); - cv_destroy(&fe_bbr_info.sem); - - break; - } case CTL_DELAY_IO: { struct ctl_io_delay_info *delay_info; #ifdef CTL_IO_DELAY diff --git a/sys/cam/ctl/ctl.h b/sys/cam/ctl/ctl.h index b1d9118..2826742 100644 --- a/sys/cam/ctl/ctl.h +++ b/sys/cam/ctl/ctl.h @@ -194,6 +194,8 @@ void ctl_portDB_changed(int portnum); #ifdef notyet void ctl_init_isc_msg(void); #endif +int ctl_ioctl_io(struct cdev *dev, u_long cmd, caddr_t addr, int flag, + struct thread *td); /* * KPI to manipulate LUN/port options diff --git a/sys/cam/ctl/ctl_backend.c b/sys/cam/ctl/ctl_backend.c index cabecb7..ae5034b 100644 --- a/sys/cam/ctl/ctl_backend.c +++ b/sys/cam/ctl/ctl_backend.c @@ -55,7 +55,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> #include <cam/ctl/ctl_backend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_ioctl.h> #include <cam/ctl/ctl_ha.h> #include <cam/ctl/ctl_private.h> diff --git a/sys/cam/ctl/ctl_backend_block.c b/sys/cam/ctl/ctl_backend_block.c index 5bb3121..65d0491 100644 --- a/sys/cam/ctl/ctl_backend_block.c +++ b/sys/cam/ctl/ctl_backend_block.c @@ -84,7 +84,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_backend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_ioctl.h> #include <cam/ctl/ctl_scsi_all.h> #include <cam/ctl/ctl_error.h> @@ -170,7 +169,6 @@ struct ctl_be_block_lun { uint64_t size_blocks; uint64_t size_bytes; uint32_t blocksize; - int blocksize_shift; uint16_t pblockexp; uint16_t pblockoff; uint16_t ublockexp; @@ -773,7 +771,7 @@ ctl_be_block_gls_file(struct ctl_be_block_lun *be_lun, DPRINTF("entered\n"); - off = roff = ((off_t)lbalen->lba) << be_lun->blocksize_shift; + off = roff = ((off_t)lbalen->lba) * be_lun->blocksize; vn_lock(be_lun->vn, LK_SHARED | LK_RETRY); error = VOP_IOCTL(be_lun->vn, FIOSEEKHOLE, &off, 0, curthread->td_ucred, curthread); @@ -791,10 +789,9 @@ ctl_be_block_gls_file(struct ctl_be_block_lun *be_lun, } VOP_UNLOCK(be_lun->vn, 0); - off >>= be_lun->blocksize_shift; data = (struct scsi_get_lba_status_data *)io->scsiio.kern_data_ptr; scsi_u64to8b(lbalen->lba, data->descr[0].addr); - scsi_ulto4b(MIN(UINT32_MAX, off - lbalen->lba), + scsi_ulto4b(MIN(UINT32_MAX, off / be_lun->blocksize - lbalen->lba), data->descr[0].length); data->descr[0].status = status; @@ -816,14 +813,14 @@ ctl_be_block_getattr_file(struct ctl_be_block_lun *be_lun, const char *attrname) if (strcmp(attrname, "blocksused") == 0) { error = VOP_GETATTR(be_lun->vn, &vattr, curthread->td_ucred); if (error == 0) - val = vattr.va_bytes >> be_lun->blocksize_shift; + val = vattr.va_bytes / be_lun->blocksize; } if (strcmp(attrname, "blocksavail") == 0 && (be_lun->vn->v_iflag & VI_DOOMED) == 0) { error = VFS_STATFS(be_lun->vn->v_mount, &statfs); if (error == 0) - val = (statfs.f_bavail * statfs.f_bsize) >> - be_lun->blocksize_shift; + val = statfs.f_bavail * statfs.f_bsize / + be_lun->blocksize; } VOP_UNLOCK(be_lun->vn, 0); return (val); @@ -934,7 +931,7 @@ ctl_be_block_gls_zvol(struct ctl_be_block_lun *be_lun, DPRINTF("entered\n"); - off = roff = ((off_t)lbalen->lba) << be_lun->blocksize_shift; + off = roff = ((off_t)lbalen->lba) * be_lun->blocksize; error = (*dev_data->csw->d_ioctl)(dev_data->cdev, FIOSEEKHOLE, (caddr_t)&off, FREAD, curthread); if (error == 0 && off > roff) @@ -950,10 +947,9 @@ ctl_be_block_gls_zvol(struct ctl_be_block_lun *be_lun, } } - off >>= be_lun->blocksize_shift; data = (struct scsi_get_lba_status_data *)io->scsiio.kern_data_ptr; scsi_u64to8b(lbalen->lba, data->descr[0].addr); - scsi_ulto4b(MIN(UINT32_MAX, off - lbalen->lba), + scsi_ulto4b(MIN(UINT32_MAX, off / be_lun->blocksize - lbalen->lba), data->descr[0].length); data->descr[0].status = status; @@ -1866,7 +1862,7 @@ ctl_be_block_open_dev(struct ctl_be_block_lun *be_lun, struct ctl_lun_req *req) struct cdevsw *devsw; char *value; int error, atomic, maxio, unmap; - off_t ps, pss, po, pos, us, uss, uo, uos; + off_t ps, pss, po, pos, us, uss, uo, uos, tmp; params = &be_lun->params; @@ -1909,8 +1905,7 @@ ctl_be_block_open_dev(struct ctl_be_block_lun *be_lun, struct ctl_lun_req *req) return (ENODEV); } - error = devsw->d_ioctl(dev, DIOCGSECTORSIZE, - (caddr_t)&be_lun->blocksize, FREAD, + error = devsw->d_ioctl(dev, DIOCGSECTORSIZE, (caddr_t)&tmp, FREAD, curthread); if (error) { snprintf(req->error_str, sizeof(req->error_str), @@ -1925,15 +1920,9 @@ ctl_be_block_open_dev(struct ctl_be_block_lun *be_lun, struct ctl_lun_req *req) * the user is asking for is an even multiple of the underlying * device's blocksize. */ - if ((params->blocksize_bytes != 0) - && (params->blocksize_bytes > be_lun->blocksize)) { - uint32_t bs_multiple, tmp_blocksize; - - bs_multiple = params->blocksize_bytes / be_lun->blocksize; - - tmp_blocksize = bs_multiple * be_lun->blocksize; - - if (tmp_blocksize == params->blocksize_bytes) { + if ((params->blocksize_bytes != 0) && + (params->blocksize_bytes >= tmp)) { + if (params->blocksize_bytes % tmp == 0) { be_lun->blocksize = params->blocksize_bytes; } else { snprintf(req->error_str, sizeof(req->error_str), @@ -1944,17 +1933,16 @@ ctl_be_block_open_dev(struct ctl_be_block_lun *be_lun, struct ctl_lun_req *req) return (EINVAL); } - } else if ((params->blocksize_bytes != 0) - && (params->blocksize_bytes != be_lun->blocksize)) { + } else if (params->blocksize_bytes != 0) { snprintf(req->error_str, sizeof(req->error_str), "requested blocksize %u < backing device " "blocksize %u", params->blocksize_bytes, be_lun->blocksize); return (EINVAL); - } + } else + be_lun->blocksize = tmp; - error = devsw->d_ioctl(dev, DIOCGMEDIASIZE, - (caddr_t)&be_lun->size_bytes, FREAD, + error = devsw->d_ioctl(dev, DIOCGMEDIASIZE, (caddr_t)&tmp, FREAD, curthread); if (error) { snprintf(req->error_str, sizeof(req->error_str), @@ -1965,7 +1953,7 @@ ctl_be_block_open_dev(struct ctl_be_block_lun *be_lun, struct ctl_lun_req *req) } if (params->lun_size_bytes != 0) { - if (params->lun_size_bytes > be_lun->size_bytes) { + if (params->lun_size_bytes > tmp) { snprintf(req->error_str, sizeof(req->error_str), "requested LUN size %ju > backing device " "size %ju", @@ -1975,7 +1963,8 @@ ctl_be_block_open_dev(struct ctl_be_block_lun *be_lun, struct ctl_lun_req *req) } be_lun->size_bytes = params->lun_size_bytes; - } + } else + be_lun->size_bytes = tmp; error = devsw->d_ioctl(dev, DIOCGSTRIPESIZE, (caddr_t)&ps, FREAD, curthread); @@ -2160,14 +2149,8 @@ ctl_be_block_open(struct ctl_be_block_softc *softc, } VOP_UNLOCK(be_lun->vn, 0); - if (error != 0) { + if (error != 0) ctl_be_block_close(be_lun); - return (error); - } - - be_lun->blocksize_shift = fls(be_lun->blocksize) - 1; - be_lun->size_blocks = be_lun->size_bytes >> be_lun->blocksize_shift; - return (0); } @@ -2224,10 +2207,14 @@ ctl_be_block_create(struct ctl_be_block_softc *softc, struct ctl_lun_req *req) goto bailout_error; } be_lun->dev_path = strdup(value, M_CTLBLK); - be_lun->blocksize = 512; - be_lun->blocksize_shift = fls(be_lun->blocksize) - 1; + be_lun->size_bytes = params->lun_size_bytes; + if (params->blocksize_bytes != 0) + be_lun->blocksize = params->blocksize_bytes; + else + be_lun->blocksize = 512; retval = ctl_be_block_open(softc, be_lun, req); + be_lun->size_blocks = be_lun->size_bytes / be_lun->blocksize; if (retval != 0) { retval = 0; req->status = CTL_LUN_WARNING; @@ -2652,10 +2639,9 @@ ctl_be_block_modify(struct ctl_be_block_softc *softc, struct ctl_lun_req *req) error = ctl_be_block_modify_file(be_lun, req); else error = EINVAL; + be_lun->size_blocks = be_lun->size_bytes / be_lun->blocksize; if (error == 0 && be_lun->size_bytes != oldsize) { - be_lun->size_blocks = be_lun->size_bytes >> - be_lun->blocksize_shift; /* * The maximum LBA is the size - 1. diff --git a/sys/cam/ctl/ctl_backend_ramdisk.c b/sys/cam/ctl/ctl_backend_ramdisk.c index ad90241..211738b 100644 --- a/sys/cam/ctl/ctl_backend_ramdisk.c +++ b/sys/cam/ctl/ctl_backend_ramdisk.c @@ -62,7 +62,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_util.h> #include <cam/ctl/ctl_backend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_debug.h> #include <cam/ctl/ctl_ioctl.h> #include <cam/ctl/ctl_error.h> diff --git a/sys/cam/ctl/ctl_cmd_table.c b/sys/cam/ctl/ctl_cmd_table.c index 08ff88a..9a7d70e 100644 --- a/sys/cam/ctl/ctl_cmd_table.c +++ b/sys/cam/ctl/ctl_cmd_table.c @@ -52,7 +52,6 @@ #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> #include <cam/ctl/ctl_backend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_ioctl.h> #include <cam/ctl/ctl_ha.h> #include <cam/ctl/ctl_private.h> diff --git a/sys/cam/ctl/ctl_error.c b/sys/cam/ctl/ctl_error.c index d4d7f79..4b41331 100644 --- a/sys/cam/ctl/ctl_error.c +++ b/sys/cam/ctl/ctl_error.c @@ -57,7 +57,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_ioctl.h> #include <cam/ctl/ctl_error.h> diff --git a/sys/cam/ctl/ctl_frontend.c b/sys/cam/ctl/ctl_frontend.c index e22b9d4..34baf44 100644 --- a/sys/cam/ctl/ctl_frontend.c +++ b/sys/cam/ctl/ctl_frontend.c @@ -55,7 +55,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_backend.h> /* XXX KDM move defines from ctl_ioctl.h to somewhere else */ #include <cam/ctl/ctl_ioctl.h> diff --git a/sys/cam/ctl/ctl_frontend_cam_sim.c b/sys/cam/ctl/ctl_frontend_cam_sim.c index 3abc572..97b361a 100644 --- a/sys/cam/ctl/ctl_frontend_cam_sim.c +++ b/sys/cam/ctl/ctl_frontend_cam_sim.c @@ -64,7 +64,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_debug.h> #define io_ptr spriv_ptr1 diff --git a/sys/cam/ctl/ctl_frontend_internal.c b/sys/cam/ctl/ctl_frontend_internal.c deleted file mode 100644 index 4768292..0000000 --- a/sys/cam/ctl/ctl_frontend_internal.c +++ /dev/null @@ -1,1612 +0,0 @@ -/*- - * Copyright (c) 2004, 2005 Silicon Graphics International Corp. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * substantially similar to the "NO WARRANTY" disclaimer below - * ("Disclaimer") and any redistribution must be conditioned upon - * including a substantially similar Disclaimer requirement for further - * binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGES. - * - * $Id: //depot/users/kenm/FreeBSD-test2/sys/cam/ctl/ctl_frontend_internal.c#5 $ - */ -/* - * CTL kernel internal frontend target driver. This allows kernel-level - * clients to send commands into CTL. - * - * This has elements of a FETD (e.g. it has to set tag numbers, initiator, - * port, target, and LUN) and elements of an initiator (LUN discovery and - * probing, error recovery, command initiation). Even though this has some - * initiator type elements, this is not intended to be a full fledged - * initiator layer. It is only intended to send a limited number of - * commands to a well known target layer. - * - * To be able to fulfill the role of a full initiator layer, it would need - * a whole lot more functionality. - * - * Author: Ken Merry <ken@FreeBSD.org> - * - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/types.h> -#include <sys/malloc.h> -#include <sys/module.h> -#include <sys/lock.h> -#include <sys/mutex.h> -#include <sys/condvar.h> -#include <sys/queue.h> -#include <sys/sbuf.h> -#include <sys/sysctl.h> -#include <vm/uma.h> -#include <cam/scsi/scsi_all.h> -#include <cam/scsi/scsi_da.h> -#include <cam/ctl/ctl_io.h> -#include <cam/ctl/ctl.h> -#include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> -#include <cam/ctl/ctl_backend.h> -#include <cam/ctl/ctl_ioctl.h> -#include <cam/ctl/ctl_util.h> -#include <cam/ctl/ctl_ha.h> -#include <cam/ctl/ctl_private.h> -#include <cam/ctl/ctl_debug.h> -#include <cam/ctl/ctl_scsi_all.h> -#include <cam/ctl/ctl_error.h> - -/* - * Task structure: - * - overall metatask, different potential metatask types (e.g. forced - * shutdown, gentle shutdown) - * - forced shutdown metatask: - * - states: report luns, pending, done? - * - list of luns pending, with the relevant I/O for that lun attached. - * This would allow moving ahead on LUNs with no errors, and going - * into error recovery on LUNs with problems. Per-LUN states might - * include inquiry, stop/offline, done. - * - * Use LUN enable for LUN list instead of getting it manually? We'd still - * need inquiry data for each LUN. - * - * How to handle processor LUN w.r.t. found/stopped counts? - */ -#ifdef oldapi -typedef enum { - CFI_TASK_NONE, - CFI_TASK_SHUTDOWN, - CFI_TASK_STARTUP -} cfi_tasktype; - -struct cfi_task_startstop { - int total_luns; - int luns_complete; - int luns_failed; - cfi_cb_t callback; - void *callback_arg; - /* XXX KDM add more fields here */ -}; - -union cfi_taskinfo { - struct cfi_task_startstop startstop; -}; - -struct cfi_metatask { - cfi_tasktype tasktype; - cfi_mt_status status; - union cfi_taskinfo taskinfo; - void *cfi_context; - STAILQ_ENTRY(cfi_metatask) links; -}; -#endif - -typedef enum { - CFI_ERR_RETRY = 0x000, - CFI_ERR_FAIL = 0x001, - CFI_ERR_LUN_RESET = 0x002, - CFI_ERR_MASK = 0x0ff, - CFI_ERR_NO_DECREMENT = 0x100 -} cfi_error_action; - -typedef enum { - CFI_ERR_SOFT, - CFI_ERR_HARD -} cfi_error_policy; - -typedef enum { - CFI_LUN_INQUIRY, - CFI_LUN_READCAPACITY, - CFI_LUN_READCAPACITY_16, - CFI_LUN_READY -} cfi_lun_state; - -struct cfi_lun { - int lun_id; - struct scsi_inquiry_data inq_data; - uint64_t num_blocks; - uint32_t blocksize; - int blocksize_powerof2; - uint32_t cur_tag_num; - cfi_lun_state state; - struct cfi_softc *softc; - STAILQ_HEAD(, cfi_lun_io) io_list; - STAILQ_ENTRY(cfi_lun) links; -}; - -struct cfi_lun_io { - struct cfi_lun *lun; - struct cfi_metatask *metatask; - cfi_error_policy policy; - void (*done_function)(union ctl_io *io); - union ctl_io *ctl_io; - struct cfi_lun_io *orig_lun_io; - STAILQ_ENTRY(cfi_lun_io) links; -}; - -typedef enum { - CFI_NONE = 0x00, - CFI_ONLINE = 0x01, -} cfi_flags; - -struct cfi_softc { - struct ctl_port port; - char fe_name[40]; - struct mtx lock; - cfi_flags flags; - STAILQ_HEAD(, cfi_lun) lun_list; - STAILQ_HEAD(, cfi_metatask) metatask_list; -}; - -MALLOC_DEFINE(M_CTL_CFI, "ctlcfi", "CTL CFI"); - -static uma_zone_t cfi_lun_zone; -static uma_zone_t cfi_metatask_zone; - -static struct cfi_softc fetd_internal_softc; - -int cfi_init(void); -void cfi_shutdown(void) __unused; -static void cfi_online(void *arg); -static void cfi_offline(void *arg); -static int cfi_lun_enable(void *arg, int lun_id); -static int cfi_lun_disable(void *arg, int lun_id); -static void cfi_datamove(union ctl_io *io); -static cfi_error_action cfi_checkcond_parse(union ctl_io *io, - struct cfi_lun_io *lun_io); -static cfi_error_action cfi_error_parse(union ctl_io *io, - struct cfi_lun_io *lun_io); -static void cfi_init_io(union ctl_io *io, struct cfi_lun *lun, - struct cfi_metatask *metatask, cfi_error_policy policy, - int retries, struct cfi_lun_io *orig_lun_io, - void (*done_function)(union ctl_io *io)); -static void cfi_done(union ctl_io *io); -static void cfi_lun_probe_done(union ctl_io *io); -static void cfi_lun_probe(struct cfi_lun *lun, int have_lock); -static void cfi_metatask_done(struct cfi_softc *softc, - struct cfi_metatask *metatask); -static void cfi_metatask_bbr_errorparse(struct cfi_metatask *metatask, - union ctl_io *io); -static void cfi_metatask_io_done(union ctl_io *io); -static void cfi_err_recovery_done(union ctl_io *io); -static void cfi_lun_io_done(union ctl_io *io); - -static struct ctl_frontend cfi_frontend = -{ - .name = "kernel", - .init = cfi_init, - .shutdown = cfi_shutdown, -}; -CTL_FRONTEND_DECLARE(ctlcfi, cfi_frontend); - -int -cfi_init(void) -{ - struct cfi_softc *softc; - struct ctl_port *port; - int retval; - - softc = &fetd_internal_softc; - - port = &softc->port; - - retval = 0; - - if (sizeof(struct cfi_lun_io) > CTL_PORT_PRIV_SIZE) { - printf("%s: size of struct cfi_lun_io %zd > " - "CTL_PORT_PRIV_SIZE %d\n", __func__, - sizeof(struct cfi_lun_io), - CTL_PORT_PRIV_SIZE); - } - memset(softc, 0, sizeof(*softc)); - - mtx_init(&softc->lock, "CTL frontend mutex", NULL, MTX_DEF); - STAILQ_INIT(&softc->lun_list); - STAILQ_INIT(&softc->metatask_list); - sprintf(softc->fe_name, "kernel"); - port->frontend = &cfi_frontend; - port->port_type = CTL_PORT_INTERNAL; - port->num_requested_ctl_io = 100; - port->port_name = softc->fe_name; - port->port_online = cfi_online; - port->port_offline = cfi_offline; - port->onoff_arg = softc; - port->lun_enable = cfi_lun_enable; - port->lun_disable = cfi_lun_disable; - port->targ_lun_arg = softc; - port->fe_datamove = cfi_datamove; - port->fe_done = cfi_done; - port->max_targets = 15; - port->max_target_id = 15; - - if (ctl_port_register(port) != 0) - { - printf("%s: internal frontend registration failed\n", __func__); - return (0); - } - - cfi_lun_zone = uma_zcreate("cfi_lun", sizeof(struct cfi_lun), - NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 0); - cfi_metatask_zone = uma_zcreate("cfi_metatask", sizeof(struct cfi_metatask), - NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 0); - - return (0); -} - -void -cfi_shutdown(void) -{ - struct cfi_softc *softc; - - softc = &fetd_internal_softc; - - /* - * XXX KDM need to clear out any I/O pending on each LUN. - */ - if (ctl_port_deregister(&softc->port) != 0) - printf("%s: ctl_frontend_deregister() failed\n", __func__); - - uma_zdestroy(cfi_lun_zone); - uma_zdestroy(cfi_metatask_zone); -} - -static void -cfi_online(void *arg) -{ - struct cfi_softc *softc; - struct cfi_lun *lun; - - softc = (struct cfi_softc *)arg; - - softc->flags |= CFI_ONLINE; - - /* - * Go through and kick off the probe for each lun. Should we check - * the LUN flags here to determine whether or not to probe it? - */ - mtx_lock(&softc->lock); - STAILQ_FOREACH(lun, &softc->lun_list, links) - cfi_lun_probe(lun, /*have_lock*/ 1); - mtx_unlock(&softc->lock); -} - -static void -cfi_offline(void *arg) -{ - struct cfi_softc *softc; - - softc = (struct cfi_softc *)arg; - - softc->flags &= ~CFI_ONLINE; -} - -static int -cfi_lun_enable(void *arg, int lun_id) -{ - struct cfi_softc *softc; - struct cfi_lun *lun; - int found; - - softc = (struct cfi_softc *)arg; - - found = 0; - mtx_lock(&softc->lock); - STAILQ_FOREACH(lun, &softc->lun_list, links) { - if (lun->lun_id == lun_id) { - found = 1; - break; - } - } - mtx_unlock(&softc->lock); - - /* - * If we already have this target/LUN, there is no reason to add - * it to our lists again. - */ - if (found != 0) - return (0); - - lun = uma_zalloc(cfi_lun_zone, M_NOWAIT | M_ZERO); - if (lun == NULL) { - printf("%s: unable to allocate LUN structure\n", __func__); - return (1); - } - - lun->lun_id = lun_id; - lun->cur_tag_num = 0; - lun->state = CFI_LUN_INQUIRY; - lun->softc = softc; - STAILQ_INIT(&lun->io_list); - - mtx_lock(&softc->lock); - STAILQ_INSERT_TAIL(&softc->lun_list, lun, links); - mtx_unlock(&softc->lock); - - cfi_lun_probe(lun, /*have_lock*/ 0); - - return (0); -} - -static int -cfi_lun_disable(void *arg, int lun_id) -{ - struct cfi_softc *softc; - struct cfi_lun *lun; - int found; - - softc = (struct cfi_softc *)arg; - - found = 0; - - /* - * XXX KDM need to do an invalidate and then a free when any - * pending I/O has completed. Or do we? CTL won't free a LUN - * while any I/O is pending. So we won't get this notification - * unless any I/O we have pending on a LUN has completed. - */ - mtx_lock(&softc->lock); - STAILQ_FOREACH(lun, &softc->lun_list, links) { - if (lun->lun_id == lun_id) { - found = 1; - break; - } - } - if (found != 0) - STAILQ_REMOVE(&softc->lun_list, lun, cfi_lun, links); - - mtx_unlock(&softc->lock); - - if (found == 0) { - printf("%s: can't find lun %d\n", __func__, lun_id); - return (1); - } - - uma_zfree(cfi_lun_zone, lun); - - return (0); -} - -static void -cfi_datamove(union ctl_io *io) -{ - struct ctl_sg_entry *ext_sglist, *kern_sglist; - struct ctl_sg_entry ext_entry, kern_entry; - int ext_sglen, ext_sg_entries, kern_sg_entries; - int ext_sg_start, ext_offset; - int len_to_copy, len_copied; - int kern_watermark, ext_watermark; - int ext_sglist_malloced; - struct ctl_scsiio *ctsio; - int i, j; - - ext_sglist_malloced = 0; - ext_sg_start = 0; - ext_offset = 0; - ext_sglist = NULL; - - CTL_DEBUG_PRINT(("%s\n", __func__)); - - ctsio = &io->scsiio; - - /* - * If this is the case, we're probably doing a BBR read and don't - * actually need to transfer the data. This will effectively - * bit-bucket the data. - */ - if (ctsio->ext_data_ptr == NULL) - goto bailout; - - /* - * To simplify things here, if we have a single buffer, stick it in - * a S/G entry and just make it a single entry S/G list. - */ - if (ctsio->io_hdr.flags & CTL_FLAG_EDPTR_SGLIST) { - int len_seen; - - ext_sglen = ctsio->ext_sg_entries * sizeof(*ext_sglist); - - ext_sglist = (struct ctl_sg_entry *)malloc(ext_sglen, M_CTL_CFI, - M_WAITOK); - ext_sglist_malloced = 1; - if (memcpy(ext_sglist, ctsio->ext_data_ptr, ext_sglen) != 0) { - ctl_set_internal_failure(ctsio, - /*sks_valid*/ 0, - /*retry_count*/ 0); - goto bailout; - } - ext_sg_entries = ctsio->ext_sg_entries; - len_seen = 0; - for (i = 0; i < ext_sg_entries; i++) { - if ((len_seen + ext_sglist[i].len) >= - ctsio->ext_data_filled) { - ext_sg_start = i; - ext_offset = ctsio->ext_data_filled - len_seen; - break; - } - len_seen += ext_sglist[i].len; - } - } else { - ext_sglist = &ext_entry; - ext_sglist->addr = ctsio->ext_data_ptr; - ext_sglist->len = ctsio->ext_data_len; - ext_sg_entries = 1; - ext_sg_start = 0; - ext_offset = ctsio->ext_data_filled; - } - - if (ctsio->kern_sg_entries > 0) { - kern_sglist = (struct ctl_sg_entry *)ctsio->kern_data_ptr; - kern_sg_entries = ctsio->kern_sg_entries; - } else { - kern_sglist = &kern_entry; - kern_sglist->addr = ctsio->kern_data_ptr; - kern_sglist->len = ctsio->kern_data_len; - kern_sg_entries = 1; - } - - - kern_watermark = 0; - ext_watermark = ext_offset; - len_copied = 0; - for (i = ext_sg_start, j = 0; - i < ext_sg_entries && j < kern_sg_entries;) { - uint8_t *ext_ptr, *kern_ptr; - - len_to_copy = MIN(ext_sglist[i].len - ext_watermark, - kern_sglist[j].len - kern_watermark); - - ext_ptr = (uint8_t *)ext_sglist[i].addr; - ext_ptr = ext_ptr + ext_watermark; - if (io->io_hdr.flags & CTL_FLAG_BUS_ADDR) { - /* - * XXX KDM fix this! - */ - panic("need to implement bus address support"); -#if 0 - kern_ptr = bus_to_virt(kern_sglist[j].addr); -#endif - } else - kern_ptr = (uint8_t *)kern_sglist[j].addr; - kern_ptr = kern_ptr + kern_watermark; - - kern_watermark += len_to_copy; - ext_watermark += len_to_copy; - - if ((ctsio->io_hdr.flags & CTL_FLAG_DATA_MASK) == - CTL_FLAG_DATA_IN) { - CTL_DEBUG_PRINT(("%s: copying %d bytes to user\n", - __func__, len_to_copy)); - CTL_DEBUG_PRINT(("%s: from %p to %p\n", __func__, - kern_ptr, ext_ptr)); - memcpy(ext_ptr, kern_ptr, len_to_copy); - } else { - CTL_DEBUG_PRINT(("%s: copying %d bytes from user\n", - __func__, len_to_copy)); - CTL_DEBUG_PRINT(("%s: from %p to %p\n", __func__, - ext_ptr, kern_ptr)); - memcpy(kern_ptr, ext_ptr, len_to_copy); - } - - len_copied += len_to_copy; - - if (ext_sglist[i].len == ext_watermark) { - i++; - ext_watermark = 0; - } - - if (kern_sglist[j].len == kern_watermark) { - j++; - kern_watermark = 0; - } - } - - ctsio->ext_data_filled += len_copied; - - CTL_DEBUG_PRINT(("%s: ext_sg_entries: %d, kern_sg_entries: %d\n", - __func__, ext_sg_entries, kern_sg_entries)); - CTL_DEBUG_PRINT(("%s: ext_data_len = %d, kern_data_len = %d\n", - __func__, ctsio->ext_data_len, ctsio->kern_data_len)); - - - /* XXX KDM set residual?? */ -bailout: - - if (ext_sglist_malloced != 0) - free(ext_sglist, M_CTL_CFI); - - io->scsiio.be_move_done(io); - - return; -} - -/* - * For any sort of check condition, busy, etc., we just retry. We do not - * decrement the retry count for unit attention type errors. These are - * normal, and we want to save the retry count for "real" errors. Otherwise, - * we could end up with situations where a command will succeed in some - * situations and fail in others, depending on whether a unit attention is - * pending. Also, some of our error recovery actions, most notably the - * LUN reset action, will cause a unit attention. - * - * We can add more detail here later if necessary. - */ -static cfi_error_action -cfi_checkcond_parse(union ctl_io *io, struct cfi_lun_io *lun_io) -{ - cfi_error_action error_action; - int error_code, sense_key, asc, ascq; - - /* - * Default to retrying the command. - */ - error_action = CFI_ERR_RETRY; - - scsi_extract_sense_len(&io->scsiio.sense_data, - io->scsiio.sense_len, - &error_code, - &sense_key, - &asc, - &ascq, - /*show_errors*/ 1); - - switch (error_code) { - case SSD_DEFERRED_ERROR: - case SSD_DESC_DEFERRED_ERROR: - error_action |= CFI_ERR_NO_DECREMENT; - break; - case SSD_CURRENT_ERROR: - case SSD_DESC_CURRENT_ERROR: - default: { - switch (sense_key) { - case SSD_KEY_UNIT_ATTENTION: - error_action |= CFI_ERR_NO_DECREMENT; - break; - case SSD_KEY_HARDWARE_ERROR: - /* - * This is our generic "something bad happened" - * error code. It often isn't recoverable. - */ - if ((asc == 0x44) && (ascq == 0x00)) - error_action = CFI_ERR_FAIL; - break; - case SSD_KEY_NOT_READY: - /* - * If the LUN is powered down, there likely isn't - * much point in retrying right now. - */ - if ((asc == 0x04) && (ascq == 0x02)) - error_action = CFI_ERR_FAIL; - /* - * If the LUN is offline, there probably isn't much - * point in retrying, either. - */ - if ((asc == 0x04) && (ascq == 0x03)) - error_action = CFI_ERR_FAIL; - break; - } - } - } - - return (error_action); -} - -static cfi_error_action -cfi_error_parse(union ctl_io *io, struct cfi_lun_io *lun_io) -{ - cfi_error_action error_action; - - error_action = CFI_ERR_RETRY; - - switch (io->io_hdr.io_type) { - case CTL_IO_SCSI: - switch (io->io_hdr.status & CTL_STATUS_MASK) { - case CTL_SCSI_ERROR: - switch (io->scsiio.scsi_status) { - case SCSI_STATUS_RESERV_CONFLICT: - /* - * For a reservation conflict, we'll usually - * want the hard error recovery policy, so - * we'll reset the LUN. - */ - if (lun_io->policy == CFI_ERR_HARD) - error_action = - CFI_ERR_LUN_RESET; - else - error_action = - CFI_ERR_RETRY; - break; - case SCSI_STATUS_CHECK_COND: - default: - error_action = cfi_checkcond_parse(io, lun_io); - break; - } - break; - default: - error_action = CFI_ERR_RETRY; - break; - } - break; - case CTL_IO_TASK: - /* - * In theory task management commands shouldn't fail... - */ - error_action = CFI_ERR_RETRY; - break; - default: - printf("%s: invalid ctl_io type %d\n", __func__, - io->io_hdr.io_type); - panic("%s: invalid ctl_io type %d\n", __func__, - io->io_hdr.io_type); - break; - } - - return (error_action); -} - -static void -cfi_init_io(union ctl_io *io, struct cfi_lun *lun, - struct cfi_metatask *metatask, cfi_error_policy policy, int retries, - struct cfi_lun_io *orig_lun_io, - void (*done_function)(union ctl_io *io)) -{ - struct cfi_lun_io *lun_io; - - io->io_hdr.nexus.initid.id = 7; - io->io_hdr.nexus.targ_port = lun->softc->port.targ_port; - io->io_hdr.nexus.targ_target.id = 0; - io->io_hdr.nexus.targ_lun = lun->lun_id; - io->io_hdr.retries = retries; - lun_io = (struct cfi_lun_io *)io->io_hdr.port_priv; - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr = lun_io; - lun_io->lun = lun; - lun_io->metatask = metatask; - lun_io->ctl_io = io; - lun_io->policy = policy; - lun_io->orig_lun_io = orig_lun_io; - lun_io->done_function = done_function; - /* - * We only set the tag number for SCSI I/Os. For task management - * commands, the tag number is only really needed for aborts, so - * the caller can set it if necessary. - */ - switch (io->io_hdr.io_type) { - case CTL_IO_SCSI: - io->scsiio.tag_num = lun->cur_tag_num++; - break; - case CTL_IO_TASK: - default: - break; - } -} - -static void -cfi_done(union ctl_io *io) -{ - struct cfi_lun_io *lun_io; - struct cfi_softc *softc; - struct cfi_lun *lun; - - lun_io = (struct cfi_lun_io *) - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; - - lun = lun_io->lun; - softc = lun->softc; - - /* - * Very minimal retry logic. We basically retry if we got an error - * back, and the retry count is greater than 0. If we ever want - * more sophisticated initiator type behavior, the CAM error - * recovery code in ../common might be helpful. - */ - if (((io->io_hdr.status & CTL_STATUS_MASK) != CTL_SUCCESS) - && (io->io_hdr.retries > 0)) { - ctl_io_status old_status; - cfi_error_action error_action; - - error_action = cfi_error_parse(io, lun_io); - - switch (error_action & CFI_ERR_MASK) { - case CFI_ERR_FAIL: - goto done; - break; /* NOTREACHED */ - case CFI_ERR_LUN_RESET: { - union ctl_io *new_io; - struct cfi_lun_io *new_lun_io; - - new_io = ctl_alloc_io(softc->port.ctl_pool_ref); - ctl_zero_io(new_io); - - new_io->io_hdr.io_type = CTL_IO_TASK; - new_io->taskio.task_action = CTL_TASK_LUN_RESET; - - cfi_init_io(new_io, - /*lun*/ lun_io->lun, - /*metatask*/ NULL, - /*policy*/ CFI_ERR_SOFT, - /*retries*/ 0, - /*orig_lun_io*/lun_io, - /*done_function*/ cfi_err_recovery_done); - - - new_lun_io = (struct cfi_lun_io *) - new_io->io_hdr.port_priv; - - mtx_lock(&lun->softc->lock); - STAILQ_INSERT_TAIL(&lun->io_list, new_lun_io, links); - mtx_unlock(&lun->softc->lock); - - io = new_io; - break; - } - case CFI_ERR_RETRY: - default: - if ((error_action & CFI_ERR_NO_DECREMENT) == 0) - io->io_hdr.retries--; - break; - } - - old_status = io->io_hdr.status; - io->io_hdr.status = CTL_STATUS_NONE; -#if 0 - io->io_hdr.flags &= ~CTL_FLAG_ALREADY_DONE; -#endif - io->io_hdr.flags &= ~CTL_FLAG_ABORT; - io->io_hdr.flags &= ~CTL_FLAG_SENT_2OTHER_SC; - - if (ctl_queue(io) != CTL_RETVAL_COMPLETE) { - printf("%s: error returned from ctl_queue()!\n", - __func__); - io->io_hdr.status = old_status; - } else - return; - } -done: - lun_io->done_function(io); -} - -static void -cfi_lun_probe_done(union ctl_io *io) -{ - struct cfi_lun *lun; - struct cfi_lun_io *lun_io; - - lun_io = (struct cfi_lun_io *) - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; - lun = lun_io->lun; - - switch (lun->state) { - case CFI_LUN_INQUIRY: { - if ((io->io_hdr.status & CTL_STATUS_MASK) != CTL_SUCCESS) { - /* print out something here?? */ - printf("%s: LUN %d probe failed because inquiry " - "failed\n", __func__, lun->lun_id); - ctl_io_error_print(io, NULL); - } else { - - if (SID_TYPE(&lun->inq_data) != T_DIRECT) { - char path_str[40]; - - lun->state = CFI_LUN_READY; - ctl_scsi_path_string(io, path_str, - sizeof(path_str)); - printf("%s", path_str); - scsi_print_inquiry(&lun->inq_data); - } else { - lun->state = CFI_LUN_READCAPACITY; - cfi_lun_probe(lun, /*have_lock*/ 0); - } - } - mtx_lock(&lun->softc->lock); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - mtx_unlock(&lun->softc->lock); - ctl_free_io(io); - break; - } - case CFI_LUN_READCAPACITY: - case CFI_LUN_READCAPACITY_16: { - uint64_t maxlba; - uint32_t blocksize; - - maxlba = 0; - blocksize = 0; - - if ((io->io_hdr.status & CTL_STATUS_MASK) != CTL_SUCCESS) { - printf("%s: LUN %d probe failed because READ CAPACITY " - "failed\n", __func__, lun->lun_id); - ctl_io_error_print(io, NULL); - } else { - - if (lun->state == CFI_LUN_READCAPACITY) { - struct scsi_read_capacity_data *rdcap; - - rdcap = (struct scsi_read_capacity_data *) - io->scsiio.ext_data_ptr; - - maxlba = scsi_4btoul(rdcap->addr); - blocksize = scsi_4btoul(rdcap->length); - if (blocksize == 0) { - printf("%s: LUN %d has invalid " - "blocksize 0, probe aborted\n", - __func__, lun->lun_id); - } else if (maxlba == 0xffffffff) { - lun->state = CFI_LUN_READCAPACITY_16; - cfi_lun_probe(lun, /*have_lock*/ 0); - } else - lun->state = CFI_LUN_READY; - } else { - struct scsi_read_capacity_data_long *rdcap_long; - - rdcap_long = (struct - scsi_read_capacity_data_long *) - io->scsiio.ext_data_ptr; - maxlba = scsi_8btou64(rdcap_long->addr); - blocksize = scsi_4btoul(rdcap_long->length); - - if (blocksize == 0) { - printf("%s: LUN %d has invalid " - "blocksize 0, probe aborted\n", - __func__, lun->lun_id); - } else - lun->state = CFI_LUN_READY; - } - } - - if (lun->state == CFI_LUN_READY) { - char path_str[40]; - - lun->num_blocks = maxlba + 1; - lun->blocksize = blocksize; - - /* - * If this is true, the blocksize is a power of 2. - * We already checked for 0 above. - */ - if (((blocksize - 1) & blocksize) == 0) { - int i; - - for (i = 0; i < 32; i++) { - if ((blocksize & (1 << i)) != 0) { - lun->blocksize_powerof2 = i; - break; - } - } - } - ctl_scsi_path_string(io, path_str,sizeof(path_str)); - printf("%s", path_str); - scsi_print_inquiry(&lun->inq_data); - printf("%s %ju blocks, blocksize %d\n", path_str, - (uintmax_t)maxlba + 1, blocksize); - } - mtx_lock(&lun->softc->lock); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - mtx_unlock(&lun->softc->lock); - free(io->scsiio.ext_data_ptr, M_CTL_CFI); - ctl_free_io(io); - break; - } - case CFI_LUN_READY: - default: - mtx_lock(&lun->softc->lock); - /* How did we get here?? */ - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - mtx_unlock(&lun->softc->lock); - ctl_free_io(io); - break; - } -} - -static void -cfi_lun_probe(struct cfi_lun *lun, int have_lock) -{ - - if (have_lock == 0) - mtx_lock(&lun->softc->lock); - if ((lun->softc->flags & CFI_ONLINE) == 0) { - if (have_lock == 0) - mtx_unlock(&lun->softc->lock); - return; - } - if (have_lock == 0) - mtx_unlock(&lun->softc->lock); - - switch (lun->state) { - case CFI_LUN_INQUIRY: { - struct cfi_lun_io *lun_io; - union ctl_io *io; - - io = ctl_alloc_io(lun->softc->port.ctl_pool_ref); - ctl_scsi_inquiry(io, - /*data_ptr*/(uint8_t *)&lun->inq_data, - /*data_len*/ sizeof(lun->inq_data), - /*byte2*/ 0, - /*page_code*/ 0, - /*tag_type*/ CTL_TAG_SIMPLE, - /*control*/ 0); - - cfi_init_io(io, - /*lun*/ lun, - /*metatask*/ NULL, - /*policy*/ CFI_ERR_SOFT, - /*retries*/ 5, - /*orig_lun_io*/ NULL, - /*done_function*/ - cfi_lun_probe_done); - - lun_io = (struct cfi_lun_io *)io->io_hdr.port_priv; - - if (have_lock == 0) - mtx_lock(&lun->softc->lock); - STAILQ_INSERT_TAIL(&lun->io_list, lun_io, links); - if (have_lock == 0) - mtx_unlock(&lun->softc->lock); - - if (ctl_queue(io) != CTL_RETVAL_COMPLETE) { - printf("%s: error returned from ctl_queue()!\n", - __func__); - STAILQ_REMOVE(&lun->io_list, lun_io, - cfi_lun_io, links); - ctl_free_io(io); - } - break; - } - case CFI_LUN_READCAPACITY: - case CFI_LUN_READCAPACITY_16: { - struct cfi_lun_io *lun_io; - uint8_t *dataptr; - union ctl_io *io; - - io = ctl_alloc_io(lun->softc->port.ctl_pool_ref); - - dataptr = malloc(sizeof(struct scsi_read_capacity_data_long), - M_CTL_CFI, M_NOWAIT); - if (dataptr == NULL) { - printf("%s: unable to allocate SCSI read capacity " - "buffer for lun %d\n", __func__, lun->lun_id); - return; - } - if (lun->state == CFI_LUN_READCAPACITY) { - ctl_scsi_read_capacity(io, - /*data_ptr*/ dataptr, - /*data_len*/ - sizeof(struct scsi_read_capacity_data_long), - /*addr*/ 0, - /*reladr*/ 0, - /*pmi*/ 0, - /*tag_type*/ CTL_TAG_SIMPLE, - /*control*/ 0); - } else { - ctl_scsi_read_capacity_16(io, - /*data_ptr*/ dataptr, - /*data_len*/ - sizeof(struct scsi_read_capacity_data_long), - /*addr*/ 0, - /*reladr*/ 0, - /*pmi*/ 0, - /*tag_type*/ CTL_TAG_SIMPLE, - /*control*/ 0); - } - cfi_init_io(io, - /*lun*/ lun, - /*metatask*/ NULL, - /*policy*/ CFI_ERR_SOFT, - /*retries*/ 7, - /*orig_lun_io*/ NULL, - /*done_function*/ cfi_lun_probe_done); - - lun_io = (struct cfi_lun_io *)io->io_hdr.port_priv; - - if (have_lock == 0) - mtx_lock(&lun->softc->lock); - STAILQ_INSERT_TAIL(&lun->io_list, lun_io, links); - if (have_lock == 0) - mtx_unlock(&lun->softc->lock); - - if (ctl_queue(io) != CTL_RETVAL_COMPLETE) { - printf("%s: error returned from ctl_queue()!\n", - __func__); - STAILQ_REMOVE(&lun->io_list, lun_io, - cfi_lun_io, links); - free(dataptr, M_CTL_CFI); - ctl_free_io(io); - } - break; - } - case CFI_LUN_READY: - default: - /* Why were we called? */ - break; - } -} - -static void -cfi_metatask_done(struct cfi_softc *softc, struct cfi_metatask *metatask) -{ - mtx_lock(&softc->lock); - STAILQ_REMOVE(&softc->metatask_list, metatask, cfi_metatask, links); - mtx_unlock(&softc->lock); - - /* - * Return status to the caller. Caller allocated storage, and is - * responsible for calling cfi_free_metatask to release it once - * they've seen the status. - */ - metatask->callback(metatask->callback_arg, metatask); -} - -static void -cfi_metatask_bbr_errorparse(struct cfi_metatask *metatask, union ctl_io *io) -{ - int error_code, sense_key, asc, ascq; - - if (metatask->tasktype != CFI_TASK_BBRREAD) - return; - - if ((io->io_hdr.status & CTL_STATUS_MASK) == CTL_SUCCESS) { - metatask->status = CFI_MT_SUCCESS; - metatask->taskinfo.bbrread.status = CFI_BBR_SUCCESS; - return; - } - - if ((io->io_hdr.status & CTL_STATUS_MASK) != CTL_SCSI_ERROR) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_ERROR; - return; - } - - metatask->taskinfo.bbrread.scsi_status = io->scsiio.scsi_status; - memcpy(&metatask->taskinfo.bbrread.sense_data, &io->scsiio.sense_data, - MIN(sizeof(metatask->taskinfo.bbrread.sense_data), - sizeof(io->scsiio.sense_data))); - - if (io->scsiio.scsi_status == SCSI_STATUS_RESERV_CONFLICT) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_RESERV_CONFLICT; - return; - } - - if (io->scsiio.scsi_status != SCSI_STATUS_CHECK_COND) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_SCSI_ERROR; - return; - } - - scsi_extract_sense_len(&io->scsiio.sense_data, - io->scsiio.sense_len, - &error_code, - &sense_key, - &asc, - &ascq, - /*show_errors*/ 1); - - switch (error_code) { - case SSD_DEFERRED_ERROR: - case SSD_DESC_DEFERRED_ERROR: - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_SCSI_ERROR; - break; - case SSD_CURRENT_ERROR: - case SSD_DESC_CURRENT_ERROR: - default: { - struct scsi_sense_data *sense; - - sense = &io->scsiio.sense_data; - - if ((asc == 0x04) && (ascq == 0x02)) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_LUN_STOPPED; - } else if ((asc == 0x04) && (ascq == 0x03)) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = - CFI_BBR_LUN_OFFLINE_CTL; - } else if ((asc == 0x44) && (ascq == 0x00)) { -#ifdef NEEDTOPORT - if (sense->sense_key_spec[0] & SSD_SCS_VALID) { - uint16_t retry_count; - - retry_count = sense->sense_key_spec[1] << 8 | - sense->sense_key_spec[2]; - if (((retry_count & 0xf000) == CSC_RAIDCORE) - && ((retry_count & 0x0f00) == CSC_SHELF_SW) - && ((retry_count & 0xff) == - RC_STS_DEVICE_OFFLINE)) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = - CFI_BBR_LUN_OFFLINE_RC; - } else { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = - CFI_BBR_SCSI_ERROR; - } - } else { -#endif /* NEEDTOPORT */ - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = - CFI_BBR_SCSI_ERROR; -#ifdef NEEDTOPORT - } -#endif - } else { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_SCSI_ERROR; - } - break; - } - } -} - -static void -cfi_metatask_io_done(union ctl_io *io) -{ - struct cfi_lun_io *lun_io; - struct cfi_metatask *metatask; - struct cfi_softc *softc; - struct cfi_lun *lun; - - lun_io = (struct cfi_lun_io *) - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; - - lun = lun_io->lun; - softc = lun->softc; - - metatask = lun_io->metatask; - - switch (metatask->tasktype) { - case CFI_TASK_STARTUP: - case CFI_TASK_SHUTDOWN: { - int failed, done, is_start; - - failed = 0; - done = 0; - if (metatask->tasktype == CFI_TASK_STARTUP) - is_start = 1; - else - is_start = 0; - - mtx_lock(&softc->lock); - if ((io->io_hdr.status & CTL_STATUS_MASK) == CTL_SUCCESS) - metatask->taskinfo.startstop.luns_complete++; - else { - metatask->taskinfo.startstop.luns_failed++; - failed = 1; - } - if ((metatask->taskinfo.startstop.luns_complete + - metatask->taskinfo.startstop.luns_failed) >= - metatask->taskinfo.startstop.total_luns) - done = 1; - - mtx_unlock(&softc->lock); - - if (failed != 0) { - printf("%s: LUN %d %s request failed\n", __func__, - lun_io->lun->lun_id, (is_start == 1) ? "start" : - "stop"); - ctl_io_error_print(io, &lun_io->lun->inq_data); - } - if (done != 0) { - if (metatask->taskinfo.startstop.luns_failed > 0) - metatask->status = CFI_MT_ERROR; - else - metatask->status = CFI_MT_SUCCESS; - cfi_metatask_done(softc, metatask); - } - mtx_lock(&softc->lock); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - mtx_unlock(&softc->lock); - - ctl_free_io(io); - break; - } - case CFI_TASK_BBRREAD: { - /* - * Translate the SCSI error into an enumeration. - */ - cfi_metatask_bbr_errorparse(metatask, io); - - mtx_lock(&softc->lock); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - mtx_unlock(&softc->lock); - - ctl_free_io(io); - - cfi_metatask_done(softc, metatask); - break; - } - default: - /* - * This shouldn't happen. - */ - mtx_lock(&softc->lock); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - mtx_unlock(&softc->lock); - - ctl_free_io(io); - break; - } -} - -static void -cfi_err_recovery_done(union ctl_io *io) -{ - struct cfi_lun_io *lun_io, *orig_lun_io; - struct cfi_lun *lun; - union ctl_io *orig_io; - - lun_io = (struct cfi_lun_io *)io->io_hdr.port_priv; - orig_lun_io = lun_io->orig_lun_io; - orig_io = orig_lun_io->ctl_io; - lun = lun_io->lun; - - if (io->io_hdr.status != CTL_SUCCESS) { - printf("%s: error recovery action failed. Original " - "error:\n", __func__); - - ctl_io_error_print(orig_lun_io->ctl_io, &lun->inq_data); - - printf("%s: error from error recovery action:\n", __func__); - - ctl_io_error_print(io, &lun->inq_data); - - printf("%s: trying original command again...\n", __func__); - } - - mtx_lock(&lun->softc->lock); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - mtx_unlock(&lun->softc->lock); - ctl_free_io(io); - - orig_io->io_hdr.retries--; - orig_io->io_hdr.status = CTL_STATUS_NONE; - - if (ctl_queue(orig_io) != CTL_RETVAL_COMPLETE) { - printf("%s: error returned from ctl_queue()!\n", __func__); - STAILQ_REMOVE(&lun->io_list, orig_lun_io, - cfi_lun_io, links); - ctl_free_io(orig_io); - } -} - -static void -cfi_lun_io_done(union ctl_io *io) -{ - struct cfi_lun *lun; - struct cfi_lun_io *lun_io; - - lun_io = (struct cfi_lun_io *) - io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; - lun = lun_io->lun; - - if (lun_io->metatask == NULL) { - printf("%s: I/O has no metatask pointer, discarding\n", - __func__); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - ctl_free_io(io); - return; - } - cfi_metatask_io_done(io); -} - -void -cfi_action(struct cfi_metatask *metatask) -{ - struct cfi_softc *softc; - - softc = &fetd_internal_softc; - - mtx_lock(&softc->lock); - - STAILQ_INSERT_TAIL(&softc->metatask_list, metatask, links); - - if ((softc->flags & CFI_ONLINE) == 0) { - mtx_unlock(&softc->lock); - metatask->status = CFI_MT_PORT_OFFLINE; - cfi_metatask_done(softc, metatask); - return; - } else - mtx_unlock(&softc->lock); - - switch (metatask->tasktype) { - case CFI_TASK_STARTUP: - case CFI_TASK_SHUTDOWN: { - union ctl_io *io; - int da_luns, ios_allocated, do_start; - struct cfi_lun *lun; - STAILQ_HEAD(, ctl_io_hdr) tmp_io_list; - - da_luns = 0; - ios_allocated = 0; - STAILQ_INIT(&tmp_io_list); - - if (metatask->tasktype == CFI_TASK_STARTUP) - do_start = 1; - else - do_start = 0; - - mtx_lock(&softc->lock); - STAILQ_FOREACH(lun, &softc->lun_list, links) { - if (lun->state != CFI_LUN_READY) - continue; - - if (SID_TYPE(&lun->inq_data) != T_DIRECT) - continue; - da_luns++; - io = ctl_alloc_io_nowait(softc->port.ctl_pool_ref); - if (io != NULL) { - ios_allocated++; - STAILQ_INSERT_TAIL(&tmp_io_list, &io->io_hdr, - links); - } - } - - if (ios_allocated < da_luns) { - printf("%s: error allocating ctl_io for %s\n", - __func__, (do_start == 1) ? "startup" : - "shutdown"); - da_luns = ios_allocated; - } - - metatask->taskinfo.startstop.total_luns = da_luns; - - STAILQ_FOREACH(lun, &softc->lun_list, links) { - struct cfi_lun_io *lun_io; - - if (lun->state != CFI_LUN_READY) - continue; - - if (SID_TYPE(&lun->inq_data) != T_DIRECT) - continue; - - io = (union ctl_io *)STAILQ_FIRST(&tmp_io_list); - if (io == NULL) - break; - - STAILQ_REMOVE(&tmp_io_list, &io->io_hdr, ctl_io_hdr, - links); - - ctl_scsi_start_stop(io, - /*start*/ do_start, - /*load_eject*/ 0, - /*immediate*/ 0, - /*power_conditions*/ - SSS_PC_START_VALID, - /*onoffline*/ 1, - /*ctl_tag_type*/ CTL_TAG_ORDERED, - /*control*/ 0); - - cfi_init_io(io, - /*lun*/ lun, - /*metatask*/ metatask, - /*policy*/ CFI_ERR_HARD, - /*retries*/ 3, - /*orig_lun_io*/ NULL, - /*done_function*/ cfi_lun_io_done); - - lun_io = (struct cfi_lun_io *) io->io_hdr.port_priv; - - STAILQ_INSERT_TAIL(&lun->io_list, lun_io, links); - - if (ctl_queue(io) != CTL_RETVAL_COMPLETE) { - printf("%s: error returned from ctl_queue()!\n", - __func__); - STAILQ_REMOVE(&lun->io_list, lun_io, - cfi_lun_io, links); - ctl_free_io(io); - metatask->taskinfo.startstop.total_luns--; - } - } - - if (STAILQ_FIRST(&tmp_io_list) != NULL) { - printf("%s: error: tmp_io_list != NULL\n", __func__); - for (io = (union ctl_io *)STAILQ_FIRST(&tmp_io_list); - io != NULL; - io = (union ctl_io *)STAILQ_FIRST(&tmp_io_list)) { - STAILQ_REMOVE(&tmp_io_list, &io->io_hdr, - ctl_io_hdr, links); - ctl_free_io(io); - } - } - mtx_unlock(&softc->lock); - - break; - } - case CFI_TASK_BBRREAD: { - union ctl_io *io; - struct cfi_lun *lun; - struct cfi_lun_io *lun_io; - cfi_bbrread_status status; - int req_lun_num; - uint32_t num_blocks; - - status = CFI_BBR_SUCCESS; - - req_lun_num = metatask->taskinfo.bbrread.lun_num; - - mtx_lock(&softc->lock); - STAILQ_FOREACH(lun, &softc->lun_list, links) { - if (lun->lun_id != req_lun_num) - continue; - if (lun->state != CFI_LUN_READY) { - status = CFI_BBR_LUN_UNCONFIG; - break; - } else - break; - } - - if (lun == NULL) - status = CFI_BBR_NO_LUN; - - if (status != CFI_BBR_SUCCESS) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = status; - mtx_unlock(&softc->lock); - cfi_metatask_done(softc, metatask); - break; - } - - /* - * Convert the number of bytes given into blocks and check - * that the number of bytes is a multiple of the blocksize. - * CTL will verify that the LBA is okay. - */ - if (lun->blocksize_powerof2 != 0) { - if ((metatask->taskinfo.bbrread.len & - (lun->blocksize - 1)) != 0) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = - CFI_BBR_BAD_LEN; - cfi_metatask_done(softc, metatask); - break; - } - - num_blocks = metatask->taskinfo.bbrread.len >> - lun->blocksize_powerof2; - } else { - /* - * XXX KDM this could result in floating point - * division, which isn't supported in the kernel on - * x86 at least. - */ - if ((metatask->taskinfo.bbrread.len % - lun->blocksize) != 0) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = - CFI_BBR_BAD_LEN; - cfi_metatask_done(softc, metatask); - break; - } - - /* - * XXX KDM this could result in floating point - * division in some cases. - */ - num_blocks = metatask->taskinfo.bbrread.len / - lun->blocksize; - - } - - io = ctl_alloc_io_nowait(softc->port.ctl_pool_ref); - if (io == NULL) { - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_NO_MEM; - mtx_unlock(&softc->lock); - cfi_metatask_done(softc, metatask); - break; - } - - /* - * XXX KDM need to do a read capacity to get the blocksize - * for this device. - */ - ctl_scsi_read_write(io, - /*data_ptr*/ NULL, - /*data_len*/ metatask->taskinfo.bbrread.len, - /*read_op*/ 1, - /*byte2*/ 0, - /*minimum_cdb_size*/ 0, - /*lba*/ metatask->taskinfo.bbrread.lba, - /*num_blocks*/ num_blocks, - /*tag_type*/ CTL_TAG_SIMPLE, - /*control*/ 0); - - cfi_init_io(io, - /*lun*/ lun, - /*metatask*/ metatask, - /*policy*/ CFI_ERR_SOFT, - /*retries*/ 3, - /*orig_lun_io*/ NULL, - /*done_function*/ cfi_lun_io_done); - - lun_io = (struct cfi_lun_io *)io->io_hdr.port_priv; - - STAILQ_INSERT_TAIL(&lun->io_list, lun_io, links); - - if (ctl_queue(io) != CTL_RETVAL_COMPLETE) { - printf("%s: error returned from ctl_queue()!\n", - __func__); - STAILQ_REMOVE(&lun->io_list, lun_io, cfi_lun_io, links); - ctl_free_io(io); - metatask->status = CFI_MT_ERROR; - metatask->taskinfo.bbrread.status = CFI_BBR_ERROR; - mtx_unlock(&softc->lock); - cfi_metatask_done(softc, metatask); - break; - } - - mtx_unlock(&softc->lock); - break; - } - default: - panic("invalid metatask type %d", metatask->tasktype); - break; /* NOTREACHED */ - } -} - -struct cfi_metatask * -cfi_alloc_metatask(int can_wait) -{ - struct cfi_metatask *metatask; - struct cfi_softc *softc; - - softc = &fetd_internal_softc; - - metatask = uma_zalloc(cfi_metatask_zone, - (can_wait ? M_WAITOK : M_NOWAIT) | M_ZERO); - if (metatask == NULL) - return (NULL); - - metatask->status = CFI_MT_NONE; - - return (metatask); -} - -void -cfi_free_metatask(struct cfi_metatask *metatask) -{ - - uma_zfree(cfi_metatask_zone, metatask); -} - -/* - * vim: ts=8 - */ diff --git a/sys/cam/ctl/ctl_frontend_internal.h b/sys/cam/ctl/ctl_frontend_internal.h deleted file mode 100644 index cb00dc6..0000000 --- a/sys/cam/ctl/ctl_frontend_internal.h +++ /dev/null @@ -1,154 +0,0 @@ -/*- - * Copyright (c) 2004 Silicon Graphics International Corp. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * substantially similar to the "NO WARRANTY" disclaimer below - * ("Disclaimer") and any redistribution must be conditioned upon - * including a substantially similar Disclaimer requirement for further - * binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGES. - * - * $Id: //depot/users/kenm/FreeBSD-test2/sys/cam/ctl/ctl_frontend_internal.h#1 $ - * $FreeBSD$ - */ -/* - * CTL kernel internal frontend target driver. This allows kernel-level - * clients to send commands into CTL. - * - * Author: Ken Merry <ken@FreeBSD.org> - */ - -#ifndef _CTL_FRONTEND_INTERNAL_H_ -#define _CTL_FRONTEND_INTERNAL_H_ - -/* - * These are general metatask error codes. If the error code is CFI_MT_ERROR, - * check any metatask-specific status codes for more detail on the problem. - */ -typedef enum { - CFI_MT_NONE, - CFI_MT_PORT_OFFLINE, - CFI_MT_ERROR, - CFI_MT_SUCCESS -} cfi_mt_status; - -typedef enum { - CFI_TASK_NONE, - CFI_TASK_SHUTDOWN, - CFI_TASK_STARTUP, - CFI_TASK_BBRREAD -} cfi_tasktype; - -struct cfi_task_startstop { - int total_luns; - int luns_complete; - int luns_failed; -}; - -/* - * Error code description: - * CFI_BBR_SUCCESS - the read was successful - * CFI_BBR_LUN_UNCONFIG - CFI probe for this lun hasn't completed - * CFI_BBR_NO_LUN - this lun doesn't exist, as far as CFI knows - * CFI_BBR_NO_MEM - memory allocation error - * CFI_BBR_BAD_LEN - data length isn't a multiple of the blocksize - * CFI_BBR_RESERV_CONFLICT - another initiator has this lun reserved, so - * we can't issue I/O at all. - * CFI_BBR_LUN_STOPPED - the lun is powered off. - * CFI_BBR_LUN_OFFLINE_CTL - the lun is offline from a CTL standpoint - * CFI_BBR_LUN_OFFLINE_RC - the lun is offline from a RAIDCore standpoint. - * This is bad, because it basically means we've - * had a double failure on the LUN. - * CFI_BBR_SCSI_ERROR - generic SCSI error, see status byte and sense - * data for more resolution if you want it. - * CFI_BBR_ERROR - the catch-all error code. - */ -typedef enum { - CFI_BBR_SUCCESS, - CFI_BBR_LUN_UNCONFIG, - CFI_BBR_NO_LUN, - CFI_BBR_NO_MEM, - CFI_BBR_BAD_LEN, - CFI_BBR_RESERV_CONFLICT, - CFI_BBR_LUN_STOPPED, - CFI_BBR_LUN_OFFLINE_CTL, - CFI_BBR_LUN_OFFLINE_RC, - CFI_BBR_SCSI_ERROR, - CFI_BBR_ERROR, -} cfi_bbrread_status; - -struct cfi_task_bbrread { - int lun_num; /* lun number */ - uint64_t lba; /* logical block address */ - int len; /* length in bytes */ - cfi_bbrread_status status; /* BBR status */ - uint8_t scsi_status; /* SCSI status */ - struct scsi_sense_data sense_data; /* SCSI sense data */ -}; - -union cfi_taskinfo { - struct cfi_task_startstop startstop; - struct cfi_task_bbrread bbrread; -}; - -struct cfi_metatask; - -typedef void (*cfi_cb_t)(void *arg, struct cfi_metatask *metatask); - -struct cfi_metatask { - cfi_tasktype tasktype; /* passed to CFI */ - cfi_mt_status status; /* returned from CFI */ - union cfi_taskinfo taskinfo; /* returned from CFI */ - struct ctl_mem_element *element; /* used by CFI, don't touch*/ - cfi_cb_t callback; /* passed to CFI */ - void *callback_arg; /* passed to CFI */ - STAILQ_ENTRY(cfi_metatask) links; /* used by CFI, don't touch*/ -}; - -#ifdef _KERNEL - -MALLOC_DECLARE(M_CTL_CFI); - -/* - * This is the API for sending meta commands (commands that are sent to more - * than one LUN) to the internal frontend: - * - Allocate a metatask using cfi_alloc_metatask(). can_wait == 0 means - * that you're calling from an interrupt context. can_wait == 1 means - * that you're calling from a thread context and don't mind waiting to - * allocate memory. - * - Setup the task type, callback and callback argument. - * - Call cfi_action(). - * - When the callback comes, note the status and any per-command status - * (see the taskinfo union) and then free the metatask with - * cfi_free_metatask(). - */ -struct cfi_metatask *cfi_alloc_metatask(int can_wait); -void cfi_free_metatask(struct cfi_metatask *metatask); -void cfi_action(struct cfi_metatask *metatask); - -#endif /* _KERNEL */ - -#endif /* _CTL_FRONTEND_INTERNAL_H_ */ - -/* - * vim: ts=8 - */ diff --git a/sys/cam/ctl/ctl_frontend_ioctl.c b/sys/cam/ctl/ctl_frontend_ioctl.c new file mode 100644 index 0000000..7d57314 --- /dev/null +++ b/sys/cam/ctl/ctl_frontend_ioctl.c @@ -0,0 +1,470 @@ +/*- + * Copyright (c) 2003-2009 Silicon Graphics International Corp. + * Copyright (c) 2012 The FreeBSD Foundation + * Copyright (c) 2015 Alexander Motin <mav@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification, immediately at the beginning of the file. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/types.h> +#include <sys/lock.h> +#include <sys/module.h> +#include <sys/mutex.h> +#include <sys/condvar.h> +#include <sys/malloc.h> +#include <sys/conf.h> +#include <sys/queue.h> +#include <sys/sysctl.h> + +#include <cam/cam.h> +#include <cam/scsi/scsi_all.h> +#include <cam/scsi/scsi_da.h> +#include <cam/ctl/ctl_io.h> +#include <cam/ctl/ctl.h> +#include <cam/ctl/ctl_frontend.h> +#include <cam/ctl/ctl_util.h> +#include <cam/ctl/ctl_backend.h> +#include <cam/ctl/ctl_ioctl.h> +#include <cam/ctl/ctl_ha.h> +#include <cam/ctl/ctl_private.h> +#include <cam/ctl/ctl_debug.h> +#include <cam/ctl/ctl_error.h> + +struct cfi_softc { + uint32_t cur_tag_num; + struct ctl_port port; +}; + +static struct cfi_softc cfi_softc; + +static int cfi_init(void); +static void cfi_shutdown(void); +static void cfi_online(void *arg); +static void cfi_offline(void *arg); +static int cfi_lun_enable(void *arg, int lun_id); +static int cfi_lun_disable(void *arg, int lun_id); +static void cfi_datamove(union ctl_io *io); +static void cfi_done(union ctl_io *io); + +static struct ctl_frontend cfi_frontend = +{ + .name = "ioctl", + .init = cfi_init, + .shutdown = cfi_shutdown, +}; +CTL_FRONTEND_DECLARE(ctlioctl, cfi_frontend); + +static int +cfi_init(void) +{ + struct cfi_softc *isoftc = &cfi_softc; + struct ctl_port *port; + + memset(isoftc, 0, sizeof(*isoftc)); + + port = &isoftc->port; + port->frontend = &cfi_frontend; + port->port_type = CTL_PORT_IOCTL; + port->num_requested_ctl_io = 100; + port->port_name = "ioctl"; + port->port_online = cfi_online; + port->port_offline = cfi_offline; + port->onoff_arg = &isoftc; + port->lun_enable = cfi_lun_enable; + port->lun_disable = cfi_lun_disable; + port->targ_lun_arg = &isoftc; + port->fe_datamove = cfi_datamove; + port->fe_done = cfi_done; + port->max_targets = 1; + port->max_target_id = 0; + port->max_initiators = 1; + + if (ctl_port_register(port) != 0) { + printf("%s: ioctl port registration failed\n", __func__); + return (0); + } + ctl_port_online(port); + return (0); +} + +void +cfi_shutdown(void) +{ + struct cfi_softc *isoftc = &cfi_softc; + struct ctl_port *port; + + port = &isoftc->port; + ctl_port_offline(port); + if (ctl_port_deregister(&isoftc->port) != 0) + printf("%s: ctl_frontend_deregister() failed\n", __func__); +} + +static void +cfi_online(void *arg) +{ +} + +static void +cfi_offline(void *arg) +{ +} + +static int +cfi_lun_enable(void *arg, int lun_id) +{ + + return (0); +} + +static int +cfi_lun_disable(void *arg, int lun_id) +{ + + return (0); +} + +/* + * Data movement routine for the CTL ioctl frontend port. + */ +static int +ctl_ioctl_do_datamove(struct ctl_scsiio *ctsio) +{ + struct ctl_sg_entry *ext_sglist, *kern_sglist; + struct ctl_sg_entry ext_entry, kern_entry; + int ext_sglen, ext_sg_entries, kern_sg_entries; + int ext_sg_start, ext_offset; + int len_to_copy, len_copied; + int kern_watermark, ext_watermark; + int ext_sglist_malloced; + int i, j; + + ext_sglist_malloced = 0; + ext_sg_start = 0; + ext_offset = 0; + + CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove\n")); + + /* + * If this flag is set, fake the data transfer. + */ + if (ctsio->io_hdr.flags & CTL_FLAG_NO_DATAMOVE) { + ctsio->ext_data_filled = ctsio->ext_data_len; + goto bailout; + } + + /* + * To simplify things here, if we have a single buffer, stick it in + * a S/G entry and just make it a single entry S/G list. + */ + if (ctsio->io_hdr.flags & CTL_FLAG_EDPTR_SGLIST) { + int len_seen; + + ext_sglen = ctsio->ext_sg_entries * sizeof(*ext_sglist); + + ext_sglist = (struct ctl_sg_entry *)malloc(ext_sglen, M_CTL, + M_WAITOK); + ext_sglist_malloced = 1; + if (copyin(ctsio->ext_data_ptr, ext_sglist, + ext_sglen) != 0) { + ctl_set_internal_failure(ctsio, + /*sks_valid*/ 0, + /*retry_count*/ 0); + goto bailout; + } + ext_sg_entries = ctsio->ext_sg_entries; + len_seen = 0; + for (i = 0; i < ext_sg_entries; i++) { + if ((len_seen + ext_sglist[i].len) >= + ctsio->ext_data_filled) { + ext_sg_start = i; + ext_offset = ctsio->ext_data_filled - len_seen; + break; + } + len_seen += ext_sglist[i].len; + } + } else { + ext_sglist = &ext_entry; + ext_sglist->addr = ctsio->ext_data_ptr; + ext_sglist->len = ctsio->ext_data_len; + ext_sg_entries = 1; + ext_sg_start = 0; + ext_offset = ctsio->ext_data_filled; + } + + if (ctsio->kern_sg_entries > 0) { + kern_sglist = (struct ctl_sg_entry *)ctsio->kern_data_ptr; + kern_sg_entries = ctsio->kern_sg_entries; + } else { + kern_sglist = &kern_entry; + kern_sglist->addr = ctsio->kern_data_ptr; + kern_sglist->len = ctsio->kern_data_len; + kern_sg_entries = 1; + } + + + kern_watermark = 0; + ext_watermark = ext_offset; + len_copied = 0; + for (i = ext_sg_start, j = 0; + i < ext_sg_entries && j < kern_sg_entries;) { + uint8_t *ext_ptr, *kern_ptr; + + len_to_copy = MIN(ext_sglist[i].len - ext_watermark, + kern_sglist[j].len - kern_watermark); + + ext_ptr = (uint8_t *)ext_sglist[i].addr; + ext_ptr = ext_ptr + ext_watermark; + if (ctsio->io_hdr.flags & CTL_FLAG_BUS_ADDR) { + /* + * XXX KDM fix this! + */ + panic("need to implement bus address support"); +#if 0 + kern_ptr = bus_to_virt(kern_sglist[j].addr); +#endif + } else + kern_ptr = (uint8_t *)kern_sglist[j].addr; + kern_ptr = kern_ptr + kern_watermark; + + kern_watermark += len_to_copy; + ext_watermark += len_to_copy; + + if ((ctsio->io_hdr.flags & CTL_FLAG_DATA_MASK) == + CTL_FLAG_DATA_IN) { + CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: copying %d " + "bytes to user\n", len_to_copy)); + CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: from %p " + "to %p\n", kern_ptr, ext_ptr)); + if (copyout(kern_ptr, ext_ptr, len_to_copy) != 0) { + ctl_set_internal_failure(ctsio, + /*sks_valid*/ 0, + /*retry_count*/ 0); + goto bailout; + } + } else { + CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: copying %d " + "bytes from user\n", len_to_copy)); + CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: from %p " + "to %p\n", ext_ptr, kern_ptr)); + if (copyin(ext_ptr, kern_ptr, len_to_copy)!= 0){ + ctl_set_internal_failure(ctsio, + /*sks_valid*/ 0, + /*retry_count*/0); + goto bailout; + } + } + + len_copied += len_to_copy; + + if (ext_sglist[i].len == ext_watermark) { + i++; + ext_watermark = 0; + } + + if (kern_sglist[j].len == kern_watermark) { + j++; + kern_watermark = 0; + } + } + + ctsio->ext_data_filled += len_copied; + + CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: ext_sg_entries: %d, " + "kern_sg_entries: %d\n", ext_sg_entries, + kern_sg_entries)); + CTL_DEBUG_PRINT(("ctl_ioctl_do_datamove: ext_data_len = %d, " + "kern_data_len = %d\n", ctsio->ext_data_len, + ctsio->kern_data_len)); + + + /* XXX KDM set residual?? */ +bailout: + + if (ext_sglist_malloced != 0) + free(ext_sglist, M_CTL); + + return (CTL_RETVAL_COMPLETE); +} + +static void +cfi_datamove(union ctl_io *io) +{ + struct ctl_fe_ioctl_params *params; + + params = (struct ctl_fe_ioctl_params *) + io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; + + mtx_lock(¶ms->ioctl_mtx); + params->state = CTL_IOCTL_DATAMOVE; + cv_broadcast(¶ms->sem); + mtx_unlock(¶ms->ioctl_mtx); +} + +static void +cfi_done(union ctl_io *io) +{ + struct ctl_fe_ioctl_params *params; + + params = (struct ctl_fe_ioctl_params *) + io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr; + + mtx_lock(¶ms->ioctl_mtx); + params->state = CTL_IOCTL_DONE; + cv_broadcast(¶ms->sem); + mtx_unlock(¶ms->ioctl_mtx); +} + +static int +cfi_submit_wait(union ctl_io *io) +{ + struct ctl_fe_ioctl_params params; + ctl_fe_ioctl_state last_state; + int done, retval; + + retval = 0; + + bzero(¶ms, sizeof(params)); + + mtx_init(¶ms.ioctl_mtx, "ctliocmtx", NULL, MTX_DEF); + cv_init(¶ms.sem, "ctlioccv"); + params.state = CTL_IOCTL_INPROG; + last_state = params.state; + + io->io_hdr.ctl_private[CTL_PRIV_FRONTEND].ptr = ¶ms; + + CTL_DEBUG_PRINT(("cfi_submit_wait\n")); + + /* This shouldn't happen */ + if ((retval = ctl_queue(io)) != CTL_RETVAL_COMPLETE) + return (retval); + + done = 0; + + do { + mtx_lock(¶ms.ioctl_mtx); + /* + * Check the state here, and don't sleep if the state has + * already changed (i.e. wakeup has already occured, but we + * weren't waiting yet). + */ + if (params.state == last_state) { + /* XXX KDM cv_wait_sig instead? */ + cv_wait(¶ms.sem, ¶ms.ioctl_mtx); + } + last_state = params.state; + + switch (params.state) { + case CTL_IOCTL_INPROG: + /* Why did we wake up? */ + /* XXX KDM error here? */ + mtx_unlock(¶ms.ioctl_mtx); + break; + case CTL_IOCTL_DATAMOVE: + CTL_DEBUG_PRINT(("got CTL_IOCTL_DATAMOVE\n")); + + /* + * change last_state back to INPROG to avoid + * deadlock on subsequent data moves. + */ + params.state = last_state = CTL_IOCTL_INPROG; + + mtx_unlock(¶ms.ioctl_mtx); + ctl_ioctl_do_datamove(&io->scsiio); + /* + * Note that in some cases, most notably writes, + * this will queue the I/O and call us back later. + * In other cases, generally reads, this routine + * will immediately call back and wake us up, + * probably using our own context. + */ + io->scsiio.be_move_done(io); + break; + case CTL_IOCTL_DONE: + mtx_unlock(¶ms.ioctl_mtx); + CTL_DEBUG_PRINT(("got CTL_IOCTL_DONE\n")); + done = 1; + break; + default: + mtx_unlock(¶ms.ioctl_mtx); + /* XXX KDM error here? */ + break; + } + } while (done == 0); + + mtx_destroy(¶ms.ioctl_mtx); + cv_destroy(¶ms.sem); + + return (CTL_RETVAL_COMPLETE); +} + +int +ctl_ioctl_io(struct cdev *dev, u_long cmd, caddr_t addr, int flag, + struct thread *td) +{ + union ctl_io *io; + void *pool_tmp; + int retval = 0; + + /* + * If we haven't been "enabled", don't allow any SCSI I/O + * to this FETD. + */ + if ((cfi_softc.port.status & CTL_PORT_STATUS_ONLINE) == 0) + return (EPERM); + + io = ctl_alloc_io(cfi_softc.port.ctl_pool_ref); + + /* + * Need to save the pool reference so it doesn't get + * spammed by the user's ctl_io. + */ + pool_tmp = io->io_hdr.pool; + memcpy(io, (void *)addr, sizeof(*io)); + io->io_hdr.pool = pool_tmp; + + /* + * No status yet, so make sure the status is set properly. + */ + io->io_hdr.status = CTL_STATUS_NONE; + + /* + * The user sets the initiator ID, target and LUN IDs. + */ + io->io_hdr.nexus.targ_port = cfi_softc.port.targ_port; + io->io_hdr.flags |= CTL_FLAG_USER_REQ; + if ((io->io_hdr.io_type == CTL_IO_SCSI) && + (io->scsiio.tag_type != CTL_TAG_UNTAGGED)) + io->scsiio.tag_num = cfi_softc.cur_tag_num++; + + retval = cfi_submit_wait(io); + if (retval == 0) + memcpy((void *)addr, io, sizeof(*io)); + ctl_free_io(io); + return (retval); +} diff --git a/sys/cam/ctl/ctl_frontend_iscsi.c b/sys/cam/ctl/ctl_frontend_iscsi.c index 652c961..7f8f8a8 100644 --- a/sys/cam/ctl/ctl_frontend_iscsi.c +++ b/sys/cam/ctl/ctl_frontend_iscsi.c @@ -61,7 +61,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_error.h> #include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_debug.h> #include <cam/ctl/ctl_ha.h> #include <cam/ctl/ctl_ioctl.h> diff --git a/sys/cam/ctl/ctl_ioctl.h b/sys/cam/ctl/ctl_ioctl.h index c7a3c29..f62bbe1 100644 --- a/sys/cam/ctl/ctl_ioctl.h +++ b/sys/cam/ctl/ctl_ioctl.h @@ -92,23 +92,6 @@ struct ctl_ooa_info { ctl_ooa_status status; /* Returned from CTL */ }; -struct ctl_hard_startstop_info { - cfi_mt_status status; - int total_luns; - int luns_complete; - int luns_failed; -}; - -struct ctl_bbrread_info { - int lun_num; /* Passed in to CTL */ - uint64_t lba; /* Passed in to CTL */ - int len; /* Passed in to CTL */ - cfi_mt_status status; /* Returned from CTL */ - cfi_bbrread_status bbr_status; /* Returned from CTL */ - uint8_t scsi_status; /* Returned from CTL */ - struct scsi_sense_data sense_data; /* Returned from CTL */ -}; - typedef enum { CTL_DELAY_TYPE_NONE, CTL_DELAY_TYPE_CONT, @@ -828,10 +811,6 @@ struct ctl_lun_map { #define CTL_DISABLE_PORT _IOW(CTL_MINOR, 0x05, struct ctl_port_entry) #define CTL_DUMP_OOA _IO(CTL_MINOR, 0x06) #define CTL_CHECK_OOA _IOWR(CTL_MINOR, 0x07, struct ctl_ooa_info) -#define CTL_HARD_STOP _IOR(CTL_MINOR, 0x08, \ - struct ctl_hard_startstop_info) -#define CTL_HARD_START _IOR(CTL_MINOR, 0x09, \ - struct ctl_hard_startstop_info) #define CTL_DELAY_IO _IOWR(CTL_MINOR, 0x10, struct ctl_io_delay_info) #define CTL_REALSYNC_GET _IOR(CTL_MINOR, 0x11, int) #define CTL_REALSYNC_SET _IOW(CTL_MINOR, 0x12, int) @@ -839,7 +818,6 @@ struct ctl_lun_map { #define CTL_GETSYNC _IOWR(CTL_MINOR, 0x14, struct ctl_sync_info) #define CTL_GETSTATS _IOWR(CTL_MINOR, 0x15, struct ctl_stats) #define CTL_ERROR_INJECT _IOWR(CTL_MINOR, 0x16, struct ctl_error_desc) -#define CTL_BBRREAD _IOWR(CTL_MINOR, 0x17, struct ctl_bbrread_info) #define CTL_GET_OOA _IOWR(CTL_MINOR, 0x18, struct ctl_ooa) #define CTL_DUMP_STRUCTS _IO(CTL_MINOR, 0x19) #define CTL_GET_PORT_LIST _IOWR(CTL_MINOR, 0x20, struct ctl_port_list) diff --git a/sys/cam/ctl/ctl_private.h b/sys/cam/ctl/ctl_private.h index a038552..6f7379a 100644 --- a/sys/cam/ctl/ctl_private.h +++ b/sys/cam/ctl/ctl_private.h @@ -47,18 +47,6 @@ #define CTL_PROCESSOR_PRODUCT "CTLPROCESSOR " #define CTL_UNKNOWN_PRODUCT "CTLDEVICE " -struct ctl_fe_ioctl_startstop_info { - struct cv sem; - struct ctl_hard_startstop_info hs_info; -}; - -struct ctl_fe_ioctl_bbrread_info { - struct cv sem; - struct ctl_bbrread_info *bbr_info; - int wakeup_done; - struct mtx *lock; -}; - typedef enum { CTL_IOCTL_INPROG, CTL_IOCTL_DATAMOVE, @@ -81,18 +69,6 @@ struct ctl_io_pool { }; typedef enum { - CTL_IOCTL_FLAG_NONE = 0x00, - CTL_IOCTL_FLAG_ENABLED = 0x01 -} ctl_ioctl_flags; - -struct ctl_ioctl_info { - ctl_ioctl_flags flags; - uint32_t cur_tag_num; - struct ctl_port port; - char port_name[24]; -}; - -typedef enum { CTL_SER_BLOCK, CTL_SER_BLOCKOPT, CTL_SER_EXTENT, @@ -472,7 +448,6 @@ struct ctl_softc { int inquiry_pq_no_lun; struct sysctl_ctx_list sysctl_ctx; struct sysctl_oid *sysctl_tree; - struct ctl_ioctl_info ioctl_info; void *othersc_pool; struct proc *ctl_proc; int targ_online; diff --git a/sys/cam/ctl/ctl_tpc.c b/sys/cam/ctl/ctl_tpc.c index 662ee3d..b1b674f 100644 --- a/sys/cam/ctl/ctl_tpc.c +++ b/sys/cam/ctl/ctl_tpc.c @@ -47,7 +47,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_util.h> #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_ioctl.h> diff --git a/sys/cam/ctl/ctl_tpc_local.c b/sys/cam/ctl/ctl_tpc_local.c index d0319ee..fb1f2ac 100644 --- a/sys/cam/ctl/ctl_tpc_local.c +++ b/sys/cam/ctl/ctl_tpc_local.c @@ -47,7 +47,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_frontend.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_util.h> #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_ioctl.h> diff --git a/sys/cddl/compat/opensolaris/sys/nvpair.h b/sys/cddl/compat/opensolaris/sys/nvpair.h index c90ab70..33b62cb 100644 --- a/sys/cddl/compat/opensolaris/sys/nvpair.h +++ b/sys/cddl/compat/opensolaris/sys/nvpair.h @@ -42,29 +42,19 @@ */ #define nvlist_add_binary illumos_nvlist_add_binary #define nvlist_add_bool illumos_nvlist_add_bool +#define nvlist_add_bool_array illumos_nvlist_add_bool_array #define nvlist_add_descriptor illumos_nvlist_add_descriptor +#define nvlist_add_descriptor_array illumos_nvlist_add_descriptor_array #define nvlist_add_null illumos_nvlist_add_null #define nvlist_add_number illumos_nvlist_add_number +#define nvlist_add_number_array illumos_nvlist_add_number_array #define nvlist_add_nvlist illumos_nvlist_add_nvlist +#define nvlist_add_nvlist_array illumos_nvlist_add_nvlist_array #define nvlist_add_nvpair illumos_nvlist_add_nvpair #define nvlist_add_string illumos_nvlist_add_string +#define nvlist_add_string_array illumos_nvlist_add_string_array #define nvlist_add_stringf illumos_nvlist_add_stringf #define nvlist_add_stringv illumos_nvlist_add_stringv -#define nvlist_addf_binary illumos_nvlist_addf_binary -#define nvlist_addf_bool illumos_nvlist_addf_bool -#define nvlist_addf_descriptor illumos_nvlist_addf_descriptor -#define nvlist_addf_null illumos_nvlist_addf_null -#define nvlist_addf_number illumos_nvlist_addf_number -#define nvlist_addf_nvlist illumos_nvlist_addf_nvlist -#define nvlist_addf_string illumos_nvlist_addf_string -#define nvlist_addv_binary illumos_nvlist_addv_binary -#define nvlist_addv_bool illumos_nvlist_addv_bool -#define nvlist_addv_descriptor illumos_nvlist_addv_descriptor -#define nvlist_addv_null illumos_nvlist_addv_null -#define nvlist_addv_number illumos_nvlist_addv_number -#define nvlist_addv_nvlist illumos_nvlist_addv_nvlist -#define nvlist_addv_string illumos_nvlist_addv_string -#define nvlist_check_header illumos_nvlist_check_header #define nvlist_clone illumos_nvlist_clone #define nvlist_create illumos_nvlist_create #define nvlist_descriptors illumos_nvlist_descriptors @@ -75,92 +65,61 @@ #define nvlist_exists illumos_nvlist_exists #define nvlist_exists_binary illumos_nvlist_exists_binary #define nvlist_exists_bool illumos_nvlist_exists_bool +#define nvlist_exists_bool_array illumos_nvlist_exists_bool_array #define nvlist_exists_descriptor illumos_nvlist_exists_descriptor +#define nvlist_exists_descriptor_array illumos_nvlist_exists_descriptor_array #define nvlist_exists_null illumos_nvlist_exists_null #define nvlist_exists_number illumos_nvlist_exists_number +#define nvlist_exists_number_array illumos_nvlist_exists_number_array #define nvlist_exists_nvlist illumos_nvlist_exists_nvlist +#define nvlist_exists_nvlist_array illumos_nvlist_exists_nvlist_array #define nvlist_exists_string illumos_nvlist_exists_string +#define nvlist_exists_string_array illumos_nvlist_exists_string_array #define nvlist_exists_type illumos_nvlist_exists_type -#define nvlist_existsf illumos_nvlist_existsf -#define nvlist_existsf_binary illumos_nvlist_existsf_binary -#define nvlist_existsf_bool illumos_nvlist_existsf_bool -#define nvlist_existsf_descriptor illumos_nvlist_existsf_descriptor -#define nvlist_existsf_null illumos_nvlist_existsf_null -#define nvlist_existsf_number illumos_nvlist_existsf_number -#define nvlist_existsf_nvlist illumos_nvlist_existsf_nvlist -#define nvlist_existsf_string illumos_nvlist_existsf_string -#define nvlist_existsf_type illumos_nvlist_existsf_type -#define nvlist_existsv illumos_nvlist_existsv -#define nvlist_existsv_binary illumos_nvlist_existsv_binary -#define nvlist_existsv_bool illumos_nvlist_existsv_bool -#define nvlist_existsv_descriptor illumos_nvlist_existsv_descriptor -#define nvlist_existsv_null illumos_nvlist_existsv_null -#define nvlist_existsv_number illumos_nvlist_existsv_number -#define nvlist_existsv_nvlist illumos_nvlist_existsv_nvlist -#define nvlist_existsv_string illumos_nvlist_existsv_string -#define nvlist_existsv_type illumos_nvlist_existsv_type #define nvlist_fdump illumos_nvlist_fdump #define nvlist_first_nvpair illumos_nvlist_first_nvpair +#define nvlist_flags illumos_nvlist_flags #define nvlist_free illumos_nvlist_free #define nvlist_free_binary illumos_nvlist_free_binary +#define nvlist_free_binary_array illumos_nvlist_free_binary_array #define nvlist_free_bool illumos_nvlist_free_bool +#define nvlist_free_bool_array illumos_nvlist_free_bool_array #define nvlist_free_descriptor illumos_nvlist_free_descriptor +#define nvlist_free_descriptor_array illumos_nvlist_free_descriptor_array #define nvlist_free_null illumos_nvlist_free_null #define nvlist_free_number illumos_nvlist_free_number +#define nvlist_free_number_array illumos_nvlist_free_number_array #define nvlist_free_nvlist illumos_nvlist_free_nvlist +#define nvlist_free_nvlist_array illumos_nvlist_free_nvlist_array #define nvlist_free_nvpair illumos_nvlist_free_nvpair #define nvlist_free_string illumos_nvlist_free_string +#define nvlist_free_string_array illumos_nvlist_free_string_array #define nvlist_free_type illumos_nvlist_free_type -#define nvlist_freef illumos_nvlist_freef -#define nvlist_freef_binary illumos_nvlist_freef_binary -#define nvlist_freef_bool illumos_nvlist_freef_bool -#define nvlist_freef_descriptor illumos_nvlist_freef_descriptor -#define nvlist_freef_null illumos_nvlist_freef_null -#define nvlist_freef_number illumos_nvlist_freef_number -#define nvlist_freef_nvlist illumos_nvlist_freef_nvlist -#define nvlist_freef_string illumos_nvlist_freef_string -#define nvlist_freef_type illumos_nvlist_freef_type -#define nvlist_freev illumos_nvlist_freev -#define nvlist_freev_binary illumos_nvlist_freev_binary -#define nvlist_freev_bool illumos_nvlist_freev_bool -#define nvlist_freev_descriptor illumos_nvlist_freev_descriptor -#define nvlist_freev_null illumos_nvlist_freev_null -#define nvlist_freev_number illumos_nvlist_freev_number -#define nvlist_freev_nvlist illumos_nvlist_freev_nvlist -#define nvlist_freev_string illumos_nvlist_freev_string -#define nvlist_freev_type illumos_nvlist_freev_type +#define nvlist_get_array_next illumos_nvlist_get_array_next #define nvlist_get_binary illumos_nvlist_get_binary #define nvlist_get_bool illumos_nvlist_get_bool +#define nvlist_get_bool_array illumos_nvlist_get_bool_array #define nvlist_get_descriptor illumos_nvlist_get_descriptor +#define nvlist_get_descriptor_array illumos_nvlist_get_descriptor_array #define nvlist_get_number illumos_nvlist_get_number +#define nvlist_get_number_array illumos_nvlist_get_number_array #define nvlist_get_nvlist illumos_nvlist_get_nvlist #define nvlist_get_nvpair illumos_nvlist_get_nvpair +#define nvlist_get_nvpair_parent illumos_nvlist_get_nvpair_parent +#define nvlist_get_pararr illumos_nvlist_get_pararr +#define nvlist_get_parent illumos_nvlist_get_parent #define nvlist_get_string illumos_nvlist_get_string -#define nvlist_getf_binary illumos_nvlist_getf_binary -#define nvlist_getf_bool illumos_nvlist_getf_bool -#define nvlist_getf_descriptor illumos_nvlist_getf_descriptor -#define nvlist_getf_number illumos_nvlist_getf_number -#define nvlist_getf_nvlist illumos_nvlist_getf_nvlist -#define nvlist_getf_string illumos_nvlist_getf_string -#define nvlist_getv_binary illumos_nvlist_getv_binary -#define nvlist_getv_bool illumos_nvlist_getv_bool -#define nvlist_getv_descriptor illumos_nvlist_getv_descriptor -#define nvlist_getv_number illumos_nvlist_getv_number -#define nvlist_getv_nvlist illumos_nvlist_getv_nvlist -#define nvlist_getv_string illumos_nvlist_getv_string +#define nvlist_in_array illumos_nvlist_in_array #define nvlist_move_binary illumos_nvlist_move_binary +#define nvlist_move_bool_array illumos_nvlist_move_bool_array #define nvlist_move_descriptor illumos_nvlist_move_descriptor +#define nvlist_move_descriptor_array illumos_nvlist_move_descriptor_array +#define nvlist_move_number_array illumos_nvlist_move_number_array #define nvlist_move_nvlist illumos_nvlist_move_nvlist +#define nvlist_move_nvlist_array illumos_nvlist_move_nvlist_array #define nvlist_move_nvpair illumos_nvlist_move_nvpair #define nvlist_move_string illumos_nvlist_move_string -#define nvlist_movef_binary illumos_nvlist_movef_binary -#define nvlist_movef_descriptor illumos_nvlist_movef_descriptor -#define nvlist_movef_nvlist illumos_nvlist_movef_nvlist -#define nvlist_movef_string illumos_nvlist_movef_string -#define nvlist_movev_binary illumos_nvlist_movev_binary -#define nvlist_movev_descriptor illumos_nvlist_movev_descriptor -#define nvlist_movev_nvlist illumos_nvlist_movev_nvlist -#define nvlist_movev_string illumos_nvlist_movev_string +#define nvlist_move_string_array illumos_nvlist_move_string_array #define nvlist_ndescriptors illumos_nvlist_ndescriptors #define nvlist_next illumos_nvlist_next #define nvlist_next_nvpair illumos_nvlist_next_nvpair @@ -168,93 +127,101 @@ #define nvlist_prev_nvpair illumos_nvlist_prev_nvpair #define nvlist_recv illumos_nvlist_recv #define nvlist_remove_nvpair illumos_nvlist_remove_nvpair -#define nvlist_report_missing illumos_nvlist_report_missing #define nvlist_send illumos_nvlist_send +#define nvlist_set_array_next illumos_nvlist_set_array_next #define nvlist_set_error illumos_nvlist_set_error +#define nvlist_set_flags illumos_nvlist_set_flags +#define nvlist_set_parent illumos_nvlist_set_parent #define nvlist_size illumos_nvlist_size #define nvlist_take_binary illumos_nvlist_take_binary #define nvlist_take_bool illumos_nvlist_take_bool +#define nvlist_take_bool_array illumos_nvlist_take_bool_array #define nvlist_take_descriptor illumos_nvlist_take_descriptor +#define nvlist_take_descriptor_array illumos_nvlist_take_descriptor_array #define nvlist_take_number illumos_nvlist_take_number +#define nvlist_take_number_array illumos_nvlist_take_number_array #define nvlist_take_nvlist illumos_nvlist_take_nvlist +#define nvlist_take_nvlist_array illumos_nvlist_take_nvlist_array #define nvlist_take_nvpair illumos_nvlist_take_nvpair #define nvlist_take_string illumos_nvlist_take_string -#define nvlist_takef_binary illumos_nvlist_takef_binary -#define nvlist_takef_bool illumos_nvlist_takef_bool -#define nvlist_takef_descriptor illumos_nvlist_takef_descriptor -#define nvlist_takef_number illumos_nvlist_takef_number -#define nvlist_takef_nvlist illumos_nvlist_takef_nvlist -#define nvlist_takef_string illumos_nvlist_takef_string -#define nvlist_takev_binary illumos_nvlist_takev_binary -#define nvlist_takev_bool illumos_nvlist_takev_bool -#define nvlist_takev_descriptor illumos_nvlist_takev_descriptor -#define nvlist_takev_number illumos_nvlist_takev_number -#define nvlist_takev_nvlist illumos_nvlist_takev_nvlist -#define nvlist_takev_string illumos_nvlist_takev_string +#define nvlist_take_string_array illumos_nvlist_take_string_array #define nvlist_unpack illumos_nvlist_unpack +#define nvlist_unpack_header illumos_nvlist_unpack_header #define nvlist_xfer illumos_nvlist_xfer -#define nvlist_xpack illumos_nvlist_xpack -#define nvlist_xunpack illumos_nvlist_xunpack -#define nvpair_allocv illumos_nvpair_allocv #define nvpair_assert illumos_nvpair_assert #define nvpair_clone illumos_nvpair_clone #define nvpair_create_binary illumos_nvpair_create_binary #define nvpair_create_bool illumos_nvpair_create_bool +#define nvpair_create_bool_array illumos_nvpair_create_bool_array #define nvpair_create_descriptor illumos_nvpair_create_descriptor +#define nvpair_create_descriptor_array illumos_nvpair_create_descriptor_array #define nvpair_create_null illumos_nvpair_create_null #define nvpair_create_number illumos_nvpair_create_number +#define nvpair_create_number_array illumos_nvpair_create_number_array #define nvpair_create_nvlist illumos_nvpair_create_nvlist +#define nvpair_create_nvlist_array illumos_nvpair_create_nvlist_array #define nvpair_create_string illumos_nvpair_create_string +#define nvpair_create_string_array illumos_nvpair_create_string_array #define nvpair_create_stringf illumos_nvpair_create_stringf #define nvpair_create_stringv illumos_nvpair_create_stringv -#define nvpair_createf_binary illumos_nvpair_createf_binary -#define nvpair_createf_bool illumos_nvpair_createf_bool -#define nvpair_createf_descriptor illumos_nvpair_createf_descriptor -#define nvpair_createf_null illumos_nvpair_createf_null -#define nvpair_createf_number illumos_nvpair_createf_number -#define nvpair_createf_nvlist illumos_nvpair_createf_nvlist -#define nvpair_createf_string illumos_nvpair_createf_string -#define nvpair_createv_binary illumos_nvpair_createv_binary -#define nvpair_createv_bool illumos_nvpair_createv_bool -#define nvpair_createv_descriptor illumos_nvpair_createv_descriptor -#define nvpair_createv_null illumos_nvpair_createv_null -#define nvpair_createv_number illumos_nvpair_createv_number -#define nvpair_createv_nvlist illumos_nvpair_createv_nvlist -#define nvpair_createv_string illumos_nvpair_createv_string #define nvpair_free illumos_nvpair_free #define nvpair_free_structure illumos_nvpair_free_structure #define nvpair_get_binary illumos_nvpair_get_binary #define nvpair_get_bool illumos_nvpair_get_bool +#define nvpair_get_bool_array illumos_nvpair_get_bool_array #define nvpair_get_descriptor illumos_nvpair_get_descriptor +#define nvpair_get_descriptor_array illumos_nvpair_get_descriptor_array #define nvpair_get_number illumos_nvpair_get_number +#define nvpair_get_number_array illumos_nvpair_get_number_array #define nvpair_get_nvlist illumos_nvpair_get_nvlist #define nvpair_get_string illumos_nvpair_get_string #define nvpair_header_size illumos_nvpair_header_size +#define nvpair_init_datasize illumos_nvpair_init_datasize #define nvpair_insert illumos_nvpair_insert #define nvpair_move_binary illumos_nvpair_move_binary +#define nvpair_move_bool_array illumos_nvpair_move_bool_array #define nvpair_move_descriptor illumos_nvpair_move_descriptor +#define nvpair_move_descriptor_array illumos_nvpair_move_descriptor_array +#define nvpair_move_number_array illumos_nvpair_move_number_array #define nvpair_move_nvlist illumos_nvpair_move_nvlist +#define nvpair_move_nvlist_array illumos_nvpair_move_nvlist_array #define nvpair_move_string illumos_nvpair_move_string -#define nvpair_movef_binary illumos_nvpair_movef_binary -#define nvpair_movef_descriptor illumos_nvpair_movef_descriptor -#define nvpair_movef_nvlist illumos_nvpair_movef_nvlist -#define nvpair_movef_string illumos_nvpair_movef_string -#define nvpair_movev_binary illumos_nvpair_movev_binary -#define nvpair_movev_descriptor illumos_nvpair_movev_descriptor -#define nvpair_movev_nvlist illumos_nvpair_movev_nvlist -#define nvpair_movev_string illumos_nvpair_movev_string +#define nvpair_move_string_array illumos_nvpair_move_string_array #define nvpair_name illumos_nvpair_name #define nvpair_next illumos_nvpair_next #define nvpair_nvlist illumos_nvpair_nvlist -#define nvpair_pack illumos_nvpair_pack +#define nvpair_pack_binary illumos_nvpair_pack_binary +#define nvpair_pack_bool illumos_nvpair_pack_bool +#define nvpair_pack_bool_array illumos_nvpair_pack_bool_array #define nvpair_pack_descriptor illumos_nvpair_pack_descriptor +#define nvpair_pack_descriptor_array illumos_nvpair_pack_descriptor_array +#define nvpair_pack_header illumos_nvpair_pack_header +#define nvpair_pack_null illumos_nvpair_pack_null +#define nvpair_pack_number illumos_nvpair_pack_number +#define nvpair_pack_number_array illumos_nvpair_pack_number_array +#define nvpair_pack_nvlist_array_next illumos_nvpair_pack_nvlist_array_next +#define nvpair_pack_nvlist_up illumos_nvpair_pack_nvlist_up +#define nvpair_pack_string illumos_nvpair_pack_string +#define nvpair_pack_string_array illumos_nvpair_pack_string_array #define nvpair_prev illumos_nvpair_prev #define nvpair_remove illumos_nvpair_remove #define nvpair_size illumos_nvpair_size #define nvpair_type illumos_nvpair_type #define nvpair_type_string illumos_nvpair_type_string #define nvpair_unpack illumos_nvpair_unpack +#define nvpair_unpack_binary illumos_nvpair_unpack_binary +#define nvpair_unpack_bool illumos_nvpair_unpack_bool +#define nvpair_unpack_bool_array illumos_nvpair_unpack_bool_array #define nvpair_unpack_descriptor illumos_nvpair_unpack_descriptor +#define nvpair_unpack_descriptor_array illumos_nvpair_unpack_descriptor_array +#define nvpair_unpack_header illumos_nvpair_unpack_header +#define nvpair_unpack_null illumos_nvpair_unpack_null +#define nvpair_unpack_number illumos_nvpair_unpack_number +#define nvpair_unpack_number_array illumos_nvpair_unpack_number_array +#define nvpair_unpack_nvlist illumos_nvpair_unpack_nvlist +#define nvpair_unpack_nvlist_array illumos_nvpair_unpack_nvlist_array +#define nvpair_unpack_string illumos_nvpair_unpack_string +#define nvpair_unpack_string_array illumos_nvpair_unpack_string_array #endif /* _KERNEL */ diff --git a/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.c b/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.c index 52a355d..d59fbf0 100644 --- a/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.c +++ b/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.c @@ -20,7 +20,7 @@ */ /* - * Copyright (c) 2013 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2013 by Saso Kiselkov. All rights reserved. * Copyright (c) 2013, Joyent, Inc. All rights reserved. * Copyright (c) 2014, Nexenta Systems, Inc. All rights reserved. @@ -129,15 +129,15 @@ zfeature_depends_on(spa_feature_t fid, spa_feature_t check) { static void zfeature_register(spa_feature_t fid, const char *guid, const char *name, - const char *desc, boolean_t readonly, boolean_t mos, - boolean_t activate_on_enable, const spa_feature_t *deps) + const char *desc, zfeature_flags_t flags, const spa_feature_t *deps) { zfeature_info_t *feature = &spa_feature_table[fid]; static spa_feature_t nodeps[] = { SPA_FEATURE_NONE }; ASSERT(name != NULL); ASSERT(desc != NULL); - ASSERT(!readonly || !mos); + ASSERT((flags & ZFEATURE_FLAG_READONLY_COMPAT) == 0 || + (flags & ZFEATURE_FLAG_MOS) == 0); ASSERT3U(fid, <, SPA_FEATURES); ASSERT(zfeature_is_valid_guid(guid)); @@ -148,9 +148,7 @@ zfeature_register(spa_feature_t fid, const char *guid, const char *name, feature->fi_guid = guid; feature->fi_uname = name; feature->fi_desc = desc; - feature->fi_can_readonly = readonly; - feature->fi_mos = mos; - feature->fi_activate_on_enable = activate_on_enable; + feature->fi_flags = flags; feature->fi_depends = deps; } @@ -159,45 +157,46 @@ zpool_feature_init(void) { zfeature_register(SPA_FEATURE_ASYNC_DESTROY, "com.delphix:async_destroy", "async_destroy", - "Destroy filesystems asynchronously.", B_TRUE, B_FALSE, - B_FALSE, NULL); + "Destroy filesystems asynchronously.", + ZFEATURE_FLAG_READONLY_COMPAT, NULL); zfeature_register(SPA_FEATURE_EMPTY_BPOBJ, "com.delphix:empty_bpobj", "empty_bpobj", - "Snapshots use less space.", B_TRUE, B_FALSE, - B_FALSE, NULL); + "Snapshots use less space.", + ZFEATURE_FLAG_READONLY_COMPAT, NULL); zfeature_register(SPA_FEATURE_LZ4_COMPRESS, "org.illumos:lz4_compress", "lz4_compress", - "LZ4 compression algorithm support.", B_FALSE, B_FALSE, - B_TRUE, NULL); + "LZ4 compression algorithm support.", + ZFEATURE_FLAG_ACTIVATE_ON_ENABLE, NULL); zfeature_register(SPA_FEATURE_MULTI_VDEV_CRASH_DUMP, "com.joyent:multi_vdev_crash_dump", "multi_vdev_crash_dump", - "Crash dumps to multiple vdev pools.", B_FALSE, B_FALSE, - B_FALSE, NULL); + "Crash dumps to multiple vdev pools.", + 0, NULL); zfeature_register(SPA_FEATURE_SPACEMAP_HISTOGRAM, "com.delphix:spacemap_histogram", "spacemap_histogram", - "Spacemaps maintain space histograms.", B_TRUE, B_FALSE, - B_FALSE, NULL); + "Spacemaps maintain space histograms.", + ZFEATURE_FLAG_READONLY_COMPAT, NULL); zfeature_register(SPA_FEATURE_ENABLED_TXG, "com.delphix:enabled_txg", "enabled_txg", - "Record txg at which a feature is enabled", B_TRUE, B_FALSE, - B_FALSE, NULL); + "Record txg at which a feature is enabled", + ZFEATURE_FLAG_READONLY_COMPAT, NULL); static spa_feature_t hole_birth_deps[] = { SPA_FEATURE_ENABLED_TXG, SPA_FEATURE_NONE }; zfeature_register(SPA_FEATURE_HOLE_BIRTH, "com.delphix:hole_birth", "hole_birth", "Retain hole birth txg for more precise zfs send", - B_FALSE, B_TRUE, B_TRUE, hole_birth_deps); + ZFEATURE_FLAG_MOS | ZFEATURE_FLAG_ACTIVATE_ON_ENABLE, + hole_birth_deps); zfeature_register(SPA_FEATURE_EXTENSIBLE_DATASET, "com.delphix:extensible_dataset", "extensible_dataset", "Enhanced dataset functionality, used by other features.", - B_FALSE, B_FALSE, B_FALSE, NULL); + 0, NULL); static const spa_feature_t bookmarks_deps[] = { SPA_FEATURE_EXTENSIBLE_DATASET, @@ -206,7 +205,7 @@ zpool_feature_init(void) zfeature_register(SPA_FEATURE_BOOKMARKS, "com.delphix:bookmarks", "bookmarks", "\"zfs bookmark\" command", - B_TRUE, B_FALSE, B_FALSE, bookmarks_deps); + ZFEATURE_FLAG_READONLY_COMPAT, bookmarks_deps); static const spa_feature_t filesystem_limits_deps[] = { SPA_FEATURE_EXTENSIBLE_DATASET, @@ -214,13 +213,14 @@ zpool_feature_init(void) }; zfeature_register(SPA_FEATURE_FS_SS_LIMIT, "com.joyent:filesystem_limits", "filesystem_limits", - "Filesystem and snapshot limits.", B_TRUE, B_FALSE, B_FALSE, - filesystem_limits_deps); + "Filesystem and snapshot limits.", + ZFEATURE_FLAG_READONLY_COMPAT, filesystem_limits_deps); zfeature_register(SPA_FEATURE_EMBEDDED_DATA, "com.delphix:embedded_data", "embedded_data", "Blocks which compress very well use even less space.", - B_FALSE, B_TRUE, B_TRUE, NULL); + ZFEATURE_FLAG_MOS | ZFEATURE_FLAG_ACTIVATE_ON_ENABLE, + NULL); static const spa_feature_t large_blocks_deps[] = { SPA_FEATURE_EXTENSIBLE_DATASET, @@ -228,6 +228,6 @@ zpool_feature_init(void) }; zfeature_register(SPA_FEATURE_LARGE_BLOCKS, "org.open-zfs:large_blocks", "large_blocks", - "Support for blocks larger than 128KB.", B_FALSE, B_FALSE, B_FALSE, - large_blocks_deps); + "Support for blocks larger than 128KB.", + ZFEATURE_FLAG_PER_DATASET, large_blocks_deps); } diff --git a/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.h b/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.h index 4ffe435..0e88a9a 100644 --- a/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.h +++ b/sys/cddl/contrib/opensolaris/common/zfs/zfeature_common.h @@ -20,7 +20,7 @@ */ /* - * Copyright (c) 2013 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2013 by Saso Kiselkov. All rights reserved. * Copyright (c) 2013, Joyent, Inc. All rights reserved. */ @@ -56,15 +56,23 @@ typedef enum spa_feature { #define SPA_FEATURE_DISABLED (-1ULL) +typedef enum zfeature_flags { + /* Can open pool readonly even if this feature is not supported. */ + ZFEATURE_FLAG_READONLY_COMPAT = (1 << 0), + /* Is this feature necessary to read the MOS? */ + ZFEATURE_FLAG_MOS = (1 << 1), + /* Activate this feature at the same time it is enabled. */ + ZFEATURE_FLAG_ACTIVATE_ON_ENABLE = (1 << 2), + /* Each dataset has a field set if it has ever used this feature. */ + ZFEATURE_FLAG_PER_DATASET = (1 << 3) +} zfeature_flags_t; + typedef struct zfeature_info { spa_feature_t fi_feature; const char *fi_uname; /* User-facing feature name */ const char *fi_guid; /* On-disk feature identifier */ const char *fi_desc; /* Feature description */ - boolean_t fi_can_readonly; /* Can open pool readonly w/o support? */ - boolean_t fi_mos; /* Is the feature necessary to read the MOS? */ - /* Activate this feature at the same time it is enabled */ - boolean_t fi_activate_on_enable; + zfeature_flags_t fi_flags; /* array of dependencies, terminated by SPA_FEATURE_NONE */ const spa_feature_t *fi_depends; } zfeature_info_t; diff --git a/sys/cddl/contrib/opensolaris/uts/common/Makefile.files b/sys/cddl/contrib/opensolaris/uts/common/Makefile.files index 4c7e225..77c7b1d 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/Makefile.files +++ b/sys/cddl/contrib/opensolaris/uts/common/Makefile.files @@ -22,7 +22,9 @@ # # Copyright (c) 1991, 2010, Oracle and/or its affiliates. All rights reserved. # Copyright (c) 2012 Nexenta Systems, Inc. All rights reserved. -# Copyright (c) 2013 by Delphix. All rights reserved. +# Copyright (c) 2012 Nexenta Systems, Inc. All rights reserved. +# Copyright (c) 2012 Joyent, Inc. All rights reserved. +# Copyright (c) 2011, 2014 by Delphix. All rights reserved. # Copyright (c) 2013 by Saso Kiselkov. All rights reserved. # # @@ -36,6 +38,7 @@ ZFS_COMMON_OBJS += \ blkptr.o \ bpobj.o \ bptree.o \ + bqueue.o \ dbuf.o \ ddt.o \ ddt_zap.o \ @@ -65,6 +68,7 @@ ZFS_COMMON_OBJS += \ lz4.o \ lzjb.o \ metaslab.o \ + multilist.o \ range_tree.o \ refcount.o \ rrwlock.o \ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c index 6de36f2..07fcb51 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c @@ -21,9 +21,9 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, Joyent, Inc. All rights reserved. - * Copyright (c) 2011, 2014 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2014 by Saso Kiselkov. All rights reserved. - * Copyright 2014 Nexenta Systems, Inc. All rights reserved. + * Copyright 2015 Nexenta Systems, Inc. All rights reserved. */ /* @@ -82,9 +82,9 @@ * types of locks: 1) the hash table lock array, and 2) the * arc list locks. * - * Buffers do not have their own mutexs, rather they rely on the - * hash table mutexs for the bulk of their protection (i.e. most - * fields in the arc_buf_hdr_t are protected by these mutexs). + * Buffers do not have their own mutexes, rather they rely on the + * hash table mutexes for the bulk of their protection (i.e. most + * fields in the arc_buf_hdr_t are protected by these mutexes). * * buf_hash_find() returns the appropriate mutex (held) when it * locates the requested buffer in the hash table. It returns @@ -129,6 +129,7 @@ #include <sys/vdev.h> #include <sys/vdev_impl.h> #include <sys/dsl_pool.h> +#include <sys/multilist.h> #ifdef _KERNEL #include <sys/dnlc.h> #endif @@ -149,21 +150,39 @@ int arc_procfd; #endif #endif /* illumos */ -static kmutex_t arc_reclaim_thr_lock; -static kcondvar_t arc_reclaim_thr_cv; /* used to signal reclaim thr */ -static uint8_t arc_thread_exit; +static kmutex_t arc_reclaim_lock; +static kcondvar_t arc_reclaim_thread_cv; +static boolean_t arc_reclaim_thread_exit; +static kcondvar_t arc_reclaim_waiters_cv; + +static kmutex_t arc_user_evicts_lock; +static kcondvar_t arc_user_evicts_cv; +static boolean_t arc_user_evicts_thread_exit; uint_t arc_reduce_dnlc_percent = 3; /* - * The number of iterations through arc_evict_*() before we - * drop & reacquire the lock. + * The number of headers to evict in arc_evict_state_impl() before + * dropping the sublist lock and evicting from another sublist. A lower + * value means we're more likely to evict the "correct" header (i.e. the + * oldest header in the arc state), but comes with higher overhead + * (i.e. more invocations of arc_evict_state_impl()). */ -int arc_evict_iterations = 100; +int zfs_arc_evict_batch_limit = 10; + +/* + * The number of sublists used for each of the arc state lists. If this + * is not set to a suitable value by the user, it will be configured to + * the number of CPUs on the system in arc_init(). + */ +int zfs_arc_num_sublists_per_state = 0; /* number of seconds before growing cache again */ static int arc_grow_retry = 60; +/* shift of arc_c for calculating overflow limit in arc_get_data_buf */ +int zfs_arc_overflow_shift = 8; + /* shift of arc_c for calculating both min and max arc_p */ static int arc_p_min_shift = 4; @@ -201,6 +220,9 @@ extern int zfs_prefetch_disable; */ static boolean_t arc_warm; +/* + * These tunables are for performance analysis. + */ uint64_t zfs_arc_max; uint64_t zfs_arc_min; uint64_t zfs_arc_meta_limit = 0; @@ -312,31 +334,22 @@ SYSCTL_PROC(_vfs_zfs, OID_AUTO, arc_meta_limit, * second level ARC benefit from these fast lookups. */ -#define ARCS_LOCK_PAD CACHE_LINE_SIZE -struct arcs_lock { - kmutex_t arcs_lock; -#ifdef _KERNEL - unsigned char pad[(ARCS_LOCK_PAD - sizeof (kmutex_t))]; -#endif -}; - -/* - * must be power of two for mask use to work - * - */ -#define ARC_BUFC_NUMDATALISTS 16 -#define ARC_BUFC_NUMMETADATALISTS 16 -#define ARC_BUFC_NUMLISTS (ARC_BUFC_NUMMETADATALISTS + ARC_BUFC_NUMDATALISTS) - typedef struct arc_state { - uint64_t arcs_lsize[ARC_BUFC_NUMTYPES]; /* amount of evictable data */ - uint64_t arcs_size; /* total amount of data in this state */ - list_t arcs_lists[ARC_BUFC_NUMLISTS]; /* list of evictable buffers */ - struct arcs_lock arcs_locks[ARC_BUFC_NUMLISTS] __aligned(CACHE_LINE_SIZE); + /* + * list of evictable buffers + */ + multilist_t arcs_list[ARC_BUFC_NUMTYPES]; + /* + * total amount of evictable data in this state + */ + uint64_t arcs_lsize[ARC_BUFC_NUMTYPES]; + /* + * total amount of data in this state; this includes: evictable, + * non-evictable, ARC_BUFC_DATA, and ARC_BUFC_METADATA. + */ + refcount_t arcs_size; } arc_state_t; -#define ARCS_LOCK(s, i) (&((s)->arcs_locks[(i)].arcs_lock)) - /* The 6 states: */ static arc_state_t ARC_anon; static arc_state_t ARC_mru; @@ -362,8 +375,6 @@ typedef struct arc_stats { kstat_named_t arcstat_mfu_ghost_hits; kstat_named_t arcstat_allocated; kstat_named_t arcstat_deleted; - kstat_named_t arcstat_stolen; - kstat_named_t arcstat_recycle_miss; /* * Number of buffers that could not be evicted because the hash lock * was held by another thread. The lock may not necessarily be held @@ -377,9 +388,15 @@ typedef struct arc_stats { * not from the spa we're trying to evict from. */ kstat_named_t arcstat_evict_skip; + /* + * Number of times arc_evict_state() was unable to evict enough + * buffers to reach it's target amount. + */ + kstat_named_t arcstat_evict_not_enough; kstat_named_t arcstat_evict_l2_cached; kstat_named_t arcstat_evict_l2_eligible; kstat_named_t arcstat_evict_l2_ineligible; + kstat_named_t arcstat_evict_l2_skip; kstat_named_t arcstat_hash_elements; kstat_named_t arcstat_hash_elements_max; kstat_named_t arcstat_hash_collisions; @@ -530,7 +547,7 @@ typedef struct arc_stats { kstat_named_t arcstat_l2_writes_sent; kstat_named_t arcstat_l2_writes_done; kstat_named_t arcstat_l2_writes_error; - kstat_named_t arcstat_l2_writes_hdr_miss; + kstat_named_t arcstat_l2_writes_lock_retry; kstat_named_t arcstat_l2_evict_lock_retry; kstat_named_t arcstat_l2_evict_reading; kstat_named_t arcstat_l2_evict_l1cached; @@ -584,13 +601,13 @@ static arc_stats_t arc_stats = { { "mfu_ghost_hits", KSTAT_DATA_UINT64 }, { "allocated", KSTAT_DATA_UINT64 }, { "deleted", KSTAT_DATA_UINT64 }, - { "stolen", KSTAT_DATA_UINT64 }, - { "recycle_miss", KSTAT_DATA_UINT64 }, { "mutex_miss", KSTAT_DATA_UINT64 }, { "evict_skip", KSTAT_DATA_UINT64 }, + { "evict_not_enough", KSTAT_DATA_UINT64 }, { "evict_l2_cached", KSTAT_DATA_UINT64 }, { "evict_l2_eligible", KSTAT_DATA_UINT64 }, { "evict_l2_ineligible", KSTAT_DATA_UINT64 }, + { "evict_l2_skip", KSTAT_DATA_UINT64 }, { "hash_elements", KSTAT_DATA_UINT64 }, { "hash_elements_max", KSTAT_DATA_UINT64 }, { "hash_collisions", KSTAT_DATA_UINT64 }, @@ -629,7 +646,7 @@ static arc_stats_t arc_stats = { { "l2_writes_sent", KSTAT_DATA_UINT64 }, { "l2_writes_done", KSTAT_DATA_UINT64 }, { "l2_writes_error", KSTAT_DATA_UINT64 }, - { "l2_writes_hdr_miss", KSTAT_DATA_UINT64 }, + { "l2_writes_lock_retry", KSTAT_DATA_UINT64 }, { "l2_evict_lock_retry", KSTAT_DATA_UINT64 }, { "l2_evict_reading", KSTAT_DATA_UINT64 }, { "l2_evict_l1cached", KSTAT_DATA_UINT64 }, @@ -806,7 +823,7 @@ typedef struct l1arc_buf_hdr { /* protected by arc state mutex */ arc_state_t *b_state; - list_node_t b_arc_node; + multilist_node_t b_arc_node; /* updated atomically */ clock_t b_arc_access; @@ -877,7 +894,6 @@ sysctl_vfs_zfs_arc_meta_limit(SYSCTL_HANDLER_ARGS) #endif static arc_buf_t *arc_eviction_list; -static kmutex_t arc_eviction_mtx; static arc_buf_hdr_t arc_eviction_hdr; #define GHOST_STATE(state) \ @@ -1011,21 +1027,21 @@ SYSCTL_INT(_vfs_zfs, OID_AUTO, l2arc_norw, CTLFLAG_RW, &l2arc_norw, 0, "no reads during writes"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, anon_size, CTLFLAG_RD, - &ARC_anon.arcs_size, 0, "size of anonymous state"); + &ARC_anon.arcs_size.rc_count, 0, "size of anonymous state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, anon_metadata_lsize, CTLFLAG_RD, &ARC_anon.arcs_lsize[ARC_BUFC_METADATA], 0, "size of anonymous state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, anon_data_lsize, CTLFLAG_RD, &ARC_anon.arcs_lsize[ARC_BUFC_DATA], 0, "size of anonymous state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mru_size, CTLFLAG_RD, - &ARC_mru.arcs_size, 0, "size of mru state"); + &ARC_mru.arcs_size.rc_count, 0, "size of mru state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mru_metadata_lsize, CTLFLAG_RD, &ARC_mru.arcs_lsize[ARC_BUFC_METADATA], 0, "size of metadata in mru state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mru_data_lsize, CTLFLAG_RD, &ARC_mru.arcs_lsize[ARC_BUFC_DATA], 0, "size of data in mru state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mru_ghost_size, CTLFLAG_RD, - &ARC_mru_ghost.arcs_size, 0, "size of mru ghost state"); + &ARC_mru_ghost.arcs_size.rc_count, 0, "size of mru ghost state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mru_ghost_metadata_lsize, CTLFLAG_RD, &ARC_mru_ghost.arcs_lsize[ARC_BUFC_METADATA], 0, "size of metadata in mru ghost state"); @@ -1034,14 +1050,14 @@ SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mru_ghost_data_lsize, CTLFLAG_RD, "size of data in mru ghost state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mfu_size, CTLFLAG_RD, - &ARC_mfu.arcs_size, 0, "size of mfu state"); + &ARC_mfu.arcs_size.rc_count, 0, "size of mfu state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mfu_metadata_lsize, CTLFLAG_RD, &ARC_mfu.arcs_lsize[ARC_BUFC_METADATA], 0, "size of metadata in mfu state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mfu_data_lsize, CTLFLAG_RD, &ARC_mfu.arcs_lsize[ARC_BUFC_DATA], 0, "size of data in mfu state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mfu_ghost_size, CTLFLAG_RD, - &ARC_mfu_ghost.arcs_size, 0, "size of mfu ghost state"); + &ARC_mfu_ghost.arcs_size.rc_count, 0, "size of mfu ghost state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mfu_ghost_metadata_lsize, CTLFLAG_RD, &ARC_mfu_ghost.arcs_lsize[ARC_BUFC_METADATA], 0, "size of metadata in mfu ghost state"); @@ -1050,7 +1066,7 @@ SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, mfu_ghost_data_lsize, CTLFLAG_RD, "size of data in mfu ghost state"); SYSCTL_UQUAD(_vfs_zfs, OID_AUTO, l2c_only_size, CTLFLAG_RD, - &ARC_l2c_only.arcs_size, 0, "size of mru state"); + &ARC_l2c_only.arcs_size.rc_count, 0, "size of mru state"); /* * L2ARC Internals @@ -1106,8 +1122,7 @@ static uint8_t l2arc_thread_exit; static void arc_get_data_buf(arc_buf_t *); static void arc_access(arc_buf_hdr_t *, kmutex_t *); -static int arc_evict_needed(arc_buf_contents_t); -static void arc_evict_ghost(arc_state_t *, uint64_t, int64_t); +static boolean_t arc_is_overflowing(); static void arc_buf_watch(arc_buf_t *); static arc_buf_contents_t arc_buf_type(arc_buf_hdr_t *); @@ -1288,6 +1303,7 @@ hdr_full_cons(void *vbuf, void *unused, int kmflag) cv_init(&hdr->b_l1hdr.b_cv, NULL, CV_DEFAULT, NULL); refcount_create(&hdr->b_l1hdr.b_refcnt); mutex_init(&hdr->b_l1hdr.b_freeze_lock, NULL, MUTEX_DEFAULT, NULL); + multilist_link_init(&hdr->b_l1hdr.b_arc_node); arc_space_consume(HDR_FULL_SIZE, ARC_SPACE_HDRS); return (0); @@ -1332,6 +1348,7 @@ hdr_full_dest(void *vbuf, void *unused) cv_destroy(&hdr->b_l1hdr.b_cv); refcount_destroy(&hdr->b_l1hdr.b_refcnt); mutex_destroy(&hdr->b_l1hdr.b_freeze_lock); + ASSERT(!multilist_link_active(&hdr->b_l1hdr.b_arc_node)); arc_space_return(HDR_FULL_SIZE, ARC_SPACE_HDRS); } @@ -1368,7 +1385,7 @@ hdr_recl(void *unused) * which is after we do arc_fini(). */ if (!arc_dead) - cv_signal(&arc_reclaim_thr_cv); + cv_signal(&arc_reclaim_thread_cv); } static void @@ -1447,18 +1464,31 @@ arc_hdr_realloc(arc_buf_hdr_t *hdr, kmem_cache_t *old, kmem_cache_t *new) * l2c_only even though it's about to change. */ nhdr->b_l1hdr.b_state = arc_l2c_only; + + /* Verify previous threads set to NULL before freeing */ + ASSERT3P(nhdr->b_l1hdr.b_tmp_cdata, ==, NULL); } else { ASSERT(hdr->b_l1hdr.b_buf == NULL); ASSERT0(hdr->b_l1hdr.b_datacnt); - ASSERT(!list_link_active(&hdr->b_l1hdr.b_arc_node)); + /* - * We might be removing the L1hdr of a buffer which was just - * written out to L2ARC. If such a buffer is compressed then we - * need to free its b_tmp_cdata before destroying the header. + * If we've reached here, We must have been called from + * arc_evict_hdr(), as such we should have already been + * removed from any ghost list we were previously on + * (which protects us from racing with arc_evict_state), + * thus no locking is needed during this check. */ - if (hdr->b_l1hdr.b_tmp_cdata != NULL && - HDR_GET_COMPRESS(hdr) != ZIO_COMPRESS_OFF) - l2arc_release_cdata_buf(hdr); + ASSERT(!multilist_link_active(&hdr->b_l1hdr.b_arc_node)); + + /* + * A buffer must not be moved into the arc_l2c_only + * state if it's not finished being written out to the + * l2arc device. Otherwise, the b_l1hdr.b_tmp_cdata field + * might try to be accessed, even though it was removed. + */ + VERIFY(!HDR_L2_WRITING(hdr)); + VERIFY3P(hdr->b_l1hdr.b_tmp_cdata, ==, NULL); + nhdr->b_flags &= ~ARC_FLAG_HAS_L1HDR; } /* @@ -1681,23 +1711,6 @@ arc_buf_freeze(arc_buf_t *buf) } static void -get_buf_info(arc_buf_hdr_t *hdr, arc_state_t *state, list_t **list, kmutex_t **lock) -{ - uint64_t buf_hashid = buf_hash(hdr->b_spa, &hdr->b_dva, hdr->b_birth); - - if (arc_buf_type(hdr) == ARC_BUFC_METADATA) - buf_hashid &= (ARC_BUFC_NUMMETADATALISTS - 1); - else { - buf_hashid &= (ARC_BUFC_NUMDATALISTS - 1); - buf_hashid += ARC_BUFC_NUMMETADATALISTS; - } - - *list = &state->arcs_lists[buf_hashid]; - *lock = ARCS_LOCK(state, buf_hashid); -} - - -static void add_reference(arc_buf_hdr_t *hdr, kmutex_t *hash_lock, void *tag) { ASSERT(HDR_HAS_L1HDR(hdr)); @@ -1708,16 +1721,13 @@ add_reference(arc_buf_hdr_t *hdr, kmutex_t *hash_lock, void *tag) (state != arc_anon)) { /* We don't use the L2-only state list. */ if (state != arc_l2c_only) { + arc_buf_contents_t type = arc_buf_type(hdr); uint64_t delta = hdr->b_size * hdr->b_l1hdr.b_datacnt; - uint64_t *size = &state->arcs_lsize[arc_buf_type(hdr)]; - list_t *list; - kmutex_t *lock; - - get_buf_info(hdr, state, &list, &lock); - ASSERT(!MUTEX_HELD(lock)); - mutex_enter(lock); - ASSERT(list_link_active(&hdr->b_l1hdr.b_arc_node)); - list_remove(list, hdr); + multilist_t *list = &state->arcs_list[type]; + uint64_t *size = &state->arcs_lsize[type]; + + multilist_remove(list, hdr); + if (GHOST_STATE(state)) { ASSERT0(hdr->b_l1hdr.b_datacnt); ASSERT3P(hdr->b_l1hdr.b_buf, ==, NULL); @@ -1726,7 +1736,6 @@ add_reference(arc_buf_hdr_t *hdr, kmutex_t *hash_lock, void *tag) ASSERT(delta > 0); ASSERT3U(*size, >=, delta); atomic_add_64(size, -delta); - mutex_exit(lock); } /* remove the prefetch flag if we get a reference */ hdr->b_flags &= ~ARC_FLAG_PREFETCH; @@ -1749,25 +1758,21 @@ remove_reference(arc_buf_hdr_t *hdr, kmutex_t *hash_lock, void *tag) */ if (((cnt = refcount_remove(&hdr->b_l1hdr.b_refcnt, tag)) == 0) && (state != arc_anon)) { - uint64_t *size = &state->arcs_lsize[arc_buf_type(hdr)]; - list_t *list; - kmutex_t *lock; + arc_buf_contents_t type = arc_buf_type(hdr); + multilist_t *list = &state->arcs_list[type]; + uint64_t *size = &state->arcs_lsize[type]; + + multilist_insert(list, hdr); - get_buf_info(hdr, state, &list, &lock); - ASSERT(!MUTEX_HELD(lock)); - mutex_enter(lock); - ASSERT(!list_link_active(&hdr->b_l1hdr.b_arc_node)); - list_insert_head(list, hdr); ASSERT(hdr->b_l1hdr.b_datacnt > 0); atomic_add_64(size, hdr->b_size * hdr->b_l1hdr.b_datacnt); - mutex_exit(lock); } return (cnt); } /* - * Move the supplied buffer to the indicated state. The mutex + * Move the supplied buffer to the indicated state. The hash lock * for the buffer must be held by the caller. */ static void @@ -1779,8 +1784,6 @@ arc_change_state(arc_state_t *new_state, arc_buf_hdr_t *hdr, uint32_t datacnt; uint64_t from_delta, to_delta; arc_buf_contents_t buftype = arc_buf_type(hdr); - list_t *list; - kmutex_t *lock; /* * We almost always have an L1 hdr here, since we call arc_hdr_realloc() @@ -1813,17 +1816,10 @@ arc_change_state(arc_state_t *new_state, arc_buf_hdr_t *hdr, */ if (refcnt == 0) { if (old_state != arc_anon && old_state != arc_l2c_only) { - int use_mutex; uint64_t *size = &old_state->arcs_lsize[buftype]; - get_buf_info(hdr, old_state, &list, &lock); - use_mutex = !MUTEX_HELD(lock); - if (use_mutex) - mutex_enter(lock); - ASSERT(HDR_HAS_L1HDR(hdr)); - ASSERT(list_link_active(&hdr->b_l1hdr.b_arc_node)); - list_remove(list, hdr); + multilist_remove(&old_state->arcs_list[buftype], hdr); /* * If prefetching out of the ghost cache, @@ -1836,12 +1832,8 @@ arc_change_state(arc_state_t *new_state, arc_buf_hdr_t *hdr, } ASSERT3U(*size, >=, from_delta); atomic_add_64(size, -from_delta); - - if (use_mutex) - mutex_exit(lock); } if (new_state != arc_anon && new_state != arc_l2c_only) { - int use_mutex; uint64_t *size = &new_state->arcs_lsize[buftype]; /* @@ -1851,23 +1843,15 @@ arc_change_state(arc_state_t *new_state, arc_buf_hdr_t *hdr, * beforehand. */ ASSERT(HDR_HAS_L1HDR(hdr)); - get_buf_info(hdr, new_state, &list, &lock); - use_mutex = !MUTEX_HELD(lock); - if (use_mutex) - mutex_enter(lock); - - list_insert_head(list, hdr); + multilist_insert(&new_state->arcs_list[buftype], hdr); /* ghost elements have a ghost size */ if (GHOST_STATE(new_state)) { - ASSERT(datacnt == 0); + ASSERT0(datacnt); ASSERT(hdr->b_l1hdr.b_buf == NULL); to_delta = hdr->b_size; } atomic_add_64(size, to_delta); - - if (use_mutex) - mutex_exit(lock); } } @@ -1876,12 +1860,73 @@ arc_change_state(arc_state_t *new_state, arc_buf_hdr_t *hdr, buf_hash_remove(hdr); /* adjust state sizes (ignore arc_l2c_only) */ - if (to_delta && new_state != arc_l2c_only) - atomic_add_64(&new_state->arcs_size, to_delta); + + if (to_delta && new_state != arc_l2c_only) { + ASSERT(HDR_HAS_L1HDR(hdr)); + if (GHOST_STATE(new_state)) { + ASSERT0(datacnt); + + /* + * We moving a header to a ghost state, we first + * remove all arc buffers. Thus, we'll have a + * datacnt of zero, and no arc buffer to use for + * the reference. As a result, we use the arc + * header pointer for the reference. + */ + (void) refcount_add_many(&new_state->arcs_size, + hdr->b_size, hdr); + } else { + ASSERT3U(datacnt, !=, 0); + + /* + * Each individual buffer holds a unique reference, + * thus we must remove each of these references one + * at a time. + */ + for (arc_buf_t *buf = hdr->b_l1hdr.b_buf; buf != NULL; + buf = buf->b_next) { + (void) refcount_add_many(&new_state->arcs_size, + hdr->b_size, buf); + } + } + } + if (from_delta && old_state != arc_l2c_only) { - ASSERT3U(old_state->arcs_size, >=, from_delta); - atomic_add_64(&old_state->arcs_size, -from_delta); + ASSERT(HDR_HAS_L1HDR(hdr)); + if (GHOST_STATE(old_state)) { + /* + * When moving a header off of a ghost state, + * there's the possibility for datacnt to be + * non-zero. This is because we first add the + * arc buffer to the header prior to changing + * the header's state. Since we used the header + * for the reference when putting the header on + * the ghost state, we must balance that and use + * the header when removing off the ghost state + * (even though datacnt is non zero). + */ + + IMPLY(datacnt == 0, new_state == arc_anon || + new_state == arc_l2c_only); + + (void) refcount_remove_many(&old_state->arcs_size, + hdr->b_size, hdr); + } else { + ASSERT3P(datacnt, !=, 0); + + /* + * Each individual buffer holds a unique reference, + * thus we must remove each of these references one + * at a time. + */ + for (arc_buf_t *buf = hdr->b_l1hdr.b_buf; buf != NULL; + buf = buf->b_next) { + (void) refcount_remove_many( + &old_state->arcs_size, hdr->b_size, buf); + } + } } + if (HDR_HAS_L1HDR(hdr)) hdr->b_l1hdr.b_state = new_state; @@ -1889,10 +1934,8 @@ arc_change_state(arc_state_t *new_state, arc_buf_hdr_t *hdr, * L2 headers should never be on the L2 state list since they don't * have L1 headers allocated. */ -#ifdef illumos - ASSERT(list_is_empty(&arc_l2c_only->arcs_list[ARC_BUFC_DATA]) && - list_is_empty(&arc_l2c_only->arcs_list[ARC_BUFC_METADATA])); -#endif + ASSERT(multilist_is_empty(&arc_l2c_only->arcs_list[ARC_BUFC_DATA]) && + multilist_is_empty(&arc_l2c_only->arcs_list[ARC_BUFC_METADATA])); } void @@ -1985,6 +2028,7 @@ arc_buf_alloc(spa_t *spa, int32_t size, void *tag, arc_buf_contents_t type) hdr->b_l1hdr.b_state = arc_anon; hdr->b_l1hdr.b_arc_access = 0; hdr->b_l1hdr.b_datacnt = 1; + hdr->b_l1hdr.b_tmp_cdata = NULL; arc_get_data_buf(buf); ASSERT(refcount_is_zero(&hdr->b_l1hdr.b_refcnt)); @@ -2120,7 +2164,7 @@ arc_buf_free_on_write(void *data, size_t size, { l2arc_data_free_t *df; - df = kmem_alloc(sizeof (l2arc_data_free_t), KM_SLEEP); + df = kmem_alloc(sizeof (*df), KM_SLEEP); df->l2df_data = data; df->l2df_size = size; df->l2df_func = free_func; @@ -2146,10 +2190,6 @@ arc_buf_data_free(arc_buf_t *buf, void (*free_func)(void *, size_t)) } } -/* - * Free up buf->b_data and if 'remove' is set, then pull the - * arc_buf_t off of the the arc_buf_hdr_t's list and free it. - */ static void arc_buf_l2_cdata_free(arc_buf_hdr_t *hdr) { @@ -2164,19 +2204,53 @@ arc_buf_l2_cdata_free(arc_buf_hdr_t *hdr) if (!HDR_HAS_L1HDR(hdr)) return; - if (hdr->b_l1hdr.b_tmp_cdata == NULL) + /* + * The header isn't being written to the l2arc device, thus it + * shouldn't have a b_tmp_cdata to free. + */ + if (!HDR_L2_WRITING(hdr)) { + ASSERT3P(hdr->b_l1hdr.b_tmp_cdata, ==, NULL); + return; + } + + /* + * The header does not have compression enabled. This can be due + * to the buffer not being compressible, or because we're + * freeing the buffer before the second phase of + * l2arc_write_buffer() has started (which does the compression + * step). In either case, b_tmp_cdata does not point to a + * separately compressed buffer, so there's nothing to free (it + * points to the same buffer as the arc_buf_t's b_data field). + */ + if (HDR_GET_COMPRESS(hdr) == ZIO_COMPRESS_OFF) { + hdr->b_l1hdr.b_tmp_cdata = NULL; + return; + } + + /* + * There's nothing to free since the buffer was all zero's and + * compressed to a zero length buffer. + */ + if (HDR_GET_COMPRESS(hdr) == ZIO_COMPRESS_EMPTY) { + ASSERT3P(hdr->b_l1hdr.b_tmp_cdata, ==, NULL); return; + } - ASSERT(HDR_L2_WRITING(hdr)); - arc_buf_free_on_write(hdr->b_l1hdr.b_tmp_cdata, hdr->b_size, - zio_data_buf_free); + ASSERT(L2ARC_IS_VALID_COMPRESS(HDR_GET_COMPRESS(hdr))); + + arc_buf_free_on_write(hdr->b_l1hdr.b_tmp_cdata, + hdr->b_size, zio_data_buf_free); ARCSTAT_BUMP(arcstat_l2_cdata_free_on_write); hdr->b_l1hdr.b_tmp_cdata = NULL; } +/* + * Free up buf->b_data and if 'remove' is set, then pull the + * arc_buf_t off of the the arc_buf_hdr_t's list and free it. + */ static void -arc_buf_destroy(arc_buf_t *buf, boolean_t recycle, boolean_t remove) +arc_buf_destroy(arc_buf_t *buf, boolean_t remove) { arc_buf_t **bufp; @@ -2191,17 +2265,17 @@ arc_buf_destroy(arc_buf_t *buf, boolean_t recycle, boolean_t remove) arc_buf_unwatch(buf); #endif - if (!recycle) { - if (type == ARC_BUFC_METADATA) { - arc_buf_data_free(buf, zio_buf_free); - arc_space_return(size, ARC_SPACE_META); - } else { - ASSERT(type == ARC_BUFC_DATA); - arc_buf_data_free(buf, zio_data_buf_free); - arc_space_return(size, ARC_SPACE_DATA); - } + if (type == ARC_BUFC_METADATA) { + arc_buf_data_free(buf, zio_buf_free); + arc_space_return(size, ARC_SPACE_META); + } else { + ASSERT(type == ARC_BUFC_DATA); + arc_buf_data_free(buf, zio_data_buf_free); + arc_space_return(size, ARC_SPACE_DATA); } - if (list_link_active(&buf->b_hdr->b_l1hdr.b_arc_node)) { + + /* protected by hash lock, if in the hash table */ + if (multilist_link_active(&buf->b_hdr->b_l1hdr.b_arc_node)) { uint64_t *cnt = &state->arcs_lsize[type]; ASSERT(refcount_is_zero( @@ -2211,8 +2285,8 @@ arc_buf_destroy(arc_buf_t *buf, boolean_t recycle, boolean_t remove) ASSERT3U(*cnt, >=, size); atomic_add_64(cnt, -size); } - ASSERT3U(state->arcs_size, >=, size); - atomic_add_64(&state->arcs_size, -size); + + (void) refcount_remove_many(&state->arcs_size, size, buf); buf->b_data = NULL; /* @@ -2339,6 +2413,7 @@ arc_hdr_destroy(arc_buf_hdr_t *hdr) if (!BUF_EMPTY(hdr)) buf_discard_identity(hdr); + if (hdr->b_freeze_cksum != NULL) { kmem_free(hdr->b_freeze_cksum, sizeof (zio_cksum_t)); hdr->b_freeze_cksum = NULL; @@ -2349,20 +2424,19 @@ arc_hdr_destroy(arc_buf_hdr_t *hdr) arc_buf_t *buf = hdr->b_l1hdr.b_buf; if (buf->b_efunc != NULL) { - mutex_enter(&arc_eviction_mtx); + mutex_enter(&arc_user_evicts_lock); mutex_enter(&buf->b_evict_lock); ASSERT(buf->b_hdr != NULL); - arc_buf_destroy(hdr->b_l1hdr.b_buf, FALSE, - FALSE); + arc_buf_destroy(hdr->b_l1hdr.b_buf, FALSE); hdr->b_l1hdr.b_buf = buf->b_next; buf->b_hdr = &arc_eviction_hdr; buf->b_next = arc_eviction_list; arc_eviction_list = buf; mutex_exit(&buf->b_evict_lock); - mutex_exit(&arc_eviction_mtx); + cv_signal(&arc_user_evicts_cv); + mutex_exit(&arc_user_evicts_lock); } else { - arc_buf_destroy(hdr->b_l1hdr.b_buf, FALSE, - TRUE); + arc_buf_destroy(hdr->b_l1hdr.b_buf, TRUE); } } #ifdef ZFS_DEBUG @@ -2375,7 +2449,7 @@ arc_hdr_destroy(arc_buf_hdr_t *hdr) ASSERT3P(hdr->b_hash_next, ==, NULL); if (HDR_HAS_L1HDR(hdr)) { - ASSERT(!list_link_active(&hdr->b_l1hdr.b_arc_node)); + ASSERT(!multilist_link_active(&hdr->b_l1hdr.b_arc_node)); ASSERT3P(hdr->b_l1hdr.b_acb, ==, NULL); kmem_cache_free(hdr_full_cache, hdr); } else { @@ -2401,7 +2475,7 @@ arc_buf_free(arc_buf_t *buf, void *tag) (void) remove_reference(hdr, hash_lock, tag); if (hdr->b_l1hdr.b_datacnt > 1) { - arc_buf_destroy(buf, FALSE, TRUE); + arc_buf_destroy(buf, TRUE); } else { ASSERT(buf == hdr->b_l1hdr.b_buf); ASSERT(buf->b_efunc == NULL); @@ -2415,16 +2489,16 @@ arc_buf_free(arc_buf_t *buf, void *tag) * this buffer unless the write completes before we finish * decrementing the reference count. */ - mutex_enter(&arc_eviction_mtx); + mutex_enter(&arc_user_evicts_lock); (void) remove_reference(hdr, NULL, tag); ASSERT(refcount_is_zero(&hdr->b_l1hdr.b_refcnt)); destroy_hdr = !HDR_IO_IN_PROGRESS(hdr); - mutex_exit(&arc_eviction_mtx); + mutex_exit(&arc_user_evicts_lock); if (destroy_hdr) arc_hdr_destroy(hdr); } else { if (remove_reference(hdr, NULL, tag) > 0) - arc_buf_destroy(buf, FALSE, TRUE); + arc_buf_destroy(buf, TRUE); else arc_hdr_destroy(hdr); } @@ -2453,7 +2527,7 @@ arc_buf_remove_ref(arc_buf_t *buf, void* tag) (void) remove_reference(hdr, hash_lock, tag); if (hdr->b_l1hdr.b_datacnt > 1) { if (no_callback) - arc_buf_destroy(buf, FALSE, TRUE); + arc_buf_destroy(buf, TRUE); } else if (no_callback) { ASSERT(hdr->b_l1hdr.b_buf == buf && buf->b_next == NULL); ASSERT(buf->b_efunc == NULL); @@ -2514,499 +2588,678 @@ arc_buf_eviction_needed(arc_buf_t *buf) } /* - * Evict buffers from list until we've removed the specified number of - * bytes. Move the removed buffers to the appropriate evict state. - * If the recycle flag is set, then attempt to "recycle" a buffer: - * - look for a buffer to evict that is `bytes' long. - * - return the data block from this buffer rather than freeing it. - * This flag is used by callers that are trying to make space for a - * new buffer in a full arc cache. + * Evict the arc_buf_hdr that is provided as a parameter. The resultant + * state of the header is dependent on it's state prior to entering this + * function. The following transitions are possible: * - * This function makes a "best effort". It skips over any buffers - * it can't get a hash_lock on, and so may not catch all candidates. - * It may also return without evicting as much space as requested. + * - arc_mru -> arc_mru_ghost + * - arc_mfu -> arc_mfu_ghost + * - arc_mru_ghost -> arc_l2c_only + * - arc_mru_ghost -> deleted + * - arc_mfu_ghost -> arc_l2c_only + * - arc_mfu_ghost -> deleted */ -static void * -arc_evict(arc_state_t *state, uint64_t spa, int64_t bytes, boolean_t recycle, - arc_buf_contents_t type) +static int64_t +arc_evict_hdr(arc_buf_hdr_t *hdr, kmutex_t *hash_lock) { - arc_state_t *evicted_state; - uint64_t bytes_evicted = 0, skipped = 0, missed = 0; - int64_t bytes_remaining; - arc_buf_hdr_t *hdr, *hdr_prev = NULL; - list_t *evicted_list, *list, *evicted_list_start, *list_start; - kmutex_t *lock, *evicted_lock; - kmutex_t *hash_lock; - boolean_t have_lock; - void *stolen = NULL; - arc_buf_hdr_t marker = { 0 }; - int count = 0; - static int evict_metadata_offset, evict_data_offset; - int i, idx, offset, list_count, lists; + arc_state_t *evicted_state, *state; + int64_t bytes_evicted = 0; - ASSERT(state == arc_mru || state == arc_mfu); + ASSERT(MUTEX_HELD(hash_lock)); + ASSERT(HDR_HAS_L1HDR(hdr)); - evicted_state = (state == arc_mru) ? arc_mru_ghost : arc_mfu_ghost; + state = hdr->b_l1hdr.b_state; + if (GHOST_STATE(state)) { + ASSERT(!HDR_IO_IN_PROGRESS(hdr)); + ASSERT(hdr->b_l1hdr.b_buf == NULL); - /* - * Decide which "type" (data vs metadata) to recycle from. - * - * If we are over the metadata limit, recycle from metadata. - * If we are under the metadata minimum, recycle from data. - * Otherwise, recycle from whichever type has the oldest (least - * recently accessed) header. This is not yet implemented. - */ - if (recycle) { - arc_buf_contents_t realtype; - if (state->arcs_lsize[ARC_BUFC_DATA] == 0) { - realtype = ARC_BUFC_METADATA; - } else if (state->arcs_lsize[ARC_BUFC_METADATA] == 0) { - realtype = ARC_BUFC_DATA; - } else if (arc_meta_used >= arc_meta_limit) { - realtype = ARC_BUFC_METADATA; - } else if (arc_meta_used <= arc_meta_min) { - realtype = ARC_BUFC_DATA; -#ifdef illumos - } else if (HDR_HAS_L1HDR(data_hdr) && - HDR_HAS_L1HDR(metadata_hdr) && - data_hdr->b_l1hdr.b_arc_access < - metadata_hdr->b_l1hdr.b_arc_access) { - realtype = ARC_BUFC_DATA; - } else { - realtype = ARC_BUFC_METADATA; -#else - } else { - /* TODO */ - realtype = type; -#endif + /* + * l2arc_write_buffers() relies on a header's L1 portion + * (i.e. it's b_tmp_cdata field) during it's write phase. + * Thus, we cannot push a header onto the arc_l2c_only + * state (removing it's L1 piece) until the header is + * done being written to the l2arc. + */ + if (HDR_HAS_L2HDR(hdr) && HDR_L2_WRITING(hdr)) { + ARCSTAT_BUMP(arcstat_evict_l2_skip); + return (bytes_evicted); } - if (realtype != type) { + + ARCSTAT_BUMP(arcstat_deleted); + bytes_evicted += hdr->b_size; + + DTRACE_PROBE1(arc__delete, arc_buf_hdr_t *, hdr); + + if (HDR_HAS_L2HDR(hdr)) { + /* + * This buffer is cached on the 2nd Level ARC; + * don't destroy the header. + */ + arc_change_state(arc_l2c_only, hdr, hash_lock); /* - * If we want to evict from a different list, - * we can not recycle, because DATA vs METADATA - * buffers are segregated into different kmem - * caches (and vmem arenas). + * dropping from L1+L2 cached to L2-only, + * realloc to remove the L1 header. */ - type = realtype; - recycle = B_FALSE; + hdr = arc_hdr_realloc(hdr, hdr_full_cache, + hdr_l2only_cache); + } else { + arc_change_state(arc_anon, hdr, hash_lock); + arc_hdr_destroy(hdr); } + return (bytes_evicted); } - if (type == ARC_BUFC_METADATA) { - offset = 0; - list_count = ARC_BUFC_NUMMETADATALISTS; - list_start = &state->arcs_lists[0]; - evicted_list_start = &evicted_state->arcs_lists[0]; - idx = evict_metadata_offset; - } else { - offset = ARC_BUFC_NUMMETADATALISTS; - list_start = &state->arcs_lists[offset]; - evicted_list_start = &evicted_state->arcs_lists[offset]; - list_count = ARC_BUFC_NUMDATALISTS; - idx = evict_data_offset; - } - bytes_remaining = evicted_state->arcs_lsize[type]; - lists = 0; + ASSERT(state == arc_mru || state == arc_mfu); + evicted_state = (state == arc_mru) ? arc_mru_ghost : arc_mfu_ghost; -evict_start: - list = &list_start[idx]; - evicted_list = &evicted_list_start[idx]; - lock = ARCS_LOCK(state, (offset + idx)); - evicted_lock = ARCS_LOCK(evicted_state, (offset + idx)); + /* prefetch buffers have a minimum lifespan */ + if (HDR_IO_IN_PROGRESS(hdr) || + ((hdr->b_flags & (ARC_FLAG_PREFETCH | ARC_FLAG_INDIRECT)) && + ddi_get_lbolt() - hdr->b_l1hdr.b_arc_access < + arc_min_prefetch_lifespan)) { + ARCSTAT_BUMP(arcstat_evict_skip); + return (bytes_evicted); + } - /* - * The ghost list lock must be acquired first in order to prevent - * a 3 party deadlock: - * - * - arc_evict_ghost acquires arc_*_ghost->arcs_mtx, followed by - * l2ad_mtx in arc_hdr_realloc - * - l2arc_write_buffers acquires l2ad_mtx, followed by arc_*->arcs_mtx - * - arc_evict acquires arc_*_ghost->arcs_mtx, followed by - * arc_*_ghost->arcs_mtx and forms a deadlock cycle. - * - * This situation is avoided by acquiring the ghost list lock first. - */ - mutex_enter(evicted_lock); - mutex_enter(lock); - - for (hdr = list_tail(list); hdr; hdr = hdr_prev) { - hdr_prev = list_prev(list, hdr); - if (HDR_HAS_L1HDR(hdr)) { - bytes_remaining -= - (hdr->b_size * hdr->b_l1hdr.b_datacnt); + ASSERT0(refcount_count(&hdr->b_l1hdr.b_refcnt)); + ASSERT3U(hdr->b_l1hdr.b_datacnt, >, 0); + while (hdr->b_l1hdr.b_buf) { + arc_buf_t *buf = hdr->b_l1hdr.b_buf; + if (!mutex_tryenter(&buf->b_evict_lock)) { + ARCSTAT_BUMP(arcstat_mutex_miss); + break; } - /* prefetch buffers have a minimum lifespan */ - if (HDR_IO_IN_PROGRESS(hdr) || - (spa && hdr->b_spa != spa) || - ((hdr->b_flags & (ARC_FLAG_PREFETCH | ARC_FLAG_INDIRECT)) && - ddi_get_lbolt() - hdr->b_l1hdr.b_arc_access < - arc_min_prefetch_lifespan)) { - skipped++; - continue; + if (buf->b_data != NULL) + bytes_evicted += hdr->b_size; + if (buf->b_efunc != NULL) { + mutex_enter(&arc_user_evicts_lock); + arc_buf_destroy(buf, FALSE); + hdr->b_l1hdr.b_buf = buf->b_next; + buf->b_hdr = &arc_eviction_hdr; + buf->b_next = arc_eviction_list; + arc_eviction_list = buf; + cv_signal(&arc_user_evicts_cv); + mutex_exit(&arc_user_evicts_lock); + mutex_exit(&buf->b_evict_lock); + } else { + mutex_exit(&buf->b_evict_lock); + arc_buf_destroy(buf, TRUE); } - /* "lookahead" for better eviction candidate */ - if (recycle && hdr->b_size != bytes && - hdr_prev && hdr_prev->b_size == bytes) - continue; + } - /* ignore markers */ - if (hdr->b_spa == 0) - continue; + if (HDR_HAS_L2HDR(hdr)) { + ARCSTAT_INCR(arcstat_evict_l2_cached, hdr->b_size); + } else { + if (l2arc_write_eligible(hdr->b_spa, hdr)) + ARCSTAT_INCR(arcstat_evict_l2_eligible, hdr->b_size); + else + ARCSTAT_INCR(arcstat_evict_l2_ineligible, hdr->b_size); + } + + if (hdr->b_l1hdr.b_datacnt == 0) { + arc_change_state(evicted_state, hdr, hash_lock); + ASSERT(HDR_IN_HASH_TABLE(hdr)); + hdr->b_flags |= ARC_FLAG_IN_HASH_TABLE; + hdr->b_flags &= ~ARC_FLAG_BUF_AVAILABLE; + DTRACE_PROBE1(arc__evict, arc_buf_hdr_t *, hdr); + } + + return (bytes_evicted); +} + +static uint64_t +arc_evict_state_impl(multilist_t *ml, int idx, arc_buf_hdr_t *marker, + uint64_t spa, int64_t bytes) +{ + multilist_sublist_t *mls; + uint64_t bytes_evicted = 0; + arc_buf_hdr_t *hdr; + kmutex_t *hash_lock; + int evict_count = 0; + + ASSERT3P(marker, !=, NULL); + IMPLY(bytes < 0, bytes == ARC_EVICT_ALL); + + mls = multilist_sublist_lock(ml, idx); + + for (hdr = multilist_sublist_prev(mls, marker); hdr != NULL; + hdr = multilist_sublist_prev(mls, marker)) { + if ((bytes != ARC_EVICT_ALL && bytes_evicted >= bytes) || + (evict_count >= zfs_arc_evict_batch_limit)) + break; /* - * It may take a long time to evict all the bufs requested. - * To avoid blocking all arc activity, periodically drop - * the arcs_mtx and give other threads a chance to run - * before reacquiring the lock. - * - * If we are looking for a buffer to recycle, we are in - * the hot code path, so don't sleep. + * To keep our iteration location, move the marker + * forward. Since we're not holding hdr's hash lock, we + * must be very careful and not remove 'hdr' from the + * sublist. Otherwise, other consumers might mistake the + * 'hdr' as not being on a sublist when they call the + * multilist_link_active() function (they all rely on + * the hash lock protecting concurrent insertions and + * removals). multilist_sublist_move_forward() was + * specifically implemented to ensure this is the case + * (only 'marker' will be removed and re-inserted). */ - if (!recycle && count++ > arc_evict_iterations) { - list_insert_after(list, hdr, &marker); - mutex_exit(lock); - mutex_exit(evicted_lock); - kpreempt(KPREEMPT_SYNC); - mutex_enter(evicted_lock); - mutex_enter(lock); - hdr_prev = list_prev(list, &marker); - list_remove(list, &marker); - count = 0; + multilist_sublist_move_forward(mls, marker); + + /* + * The only case where the b_spa field should ever be + * zero, is the marker headers inserted by + * arc_evict_state(). It's possible for multiple threads + * to be calling arc_evict_state() concurrently (e.g. + * dsl_pool_close() and zio_inject_fault()), so we must + * skip any markers we see from these other threads. + */ + if (hdr->b_spa == 0) + continue; + + /* we're only interested in evicting buffers of a certain spa */ + if (spa != 0 && hdr->b_spa != spa) { + ARCSTAT_BUMP(arcstat_evict_skip); continue; } hash_lock = HDR_LOCK(hdr); - have_lock = MUTEX_HELD(hash_lock); - if (have_lock || mutex_tryenter(hash_lock)) { - ASSERT0(refcount_count(&hdr->b_l1hdr.b_refcnt)); - ASSERT3U(hdr->b_l1hdr.b_datacnt, >, 0); - while (hdr->b_l1hdr.b_buf) { - arc_buf_t *buf = hdr->b_l1hdr.b_buf; - if (!mutex_tryenter(&buf->b_evict_lock)) { - missed += 1; - break; - } - if (buf->b_data != NULL) { - bytes_evicted += hdr->b_size; - if (recycle && - arc_buf_type(hdr) == type && - hdr->b_size == bytes && - !HDR_L2_WRITING(hdr)) { - stolen = buf->b_data; - recycle = FALSE; - } - } - if (buf->b_efunc != NULL) { - mutex_enter(&arc_eviction_mtx); - arc_buf_destroy(buf, - buf->b_data == stolen, FALSE); - hdr->b_l1hdr.b_buf = buf->b_next; - buf->b_hdr = &arc_eviction_hdr; - buf->b_next = arc_eviction_list; - arc_eviction_list = buf; - mutex_exit(&arc_eviction_mtx); - mutex_exit(&buf->b_evict_lock); - } else { - mutex_exit(&buf->b_evict_lock); - arc_buf_destroy(buf, - buf->b_data == stolen, TRUE); - } - } - if (HDR_HAS_L2HDR(hdr)) { - ARCSTAT_INCR(arcstat_evict_l2_cached, - hdr->b_size); - } else { - if (l2arc_write_eligible(hdr->b_spa, hdr)) { - ARCSTAT_INCR(arcstat_evict_l2_eligible, - hdr->b_size); - } else { - ARCSTAT_INCR( - arcstat_evict_l2_ineligible, - hdr->b_size); - } - } + /* + * We aren't calling this function from any code path + * that would already be holding a hash lock, so we're + * asserting on this assumption to be defensive in case + * this ever changes. Without this check, it would be + * possible to incorrectly increment arcstat_mutex_miss + * below (e.g. if the code changed such that we called + * this function with a hash lock held). + */ + ASSERT(!MUTEX_HELD(hash_lock)); - if (hdr->b_l1hdr.b_datacnt == 0) { - arc_change_state(evicted_state, hdr, hash_lock); - ASSERT(HDR_IN_HASH_TABLE(hdr)); - hdr->b_flags |= ARC_FLAG_IN_HASH_TABLE; - hdr->b_flags &= ~ARC_FLAG_BUF_AVAILABLE; - DTRACE_PROBE1(arc__evict, arc_buf_hdr_t *, hdr); - } - if (!have_lock) - mutex_exit(hash_lock); - if (bytes >= 0 && bytes_evicted >= bytes) - break; - if (bytes_remaining > 0) { - mutex_exit(evicted_lock); - mutex_exit(lock); - idx = ((idx + 1) & (list_count - 1)); - lists++; - goto evict_start; - } - } else { - missed += 1; - } - } + if (mutex_tryenter(hash_lock)) { + uint64_t evicted = arc_evict_hdr(hdr, hash_lock); + mutex_exit(hash_lock); - mutex_exit(lock); - mutex_exit(evicted_lock); + bytes_evicted += evicted; - idx = ((idx + 1) & (list_count - 1)); - lists++; + /* + * If evicted is zero, arc_evict_hdr() must have + * decided to skip this header, don't increment + * evict_count in this case. + */ + if (evicted != 0) + evict_count++; - if (bytes_evicted < bytes) { - if (lists < list_count) - goto evict_start; - else - dprintf("only evicted %lld bytes from %x", - (longlong_t)bytes_evicted, state); + /* + * If arc_size isn't overflowing, signal any + * threads that might happen to be waiting. + * + * For each header evicted, we wake up a single + * thread. If we used cv_broadcast, we could + * wake up "too many" threads causing arc_size + * to significantly overflow arc_c; since + * arc_get_data_buf() doesn't check for overflow + * when it's woken up (it doesn't because it's + * possible for the ARC to be overflowing while + * full of un-evictable buffers, and the + * function should proceed in this case). + * + * If threads are left sleeping, due to not + * using cv_broadcast, they will be woken up + * just before arc_reclaim_thread() sleeps. + */ + mutex_enter(&arc_reclaim_lock); + if (!arc_is_overflowing()) + cv_signal(&arc_reclaim_waiters_cv); + mutex_exit(&arc_reclaim_lock); + } else { + ARCSTAT_BUMP(arcstat_mutex_miss); + } } - if (type == ARC_BUFC_METADATA) - evict_metadata_offset = idx; - else - evict_data_offset = idx; - if (skipped) - ARCSTAT_INCR(arcstat_evict_skip, skipped); - - if (missed) - ARCSTAT_INCR(arcstat_mutex_miss, missed); - - /* - * Note: we have just evicted some data into the ghost state, - * potentially putting the ghost size over the desired size. Rather - * that evicting from the ghost list in this hot code path, leave - * this chore to the arc_reclaim_thread(). - */ + multilist_sublist_unlock(mls); - if (stolen) - ARCSTAT_BUMP(arcstat_stolen); - return (stolen); + return (bytes_evicted); } /* - * Remove buffers from list until we've removed the specified number of - * bytes. Destroy the buffers that are removed. + * Evict buffers from the given arc state, until we've removed the + * specified number of bytes. Move the removed buffers to the + * appropriate evict state. + * + * This function makes a "best effort". It skips over any buffers + * it can't get a hash_lock on, and so, may not catch all candidates. + * It may also return without evicting as much space as requested. + * + * If bytes is specified using the special value ARC_EVICT_ALL, this + * will evict all available (i.e. unlocked and evictable) buffers from + * the given arc state; which is used by arc_flush(). */ -static void -arc_evict_ghost(arc_state_t *state, uint64_t spa, int64_t bytes) +static uint64_t +arc_evict_state(arc_state_t *state, uint64_t spa, int64_t bytes, + arc_buf_contents_t type) { - arc_buf_hdr_t *hdr, *hdr_prev; - arc_buf_hdr_t marker = { 0 }; - list_t *list, *list_start; - kmutex_t *hash_lock, *lock; - uint64_t bytes_deleted = 0; - uint64_t bufs_skipped = 0; - int count = 0; - static int evict_offset; - int list_count, idx = evict_offset; - int offset, lists = 0; - - ASSERT(GHOST_STATE(state)); + uint64_t total_evicted = 0; + multilist_t *ml = &state->arcs_list[type]; + int num_sublists; + arc_buf_hdr_t **markers; + + IMPLY(bytes < 0, bytes == ARC_EVICT_ALL); + + num_sublists = multilist_get_num_sublists(ml); /* - * data lists come after metadata lists + * If we've tried to evict from each sublist, made some + * progress, but still have not hit the target number of bytes + * to evict, we want to keep trying. The markers allow us to + * pick up where we left off for each individual sublist, rather + * than starting from the tail each time. */ - list_start = &state->arcs_lists[ARC_BUFC_NUMMETADATALISTS]; - list_count = ARC_BUFC_NUMDATALISTS; - offset = ARC_BUFC_NUMMETADATALISTS; - -evict_start: - list = &list_start[idx]; - lock = ARCS_LOCK(state, idx + offset); - - mutex_enter(lock); - for (hdr = list_tail(list); hdr; hdr = hdr_prev) { - hdr_prev = list_prev(list, hdr); - if (arc_buf_type(hdr) >= ARC_BUFC_NUMTYPES) - panic("invalid hdr=%p", (void *)hdr); - if (spa && hdr->b_spa != spa) - continue; + markers = kmem_zalloc(sizeof (*markers) * num_sublists, KM_SLEEP); + for (int i = 0; i < num_sublists; i++) { + markers[i] = kmem_cache_alloc(hdr_full_cache, KM_SLEEP); - /* ignore markers */ - if (hdr->b_spa == 0) - continue; + /* + * A b_spa of 0 is used to indicate that this header is + * a marker. This fact is used in arc_adjust_type() and + * arc_evict_state_impl(). + */ + markers[i]->b_spa = 0; - hash_lock = HDR_LOCK(hdr); - /* caller may be trying to modify this buffer, skip it */ - if (MUTEX_HELD(hash_lock)) - continue; + multilist_sublist_t *mls = multilist_sublist_lock(ml, i); + multilist_sublist_insert_tail(mls, markers[i]); + multilist_sublist_unlock(mls); + } + /* + * While we haven't hit our target number of bytes to evict, or + * we're evicting all available buffers. + */ + while (total_evicted < bytes || bytes == ARC_EVICT_ALL) { /* - * It may take a long time to evict all the bufs requested. - * To avoid blocking all arc activity, periodically drop - * the arcs_mtx and give other threads a chance to run - * before reacquiring the lock. + * Start eviction using a randomly selected sublist, + * this is to try and evenly balance eviction across all + * sublists. Always starting at the same sublist + * (e.g. index 0) would cause evictions to favor certain + * sublists over others. */ - if (count++ > arc_evict_iterations) { - list_insert_after(list, hdr, &marker); - mutex_exit(lock); - kpreempt(KPREEMPT_SYNC); - mutex_enter(lock); - hdr_prev = list_prev(list, &marker); - list_remove(list, &marker); - count = 0; - continue; - } - if (mutex_tryenter(hash_lock)) { - ASSERT(!HDR_IO_IN_PROGRESS(hdr)); - ASSERT(!HDR_HAS_L1HDR(hdr) || - hdr->b_l1hdr.b_buf == NULL); - ARCSTAT_BUMP(arcstat_deleted); - bytes_deleted += hdr->b_size; + int sublist_idx = multilist_get_random_index(ml); + uint64_t scan_evicted = 0; - if (HDR_HAS_L2HDR(hdr)) { - /* - * This buffer is cached on the 2nd Level ARC; - * don't destroy the header. - */ - arc_change_state(arc_l2c_only, hdr, hash_lock); - /* - * dropping from L1+L2 cached to L2-only, - * realloc to remove the L1 header. - */ - hdr = arc_hdr_realloc(hdr, hdr_full_cache, - hdr_l2only_cache); - mutex_exit(hash_lock); - } else { - arc_change_state(arc_anon, hdr, hash_lock); - mutex_exit(hash_lock); - arc_hdr_destroy(hdr); - } + for (int i = 0; i < num_sublists; i++) { + uint64_t bytes_remaining; + uint64_t bytes_evicted; - DTRACE_PROBE1(arc__delete, arc_buf_hdr_t *, hdr); - if (bytes >= 0 && bytes_deleted >= bytes) + if (bytes == ARC_EVICT_ALL) + bytes_remaining = ARC_EVICT_ALL; + else if (total_evicted < bytes) + bytes_remaining = bytes - total_evicted; + else break; - } else if (bytes < 0) { + + bytes_evicted = arc_evict_state_impl(ml, sublist_idx, + markers[sublist_idx], spa, bytes_remaining); + + scan_evicted += bytes_evicted; + total_evicted += bytes_evicted; + + /* we've reached the end, wrap to the beginning */ + if (++sublist_idx >= num_sublists) + sublist_idx = 0; + } + + /* + * If we didn't evict anything during this scan, we have + * no reason to believe we'll evict more during another + * scan, so break the loop. + */ + if (scan_evicted == 0) { + /* This isn't possible, let's make that obvious */ + ASSERT3S(bytes, !=, 0); + /* - * Insert a list marker and then wait for the - * hash lock to become available. Once its - * available, restart from where we left off. + * When bytes is ARC_EVICT_ALL, the only way to + * break the loop is when scan_evicted is zero. + * In that case, we actually have evicted enough, + * so we don't want to increment the kstat. */ - list_insert_after(list, hdr, &marker); - mutex_exit(lock); - mutex_enter(hash_lock); - mutex_exit(hash_lock); - mutex_enter(lock); - hdr_prev = list_prev(list, &marker); - list_remove(list, &marker); - } else { - bufs_skipped += 1; + if (bytes != ARC_EVICT_ALL) { + ASSERT3S(total_evicted, <, bytes); + ARCSTAT_BUMP(arcstat_evict_not_enough); + } + + break; } + } + for (int i = 0; i < num_sublists; i++) { + multilist_sublist_t *mls = multilist_sublist_lock(ml, i); + multilist_sublist_remove(mls, markers[i]); + multilist_sublist_unlock(mls); + + kmem_cache_free(hdr_full_cache, markers[i]); } - mutex_exit(lock); - idx = ((idx + 1) & (ARC_BUFC_NUMDATALISTS - 1)); - lists++; + kmem_free(markers, sizeof (*markers) * num_sublists); - if (lists < list_count) - goto evict_start; + return (total_evicted); +} - evict_offset = idx; - if ((uintptr_t)list > (uintptr_t)&state->arcs_lists[ARC_BUFC_NUMMETADATALISTS] && - (bytes < 0 || bytes_deleted < bytes)) { - list_start = &state->arcs_lists[0]; - list_count = ARC_BUFC_NUMMETADATALISTS; - offset = lists = 0; - goto evict_start; +/* + * Flush all "evictable" data of the given type from the arc state + * specified. This will not evict any "active" buffers (i.e. referenced). + * + * When 'retry' is set to FALSE, the function will make a single pass + * over the state and evict any buffers that it can. Since it doesn't + * continually retry the eviction, it might end up leaving some buffers + * in the ARC due to lock misses. + * + * When 'retry' is set to TRUE, the function will continually retry the + * eviction until *all* evictable buffers have been removed from the + * state. As a result, if concurrent insertions into the state are + * allowed (e.g. if the ARC isn't shutting down), this function might + * wind up in an infinite loop, continually trying to evict buffers. + */ +static uint64_t +arc_flush_state(arc_state_t *state, uint64_t spa, arc_buf_contents_t type, + boolean_t retry) +{ + uint64_t evicted = 0; + + while (state->arcs_lsize[type] != 0) { + evicted += arc_evict_state(state, spa, ARC_EVICT_ALL, type); + + if (!retry) + break; } - if (bufs_skipped) { - ARCSTAT_INCR(arcstat_mutex_miss, bufs_skipped); - ASSERT(bytes >= 0); + return (evicted); +} + +/* + * Evict the specified number of bytes from the state specified, + * restricting eviction to the spa and type given. This function + * prevents us from trying to evict more from a state's list than + * is "evictable", and to skip evicting altogether when passed a + * negative value for "bytes". In contrast, arc_evict_state() will + * evict everything it can, when passed a negative value for "bytes". + */ +static uint64_t +arc_adjust_impl(arc_state_t *state, uint64_t spa, int64_t bytes, + arc_buf_contents_t type) +{ + int64_t delta; + + if (bytes > 0 && state->arcs_lsize[type] > 0) { + delta = MIN(state->arcs_lsize[type], bytes); + return (arc_evict_state(state, spa, delta, type)); } - if (bytes_deleted < bytes) - dprintf("only deleted %lld bytes from %p", - (longlong_t)bytes_deleted, state); + return (0); } -static void +/* + * Evict metadata buffers from the cache, such that arc_meta_used is + * capped by the arc_meta_limit tunable. + */ +static uint64_t +arc_adjust_meta(void) +{ + uint64_t total_evicted = 0; + int64_t target; + + /* + * If we're over the meta limit, we want to evict enough + * metadata to get back under the meta limit. We don't want to + * evict so much that we drop the MRU below arc_p, though. If + * we're over the meta limit more than we're over arc_p, we + * evict some from the MRU here, and some from the MFU below. + */ + target = MIN((int64_t)(arc_meta_used - arc_meta_limit), + (int64_t)(refcount_count(&arc_anon->arcs_size) + + refcount_count(&arc_mru->arcs_size) - arc_p)); + + total_evicted += arc_adjust_impl(arc_mru, 0, target, ARC_BUFC_METADATA); + + /* + * Similar to the above, we want to evict enough bytes to get us + * below the meta limit, but not so much as to drop us below the + * space alloted to the MFU (which is defined as arc_c - arc_p). + */ + target = MIN((int64_t)(arc_meta_used - arc_meta_limit), + (int64_t)(refcount_count(&arc_mfu->arcs_size) - (arc_c - arc_p))); + + total_evicted += arc_adjust_impl(arc_mfu, 0, target, ARC_BUFC_METADATA); + + return (total_evicted); +} + +/* + * Return the type of the oldest buffer in the given arc state + * + * This function will select a random sublist of type ARC_BUFC_DATA and + * a random sublist of type ARC_BUFC_METADATA. The tail of each sublist + * is compared, and the type which contains the "older" buffer will be + * returned. + */ +static arc_buf_contents_t +arc_adjust_type(arc_state_t *state) +{ + multilist_t *data_ml = &state->arcs_list[ARC_BUFC_DATA]; + multilist_t *meta_ml = &state->arcs_list[ARC_BUFC_METADATA]; + int data_idx = multilist_get_random_index(data_ml); + int meta_idx = multilist_get_random_index(meta_ml); + multilist_sublist_t *data_mls; + multilist_sublist_t *meta_mls; + arc_buf_contents_t type; + arc_buf_hdr_t *data_hdr; + arc_buf_hdr_t *meta_hdr; + + /* + * We keep the sublist lock until we're finished, to prevent + * the headers from being destroyed via arc_evict_state(). + */ + data_mls = multilist_sublist_lock(data_ml, data_idx); + meta_mls = multilist_sublist_lock(meta_ml, meta_idx); + + /* + * These two loops are to ensure we skip any markers that + * might be at the tail of the lists due to arc_evict_state(). + */ + + for (data_hdr = multilist_sublist_tail(data_mls); data_hdr != NULL; + data_hdr = multilist_sublist_prev(data_mls, data_hdr)) { + if (data_hdr->b_spa != 0) + break; + } + + for (meta_hdr = multilist_sublist_tail(meta_mls); meta_hdr != NULL; + meta_hdr = multilist_sublist_prev(meta_mls, meta_hdr)) { + if (meta_hdr->b_spa != 0) + break; + } + + if (data_hdr == NULL && meta_hdr == NULL) { + type = ARC_BUFC_DATA; + } else if (data_hdr == NULL) { + ASSERT3P(meta_hdr, !=, NULL); + type = ARC_BUFC_METADATA; + } else if (meta_hdr == NULL) { + ASSERT3P(data_hdr, !=, NULL); + type = ARC_BUFC_DATA; + } else { + ASSERT3P(data_hdr, !=, NULL); + ASSERT3P(meta_hdr, !=, NULL); + + /* The headers can't be on the sublist without an L1 header */ + ASSERT(HDR_HAS_L1HDR(data_hdr)); + ASSERT(HDR_HAS_L1HDR(meta_hdr)); + + if (data_hdr->b_l1hdr.b_arc_access < + meta_hdr->b_l1hdr.b_arc_access) { + type = ARC_BUFC_DATA; + } else { + type = ARC_BUFC_METADATA; + } + } + + multilist_sublist_unlock(meta_mls); + multilist_sublist_unlock(data_mls); + + return (type); +} + +/* + * Evict buffers from the cache, such that arc_size is capped by arc_c. + */ +static uint64_t arc_adjust(void) { - int64_t adjustment, delta; + uint64_t total_evicted = 0; + uint64_t bytes; + int64_t target; + + /* + * If we're over arc_meta_limit, we want to correct that before + * potentially evicting data buffers below. + */ + total_evicted += arc_adjust_meta(); /* * Adjust MRU size + * + * If we're over the target cache size, we want to evict enough + * from the list to get back to our target size. We don't want + * to evict too much from the MRU, such that it drops below + * arc_p. So, if we're over our target cache size more than + * the MRU is over arc_p, we'll evict enough to get back to + * arc_p here, and then evict more from the MFU below. */ + target = MIN((int64_t)(arc_size - arc_c), + (int64_t)(refcount_count(&arc_anon->arcs_size) + + refcount_count(&arc_mru->arcs_size) + arc_meta_used - arc_p)); - adjustment = MIN((int64_t)(arc_size - arc_c), - (int64_t)(arc_anon->arcs_size + arc_mru->arcs_size + arc_meta_used - - arc_p)); + /* + * If we're below arc_meta_min, always prefer to evict data. + * Otherwise, try to satisfy the requested number of bytes to + * evict from the type which contains older buffers; in an + * effort to keep newer buffers in the cache regardless of their + * type. If we cannot satisfy the number of bytes from this + * type, spill over into the next type. + */ + if (arc_adjust_type(arc_mru) == ARC_BUFC_METADATA && + arc_meta_used > arc_meta_min) { + bytes = arc_adjust_impl(arc_mru, 0, target, ARC_BUFC_METADATA); + total_evicted += bytes; - if (adjustment > 0 && arc_mru->arcs_lsize[ARC_BUFC_DATA] > 0) { - delta = MIN(arc_mru->arcs_lsize[ARC_BUFC_DATA], adjustment); - (void) arc_evict(arc_mru, 0, delta, FALSE, ARC_BUFC_DATA); - adjustment -= delta; - } + /* + * If we couldn't evict our target number of bytes from + * metadata, we try to get the rest from data. + */ + target -= bytes; + + total_evicted += + arc_adjust_impl(arc_mru, 0, target, ARC_BUFC_DATA); + } else { + bytes = arc_adjust_impl(arc_mru, 0, target, ARC_BUFC_DATA); + total_evicted += bytes; + + /* + * If we couldn't evict our target number of bytes from + * data, we try to get the rest from metadata. + */ + target -= bytes; - if (adjustment > 0 && arc_mru->arcs_lsize[ARC_BUFC_METADATA] > 0) { - delta = MIN(arc_mru->arcs_lsize[ARC_BUFC_METADATA], adjustment); - (void) arc_evict(arc_mru, 0, delta, FALSE, - ARC_BUFC_METADATA); + total_evicted += + arc_adjust_impl(arc_mru, 0, target, ARC_BUFC_METADATA); } /* * Adjust MFU size + * + * Now that we've tried to evict enough from the MRU to get its + * size back to arc_p, if we're still above the target cache + * size, we evict the rest from the MFU. */ + target = arc_size - arc_c; - adjustment = arc_size - arc_c; + if (arc_adjust_type(arc_mfu) == ARC_BUFC_METADATA && + arc_meta_used > arc_meta_min) { + bytes = arc_adjust_impl(arc_mfu, 0, target, ARC_BUFC_METADATA); + total_evicted += bytes; - if (adjustment > 0 && arc_mfu->arcs_lsize[ARC_BUFC_DATA] > 0) { - delta = MIN(adjustment, arc_mfu->arcs_lsize[ARC_BUFC_DATA]); - (void) arc_evict(arc_mfu, 0, delta, FALSE, ARC_BUFC_DATA); - adjustment -= delta; - } + /* + * If we couldn't evict our target number of bytes from + * metadata, we try to get the rest from data. + */ + target -= bytes; + + total_evicted += + arc_adjust_impl(arc_mfu, 0, target, ARC_BUFC_DATA); + } else { + bytes = arc_adjust_impl(arc_mfu, 0, target, ARC_BUFC_DATA); + total_evicted += bytes; + + /* + * If we couldn't evict our target number of bytes from + * data, we try to get the rest from data. + */ + target -= bytes; - if (adjustment > 0 && arc_mfu->arcs_lsize[ARC_BUFC_METADATA] > 0) { - int64_t delta = MIN(adjustment, - arc_mfu->arcs_lsize[ARC_BUFC_METADATA]); - (void) arc_evict(arc_mfu, 0, delta, FALSE, - ARC_BUFC_METADATA); + total_evicted += + arc_adjust_impl(arc_mfu, 0, target, ARC_BUFC_METADATA); } /* * Adjust ghost lists + * + * In addition to the above, the ARC also defines target values + * for the ghost lists. The sum of the mru list and mru ghost + * list should never exceed the target size of the cache, and + * the sum of the mru list, mfu list, mru ghost list, and mfu + * ghost list should never exceed twice the target size of the + * cache. The following logic enforces these limits on the ghost + * caches, and evicts from them as needed. */ + target = refcount_count(&arc_mru->arcs_size) + + refcount_count(&arc_mru_ghost->arcs_size) - arc_c; - adjustment = arc_mru->arcs_size + arc_mru_ghost->arcs_size - arc_c; + bytes = arc_adjust_impl(arc_mru_ghost, 0, target, ARC_BUFC_DATA); + total_evicted += bytes; - if (adjustment > 0 && arc_mru_ghost->arcs_size > 0) { - delta = MIN(arc_mru_ghost->arcs_size, adjustment); - arc_evict_ghost(arc_mru_ghost, 0, delta); - } + target -= bytes; - adjustment = - arc_mru_ghost->arcs_size + arc_mfu_ghost->arcs_size - arc_c; + total_evicted += + arc_adjust_impl(arc_mru_ghost, 0, target, ARC_BUFC_METADATA); - if (adjustment > 0 && arc_mfu_ghost->arcs_size > 0) { - delta = MIN(arc_mfu_ghost->arcs_size, adjustment); - arc_evict_ghost(arc_mfu_ghost, 0, delta); - } + /* + * We assume the sum of the mru list and mfu list is less than + * or equal to arc_c (we enforced this above), which means we + * can use the simpler of the two equations below: + * + * mru + mfu + mru ghost + mfu ghost <= 2 * arc_c + * mru ghost + mfu ghost <= arc_c + */ + target = refcount_count(&arc_mru_ghost->arcs_size) + + refcount_count(&arc_mfu_ghost->arcs_size) - arc_c; + + bytes = arc_adjust_impl(arc_mfu_ghost, 0, target, ARC_BUFC_DATA); + total_evicted += bytes; + + target -= bytes; + + total_evicted += + arc_adjust_impl(arc_mfu_ghost, 0, target, ARC_BUFC_METADATA); + + return (total_evicted); } static void arc_do_user_evicts(void) { - static arc_buf_t *tmp_arc_eviction_list; - - /* - * Move list over to avoid LOR - */ -restart: - mutex_enter(&arc_eviction_mtx); - tmp_arc_eviction_list = arc_eviction_list; - arc_eviction_list = NULL; - mutex_exit(&arc_eviction_mtx); - - while (tmp_arc_eviction_list != NULL) { - arc_buf_t *buf = tmp_arc_eviction_list; - tmp_arc_eviction_list = buf->b_next; + mutex_enter(&arc_user_evicts_lock); + while (arc_eviction_list != NULL) { + arc_buf_t *buf = arc_eviction_list; + arc_eviction_list = buf->b_next; mutex_enter(&buf->b_evict_lock); buf->b_hdr = NULL; mutex_exit(&buf->b_evict_lock); + mutex_exit(&arc_user_evicts_lock); if (buf->b_efunc != NULL) VERIFY0(buf->b_efunc(buf->b_private)); @@ -3014,58 +3267,45 @@ restart: buf->b_efunc = NULL; buf->b_private = NULL; kmem_cache_free(buf_cache, buf); + mutex_enter(&arc_user_evicts_lock); } - - if (arc_eviction_list != NULL) - goto restart; + mutex_exit(&arc_user_evicts_lock); } -/* - * Flush all *evictable* data from the cache for the given spa. - * NOTE: this will not touch "active" (i.e. referenced) data. - */ void -arc_flush(spa_t *spa) +arc_flush(spa_t *spa, boolean_t retry) { uint64_t guid = 0; + /* + * If retry is TRUE, a spa must not be specified since we have + * no good way to determine if all of a spa's buffers have been + * evicted from an arc state. + */ + ASSERT(!retry || spa == 0); + if (spa != NULL) guid = spa_load_guid(spa); - while (arc_mru->arcs_lsize[ARC_BUFC_DATA]) { - (void) arc_evict(arc_mru, guid, -1, FALSE, ARC_BUFC_DATA); - if (spa != NULL) - break; - } - while (arc_mru->arcs_lsize[ARC_BUFC_METADATA]) { - (void) arc_evict(arc_mru, guid, -1, FALSE, ARC_BUFC_METADATA); - if (spa != NULL) - break; - } - while (arc_mfu->arcs_lsize[ARC_BUFC_DATA]) { - (void) arc_evict(arc_mfu, guid, -1, FALSE, ARC_BUFC_DATA); - if (spa != NULL) - break; - } - while (arc_mfu->arcs_lsize[ARC_BUFC_METADATA]) { - (void) arc_evict(arc_mfu, guid, -1, FALSE, ARC_BUFC_METADATA); - if (spa != NULL) - break; - } + (void) arc_flush_state(arc_mru, guid, ARC_BUFC_DATA, retry); + (void) arc_flush_state(arc_mru, guid, ARC_BUFC_METADATA, retry); + + (void) arc_flush_state(arc_mfu, guid, ARC_BUFC_DATA, retry); + (void) arc_flush_state(arc_mfu, guid, ARC_BUFC_METADATA, retry); - arc_evict_ghost(arc_mru_ghost, guid, -1); - arc_evict_ghost(arc_mfu_ghost, guid, -1); + (void) arc_flush_state(arc_mru_ghost, guid, ARC_BUFC_DATA, retry); + (void) arc_flush_state(arc_mru_ghost, guid, ARC_BUFC_METADATA, retry); + + (void) arc_flush_state(arc_mfu_ghost, guid, ARC_BUFC_DATA, retry); + (void) arc_flush_state(arc_mfu_ghost, guid, ARC_BUFC_METADATA, retry); - mutex_enter(&arc_reclaim_thr_lock); arc_do_user_evicts(); - mutex_exit(&arc_reclaim_thr_lock); ASSERT(spa || arc_eviction_list == NULL); } void arc_shrink(int64_t to_free) { - if (arc_c > arc_c_min) { DTRACE_PROBE4(arc__shrink, uint64_t, arc_c, uint64_t, arc_c_min, uint64_t, arc_p, uint64_t, to_free); @@ -3090,7 +3330,7 @@ arc_shrink(int64_t to_free) if (arc_size > arc_c) { DTRACE_PROBE2(arc__shrink_adjust, uint64_t, arc_size, uint64_t, arc_c); - arc_adjust(); + (void) arc_adjust(); } } @@ -3329,17 +3569,37 @@ arc_kmem_reap_now(void) DTRACE_PROBE(arc__kmem_reap_end); } +/* + * Threads can block in arc_get_data_buf() waiting for this thread to evict + * enough data and signal them to proceed. When this happens, the threads in + * arc_get_data_buf() are sleeping while holding the hash lock for their + * particular arc header. Thus, we must be careful to never sleep on a + * hash lock in this thread. This is to prevent the following deadlock: + * + * - Thread A sleeps on CV in arc_get_data_buf() holding hash lock "L", + * waiting for the reclaim thread to signal it. + * + * - arc_reclaim_thread() tries to acquire hash lock "L" using mutex_enter, + * fails, and goes to sleep forever. + * + * This possible deadlock is avoided by always acquiring a hash lock + * using mutex_tryenter() from arc_reclaim_thread(). + */ static void arc_reclaim_thread(void *dummy __unused) { clock_t growtime = 0; callb_cpr_t cpr; - CALLB_CPR_INIT(&cpr, &arc_reclaim_thr_lock, callb_generic_cpr, FTAG); + CALLB_CPR_INIT(&cpr, &arc_reclaim_lock, callb_generic_cpr, FTAG); - mutex_enter(&arc_reclaim_thr_lock); - while (arc_thread_exit == 0) { + mutex_enter(&arc_reclaim_lock); + while (!arc_reclaim_thread_exit) { int64_t free_memory = arc_available_memory(); + uint64_t evicted = 0; + + mutex_exit(&arc_reclaim_lock); + if (free_memory < 0) { arc_no_grow = B_TRUE; @@ -3373,17 +3633,60 @@ arc_reclaim_thread(void *dummy __unused) arc_no_grow = B_FALSE; } - arc_adjust(); + evicted = arc_adjust(); - if (arc_eviction_list != NULL) - arc_do_user_evicts(); + mutex_enter(&arc_reclaim_lock); + /* + * If evicted is zero, we couldn't evict anything via + * arc_adjust(). This could be due to hash lock + * collisions, but more likely due to the majority of + * arc buffers being unevictable. Therefore, even if + * arc_size is above arc_c, another pass is unlikely to + * be helpful and could potentially cause us to enter an + * infinite loop. + */ + if (arc_size <= arc_c || evicted == 0) { #ifdef _KERNEL - if (needfree) { needfree = 0; - wakeup(&needfree); - } #endif + /* + * We're either no longer overflowing, or we + * can't evict anything more, so we should wake + * up any threads before we go to sleep. + */ + cv_broadcast(&arc_reclaim_waiters_cv); + + /* + * Block until signaled, or after one second (we + * might need to perform arc_kmem_reap_now() + * even if we aren't being signalled) + */ + CALLB_CPR_SAFE_BEGIN(&cpr); + (void) cv_timedwait(&arc_reclaim_thread_cv, + &arc_reclaim_lock, hz); + CALLB_CPR_SAFE_END(&cpr, &arc_reclaim_lock); + } + } + + arc_reclaim_thread_exit = FALSE; + cv_broadcast(&arc_reclaim_thread_cv); + CALLB_CPR_EXIT(&cpr); /* drops arc_reclaim_lock */ + thread_exit(); +} + +static void +arc_user_evicts_thread(void *dummy __unused) +{ + callb_cpr_t cpr; + + CALLB_CPR_INIT(&cpr, &arc_user_evicts_lock, callb_generic_cpr, FTAG); + + mutex_enter(&arc_user_evicts_lock); + while (!arc_user_evicts_thread_exit) { + mutex_exit(&arc_user_evicts_lock); + + arc_do_user_evicts(); /* * This is necessary in order for the mdb ::arc dcmd to @@ -3399,16 +3702,21 @@ arc_reclaim_thread(void *dummy __unused) if (arc_ksp != NULL) arc_ksp->ks_update(arc_ksp, KSTAT_READ); - /* block until needed, or one second, whichever is shorter */ + mutex_enter(&arc_user_evicts_lock); + + /* + * Block until signaled, or after one second (we need to + * call the arc's kstat update function regularly). + */ CALLB_CPR_SAFE_BEGIN(&cpr); - (void) cv_timedwait(&arc_reclaim_thr_cv, - &arc_reclaim_thr_lock, hz); - CALLB_CPR_SAFE_END(&cpr, &arc_reclaim_thr_lock); + (void) cv_timedwait(&arc_user_evicts_cv, + &arc_user_evicts_lock, hz); + CALLB_CPR_SAFE_END(&cpr, &arc_user_evicts_lock); } - arc_thread_exit = 0; - cv_broadcast(&arc_reclaim_thr_cv); - CALLB_CPR_EXIT(&cpr); /* drops arc_reclaim_thr_lock */ + arc_user_evicts_thread_exit = FALSE; + cv_broadcast(&arc_user_evicts_cv); + CALLB_CPR_EXIT(&cpr); /* drops arc_user_evicts_lock */ thread_exit(); } @@ -3422,6 +3730,8 @@ arc_adapt(int bytes, arc_state_t *state) { int mult; uint64_t arc_p_min = (arc_c >> arc_p_min_shift); + int64_t mrug_size = refcount_count(&arc_mru_ghost->arcs_size); + int64_t mfug_size = refcount_count(&arc_mfu_ghost->arcs_size); if (state == arc_l2c_only) return; @@ -3436,16 +3746,14 @@ arc_adapt(int bytes, arc_state_t *state) * target size of the MRU list. */ if (state == arc_mru_ghost) { - mult = ((arc_mru_ghost->arcs_size >= arc_mfu_ghost->arcs_size) ? - 1 : (arc_mfu_ghost->arcs_size/arc_mru_ghost->arcs_size)); + mult = (mrug_size >= mfug_size) ? 1 : (mfug_size / mrug_size); mult = MIN(mult, 10); /* avoid wild arc_p adjustment */ arc_p = MIN(arc_c - arc_p_min, arc_p + bytes * mult); } else if (state == arc_mfu_ghost) { uint64_t delta; - mult = ((arc_mfu_ghost->arcs_size >= arc_mru_ghost->arcs_size) ? - 1 : (arc_mru_ghost->arcs_size/arc_mfu_ghost->arcs_size)); + mult = (mfug_size >= mrug_size) ? 1 : (mrug_size / mfug_size); mult = MIN(mult, 10); delta = MIN(bytes * mult, arc_p); @@ -3454,7 +3762,7 @@ arc_adapt(int bytes, arc_state_t *state) ASSERT((int64_t)arc_p >= 0); if (arc_reclaim_needed()) { - cv_signal(&arc_reclaim_thr_cv); + cv_signal(&arc_reclaim_thread_cv); return; } @@ -3482,43 +3790,25 @@ arc_adapt(int bytes, arc_state_t *state) } /* - * Check if the cache has reached its limits and eviction is required - * prior to insert. + * Check if arc_size has grown past our upper threshold, determined by + * zfs_arc_overflow_shift. */ -static int -arc_evict_needed(arc_buf_contents_t type) +static boolean_t +arc_is_overflowing(void) { - if (type == ARC_BUFC_METADATA && arc_meta_used >= arc_meta_limit) - return (1); + /* Always allow at least one block of overflow */ + uint64_t overflow = MAX(SPA_MAXBLOCKSIZE, + arc_c >> zfs_arc_overflow_shift); - if (arc_reclaim_needed()) - return (1); - - return (arc_size > arc_c); + return (arc_size >= arc_c + overflow); } /* - * The buffer, supplied as the first argument, needs a data block. - * So, if we are at cache max, determine which cache should be victimized. - * We have the following cases: - * - * 1. Insert for MRU, p > sizeof(arc_anon + arc_mru) -> - * In this situation if we're out of space, but the resident size of the MFU is - * under the limit, victimize the MFU cache to satisfy this insertion request. - * - * 2. Insert for MRU, p <= sizeof(arc_anon + arc_mru) -> - * Here, we've used up all of the available space for the MRU, so we need to - * evict from our own cache instead. Evict from the set of resident MRU - * entries. - * - * 3. Insert for MFU (c - p) > sizeof(arc_mfu) -> - * c minus p represents the MFU space in the cache, since p is the size of the - * cache that is dedicated to the MRU. In this situation there's still space on - * the MFU side, so the MRU side needs to be victimized. - * - * 4. Insert for MFU (c - p) < sizeof(arc_mfu) -> - * MFU's resident set is consuming more space than it has been allotted. In - * this situation, we must victimize our own cache, the MFU, for this insertion. + * The buffer, supplied as the first argument, needs a data block. If we + * are hitting the hard limit for the cache size, we must sleep, waiting + * for the eviction thread to catch up. If we're past the target size + * but below the hard limit, we'll only signal the reclaim thread and + * continue on. */ static void arc_get_data_buf(arc_buf_t *buf) @@ -3530,62 +3820,70 @@ arc_get_data_buf(arc_buf_t *buf) arc_adapt(size, state); /* - * We have not yet reached cache maximum size, - * just allocate a new buffer. + * If arc_size is currently overflowing, and has grown past our + * upper limit, we must be adding data faster than the evict + * thread can evict. Thus, to ensure we don't compound the + * problem by adding more data and forcing arc_size to grow even + * further past it's target size, we halt and wait for the + * eviction thread to catch up. + * + * It's also possible that the reclaim thread is unable to evict + * enough buffers to get arc_size below the overflow limit (e.g. + * due to buffers being un-evictable, or hash lock collisions). + * In this case, we want to proceed regardless if we're + * overflowing; thus we don't use a while loop here. */ - if (!arc_evict_needed(type)) { - if (type == ARC_BUFC_METADATA) { - buf->b_data = zio_buf_alloc(size); - arc_space_consume(size, ARC_SPACE_META); - } else { - ASSERT(type == ARC_BUFC_DATA); - buf->b_data = zio_data_buf_alloc(size); - arc_space_consume(size, ARC_SPACE_DATA); + if (arc_is_overflowing()) { + mutex_enter(&arc_reclaim_lock); + + /* + * Now that we've acquired the lock, we may no longer be + * over the overflow limit, lets check. + * + * We're ignoring the case of spurious wake ups. If that + * were to happen, it'd let this thread consume an ARC + * buffer before it should have (i.e. before we're under + * the overflow limit and were signalled by the reclaim + * thread). As long as that is a rare occurrence, it + * shouldn't cause any harm. + */ + if (arc_is_overflowing()) { + cv_signal(&arc_reclaim_thread_cv); + cv_wait(&arc_reclaim_waiters_cv, &arc_reclaim_lock); } - goto out; + + mutex_exit(&arc_reclaim_lock); } - /* - * If we are prefetching from the mfu ghost list, this buffer - * will end up on the mru list; so steal space from there. - */ - if (state == arc_mfu_ghost) - state = HDR_PREFETCH(buf->b_hdr) ? arc_mru : arc_mfu; - else if (state == arc_mru_ghost) - state = arc_mru; - - if (state == arc_mru || state == arc_anon) { - uint64_t mru_used = arc_anon->arcs_size + arc_mru->arcs_size; - state = (arc_mfu->arcs_lsize[type] >= size && - arc_p > mru_used) ? arc_mfu : arc_mru; + if (type == ARC_BUFC_METADATA) { + buf->b_data = zio_buf_alloc(size); + arc_space_consume(size, ARC_SPACE_META); } else { - /* MFU cases */ - uint64_t mfu_space = arc_c - arc_p; - state = (arc_mru->arcs_lsize[type] >= size && - mfu_space > arc_mfu->arcs_size) ? arc_mru : arc_mfu; + ASSERT(type == ARC_BUFC_DATA); + buf->b_data = zio_data_buf_alloc(size); + arc_space_consume(size, ARC_SPACE_DATA); } - if ((buf->b_data = arc_evict(state, 0, size, TRUE, type)) == NULL) { - if (type == ARC_BUFC_METADATA) { - buf->b_data = zio_buf_alloc(size); - arc_space_consume(size, ARC_SPACE_META); - } else { - ASSERT(type == ARC_BUFC_DATA); - buf->b_data = zio_data_buf_alloc(size); - arc_space_consume(size, ARC_SPACE_DATA); - } - ARCSTAT_BUMP(arcstat_recycle_miss); - } - ASSERT(buf->b_data != NULL); -out: + /* * Update the state size. Note that ghost states have a * "ghost size" and so don't need to be updated. */ if (!GHOST_STATE(buf->b_hdr->b_l1hdr.b_state)) { arc_buf_hdr_t *hdr = buf->b_hdr; + arc_state_t *state = hdr->b_l1hdr.b_state; + + (void) refcount_add_many(&state->arcs_size, size, buf); - atomic_add_64(&hdr->b_l1hdr.b_state->arcs_size, size); - if (list_link_active(&hdr->b_l1hdr.b_arc_node)) { + /* + * If this is reached via arc_read, the link is + * protected by the hash lock. If reached via + * arc_buf_alloc, the header should not be accessed by + * any other thread. And, if reached via arc_read_done, + * the hash lock will protect it if it's found in the + * hash table; otherwise no other thread should be + * trying to [add|remove]_reference it. + */ + if (multilist_link_active(&hdr->b_l1hdr.b_arc_node)) { ASSERT(refcount_is_zero(&hdr->b_l1hdr.b_refcnt)); atomic_add_64(&hdr->b_l1hdr.b_state->arcs_lsize[type], size); @@ -3595,7 +3893,8 @@ out: * data, and we have outgrown arc_p, update arc_p */ if (arc_size < arc_c && hdr->b_l1hdr.b_state == arc_anon && - arc_anon->arcs_size + arc_mru->arcs_size > arc_p) + (refcount_count(&arc_anon->arcs_size) + + refcount_count(&arc_mru->arcs_size) > arc_p)) arc_p = MIN(arc_c, arc_p + size); } ARCSTAT_BUMP(arcstat_allocated); @@ -3638,7 +3937,8 @@ arc_access(arc_buf_hdr_t *hdr, kmutex_t *hash_lock) */ if (HDR_PREFETCH(hdr)) { if (refcount_count(&hdr->b_l1hdr.b_refcnt) == 0) { - ASSERT(list_link_active( + /* link protected by hash lock */ + ASSERT(multilist_link_active( &hdr->b_l1hdr.b_arc_node)); } else { hdr->b_flags &= ~ARC_FLAG_PREFETCH; @@ -3698,7 +3998,8 @@ arc_access(arc_buf_hdr_t *hdr, kmutex_t *hash_lock) */ if ((HDR_PREFETCH(hdr)) != 0) { ASSERT(refcount_is_zero(&hdr->b_l1hdr.b_refcnt)); - ASSERT(list_link_active(&hdr->b_l1hdr.b_arc_node)); + /* link protected by hash_lock */ + ASSERT(multilist_link_active(&hdr->b_l1hdr.b_arc_node)); } ARCSTAT_BUMP(arcstat_mfu_hits); hdr->b_l1hdr.b_arc_access = ddi_get_lbolt(); @@ -3903,7 +4204,7 @@ arc_read_done(zio_t *zio) } /* - * "Read" the block block at the specified DVA (in bp) via the + * "Read" the block at the specified DVA (in bp) via the * cache. If the block is found in the cache, invoke the provided * callback immediately and return. Note that the `zio' parameter * in the callback will be NULL in this case, since no IO was @@ -4070,7 +4371,7 @@ top: ASSERT(GHOST_STATE(hdr->b_l1hdr.b_state)); ASSERT(!HDR_IO_IN_PROGRESS(hdr)); ASSERT(refcount_is_zero(&hdr->b_l1hdr.b_refcnt)); - ASSERT(hdr->b_l1hdr.b_buf == NULL); + ASSERT3P(hdr->b_l1hdr.b_buf, ==, NULL); /* if this is a prefetch, we don't have a reference */ if (*arc_flags & ARC_FLAG_PREFETCH) @@ -4297,8 +4598,6 @@ arc_clear_callback(arc_buf_t *buf) kmutex_t *hash_lock; arc_evict_func_t *efunc = buf->b_efunc; void *private = buf->b_private; - list_t *list, *evicted_list; - kmutex_t *lock, *evicted_lock; mutex_enter(&buf->b_evict_lock); hdr = buf->b_hdr; @@ -4334,7 +4633,7 @@ arc_clear_callback(arc_buf_t *buf) if (hdr->b_l1hdr.b_datacnt > 1) { mutex_exit(&buf->b_evict_lock); - arc_buf_destroy(buf, FALSE, TRUE); + arc_buf_destroy(buf, TRUE); } else { ASSERT(buf == hdr->b_l1hdr.b_buf); hdr->b_flags |= ARC_FLAG_BUF_AVAILABLE; @@ -4364,6 +4663,9 @@ arc_release(arc_buf_t *buf, void *tag) */ mutex_enter(&buf->b_evict_lock); + + ASSERT(HDR_HAS_L1HDR(hdr)); + /* * We don't grab the hash lock prior to this check, because if * the buffer's header is in the arc_anon state, it won't be @@ -4449,8 +4751,10 @@ arc_release(arc_buf_t *buf, void *tag) buf->b_next = NULL; ASSERT3P(state, !=, arc_l2c_only); - ASSERT3U(state->arcs_size, >=, hdr->b_size); - atomic_add_64(&state->arcs_size, -hdr->b_size); + + (void) refcount_remove_many( + &state->arcs_size, hdr->b_size, buf); + if (refcount_is_zero(&hdr->b_l1hdr.b_refcnt)) { ASSERT3P(state, !=, arc_l2c_only); uint64_t *size = &state->arcs_lsize[type]; @@ -4487,17 +4791,18 @@ arc_release(arc_buf_t *buf, void *tag) nhdr->b_l1hdr.b_datacnt = 1; nhdr->b_l1hdr.b_state = arc_anon; nhdr->b_l1hdr.b_arc_access = 0; + nhdr->b_l1hdr.b_tmp_cdata = NULL; nhdr->b_freeze_cksum = NULL; (void) refcount_add(&nhdr->b_l1hdr.b_refcnt, tag); buf->b_hdr = nhdr; mutex_exit(&buf->b_evict_lock); - atomic_add_64(&arc_anon->arcs_size, blksz); + (void) refcount_add_many(&arc_anon->arcs_size, blksz, buf); } else { mutex_exit(&buf->b_evict_lock); ASSERT(refcount_count(&hdr->b_l1hdr.b_refcnt) == 1); - /* protected by hash lock */ - ASSERT(!list_link_active(&hdr->b_l1hdr.b_arc_node)); + /* protected by hash lock, or hdr is on arc_anon */ + ASSERT(!multilist_link_active(&hdr->b_l1hdr.b_arc_node)); ASSERT(!HDR_IO_IN_PROGRESS(hdr)); arc_change_state(arc_anon, hdr, hash_lock); hdr->b_l1hdr.b_arc_access = 0; @@ -4759,7 +5064,8 @@ arc_tempreserve_space(uint64_t reserve, uint64_t txg) * network delays from blocking transactions that are ready to be * assigned to a txg. */ - anon_size = MAX((int64_t)(arc_anon->arcs_size - arc_loaned_bytes), 0); + anon_size = MAX((int64_t)(refcount_count(&arc_anon->arcs_size) - + arc_loaned_bytes), 0); /* * Writes will, almost always, require additional memory allocations @@ -4796,7 +5102,7 @@ static void arc_kstat_update_state(arc_state_t *state, kstat_named_t *size, kstat_named_t *evict_data, kstat_named_t *evict_metadata) { - size->value.ui64 = state->arcs_size; + size->value.ui64 = refcount_count(&state->arcs_size); evict_data->value.ui64 = state->arcs_lsize[ARC_BUFC_DATA]; evict_metadata->value.ui64 = state->arcs_lsize[ARC_BUFC_METADATA]; } @@ -4834,6 +5140,41 @@ arc_kstat_update(kstat_t *ksp, int rw) return (0); } +/* + * This function *must* return indices evenly distributed between all + * sublists of the multilist. This is needed due to how the ARC eviction + * code is laid out; arc_evict_state() assumes ARC buffers are evenly + * distributed between all sublists and uses this assumption when + * deciding which sublist to evict from and how much to evict from it. + */ +unsigned int +arc_state_multilist_index_func(multilist_t *ml, void *obj) +{ + arc_buf_hdr_t *hdr = obj; + + /* + * We rely on b_dva to generate evenly distributed index + * numbers using buf_hash below. So, as an added precaution, + * let's make sure we never add empty buffers to the arc lists. + */ + ASSERT(!BUF_EMPTY(hdr)); + + /* + * The assumption here, is the hash value for a given + * arc_buf_hdr_t will remain constant throughout it's lifetime + * (i.e. it's b_spa, b_dva, and b_birth fields don't change). + * Thus, we don't need to store the header's sublist index + * on insertion, as this index can be recalculated on removal. + * + * Also, the low order bits of the hash value are thought to be + * distributed evenly. Otherwise, in the case that the multilist + * has a power of two number of sublists, each sublists' usage + * would not be evenly distributed. + */ + return (buf_hash(hdr->b_spa, &hdr->b_dva, hdr->b_birth) % + multilist_get_num_sublists(ml)); +} + #ifdef _KERNEL static eventhandler_tag arc_event_lowmem = NULL; @@ -4841,11 +5182,11 @@ static void arc_lowmem(void *arg __unused, int howto __unused) { - mutex_enter(&arc_reclaim_thr_lock); + mutex_enter(&arc_reclaim_lock); /* XXX: Memory deficit should be passed as argument. */ needfree = btoc(arc_c >> arc_shrink_shift); DTRACE_PROBE(arc__needfree); - cv_signal(&arc_reclaim_thr_cv); + cv_signal(&arc_reclaim_thread_cv); /* * It is unsafe to block here in arbitrary threads, because we can come @@ -4853,8 +5194,8 @@ arc_lowmem(void *arg __unused, int howto __unused) * with ARC reclaim thread. */ if (curproc == pageproc) - msleep(&needfree, &arc_reclaim_thr_lock, 0, "zfs:lowmem", 0); - mutex_exit(&arc_reclaim_thr_lock); + (void) cv_wait(&arc_reclaim_waiters_cv, &arc_reclaim_lock); + mutex_exit(&arc_reclaim_lock); } #endif @@ -4863,8 +5204,12 @@ arc_init(void) { int i, prefetch_tunable_set = 0; - mutex_init(&arc_reclaim_thr_lock, NULL, MUTEX_DEFAULT, NULL); - cv_init(&arc_reclaim_thr_cv, NULL, CV_DEFAULT, NULL); + mutex_init(&arc_reclaim_lock, NULL, MUTEX_DEFAULT, NULL); + cv_init(&arc_reclaim_thread_cv, NULL, CV_DEFAULT, NULL); + cv_init(&arc_reclaim_waiters_cv, NULL, CV_DEFAULT, NULL); + + mutex_init(&arc_user_evicts_lock, NULL, MUTEX_DEFAULT, NULL); + cv_init(&arc_user_evicts_cv, NULL, CV_DEFAULT, NULL); /* Convert seconds to clock ticks */ arc_min_prefetch_lifespan = 1 * hz; @@ -4936,6 +5281,9 @@ arc_init(void) if (zfs_arc_p_min_shift > 0) arc_p_min_shift = zfs_arc_p_min_shift; + if (zfs_arc_num_sublists_per_state < 1) + zfs_arc_num_sublists_per_state = MAX(max_ncpus, 1); + /* if kmem_flags are set, lets try to use less memory */ if (kmem_debugging()) arc_c = arc_c / 2; @@ -4953,45 +5301,59 @@ arc_init(void) arc_l2c_only = &ARC_l2c_only; arc_size = 0; - for (i = 0; i < ARC_BUFC_NUMLISTS; i++) { - mutex_init(&arc_anon->arcs_locks[i].arcs_lock, - NULL, MUTEX_DEFAULT, NULL); - mutex_init(&arc_mru->arcs_locks[i].arcs_lock, - NULL, MUTEX_DEFAULT, NULL); - mutex_init(&arc_mru_ghost->arcs_locks[i].arcs_lock, - NULL, MUTEX_DEFAULT, NULL); - mutex_init(&arc_mfu->arcs_locks[i].arcs_lock, - NULL, MUTEX_DEFAULT, NULL); - mutex_init(&arc_mfu_ghost->arcs_locks[i].arcs_lock, - NULL, MUTEX_DEFAULT, NULL); - mutex_init(&arc_l2c_only->arcs_locks[i].arcs_lock, - NULL, MUTEX_DEFAULT, NULL); - - list_create(&arc_mru->arcs_lists[i], - sizeof (arc_buf_hdr_t), - offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node)); - list_create(&arc_mru_ghost->arcs_lists[i], - sizeof (arc_buf_hdr_t), - offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node)); - list_create(&arc_mfu->arcs_lists[i], - sizeof (arc_buf_hdr_t), - offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node)); - list_create(&arc_mfu_ghost->arcs_lists[i], - sizeof (arc_buf_hdr_t), - offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node)); - list_create(&arc_mfu_ghost->arcs_lists[i], - sizeof (arc_buf_hdr_t), - offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node)); - list_create(&arc_l2c_only->arcs_lists[i], - sizeof (arc_buf_hdr_t), - offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node)); - } + multilist_create(&arc_mru->arcs_list[ARC_BUFC_METADATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_mru->arcs_list[ARC_BUFC_DATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_mru_ghost->arcs_list[ARC_BUFC_METADATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_mru_ghost->arcs_list[ARC_BUFC_DATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_mfu->arcs_list[ARC_BUFC_METADATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_mfu->arcs_list[ARC_BUFC_DATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_mfu_ghost->arcs_list[ARC_BUFC_METADATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_mfu_ghost->arcs_list[ARC_BUFC_DATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_l2c_only->arcs_list[ARC_BUFC_METADATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + multilist_create(&arc_l2c_only->arcs_list[ARC_BUFC_DATA], + sizeof (arc_buf_hdr_t), + offsetof(arc_buf_hdr_t, b_l1hdr.b_arc_node), + zfs_arc_num_sublists_per_state, arc_state_multilist_index_func); + + refcount_create(&arc_anon->arcs_size); + refcount_create(&arc_mru->arcs_size); + refcount_create(&arc_mru_ghost->arcs_size); + refcount_create(&arc_mfu->arcs_size); + refcount_create(&arc_mfu_ghost->arcs_size); + refcount_create(&arc_l2c_only->arcs_size); buf_init(); - arc_thread_exit = 0; + arc_reclaim_thread_exit = FALSE; + arc_user_evicts_thread_exit = FALSE; arc_eviction_list = NULL; - mutex_init(&arc_eviction_mtx, NULL, MUTEX_DEFAULT, NULL); bzero(&arc_eviction_hdr, sizeof (arc_buf_hdr_t)); arc_ksp = kstat_create("zfs", 0, "arcstats", "misc", KSTAT_TYPE_NAMED, @@ -5011,6 +5373,9 @@ arc_init(void) EVENTHANDLER_PRI_FIRST); #endif + (void) thread_create(NULL, 0, arc_user_evicts_thread, NULL, 0, &p0, + TS_RUN, minclsyspri); + arc_dead = FALSE; arc_warm = B_FALSE; @@ -5069,16 +5434,32 @@ arc_init(void) void arc_fini(void) { - int i; + mutex_enter(&arc_reclaim_lock); + arc_reclaim_thread_exit = TRUE; + /* + * The reclaim thread will set arc_reclaim_thread_exit back to + * FALSE when it is finished exiting; we're waiting for that. + */ + while (arc_reclaim_thread_exit) { + cv_signal(&arc_reclaim_thread_cv); + cv_wait(&arc_reclaim_thread_cv, &arc_reclaim_lock); + } + mutex_exit(&arc_reclaim_lock); - mutex_enter(&arc_reclaim_thr_lock); - arc_thread_exit = 1; - cv_signal(&arc_reclaim_thr_cv); - while (arc_thread_exit != 0) - cv_wait(&arc_reclaim_thr_cv, &arc_reclaim_thr_lock); - mutex_exit(&arc_reclaim_thr_lock); + mutex_enter(&arc_user_evicts_lock); + arc_user_evicts_thread_exit = TRUE; + /* + * The user evicts thread will set arc_user_evicts_thread_exit + * to FALSE when it is finished exiting; we're waiting for that. + */ + while (arc_user_evicts_thread_exit) { + cv_signal(&arc_user_evicts_cv); + cv_wait(&arc_user_evicts_cv, &arc_user_evicts_lock); + } + mutex_exit(&arc_user_evicts_lock); - arc_flush(NULL); + /* Use TRUE to ensure *all* buffers are evicted */ + arc_flush(NULL, TRUE); arc_dead = TRUE; @@ -5087,24 +5468,28 @@ arc_fini(void) arc_ksp = NULL; } - mutex_destroy(&arc_eviction_mtx); - mutex_destroy(&arc_reclaim_thr_lock); - cv_destroy(&arc_reclaim_thr_cv); + mutex_destroy(&arc_reclaim_lock); + cv_destroy(&arc_reclaim_thread_cv); + cv_destroy(&arc_reclaim_waiters_cv); - for (i = 0; i < ARC_BUFC_NUMLISTS; i++) { - list_destroy(&arc_mru->arcs_lists[i]); - list_destroy(&arc_mru_ghost->arcs_lists[i]); - list_destroy(&arc_mfu->arcs_lists[i]); - list_destroy(&arc_mfu_ghost->arcs_lists[i]); - list_destroy(&arc_l2c_only->arcs_lists[i]); + mutex_destroy(&arc_user_evicts_lock); + cv_destroy(&arc_user_evicts_cv); - mutex_destroy(&arc_anon->arcs_locks[i].arcs_lock); - mutex_destroy(&arc_mru->arcs_locks[i].arcs_lock); - mutex_destroy(&arc_mru_ghost->arcs_locks[i].arcs_lock); - mutex_destroy(&arc_mfu->arcs_locks[i].arcs_lock); - mutex_destroy(&arc_mfu_ghost->arcs_locks[i].arcs_lock); - mutex_destroy(&arc_l2c_only->arcs_locks[i].arcs_lock); - } + refcount_destroy(&arc_anon->arcs_size); + refcount_destroy(&arc_mru->arcs_size); + refcount_destroy(&arc_mru_ghost->arcs_size); + refcount_destroy(&arc_mfu->arcs_size); + refcount_destroy(&arc_mfu_ghost->arcs_size); + refcount_destroy(&arc_l2c_only->arcs_size); + + multilist_destroy(&arc_mru->arcs_list[ARC_BUFC_METADATA]); + multilist_destroy(&arc_mru_ghost->arcs_list[ARC_BUFC_METADATA]); + multilist_destroy(&arc_mfu->arcs_list[ARC_BUFC_METADATA]); + multilist_destroy(&arc_mfu_ghost->arcs_list[ARC_BUFC_METADATA]); + multilist_destroy(&arc_mru->arcs_list[ARC_BUFC_DATA]); + multilist_destroy(&arc_mru_ghost->arcs_list[ARC_BUFC_DATA]); + multilist_destroy(&arc_mfu->arcs_list[ARC_BUFC_DATA]); + multilist_destroy(&arc_mfu_ghost->arcs_list[ARC_BUFC_DATA]); buf_fini(); @@ -5450,39 +5835,68 @@ l2arc_write_done(zio_t *zio) if (zio->io_error != 0) ARCSTAT_BUMP(arcstat_l2_writes_error); - mutex_enter(&dev->l2ad_mtx); - /* * All writes completed, or an error was hit. */ +top: + mutex_enter(&dev->l2ad_mtx); for (hdr = list_prev(buflist, head); hdr; hdr = hdr_prev) { hdr_prev = list_prev(buflist, hdr); hash_lock = HDR_LOCK(hdr); + + /* + * We cannot use mutex_enter or else we can deadlock + * with l2arc_write_buffers (due to swapping the order + * the hash lock and l2ad_mtx are taken). + */ if (!mutex_tryenter(hash_lock)) { /* - * This buffer misses out. It may be in a stage - * of eviction. Its ARC_FLAG_L2_WRITING flag will be - * left set, denying reads to this buffer. + * Missed the hash lock. We must retry so we + * don't leave the ARC_FLAG_L2_WRITING bit set. */ - ARCSTAT_BUMP(arcstat_l2_writes_hdr_miss); - continue; + ARCSTAT_BUMP(arcstat_l2_writes_lock_retry); + + /* + * We don't want to rescan the headers we've + * already marked as having been written out, so + * we reinsert the head node so we can pick up + * where we left off. + */ + list_remove(buflist, head); + list_insert_after(buflist, hdr, head); + + mutex_exit(&dev->l2ad_mtx); + + /* + * We wait for the hash lock to become available + * to try and prevent busy waiting, and increase + * the chance we'll be able to acquire the lock + * the next time around. + */ + mutex_enter(hash_lock); + mutex_exit(hash_lock); + goto top; } /* - * It's possible that this buffer got evicted from the L1 cache - * before we grabbed the vdev + hash locks, in which case - * arc_hdr_realloc freed b_tmp_cdata for us if it was allocated. - * Only free the buffer if we still have an L1 hdr. + * We could not have been moved into the arc_l2c_only + * state while in-flight due to our ARC_FLAG_L2_WRITING + * bit being set. Let's just ensure that's being enforced. */ - if (HDR_HAS_L1HDR(hdr) && hdr->b_l1hdr.b_tmp_cdata != NULL && - HDR_GET_COMPRESS(hdr) != ZIO_COMPRESS_OFF) - l2arc_release_cdata_buf(hdr); + ASSERT(HDR_HAS_L1HDR(hdr)); + + /* + * We may have allocated a buffer for L2ARC compression, + * we must release it to avoid leaking this data. + */ + l2arc_release_cdata_buf(hdr); if (zio->io_error != 0) { /* * Error - drop L2ARC entry. */ + list_remove(buflist, hdr); trim_map_free(hdr->b_l2hdr.b_dev->l2ad_vdev, hdr->b_l2hdr.b_daddr, hdr->b_l2hdr.b_asize, 0); hdr->b_flags &= ~ARC_FLAG_HAS_L2HDR; @@ -5496,7 +5910,8 @@ l2arc_write_done(zio_t *zio) } /* - * Allow ARC to begin reads to this L2ARC entry. + * Allow ARC to begin reads and ghost list evictions to + * this L2ARC entry. */ hdr->b_flags &= ~ARC_FLAG_L2_WRITING; @@ -5604,36 +6019,37 @@ l2arc_read_done(zio_t *zio) * the data lists. This function returns a locked list, and also returns * the lock pointer. */ -static list_t * -l2arc_list_locked(int list_num, kmutex_t **lock) +static multilist_sublist_t * +l2arc_sublist_lock(int list_num) { - list_t *list = NULL; - int idx; - - ASSERT(list_num >= 0 && list_num < 2 * ARC_BUFC_NUMLISTS); - - if (list_num < ARC_BUFC_NUMMETADATALISTS) { - idx = list_num; - list = &arc_mfu->arcs_lists[idx]; - *lock = ARCS_LOCK(arc_mfu, idx); - } else if (list_num < ARC_BUFC_NUMMETADATALISTS * 2) { - idx = list_num - ARC_BUFC_NUMMETADATALISTS; - list = &arc_mru->arcs_lists[idx]; - *lock = ARCS_LOCK(arc_mru, idx); - } else if (list_num < (ARC_BUFC_NUMMETADATALISTS * 2 + - ARC_BUFC_NUMDATALISTS)) { - idx = list_num - ARC_BUFC_NUMMETADATALISTS; - list = &arc_mfu->arcs_lists[idx]; - *lock = ARCS_LOCK(arc_mfu, idx); - } else { - idx = list_num - ARC_BUFC_NUMLISTS; - list = &arc_mru->arcs_lists[idx]; - *lock = ARCS_LOCK(arc_mru, idx); + multilist_t *ml = NULL; + unsigned int idx; + + ASSERT(list_num >= 0 && list_num <= 3); + + switch (list_num) { + case 0: + ml = &arc_mfu->arcs_list[ARC_BUFC_METADATA]; + break; + case 1: + ml = &arc_mru->arcs_list[ARC_BUFC_METADATA]; + break; + case 2: + ml = &arc_mfu->arcs_list[ARC_BUFC_DATA]; + break; + case 3: + ml = &arc_mru->arcs_list[ARC_BUFC_DATA]; + break; } - ASSERT(!(MUTEX_HELD(*lock))); - mutex_enter(*lock); - return (list); + /* + * Return a randomly-selected sublist. This is acceptable + * because the caller feeds only a little bit of data for each + * call (8MB). Subsequent calls will result in different + * sublists being selected. + */ + idx = multilist_get_random_index(ml); + return (multilist_sublist_lock(ml, idx)); } /* @@ -5678,6 +6094,12 @@ top: hdr_prev = list_prev(buflist, hdr); hash_lock = HDR_LOCK(hdr); + + /* + * We cannot use mutex_enter or else we can deadlock + * with l2arc_write_buffers (due to swapping the order + * the hash lock and l2ad_mtx are taken). + */ if (!mutex_tryenter(hash_lock)) { /* * Missed the hash lock. Retry. @@ -5733,6 +6155,10 @@ top: hdr->b_flags |= ARC_FLAG_L2_EVICTED; } + /* Ensure this header has finished being written */ + ASSERT(!HDR_L2_WRITING(hdr)); + ASSERT3P(hdr->b_l1hdr.b_tmp_cdata, ==, NULL); + arc_hdr_l2hdr_destroy(hdr); } mutex_exit(hash_lock); @@ -5756,11 +6182,9 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, boolean_t *headroom_boost) { arc_buf_hdr_t *hdr, *hdr_prev, *head; - list_t *list; uint64_t write_asize, write_psize, write_sz, headroom, buf_compress_minsz; void *buf_data; - kmutex_t *list_lock; boolean_t full; l2arc_write_callback_t *cb; zio_t *pio, *wzio; @@ -5790,11 +6214,10 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, /* * Copy buffers for L2ARC writing. */ - mutex_enter(&dev->l2ad_mtx); - for (try = 0; try < 2 * ARC_BUFC_NUMLISTS; try++) { + for (try = 0; try <= 3; try++) { + multilist_sublist_t *mls = l2arc_sublist_lock(try); uint64_t passed_sz = 0; - list = l2arc_list_locked(try, &list_lock); ARCSTAT_BUMP(arcstat_l2_write_buffer_list_iter); /* @@ -5804,13 +6227,13 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, * head of the ARC lists rather than the tail. */ if (arc_warm == B_FALSE) - hdr = list_head(list); + hdr = multilist_sublist_head(mls); else - hdr = list_tail(list); + hdr = multilist_sublist_tail(mls); if (hdr == NULL) ARCSTAT_BUMP(arcstat_l2_write_buffer_list_null_iter); - headroom = target_sz * l2arc_headroom * 2 / ARC_BUFC_NUMLISTS; + headroom = target_sz * l2arc_headroom; if (do_headroom_boost) headroom = (headroom * l2arc_headroom_boost) / 100; @@ -5819,9 +6242,9 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, uint64_t buf_sz; if (arc_warm == B_FALSE) - hdr_prev = list_next(list, hdr); + hdr_prev = multilist_sublist_next(mls, hdr); else - hdr_prev = list_prev(list, hdr); + hdr_prev = multilist_sublist_prev(mls, hdr); ARCSTAT_INCR(arcstat_l2_write_buffer_bytes_scanned, hdr->b_size); hash_lock = HDR_LOCK(hdr); @@ -5861,7 +6284,9 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, * l2arc_write_done() can find where the * write buffers begin without searching. */ + mutex_enter(&dev->l2ad_mtx); list_insert_head(&dev->l2ad_buflist, head); + mutex_exit(&dev->l2ad_mtx); cb = kmem_alloc( sizeof (l2arc_write_callback_t), KM_SLEEP); @@ -5915,7 +6340,9 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, buf_sz = hdr->b_size; hdr->b_flags |= ARC_FLAG_HAS_L2HDR; + mutex_enter(&dev->l2ad_mtx); list_insert_head(&dev->l2ad_buflist, hdr); + mutex_exit(&dev->l2ad_mtx); /* * Compute and store the buffer cksum before @@ -5929,7 +6356,7 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, write_sz += buf_sz; } - mutex_exit(list_lock); + multilist_sublist_unlock(mls); if (full == B_TRUE) break; @@ -5938,12 +6365,13 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, /* No buffers selected for writing? */ if (pio == NULL) { ASSERT0(write_sz); - mutex_exit(&dev->l2ad_mtx); ASSERT(!HDR_HAS_L1HDR(head)); kmem_cache_free(hdr_l2only_cache, head); return (0); } + mutex_enter(&dev->l2ad_mtx); + /* * Now start writing the buffers. We're starting at the write head * and work backwards, retracing the course of the buffer selector @@ -5954,6 +6382,14 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, uint64_t buf_sz; /* + * We rely on the L1 portion of the header below, so + * it's invalid for this header to have been evicted out + * of the ghost cache, prior to being written out. The + * ARC_FLAG_L2_WRITING bit ensures this won't happen. + */ + ASSERT(HDR_HAS_L1HDR(hdr)); + + /* * We shouldn't need to lock the buffer here, since we flagged * it as ARC_FLAG_L2_WRITING in the previous step, but we must * take care to only access its L2 cache parameters. In @@ -5981,14 +6417,6 @@ l2arc_write_buffers(spa_t *spa, l2arc_dev_t *dev, uint64_t target_sz, buf_sz = hdr->b_l2hdr.b_asize; /* - * If the data has not been compressed, then clear b_tmp_cdata - * to make sure that it points only to a temporary compression - * buffer. - */ - if (!L2ARC_IS_VALID_COMPRESS(HDR_GET_COMPRESS(hdr))) - hdr->b_l1hdr.b_tmp_cdata = NULL; - - /* * We need to do this regardless if buf_sz is zero or * not, otherwise, when this l2hdr is evicted we'll * remove a reference that was never added. @@ -6081,6 +6509,12 @@ l2arc_compress_buf(arc_buf_hdr_t *hdr) csize = zio_compress_data(ZIO_COMPRESS_LZ4, hdr->b_l1hdr.b_tmp_cdata, cdata, l2hdr->b_asize); + rounded = P2ROUNDUP(csize, (size_t)SPA_MINBLOCKSIZE); + if (rounded > csize) { + bzero((char *)cdata + csize, rounded - csize); + csize = rounded; + } + if (csize == 0) { /* zero block, indicate that there's nothing to write */ zio_data_buf_free(cdata, len); @@ -6089,19 +6523,11 @@ l2arc_compress_buf(arc_buf_hdr_t *hdr) hdr->b_l1hdr.b_tmp_cdata = NULL; ARCSTAT_BUMP(arcstat_l2_compress_zeros); return (B_TRUE); - } - - rounded = P2ROUNDUP(csize, - (size_t)1 << l2hdr->b_dev->l2ad_vdev->vdev_ashift); - if (rounded < len) { + } else if (csize > 0 && csize < len) { /* * Compression succeeded, we'll keep the cdata around for * writing and release it afterwards. */ - if (rounded > csize) { - bzero((char *)cdata + csize, rounded - csize); - csize = rounded; - } HDR_SET_COMPRESS(hdr, ZIO_COMPRESS_LZ4); l2hdr->b_asize = csize; hdr->b_l1hdr.b_tmp_cdata = cdata; @@ -6189,8 +6615,26 @@ l2arc_decompress_zio(zio_t *zio, arc_buf_hdr_t *hdr, enum zio_compress c) static void l2arc_release_cdata_buf(arc_buf_hdr_t *hdr) { + enum zio_compress comp = HDR_GET_COMPRESS(hdr); + ASSERT(HDR_HAS_L1HDR(hdr)); - if (HDR_GET_COMPRESS(hdr) != ZIO_COMPRESS_EMPTY) { + ASSERT(comp == ZIO_COMPRESS_OFF || L2ARC_IS_VALID_COMPRESS(comp)); + + if (comp == ZIO_COMPRESS_OFF) { + /* + * In this case, b_tmp_cdata points to the same buffer + * as the arc_buf_t's b_data field. We don't want to + * free it, since the arc_buf_t will handle that. + */ + hdr->b_l1hdr.b_tmp_cdata = NULL; + } else if (comp == ZIO_COMPRESS_EMPTY) { + /* + * In this case, b_tmp_cdata was compressed to an empty + * buffer, thus there's nothing to free and b_tmp_cdata + * should have been set to NULL in l2arc_write_buffers(). + */ + ASSERT3P(hdr->b_l1hdr.b_tmp_cdata, ==, NULL); + } else { /* * If the data was compressed, then we've allocated a * temporary buffer for it, so now we need to release it. @@ -6199,9 +6643,8 @@ l2arc_release_cdata_buf(arc_buf_hdr_t *hdr) zio_data_buf_free(hdr->b_l1hdr.b_tmp_cdata, hdr->b_size); hdr->b_l1hdr.b_tmp_cdata = NULL; - } else { - ASSERT(hdr->b_l1hdr.b_tmp_cdata == NULL); } + } /* diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c index 5f7d76f..b2b9887 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c @@ -154,7 +154,7 @@ bptree_visit_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, int err; struct bptree_args *ba = arg; - if (BP_IS_HOLE(bp)) + if (bp == NULL || BP_IS_HOLE(bp)) return (0); err = ba->ba_func(ba->ba_arg, bp, ba->ba_tx); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/bqueue.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/bqueue.c new file mode 100644 index 0000000..1ddc697 --- /dev/null +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/bqueue.c @@ -0,0 +1,111 @@ +/* + * CDDL HEADER START + * + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + * + * CDDL HEADER END + */ +/* + * Copyright (c) 2014 by Delphix. All rights reserved. + */ + +#include <sys/bqueue.h> +#include <sys/zfs_context.h> + +static inline bqueue_node_t * +obj2node(bqueue_t *q, void *data) +{ + return ((bqueue_node_t *)((char *)data + q->bq_node_offset)); +} + +/* + * Initialize a blocking queue The maximum capacity of the queue is set to + * size. Types that want to be stored in a bqueue must contain a bqueue_node_t, + * and offset should give its offset from the start of the struct. Return 0 on + * success, or -1 on failure. + */ +int +bqueue_init(bqueue_t *q, uint64_t size, size_t node_offset) +{ + list_create(&q->bq_list, node_offset + sizeof (bqueue_node_t), + node_offset + offsetof(bqueue_node_t, bqn_node)); + cv_init(&q->bq_add_cv, NULL, CV_DEFAULT, NULL); + cv_init(&q->bq_pop_cv, NULL, CV_DEFAULT, NULL); + mutex_init(&q->bq_lock, NULL, MUTEX_DEFAULT, NULL); + q->bq_node_offset = node_offset; + q->bq_size = 0; + q->bq_maxsize = size; + return (0); +} + +/* + * Destroy a blocking queue. This function asserts that there are no + * elements in the queue, and no one is blocked on the condition + * variables. + */ +void +bqueue_destroy(bqueue_t *q) +{ + ASSERT0(q->bq_size); + cv_destroy(&q->bq_add_cv); + cv_destroy(&q->bq_pop_cv); + mutex_destroy(&q->bq_lock); + list_destroy(&q->bq_list); +} + +/* + * Add data to q, consuming size units of capacity. If there is insufficient + * capacity to consume size units, block until capacity exists. Asserts size is + * > 0. + */ +void +bqueue_enqueue(bqueue_t *q, void *data, uint64_t item_size) +{ + ASSERT3U(item_size, >, 0); + ASSERT3U(item_size, <, q->bq_maxsize); + mutex_enter(&q->bq_lock); + obj2node(q, data)->bqn_size = item_size; + while (q->bq_size + item_size > q->bq_maxsize) { + cv_wait(&q->bq_add_cv, &q->bq_lock); + } + q->bq_size += item_size; + list_insert_tail(&q->bq_list, data); + cv_signal(&q->bq_pop_cv); + mutex_exit(&q->bq_lock); +} +/* + * Take the first element off of q. If there are no elements on the queue, wait + * until one is put there. Return the removed element. + */ +void * +bqueue_dequeue(bqueue_t *q) +{ + void *ret; + uint64_t item_size; + mutex_enter(&q->bq_lock); + while (q->bq_size == 0) { + cv_wait(&q->bq_pop_cv, &q->bq_lock); + } + ret = list_remove_head(&q->bq_list); + item_size = obj2node(q, ret)->bqn_size; + q->bq_size -= item_size; + mutex_exit(&q->bq_lock); + cv_signal(&q->bq_add_cv); + return (ret); +} + +/* + * Returns true if the space used is 0. + */ +boolean_t +bqueue_empty(bqueue_t *q) +{ + return (q->bq_size == 0); +} diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c index 79b6aed..16d8a2e 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c @@ -548,11 +548,35 @@ dbuf_loan_arcbuf(dmu_buf_impl_t *db) return (abuf); } +/* + * Calculate which level n block references the data at the level 0 offset + * provided. + */ uint64_t -dbuf_whichblock(dnode_t *dn, uint64_t offset) +dbuf_whichblock(dnode_t *dn, int64_t level, uint64_t offset) { - if (dn->dn_datablkshift) { - return (offset >> dn->dn_datablkshift); + if (dn->dn_datablkshift != 0 && dn->dn_indblkshift != 0) { + /* + * The level n blkid is equal to the level 0 blkid divided by + * the number of level 0s in a level n block. + * + * The level 0 blkid is offset >> datablkshift = + * offset / 2^datablkshift. + * + * The number of level 0s in a level n is the number of block + * pointers in an indirect block, raised to the power of level. + * This is 2^(indblkshift - SPA_BLKPTRSHIFT)^level = + * 2^(level*(indblkshift - SPA_BLKPTRSHIFT)). + * + * Thus, the level n blkid is: offset / + * ((2^datablkshift)*(2^(level*(indblkshift - SPA_BLKPTRSHIFT))) + * = offset / 2^(datablkshift + level * + * (indblkshift - SPA_BLKPTRSHIFT)) + * = offset >> (datablkshift + level * + * (indblkshift - SPA_BLKPTRSHIFT)) + */ + return (offset >> (dn->dn_datablkshift + level * + (dn->dn_indblkshift - SPA_BLKPTRSHIFT))); } else { ASSERT3U(offset, <, dn->dn_datablksz); return (0); @@ -1549,6 +1573,11 @@ dmu_buf_write_embedded(dmu_buf_t *dbuf, void *data, struct dirty_leaf *dl; dmu_object_type_t type; + if (etype == BP_EMBEDDED_TYPE_DATA) { + ASSERT(spa_feature_is_active(dmu_objset_spa(db->db_objset), + SPA_FEATURE_EMBEDDED_DATA)); + } + DB_DNODE_ENTER(db); type = DB_DNODE(db)->dn_type; DB_DNODE_EXIT(db); @@ -1715,6 +1744,12 @@ dbuf_clear(dmu_buf_impl_t *db) dbuf_rele(parent, db); } +/* + * Note: While bpp will always be updated if the function returns success, + * parentp will not be updated if the dnode does not have dn_dbuf filled in; + * this happens when the dnode is the meta-dnode, or a userused or groupused + * object. + */ static int dbuf_findbp(dnode_t *dn, int level, uint64_t blkid, int fail_sparse, dmu_buf_impl_t **parentp, blkptr_t **bpp) @@ -1755,7 +1790,7 @@ dbuf_findbp(dnode_t *dn, int level, uint64_t blkid, int fail_sparse, } else if (level < nlevels-1) { /* this block is referenced from an indirect block */ int err = dbuf_hold_impl(dn, level+1, - blkid >> epbs, fail_sparse, NULL, parentp); + blkid >> epbs, fail_sparse, FALSE, NULL, parentp); if (err) return (err); err = dbuf_read(*parentp, NULL, @@ -1930,11 +1965,96 @@ dbuf_destroy(dmu_buf_impl_t *db) arc_space_return(sizeof (dmu_buf_impl_t), ARC_SPACE_OTHER); } +typedef struct dbuf_prefetch_arg { + spa_t *dpa_spa; /* The spa to issue the prefetch in. */ + zbookmark_phys_t dpa_zb; /* The target block to prefetch. */ + int dpa_epbs; /* Entries (blkptr_t's) Per Block Shift. */ + int dpa_curlevel; /* The current level that we're reading */ + zio_priority_t dpa_prio; /* The priority I/Os should be issued at. */ + zio_t *dpa_zio; /* The parent zio_t for all prefetches. */ + arc_flags_t dpa_aflags; /* Flags to pass to the final prefetch. */ +} dbuf_prefetch_arg_t; + +/* + * Actually issue the prefetch read for the block given. + */ +static void +dbuf_issue_final_prefetch(dbuf_prefetch_arg_t *dpa, blkptr_t *bp) +{ + if (BP_IS_HOLE(bp) || BP_IS_EMBEDDED(bp)) + return; + + arc_flags_t aflags = + dpa->dpa_aflags | ARC_FLAG_NOWAIT | ARC_FLAG_PREFETCH; + + ASSERT3U(dpa->dpa_curlevel, ==, BP_GET_LEVEL(bp)); + ASSERT3U(dpa->dpa_curlevel, ==, dpa->dpa_zb.zb_level); + ASSERT(dpa->dpa_zio != NULL); + (void) arc_read(dpa->dpa_zio, dpa->dpa_spa, bp, NULL, NULL, + dpa->dpa_prio, ZIO_FLAG_CANFAIL | ZIO_FLAG_SPECULATIVE, + &aflags, &dpa->dpa_zb); +} + +/* + * Called when an indirect block above our prefetch target is read in. This + * will either read in the next indirect block down the tree or issue the actual + * prefetch if the next block down is our target. + */ +static void +dbuf_prefetch_indirect_done(zio_t *zio, arc_buf_t *abuf, void *private) +{ + dbuf_prefetch_arg_t *dpa = private; + + ASSERT3S(dpa->dpa_zb.zb_level, <, dpa->dpa_curlevel); + ASSERT3S(dpa->dpa_curlevel, >, 0); + if (zio != NULL) { + ASSERT3S(BP_GET_LEVEL(zio->io_bp), ==, dpa->dpa_curlevel); + ASSERT3U(BP_GET_LSIZE(zio->io_bp), ==, zio->io_size); + ASSERT3P(zio->io_spa, ==, dpa->dpa_spa); + } + + dpa->dpa_curlevel--; + + uint64_t nextblkid = dpa->dpa_zb.zb_blkid >> + (dpa->dpa_epbs * (dpa->dpa_curlevel - dpa->dpa_zb.zb_level)); + blkptr_t *bp = ((blkptr_t *)abuf->b_data) + + P2PHASE(nextblkid, 1ULL << dpa->dpa_epbs); + if (BP_IS_HOLE(bp) || (zio != NULL && zio->io_error != 0)) { + kmem_free(dpa, sizeof (*dpa)); + } else if (dpa->dpa_curlevel == dpa->dpa_zb.zb_level) { + ASSERT3U(nextblkid, ==, dpa->dpa_zb.zb_blkid); + dbuf_issue_final_prefetch(dpa, bp); + kmem_free(dpa, sizeof (*dpa)); + } else { + arc_flags_t iter_aflags = ARC_FLAG_NOWAIT; + zbookmark_phys_t zb; + + ASSERT3U(dpa->dpa_curlevel, ==, BP_GET_LEVEL(bp)); + + SET_BOOKMARK(&zb, dpa->dpa_zb.zb_objset, + dpa->dpa_zb.zb_object, dpa->dpa_curlevel, nextblkid); + + (void) arc_read(dpa->dpa_zio, dpa->dpa_spa, + bp, dbuf_prefetch_indirect_done, dpa, dpa->dpa_prio, + ZIO_FLAG_CANFAIL | ZIO_FLAG_SPECULATIVE, + &iter_aflags, &zb); + } + (void) arc_buf_remove_ref(abuf, private); +} + +/* + * Issue prefetch reads for the given block on the given level. If the indirect + * blocks above that block are not in memory, we will read them in + * asynchronously. As a result, this call never blocks waiting for a read to + * complete. + */ void -dbuf_prefetch(dnode_t *dn, uint64_t blkid, zio_priority_t prio) +dbuf_prefetch(dnode_t *dn, int64_t level, uint64_t blkid, zio_priority_t prio, + arc_flags_t aflags) { - dmu_buf_impl_t *db = NULL; - blkptr_t *bp = NULL; + blkptr_t bp; + int epbs, nlevels, curlevel; + uint64_t curblkid; ASSERT(blkid != DMU_BONUS_BLKID); ASSERT(RW_LOCK_HELD(&dn->dn_struct_rwlock)); @@ -1942,35 +2062,104 @@ dbuf_prefetch(dnode_t *dn, uint64_t blkid, zio_priority_t prio) if (dnode_block_freed(dn, blkid)) return; - /* dbuf_find() returns with db_mtx held */ - if (db = dbuf_find(dn->dn_objset, dn->dn_object, 0, blkid)) { + /* + * This dnode hasn't been written to disk yet, so there's nothing to + * prefetch. + */ + nlevels = dn->dn_phys->dn_nlevels; + if (level >= nlevels || dn->dn_phys->dn_nblkptr == 0) + return; + + epbs = dn->dn_phys->dn_indblkshift - SPA_BLKPTRSHIFT; + if (dn->dn_phys->dn_maxblkid < blkid << (epbs * level)) + return; + + dmu_buf_impl_t *db = dbuf_find(dn->dn_objset, dn->dn_object, + level, blkid); + if (db != NULL) { + mutex_exit(&db->db_mtx); /* - * This dbuf is already in the cache. We assume that - * it is already CACHED, or else about to be either - * read or filled. + * This dbuf already exists. It is either CACHED, or + * (we assume) about to be read or filled. */ - mutex_exit(&db->db_mtx); return; } - if (dbuf_findbp(dn, 0, blkid, TRUE, &db, &bp) == 0) { - if (bp && !BP_IS_HOLE(bp) && !BP_IS_EMBEDDED(bp)) { - dsl_dataset_t *ds = dn->dn_objset->os_dsl_dataset; - arc_flags_t aflags = - ARC_FLAG_NOWAIT | ARC_FLAG_PREFETCH; - zbookmark_phys_t zb; + /* + * Find the closest ancestor (indirect block) of the target block + * that is present in the cache. In this indirect block, we will + * find the bp that is at curlevel, curblkid. + */ + curlevel = level; + curblkid = blkid; + while (curlevel < nlevels - 1) { + int parent_level = curlevel + 1; + uint64_t parent_blkid = curblkid >> epbs; + dmu_buf_impl_t *db; + + if (dbuf_hold_impl(dn, parent_level, parent_blkid, + FALSE, TRUE, FTAG, &db) == 0) { + blkptr_t *bpp = db->db_buf->b_data; + bp = bpp[P2PHASE(curblkid, 1 << epbs)]; + dbuf_rele(db, FTAG); + break; + } - SET_BOOKMARK(&zb, ds ? ds->ds_object : DMU_META_OBJSET, - dn->dn_object, 0, blkid); + curlevel = parent_level; + curblkid = parent_blkid; + } - (void) arc_read(NULL, dn->dn_objset->os_spa, - bp, NULL, NULL, prio, - ZIO_FLAG_CANFAIL | ZIO_FLAG_SPECULATIVE, - &aflags, &zb); - } - if (db) - dbuf_rele(db, NULL); + if (curlevel == nlevels - 1) { + /* No cached indirect blocks found. */ + ASSERT3U(curblkid, <, dn->dn_phys->dn_nblkptr); + bp = dn->dn_phys->dn_blkptr[curblkid]; + } + if (BP_IS_HOLE(&bp)) + return; + + ASSERT3U(curlevel, ==, BP_GET_LEVEL(&bp)); + + zio_t *pio = zio_root(dmu_objset_spa(dn->dn_objset), NULL, NULL, + ZIO_FLAG_CANFAIL); + + dbuf_prefetch_arg_t *dpa = kmem_zalloc(sizeof (*dpa), KM_SLEEP); + dsl_dataset_t *ds = dn->dn_objset->os_dsl_dataset; + SET_BOOKMARK(&dpa->dpa_zb, ds != NULL ? ds->ds_object : DMU_META_OBJSET, + dn->dn_object, level, blkid); + dpa->dpa_curlevel = curlevel; + dpa->dpa_prio = prio; + dpa->dpa_aflags = aflags; + dpa->dpa_spa = dn->dn_objset->os_spa; + dpa->dpa_epbs = epbs; + dpa->dpa_zio = pio; + + /* + * If we have the indirect just above us, no need to do the asynchronous + * prefetch chain; we'll just run the last step ourselves. If we're at + * a higher level, though, we want to issue the prefetches for all the + * indirect blocks asynchronously, so we can go on with whatever we were + * doing. + */ + if (curlevel == level) { + ASSERT3U(curblkid, ==, blkid); + dbuf_issue_final_prefetch(dpa, &bp); + kmem_free(dpa, sizeof (*dpa)); + } else { + arc_flags_t iter_aflags = ARC_FLAG_NOWAIT; + zbookmark_phys_t zb; + + SET_BOOKMARK(&zb, ds != NULL ? ds->ds_object : DMU_META_OBJSET, + dn->dn_object, curlevel, curblkid); + (void) arc_read(dpa->dpa_zio, dpa->dpa_spa, + &bp, dbuf_prefetch_indirect_done, dpa, prio, + ZIO_FLAG_CANFAIL | ZIO_FLAG_SPECULATIVE, + &iter_aflags, &zb); } + /* + * We use pio here instead of dpa_zio since it's possible that + * dpa may have already been freed. + */ + zio_nowait(pio); } /* @@ -1978,7 +2167,8 @@ dbuf_prefetch(dnode_t *dn, uint64_t blkid, zio_priority_t prio) * Note: dn_struct_rwlock must be held. */ int -dbuf_hold_impl(dnode_t *dn, uint8_t level, uint64_t blkid, int fail_sparse, +dbuf_hold_impl(dnode_t *dn, uint8_t level, uint64_t blkid, + boolean_t fail_sparse, boolean_t fail_uncached, void *tag, dmu_buf_impl_t **dbp) { dmu_buf_impl_t *db, *parent = NULL; @@ -1996,6 +2186,9 @@ top: blkptr_t *bp = NULL; int err; + if (fail_uncached) + return (SET_ERROR(ENOENT)); + ASSERT3P(parent, ==, NULL); err = dbuf_findbp(dn, level, blkid, fail_sparse, &parent, &bp); if (fail_sparse) { @@ -2012,6 +2205,11 @@ top: db = dbuf_create(dn, level, blkid, parent, bp); } + if (fail_uncached && db->db_state != DB_CACHED) { + mutex_exit(&db->db_mtx); + return (SET_ERROR(ENOENT)); + } + if (db->db_buf && refcount_is_zero(&db->db_holds)) { arc_buf_add_ref(db->db_buf, db); if (db->db_buf->b_data == NULL) { @@ -2067,16 +2265,14 @@ top: dmu_buf_impl_t * dbuf_hold(dnode_t *dn, uint64_t blkid, void *tag) { - dmu_buf_impl_t *db; - int err = dbuf_hold_impl(dn, 0, blkid, FALSE, tag, &db); - return (err ? NULL : db); + return (dbuf_hold_level(dn, 0, blkid, tag)); } dmu_buf_impl_t * dbuf_hold_level(dnode_t *dn, int level, uint64_t blkid, void *tag) { dmu_buf_impl_t *db; - int err = dbuf_hold_impl(dn, level, blkid, FALSE, tag, &db); + int err = dbuf_hold_impl(dn, level, blkid, FALSE, FALSE, tag, &db); return (err ? NULL : db); } @@ -2429,8 +2625,8 @@ dbuf_check_blkptr(dnode_t *dn, dmu_buf_impl_t *db) if (parent == NULL) { mutex_exit(&db->db_mtx); rw_enter(&dn->dn_struct_rwlock, RW_READER); - (void) dbuf_hold_impl(dn, db->db_level+1, - db->db_blkid >> epbs, FALSE, db, &parent); + parent = dbuf_hold_level(dn, db->db_level + 1, + db->db_blkid >> epbs, db); rw_exit(&dn->dn_struct_rwlock); mutex_enter(&db->db_mtx); db->db_parent = parent; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c index f45071b..91cd511 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c @@ -141,7 +141,7 @@ dmu_buf_hold_noread(objset_t *os, uint64_t object, uint64_t offset, err = dnode_hold(os, object, FTAG, &dn); if (err) return (err); - blkid = dbuf_whichblock(dn, offset); + blkid = dbuf_whichblock(dn, 0, offset); rw_enter(&dn->dn_struct_rwlock, RW_READER); db = dbuf_hold(dn, blkid, tag); rw_exit(&dn->dn_struct_rwlock); @@ -424,7 +424,7 @@ dmu_buf_hold_array_by_dnode(dnode_t *dn, uint64_t offset, uint64_t length, dbp = kmem_zalloc(sizeof (dmu_buf_t *) * nblks, KM_SLEEP); zio = zio_root(dn->dn_objset->os_spa, NULL, NULL, ZIO_FLAG_CANFAIL); - blkid = dbuf_whichblock(dn, offset); + blkid = dbuf_whichblock(dn, 0, offset); for (i = 0; i < nblks; i++) { dmu_buf_impl_t *db = dbuf_hold(dn, blkid+i, tag); if (db == NULL) { @@ -528,17 +528,16 @@ dmu_buf_rele_array(dmu_buf_t **dbp_fake, int numbufs, void *tag) } /* - * Issue prefetch i/os for the given blocks. + * Issue prefetch i/os for the given blocks. If level is greater than 0, the + * indirect blocks prefeteched will be those that point to the blocks containing + * the data starting at offset, and continuing to offset + len. * - * Note: The assumption is that we *know* these blocks will be needed - * almost immediately. Therefore, the prefetch i/os will be issued at - * ZIO_PRIORITY_SYNC_READ - * - * Note: indirect blocks and other metadata will be read synchronously, - * causing this function to block if they are not already cached. + * Note that if the indirect blocks above the blocks being prefetched are not in + * cache, they will be asychronously read in. */ void -dmu_prefetch(objset_t *os, uint64_t object, uint64_t offset, uint64_t len) +dmu_prefetch(objset_t *os, uint64_t object, int64_t level, uint64_t offset, + uint64_t len, zio_priority_t pri) { dnode_t *dn; uint64_t blkid; @@ -554,8 +553,9 @@ dmu_prefetch(objset_t *os, uint64_t object, uint64_t offset, uint64_t len) return; rw_enter(&dn->dn_struct_rwlock, RW_READER); - blkid = dbuf_whichblock(dn, object * sizeof (dnode_phys_t)); - dbuf_prefetch(dn, blkid, ZIO_PRIORITY_SYNC_READ); + blkid = dbuf_whichblock(dn, level, + object * sizeof (dnode_phys_t)); + dbuf_prefetch(dn, level, blkid, pri, 0); rw_exit(&dn->dn_struct_rwlock); return; } @@ -570,18 +570,24 @@ dmu_prefetch(objset_t *os, uint64_t object, uint64_t offset, uint64_t len) return; rw_enter(&dn->dn_struct_rwlock, RW_READER); - if (dn->dn_datablkshift) { - int blkshift = dn->dn_datablkshift; - nblks = (P2ROUNDUP(offset + len, 1 << blkshift) - - P2ALIGN(offset, 1 << blkshift)) >> blkshift; + /* + * offset + len - 1 is the last byte we want to prefetch for, and offset + * is the first. Then dbuf_whichblk(dn, level, off + len - 1) is the + * last block we want to prefetch, and dbuf_whichblock(dn, level, + * offset) is the first. Then the number we need to prefetch is the + * last - first + 1. + */ + if (level > 0 || dn->dn_datablkshift != 0) { + nblks = dbuf_whichblock(dn, level, offset + len - 1) - + dbuf_whichblock(dn, level, offset) + 1; } else { nblks = (offset < dn->dn_datablksz); } if (nblks != 0) { - blkid = dbuf_whichblock(dn, offset); + blkid = dbuf_whichblock(dn, level, offset); for (int i = 0; i < nblks; i++) - dbuf_prefetch(dn, blkid + i, ZIO_PRIORITY_SYNC_READ); + dbuf_prefetch(dn, level, blkid + i, pri, 0); } rw_exit(&dn->dn_struct_rwlock); @@ -1393,7 +1399,7 @@ dmu_assign_arcbuf(dmu_buf_t *handle, uint64_t offset, arc_buf_t *buf, DB_DNODE_ENTER(dbuf); dn = DB_DNODE(dbuf); rw_enter(&dn->dn_struct_rwlock, RW_READER); - blkid = dbuf_whichblock(dn, offset); + blkid = dbuf_whichblock(dn, 0, offset); VERIFY((db = dbuf_hold(dn, blkid, FTAG)) != NULL); rw_exit(&dn->dn_struct_rwlock); DB_DNODE_EXIT(dbuf); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_diff.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_diff.c index bd9e894..e88968b 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_diff.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_diff.c @@ -138,7 +138,7 @@ diff_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, if (issig(JUSTLOOKING) && issig(FORREAL)) return (SET_ERROR(EINTR)); - if (zb->zb_object != DMU_META_DNODE_OBJECT) + if (bp == NULL || zb->zb_object != DMU_META_DNODE_OBJECT) return (0); if (BP_IS_HOLE(bp)) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_object.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_object.c index 808864a..6ca021e 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_object.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_object.c @@ -148,6 +148,11 @@ dmu_object_free(objset_t *os, uint64_t object, dmu_tx_t *tx) return (0); } +/* + * Return (in *objectp) the next object which is allocated (or a hole) + * after *object, taking into account only objects that may have been modified + * after the specified txg. + */ int dmu_object_next(objset_t *os, uint64_t *objectp, boolean_t hole, uint64_t txg) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c index be1f46d..267aa35 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c @@ -21,7 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright 2011 Nexenta Systems, Inc. All rights reserved. - * Copyright (c) 2011, 2014 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2014, Joyent, Inc. All rights reserved. * Copyright (c) 2012, Martin Matuska <mm@FreeBSD.org>. All rights reserved. * Copyright 2014 HybridCluster. All rights reserved. @@ -53,6 +53,7 @@ #include <sys/blkptr.h> #include <sys/dsl_bookmark.h> #include <sys/zfeature.h> +#include <sys/bqueue.h> #ifdef __FreeBSD__ #undef dump_write @@ -61,10 +62,34 @@ /* Set this tunable to TRUE to replace corrupt data with 0x2f5baddb10c */ int zfs_send_corrupt_data = B_FALSE; +int zfs_send_queue_length = 16 * 1024 * 1024; +int zfs_recv_queue_length = 16 * 1024 * 1024; static char *dmu_recv_tag = "dmu_recv_tag"; static const char *recv_clone_name = "%recv"; +#define BP_SPAN(datablkszsec, indblkshift, level) \ + (((uint64_t)datablkszsec) << (SPA_MINBLOCKSHIFT + \ + (level) * (indblkshift - SPA_BLKPTRSHIFT))) + +struct send_thread_arg { + bqueue_t q; + dsl_dataset_t *ds; /* Dataset to traverse */ + uint64_t fromtxg; /* Traverse from this txg */ + int flags; /* flags to pass to traverse_dataset */ + int error_code; + boolean_t cancel; +}; + +struct send_block_record { + boolean_t eos_marker; /* Marks the end of the stream */ + blkptr_t bp; + zbookmark_phys_t zb; + uint8_t indblkshift; + uint16_t datablkszsec; + bqueue_node_t ln; +}; + static int dump_bytes(dmu_sendarg_t *dsp, void *buf, int len) { @@ -455,58 +480,116 @@ backup_do_embed(dmu_sendarg_t *dsp, const blkptr_t *bp) return (B_FALSE); } -#define BP_SPAN(dnp, level) \ - (((uint64_t)dnp->dn_datablkszsec) << (SPA_MINBLOCKSHIFT + \ - (level) * (dnp->dn_indblkshift - SPA_BLKPTRSHIFT))) +/* + * This is the callback function to traverse_dataset that acts as the worker + * thread for dmu_send_impl. + */ +/*ARGSUSED*/ +static int +send_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, + const zbookmark_phys_t *zb, const struct dnode_phys *dnp, void *arg) +{ + struct send_thread_arg *sta = arg; + struct send_block_record *record; + uint64_t record_size; + int err = 0; -/* ARGSUSED */ + if (sta->cancel) + return (SET_ERROR(EINTR)); + + if (bp == NULL) { + ASSERT3U(zb->zb_level, ==, ZB_DNODE_LEVEL); + return (0); + } else if (zb->zb_level < 0) { + return (0); + } + + record = kmem_zalloc(sizeof (struct send_block_record), KM_SLEEP); + record->eos_marker = B_FALSE; + record->bp = *bp; + record->zb = *zb; + record->indblkshift = dnp->dn_indblkshift; + record->datablkszsec = dnp->dn_datablkszsec; + record_size = dnp->dn_datablkszsec << SPA_MINBLOCKSHIFT; + bqueue_enqueue(&sta->q, record, record_size); + + return (err); +} + +/* + * This function kicks off the traverse_dataset. It also handles setting the + * error code of the thread in case something goes wrong, and pushes the End of + * Stream record when the traverse_dataset call has finished. If there is no + * dataset to traverse, the thread immediately pushes End of Stream marker. + */ +static void +send_traverse_thread(void *arg) +{ + struct send_thread_arg *st_arg = arg; + int err; + struct send_block_record *data; + + if (st_arg->ds != NULL) { + err = traverse_dataset(st_arg->ds, st_arg->fromtxg, + st_arg->flags, send_cb, arg); + if (err != EINTR) + st_arg->error_code = err; + } + data = kmem_zalloc(sizeof (*data), KM_SLEEP); + data->eos_marker = B_TRUE; + bqueue_enqueue(&st_arg->q, data, 1); + thread_exit(); +} + +/* + * This function actually handles figuring out what kind of record needs to be + * dumped, reading the data (which has hopefully been prefetched), and calling + * the appropriate helper function. + */ static int -backup_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, - const zbookmark_phys_t *zb, const dnode_phys_t *dnp, void *arg) +do_dump(dmu_sendarg_t *dsa, struct send_block_record *data) { - dmu_sendarg_t *dsp = arg; + dsl_dataset_t *ds = dmu_objset_ds(dsa->dsa_os); + const blkptr_t *bp = &data->bp; + const zbookmark_phys_t *zb = &data->zb; + uint8_t indblkshift = data->indblkshift; + uint16_t dblkszsec = data->datablkszsec; + spa_t *spa = ds->ds_dir->dd_pool->dp_spa; dmu_object_type_t type = bp ? BP_GET_TYPE(bp) : DMU_OT_NONE; int err = 0; - if (issig(JUSTLOOKING) && issig(FORREAL)) - return (SET_ERROR(EINTR)); + ASSERT3U(zb->zb_level, >=, 0); if (zb->zb_object != DMU_META_DNODE_OBJECT && DMU_OBJECT_IS_SPECIAL(zb->zb_object)) { return (0); - } else if (zb->zb_level == ZB_ZIL_LEVEL) { - /* - * If we are sending a non-snapshot (which is allowed on - * read-only pools), it may have a ZIL, which must be ignored. - */ - return (0); } else if (BP_IS_HOLE(bp) && zb->zb_object == DMU_META_DNODE_OBJECT) { - uint64_t span = BP_SPAN(dnp, zb->zb_level); + uint64_t span = BP_SPAN(dblkszsec, indblkshift, zb->zb_level); uint64_t dnobj = (zb->zb_blkid * span) >> DNODE_SHIFT; - err = dump_freeobjects(dsp, dnobj, span >> DNODE_SHIFT); + err = dump_freeobjects(dsa, dnobj, span >> DNODE_SHIFT); } else if (BP_IS_HOLE(bp)) { - uint64_t span = BP_SPAN(dnp, zb->zb_level); - err = dump_free(dsp, zb->zb_object, zb->zb_blkid * span, span); + uint64_t span = BP_SPAN(dblkszsec, indblkshift, zb->zb_level); + uint64_t offset = zb->zb_blkid * span; + err = dump_free(dsa, zb->zb_object, offset, span); } else if (zb->zb_level > 0 || type == DMU_OT_OBJSET) { return (0); } else if (type == DMU_OT_DNODE) { - dnode_phys_t *blk; - int i; int blksz = BP_GET_LSIZE(bp); arc_flags_t aflags = ARC_FLAG_WAIT; arc_buf_t *abuf; + ASSERT0(zb->zb_level); + if (arc_read(NULL, spa, bp, arc_getbuf_func, &abuf, ZIO_PRIORITY_ASYNC_READ, ZIO_FLAG_CANFAIL, &aflags, zb) != 0) return (SET_ERROR(EIO)); - blk = abuf->b_data; - for (i = 0; i < blksz >> DNODE_SHIFT; i++) { - uint64_t dnobj = (zb->zb_blkid << - (DNODE_BLOCK_SHIFT - DNODE_SHIFT)) + i; - err = dump_dnode(dsp, dnobj, blk+i); + dnode_phys_t *blk = abuf->b_data; + uint64_t dnobj = zb->zb_blkid * (blksz >> DNODE_SHIFT); + for (int i = 0; i < blksz >> DNODE_SHIFT; i++) { + err = dump_dnode(dsa, dnobj + i, blk + i); if (err != 0) break; } @@ -521,20 +604,21 @@ backup_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, &aflags, zb) != 0) return (SET_ERROR(EIO)); - err = dump_spill(dsp, zb->zb_object, blksz, abuf->b_data); + err = dump_spill(dsa, zb->zb_object, blksz, abuf->b_data); (void) arc_buf_remove_ref(abuf, &abuf); - } else if (backup_do_embed(dsp, bp)) { + } else if (backup_do_embed(dsa, bp)) { /* it's an embedded level-0 block of a regular object */ - int blksz = dnp->dn_datablkszsec << SPA_MINBLOCKSHIFT; - err = dump_write_embedded(dsp, zb->zb_object, + int blksz = dblkszsec << SPA_MINBLOCKSHIFT; + ASSERT0(zb->zb_level); + err = dump_write_embedded(dsa, zb->zb_object, zb->zb_blkid * blksz, blksz, bp); - } else { /* it's a level-0 block of a regular object */ + } else { + /* it's a level-0 block of a regular object */ arc_flags_t aflags = ARC_FLAG_WAIT; arc_buf_t *abuf; - int blksz = BP_GET_LSIZE(bp); + int blksz = dblkszsec << SPA_MINBLOCKSHIFT; uint64_t offset; - ASSERT3U(blksz, ==, dnp->dn_datablkszsec << SPA_MINBLOCKSHIFT); ASSERT0(zb->zb_level); if (arc_read(NULL, spa, bp, arc_getbuf_func, &abuf, ZIO_PRIORITY_ASYNC_READ, ZIO_FLAG_CANFAIL, @@ -555,20 +639,20 @@ backup_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, offset = zb->zb_blkid * blksz; - if (!(dsp->dsa_featureflags & + if (!(dsa->dsa_featureflags & DMU_BACKUP_FEATURE_LARGE_BLOCKS) && blksz > SPA_OLD_MAXBLOCKSIZE) { char *buf = abuf->b_data; while (blksz > 0 && err == 0) { int n = MIN(blksz, SPA_OLD_MAXBLOCKSIZE); - err = dump_write(dsp, type, zb->zb_object, + err = dump_write(dsa, type, zb->zb_object, offset, n, NULL, buf); offset += n; buf += n; blksz -= n; } } else { - err = dump_write(dsp, type, zb->zb_object, + err = dump_write(dsa, type, zb->zb_object, offset, blksz, bp, abuf->b_data); } (void) arc_buf_remove_ref(abuf, &abuf); @@ -579,11 +663,24 @@ backup_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, } /* - * Releases dp using the specified tag. + * Pop the new data off the queue, and free the old data. + */ +static struct send_block_record * +get_next_record(bqueue_t *bq, struct send_block_record *data) +{ + struct send_block_record *tmp = bqueue_dequeue(bq); + kmem_free(data, sizeof (*data)); + return (tmp); +} + +/* + * Actually do the bulk of the work in a zfs send. + * + * Note: Releases dp using the specified tag. */ static int -dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *ds, - zfs_bookmark_phys_t *fromzb, boolean_t is_clone, boolean_t embedok, +dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *to_ds, + zfs_bookmark_phys_t *ancestor_zb, boolean_t is_clone, boolean_t embedok, #ifdef illumos boolean_t large_block_ok, int outfd, vnode_t *vp, offset_t *off) #else @@ -596,8 +693,9 @@ dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *ds, int err; uint64_t fromtxg = 0; uint64_t featureflags = 0; + struct send_thread_arg to_arg; - err = dmu_objset_from_ds(ds, &os); + err = dmu_objset_from_ds(to_ds, &os); if (err != 0) { dsl_pool_rele(dp, tag); return (err); @@ -623,35 +721,34 @@ dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *ds, } #endif - if (large_block_ok && ds->ds_large_blocks) + if (large_block_ok && to_ds->ds_feature_inuse[SPA_FEATURE_LARGE_BLOCKS]) featureflags |= DMU_BACKUP_FEATURE_LARGE_BLOCKS; if (embedok && spa_feature_is_active(dp->dp_spa, SPA_FEATURE_EMBEDDED_DATA)) { featureflags |= DMU_BACKUP_FEATURE_EMBED_DATA; if (spa_feature_is_active(dp->dp_spa, SPA_FEATURE_LZ4_COMPRESS)) featureflags |= DMU_BACKUP_FEATURE_EMBED_DATA_LZ4; - } else { - embedok = B_FALSE; } DMU_SET_FEATUREFLAGS(drr->drr_u.drr_begin.drr_versioninfo, featureflags); drr->drr_u.drr_begin.drr_creation_time = - dsl_dataset_phys(ds)->ds_creation_time; + dsl_dataset_phys(to_ds)->ds_creation_time; drr->drr_u.drr_begin.drr_type = dmu_objset_type(os); if (is_clone) drr->drr_u.drr_begin.drr_flags |= DRR_FLAG_CLONE; - drr->drr_u.drr_begin.drr_toguid = dsl_dataset_phys(ds)->ds_guid; - if (dsl_dataset_phys(ds)->ds_flags & DS_FLAG_CI_DATASET) + drr->drr_u.drr_begin.drr_toguid = dsl_dataset_phys(to_ds)->ds_guid; + if (dsl_dataset_phys(to_ds)->ds_flags & DS_FLAG_CI_DATASET) drr->drr_u.drr_begin.drr_flags |= DRR_FLAG_CI_DATA; - if (fromzb != NULL) { - drr->drr_u.drr_begin.drr_fromguid = fromzb->zbm_guid; - fromtxg = fromzb->zbm_creation_txg; + if (ancestor_zb != NULL) { + drr->drr_u.drr_begin.drr_fromguid = + ancestor_zb->zbm_guid; + fromtxg = ancestor_zb->zbm_creation_txg; } - dsl_dataset_name(ds, drr->drr_u.drr_begin.drr_toname); - if (!ds->ds_is_snapshot) { + dsl_dataset_name(to_ds, drr->drr_u.drr_begin.drr_toname); + if (!to_ds->ds_is_snapshot) { (void) strlcat(drr->drr_u.drr_begin.drr_toname, "@--head--", sizeof (drr->drr_u.drr_begin.drr_toname)); } @@ -665,16 +762,16 @@ dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *ds, dsp->dsa_fp = fp; dsp->dsa_os = os; dsp->dsa_off = off; - dsp->dsa_toguid = dsl_dataset_phys(ds)->ds_guid; + dsp->dsa_toguid = dsl_dataset_phys(to_ds)->ds_guid; dsp->dsa_pending_op = PENDING_NONE; - dsp->dsa_incremental = (fromzb != NULL); + dsp->dsa_incremental = (ancestor_zb != NULL); dsp->dsa_featureflags = featureflags; - mutex_enter(&ds->ds_sendstream_lock); - list_insert_head(&ds->ds_sendstreams, dsp); - mutex_exit(&ds->ds_sendstream_lock); + mutex_enter(&to_ds->ds_sendstream_lock); + list_insert_head(&to_ds->ds_sendstreams, dsp); + mutex_exit(&to_ds->ds_sendstream_lock); - dsl_dataset_long_hold(ds, FTAG); + dsl_dataset_long_hold(to_ds, FTAG); dsl_pool_rele(dp, tag); if (dump_record(dsp, NULL, 0) != 0) { @@ -682,8 +779,41 @@ dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *ds, goto out; } - err = traverse_dataset(ds, fromtxg, TRAVERSE_PRE | TRAVERSE_PREFETCH, - backup_cb, dsp); + err = bqueue_init(&to_arg.q, zfs_send_queue_length, + offsetof(struct send_block_record, ln)); + to_arg.error_code = 0; + to_arg.cancel = B_FALSE; + to_arg.ds = to_ds; + to_arg.fromtxg = fromtxg; + to_arg.flags = TRAVERSE_PRE | TRAVERSE_PREFETCH; + (void) thread_create(NULL, 0, send_traverse_thread, &to_arg, 0, curproc, + TS_RUN, minclsyspri); + + struct send_block_record *to_data; + to_data = bqueue_dequeue(&to_arg.q); + + while (!to_data->eos_marker && err == 0) { + err = do_dump(dsp, to_data); + to_data = get_next_record(&to_arg.q, to_data); + if (issig(JUSTLOOKING) && issig(FORREAL)) + err = EINTR; + } + + if (err != 0) { + to_arg.cancel = B_TRUE; + while (!to_data->eos_marker) { + to_data = get_next_record(&to_arg.q, to_data); + } + } + kmem_free(to_data, sizeof (*to_data)); + + bqueue_destroy(&to_arg.q); + + if (err == 0 && to_arg.error_code != 0) + err = to_arg.error_code; + + if (err != 0) + goto out; if (dsp->dsa_pending_op != PENDING_NONE) if (dump_record(dsp, NULL, 0) != 0) @@ -700,20 +830,18 @@ dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *ds, drr->drr_u.drr_end.drr_checksum = dsp->dsa_zc; drr->drr_u.drr_end.drr_toguid = dsp->dsa_toguid; - if (dump_record(dsp, NULL, 0) != 0) { + if (dump_record(dsp, NULL, 0) != 0) err = dsp->dsa_err; - goto out; - } out: - mutex_enter(&ds->ds_sendstream_lock); - list_remove(&ds->ds_sendstreams, dsp); - mutex_exit(&ds->ds_sendstream_lock); + mutex_enter(&to_ds->ds_sendstream_lock); + list_remove(&to_ds->ds_sendstreams, dsp); + mutex_exit(&to_ds->ds_sendstream_lock); kmem_free(drr, sizeof (dmu_replay_record_t)); kmem_free(dsp, sizeof (dmu_sendarg_t)); - dsl_dataset_long_rele(ds, FTAG); + dsl_dataset_long_rele(to_ds, FTAG); return (err); } @@ -1144,7 +1272,8 @@ dmu_recv_begin_check(void *arg, dmu_tx_t *tx) * If it's a non-clone incremental, we are missing the * target fs, so fail the recv. */ - if (fromguid != 0 && !(flags & DRR_FLAG_CLONE)) + if (fromguid != 0 && !(flags & DRR_FLAG_CLONE || + drba->drba_origin)) return (SET_ERROR(ENOENT)); /* Open the parent of tofs */ @@ -1250,13 +1379,6 @@ dmu_recv_begin_sync(void *arg, dmu_tx_t *tx) } VERIFY0(dsl_dataset_own_obj(dp, dsobj, dmu_recv_tag, &newds)); - if ((DMU_GET_FEATUREFLAGS(drrb->drr_versioninfo) & - DMU_BACKUP_FEATURE_LARGE_BLOCKS) && - !newds->ds_large_blocks) { - dsl_dataset_activate_large_blocks_sync_impl(dsobj, tx); - newds->ds_large_blocks = B_TRUE; - } - dmu_buf_will_dirty(newds->ds_dbuf, tx); dsl_dataset_phys(newds)->ds_flags |= DS_FLAG_INCONSISTENT; @@ -1326,22 +1448,58 @@ dmu_recv_begin(char *tofs, char *tosnap, struct drr_begin *drrb, &drba, 5, ZFS_SPACE_CHECK_NORMAL)); } -struct restorearg { +struct receive_record_arg { + dmu_replay_record_t header; + void *payload; /* Pointer to a buffer containing the payload */ + /* + * If the record is a write, pointer to the arc_buf_t containing the + * payload. + */ + arc_buf_t *write_buf; + int payload_size; + boolean_t eos_marker; /* Marks the end of the stream */ + bqueue_node_t node; +}; + +struct receive_writer_arg { objset_t *os; - int err; boolean_t byteswap; + bqueue_t q; + /* + * These three args are used to signal to the main thread that we're + * done. + */ + kmutex_t mutex; + kcondvar_t cv; + boolean_t done; + int err; + /* A map from guid to dataset to help handle dedup'd streams. */ + avl_tree_t *guid_to_ds_map; +}; + +struct receive_arg { + objset_t *os; kthread_t *td; struct file *fp; - uint64_t voff; - int bufsize; /* amount of memory allocated for buf */ - - dmu_replay_record_t *drr; - dmu_replay_record_t *next_drr; - char *buf; + uint64_t voff; /* The current offset in the stream */ + /* + * A record that has had its payload read in, but hasn't yet been handed + * off to the worker thread. + */ + struct receive_record_arg *rrd; + /* A record that has had its header read in, but not its payload. */ + struct receive_record_arg *next_rrd; zio_cksum_t cksum; zio_cksum_t prev_cksum; + int err; + boolean_t byteswap; + /* Sorted list of objects not to issue prefetches for. */ + list_t ignore_obj_list; +}; - avl_tree_t *guid_to_ds_map; +struct receive_ign_obj_node { + list_node_t node; + uint64_t object; }; typedef struct guid_map_entry { @@ -1380,7 +1538,7 @@ free_guid_map_onexit(void *arg) } static int -restore_bytes(struct restorearg *ra, void *buf, int len, off_t off, ssize_t *resid) +restore_bytes(struct receive_arg *ra, void *buf, int len, off_t off, ssize_t *resid) { struct uio auio; struct iovec aiov; @@ -1406,13 +1564,12 @@ restore_bytes(struct restorearg *ra, void *buf, int len, off_t off, ssize_t *res } static int -restore_read(struct restorearg *ra, int len, void *buf) +receive_read(struct receive_arg *ra, int len, void *buf) { int done = 0; /* some things will require 8-byte alignment, so everything must */ ASSERT0(len % 8); - ASSERT3U(len, <=, ra->bufsize); while (done < len) { ssize_t resid; @@ -1529,7 +1686,8 @@ deduce_nblkptr(dmu_object_type_t bonus_type, uint64_t bonus_size) } static int -restore_object(struct restorearg *ra, struct drr_object *drro, void *data) +receive_object(struct receive_writer_arg *rwa, struct drr_object *drro, + void *data) { dmu_object_info_t doi; dmu_tx_t *tx; @@ -1543,12 +1701,12 @@ restore_object(struct restorearg *ra, struct drr_object *drro, void *data) drro->drr_compress >= ZIO_COMPRESS_FUNCTIONS || P2PHASE(drro->drr_blksz, SPA_MINBLOCKSIZE) || drro->drr_blksz < SPA_MINBLOCKSIZE || - drro->drr_blksz > spa_maxblocksize(dmu_objset_spa(ra->os)) || + drro->drr_blksz > spa_maxblocksize(dmu_objset_spa(rwa->os)) || drro->drr_bonuslen > DN_MAX_BONUSLEN) { return (SET_ERROR(EINVAL)); } - err = dmu_object_info(ra->os, drro->drr_object, &doi); + err = dmu_object_info(rwa->os, drro->drr_object, &doi); if (err != 0 && err != ENOENT) return (SET_ERROR(EINVAL)); @@ -1567,14 +1725,14 @@ restore_object(struct restorearg *ra, struct drr_object *drro, void *data) if (drro->drr_blksz != doi.doi_data_block_size || nblkptr < doi.doi_nblkptr) { - err = dmu_free_long_range(ra->os, drro->drr_object, + err = dmu_free_long_range(rwa->os, drro->drr_object, 0, DMU_OBJECT_END); if (err != 0) return (SET_ERROR(EINVAL)); } } - tx = dmu_tx_create(ra->os); + tx = dmu_tx_create(rwa->os); dmu_tx_hold_bonus(tx, object); err = dmu_tx_assign(tx, TXG_WAIT); if (err != 0) { @@ -1584,7 +1742,7 @@ restore_object(struct restorearg *ra, struct drr_object *drro, void *data) if (object == DMU_NEW_OBJECT) { /* currently free, want to be allocated */ - err = dmu_object_claim(ra->os, drro->drr_object, + err = dmu_object_claim(rwa->os, drro->drr_object, drro->drr_type, drro->drr_blksz, drro->drr_bonustype, drro->drr_bonuslen, tx); } else if (drro->drr_type != doi.doi_type || @@ -1592,7 +1750,7 @@ restore_object(struct restorearg *ra, struct drr_object *drro, void *data) drro->drr_bonustype != doi.doi_bonus_type || drro->drr_bonuslen != doi.doi_bonus_size) { /* currently allocated, but with different properties */ - err = dmu_object_reclaim(ra->os, drro->drr_object, + err = dmu_object_reclaim(rwa->os, drro->drr_object, drro->drr_type, drro->drr_blksz, drro->drr_bonustype, drro->drr_bonuslen, tx); } @@ -1601,20 +1759,20 @@ restore_object(struct restorearg *ra, struct drr_object *drro, void *data) return (SET_ERROR(EINVAL)); } - dmu_object_set_checksum(ra->os, drro->drr_object, + dmu_object_set_checksum(rwa->os, drro->drr_object, drro->drr_checksumtype, tx); - dmu_object_set_compress(ra->os, drro->drr_object, + dmu_object_set_compress(rwa->os, drro->drr_object, drro->drr_compress, tx); if (data != NULL) { dmu_buf_t *db; - VERIFY0(dmu_bonus_hold(ra->os, drro->drr_object, FTAG, &db)); + VERIFY0(dmu_bonus_hold(rwa->os, drro->drr_object, FTAG, &db)); dmu_buf_will_dirty(db, tx); ASSERT3U(db->db_size, >=, drro->drr_bonuslen); bcopy(data, db->db_data, drro->drr_bonuslen); - if (ra->byteswap) { + if (rwa->byteswap) { dmu_object_byteswap_t byteswap = DMU_OT_BYTESWAP(drro->drr_bonustype); dmu_ot_byteswap[byteswap].ob_func(db->db_data, @@ -1628,7 +1786,7 @@ restore_object(struct restorearg *ra, struct drr_object *drro, void *data) /* ARGSUSED */ static int -restore_freeobjects(struct restorearg *ra, +receive_freeobjects(struct receive_writer_arg *rwa, struct drr_freeobjects *drrfo) { uint64_t obj; @@ -1638,13 +1796,13 @@ restore_freeobjects(struct restorearg *ra, for (obj = drrfo->drr_firstobj; obj < drrfo->drr_firstobj + drrfo->drr_numobjs; - (void) dmu_object_next(ra->os, &obj, FALSE, 0)) { + (void) dmu_object_next(rwa->os, &obj, FALSE, 0)) { int err; - if (dmu_object_info(ra->os, obj, NULL) != 0) + if (dmu_object_info(rwa->os, obj, NULL) != 0) continue; - err = dmu_free_long_object(ra->os, obj); + err = dmu_free_long_object(rwa->os, obj); if (err != 0) return (err); } @@ -1652,7 +1810,8 @@ restore_freeobjects(struct restorearg *ra, } static int -restore_write(struct restorearg *ra, struct drr_write *drrw, arc_buf_t *abuf) +receive_write(struct receive_writer_arg *rwa, struct drr_write *drrw, + arc_buf_t *abuf) { dmu_tx_t *tx; int err; @@ -1661,10 +1820,10 @@ restore_write(struct restorearg *ra, struct drr_write *drrw, arc_buf_t *abuf) !DMU_OT_IS_VALID(drrw->drr_type)) return (SET_ERROR(EINVAL)); - if (dmu_object_info(ra->os, drrw->drr_object, NULL) != 0) + if (dmu_object_info(rwa->os, drrw->drr_object, NULL) != 0) return (SET_ERROR(EINVAL)); - tx = dmu_tx_create(ra->os); + tx = dmu_tx_create(rwa->os); dmu_tx_hold_write(tx, drrw->drr_object, drrw->drr_offset, drrw->drr_length); @@ -1673,7 +1832,7 @@ restore_write(struct restorearg *ra, struct drr_write *drrw, arc_buf_t *abuf) dmu_tx_abort(tx); return (err); } - if (ra->byteswap) { + if (rwa->byteswap) { dmu_object_byteswap_t byteswap = DMU_OT_BYTESWAP(drrw->drr_type); dmu_ot_byteswap[byteswap].ob_func(abuf->b_data, @@ -1681,7 +1840,7 @@ restore_write(struct restorearg *ra, struct drr_write *drrw, arc_buf_t *abuf) } dmu_buf_t *bonus; - if (dmu_bonus_hold(ra->os, drrw->drr_object, FTAG, &bonus) != 0) + if (dmu_bonus_hold(rwa->os, drrw->drr_object, FTAG, &bonus) != 0) return (SET_ERROR(EINVAL)); dmu_assign_arcbuf(bonus, drrw->drr_offset, abuf, tx); dmu_tx_commit(tx); @@ -1697,7 +1856,8 @@ restore_write(struct restorearg *ra, struct drr_write *drrw, arc_buf_t *abuf) * data from the stream to fulfill this write. */ static int -restore_write_byref(struct restorearg *ra, struct drr_write_byref *drrwbr) +receive_write_byref(struct receive_writer_arg *rwa, + struct drr_write_byref *drrwbr) { dmu_tx_t *tx; int err; @@ -1716,14 +1876,14 @@ restore_write_byref(struct restorearg *ra, struct drr_write_byref *drrwbr) */ if (drrwbr->drr_toguid != drrwbr->drr_refguid) { gmesrch.guid = drrwbr->drr_refguid; - if ((gmep = avl_find(ra->guid_to_ds_map, &gmesrch, + if ((gmep = avl_find(rwa->guid_to_ds_map, &gmesrch, &where)) == NULL) { return (SET_ERROR(EINVAL)); } if (dmu_objset_from_ds(gmep->gme_ds, &ref_os)) return (SET_ERROR(EINVAL)); } else { - ref_os = ra->os; + ref_os = rwa->os; } err = dmu_buf_hold(ref_os, drrwbr->drr_refobject, @@ -1731,7 +1891,7 @@ restore_write_byref(struct restorearg *ra, struct drr_write_byref *drrwbr) if (err != 0) return (err); - tx = dmu_tx_create(ra->os); + tx = dmu_tx_create(rwa->os); dmu_tx_hold_write(tx, drrwbr->drr_object, drrwbr->drr_offset, drrwbr->drr_length); @@ -1740,7 +1900,7 @@ restore_write_byref(struct restorearg *ra, struct drr_write_byref *drrwbr) dmu_tx_abort(tx); return (err); } - dmu_write(ra->os, drrwbr->drr_object, + dmu_write(rwa->os, drrwbr->drr_object, drrwbr->drr_offset, drrwbr->drr_length, dbp->db_data, tx); dmu_buf_rele(dbp, FTAG); dmu_tx_commit(tx); @@ -1748,7 +1908,7 @@ restore_write_byref(struct restorearg *ra, struct drr_write_byref *drrwbr) } static int -restore_write_embedded(struct restorearg *ra, +receive_write_embedded(struct receive_writer_arg *rwa, struct drr_write_embedded *drrwnp, void *data) { dmu_tx_t *tx; @@ -1765,7 +1925,7 @@ restore_write_embedded(struct restorearg *ra, if (drrwnp->drr_compression >= ZIO_COMPRESS_FUNCTIONS) return (EINVAL); - tx = dmu_tx_create(ra->os); + tx = dmu_tx_create(rwa->os); dmu_tx_hold_write(tx, drrwnp->drr_object, drrwnp->drr_offset, drrwnp->drr_length); @@ -1775,36 +1935,37 @@ restore_write_embedded(struct restorearg *ra, return (err); } - dmu_write_embedded(ra->os, drrwnp->drr_object, + dmu_write_embedded(rwa->os, drrwnp->drr_object, drrwnp->drr_offset, data, drrwnp->drr_etype, drrwnp->drr_compression, drrwnp->drr_lsize, drrwnp->drr_psize, - ra->byteswap ^ ZFS_HOST_BYTEORDER, tx); + rwa->byteswap ^ ZFS_HOST_BYTEORDER, tx); dmu_tx_commit(tx); return (0); } static int -restore_spill(struct restorearg *ra, struct drr_spill *drrs, void *data) +receive_spill(struct receive_writer_arg *rwa, struct drr_spill *drrs, + void *data) { dmu_tx_t *tx; dmu_buf_t *db, *db_spill; int err; if (drrs->drr_length < SPA_MINBLOCKSIZE || - drrs->drr_length > spa_maxblocksize(dmu_objset_spa(ra->os))) + drrs->drr_length > spa_maxblocksize(dmu_objset_spa(rwa->os))) return (SET_ERROR(EINVAL)); - if (dmu_object_info(ra->os, drrs->drr_object, NULL) != 0) + if (dmu_object_info(rwa->os, drrs->drr_object, NULL) != 0) return (SET_ERROR(EINVAL)); - VERIFY0(dmu_bonus_hold(ra->os, drrs->drr_object, FTAG, &db)); + VERIFY0(dmu_bonus_hold(rwa->os, drrs->drr_object, FTAG, &db)); if ((err = dmu_spill_hold_by_bonus(db, FTAG, &db_spill)) != 0) { dmu_buf_rele(db, FTAG); return (err); } - tx = dmu_tx_create(ra->os); + tx = dmu_tx_create(rwa->os); dmu_tx_hold_spill(tx, db->db_object); @@ -1831,7 +1992,7 @@ restore_spill(struct restorearg *ra, struct drr_spill *drrs, void *data) /* ARGSUSED */ static int -restore_free(struct restorearg *ra, struct drr_free *drrf) +receive_free(struct receive_writer_arg *rwa, struct drr_free *drrf) { int err; @@ -1839,11 +2000,12 @@ restore_free(struct restorearg *ra, struct drr_free *drrf) drrf->drr_offset + drrf->drr_length < drrf->drr_offset) return (SET_ERROR(EINVAL)); - if (dmu_object_info(ra->os, drrf->drr_object, NULL) != 0) + if (dmu_object_info(rwa->os, drrf->drr_object, NULL) != 0) return (SET_ERROR(EINVAL)); - err = dmu_free_long_range(ra->os, drrf->drr_object, + err = dmu_free_long_range(rwa->os, drrf->drr_object, drrf->drr_offset, drrf->drr_length); + return (err); } @@ -1858,7 +2020,7 @@ dmu_recv_cleanup_ds(dmu_recv_cookie_t *drc) } static void -restore_cksum(struct restorearg *ra, int len, void *buf) +receive_cksum(struct receive_arg *ra, int len, void *buf) { if (ra->byteswap) { fletcher_4_incremental_byteswap(buf, len, &ra->cksum); @@ -1868,30 +2030,42 @@ restore_cksum(struct restorearg *ra, int len, void *buf) } /* - * If len != 0, read payload into buf. - * Read next record's header into ra->next_drr. + * Read the payload into a buffer of size len, and update the current record's + * payload field. + * Allocate ra->next_rrd and read the next record's header into + * ra->next_rrd->header. * Verify checksum of payload and next record. */ static int -restore_read_payload_and_next_header(struct restorearg *ra, int len, void *buf) +receive_read_payload_and_next_header(struct receive_arg *ra, int len, void *buf) { int err; if (len != 0) { - ASSERT3U(len, <=, ra->bufsize); - err = restore_read(ra, len, buf); + ASSERT3U(len, <=, SPA_MAXBLOCKSIZE); + ra->rrd->payload = buf; + ra->rrd->payload_size = len; + err = receive_read(ra, len, ra->rrd->payload); if (err != 0) return (err); - restore_cksum(ra, len, buf); + receive_cksum(ra, len, ra->rrd->payload); } ra->prev_cksum = ra->cksum; - err = restore_read(ra, sizeof (*ra->next_drr), ra->next_drr); - if (err != 0) + ra->next_rrd = kmem_zalloc(sizeof (*ra->next_rrd), KM_SLEEP); + err = receive_read(ra, sizeof (ra->next_rrd->header), + &ra->next_rrd->header); + if (err != 0) { + kmem_free(ra->next_rrd, sizeof (*ra->next_rrd)); + ra->next_rrd = NULL; return (err); - if (ra->next_drr->drr_type == DRR_BEGIN) + } + if (ra->next_rrd->header.drr_type == DRR_BEGIN) { + kmem_free(ra->next_rrd, sizeof (*ra->next_rrd)); + ra->next_rrd = NULL; return (SET_ERROR(EINVAL)); + } /* * Note: checksum is of everything up to but not including the @@ -1899,107 +2073,248 @@ restore_read_payload_and_next_header(struct restorearg *ra, int len, void *buf) */ ASSERT3U(offsetof(dmu_replay_record_t, drr_u.drr_checksum.drr_checksum), ==, sizeof (dmu_replay_record_t) - sizeof (zio_cksum_t)); - restore_cksum(ra, + receive_cksum(ra, offsetof(dmu_replay_record_t, drr_u.drr_checksum.drr_checksum), - ra->next_drr); + &ra->next_rrd->header); - zio_cksum_t cksum_orig = ra->next_drr->drr_u.drr_checksum.drr_checksum; - zio_cksum_t *cksump = &ra->next_drr->drr_u.drr_checksum.drr_checksum; + zio_cksum_t cksum_orig = + ra->next_rrd->header.drr_u.drr_checksum.drr_checksum; + zio_cksum_t *cksump = + &ra->next_rrd->header.drr_u.drr_checksum.drr_checksum; if (ra->byteswap) - byteswap_record(ra->next_drr); + byteswap_record(&ra->next_rrd->header); if ((!ZIO_CHECKSUM_IS_ZERO(cksump)) && - !ZIO_CHECKSUM_EQUAL(ra->cksum, *cksump)) + !ZIO_CHECKSUM_EQUAL(ra->cksum, *cksump)) { + kmem_free(ra->next_rrd, sizeof (*ra->next_rrd)); + ra->next_rrd = NULL; return (SET_ERROR(ECKSUM)); + } - restore_cksum(ra, sizeof (cksum_orig), &cksum_orig); + receive_cksum(ra, sizeof (cksum_orig), &cksum_orig); return (0); } +/* + * Issue the prefetch reads for any necessary indirect blocks. + * + * We use the object ignore list to tell us whether or not to issue prefetches + * for a given object. We do this for both correctness (in case the blocksize + * of an object has changed) and performance (if the object doesn't exist, don't + * needlessly try to issue prefetches). We also trim the list as we go through + * the stream to prevent it from growing to an unbounded size. + * + * The object numbers within will always be in sorted order, and any write + * records we see will also be in sorted order, but they're not sorted with + * respect to each other (i.e. we can get several object records before + * receiving each object's write records). As a result, once we've reached a + * given object number, we can safely remove any reference to lower object + * numbers in the ignore list. In practice, we receive up to 32 object records + * before receiving write records, so the list can have up to 32 nodes in it. + */ +/* ARGSUSED */ +static void +receive_read_prefetch(struct receive_arg *ra, + uint64_t object, uint64_t offset, uint64_t length) +{ + struct receive_ign_obj_node *node = list_head(&ra->ignore_obj_list); + while (node != NULL && node->object < object) { + VERIFY3P(node, ==, list_remove_head(&ra->ignore_obj_list)); + kmem_free(node, sizeof (*node)); + node = list_head(&ra->ignore_obj_list); + } + if (node == NULL || node->object > object) { + dmu_prefetch(ra->os, object, 1, offset, length, + ZIO_PRIORITY_SYNC_READ); + } +} + +/* + * Read records off the stream, issuing any necessary prefetches. + */ static int -restore_process_record(struct restorearg *ra) +receive_read_record(struct receive_arg *ra) { int err; - switch (ra->drr->drr_type) { + switch (ra->rrd->header.drr_type) { case DRR_OBJECT: { - struct drr_object *drro = &ra->drr->drr_u.drr_object; - err = restore_read_payload_and_next_header(ra, - P2ROUNDUP(drro->drr_bonuslen, 8), ra->buf); - if (err != 0) + struct drr_object *drro = &ra->rrd->header.drr_u.drr_object; + uint32_t size = P2ROUNDUP(drro->drr_bonuslen, 8); + void *buf = kmem_zalloc(size, KM_SLEEP); + dmu_object_info_t doi; + err = receive_read_payload_and_next_header(ra, size, buf); + if (err != 0) { + kmem_free(buf, size); return (err); - return (restore_object(ra, drro, ra->buf)); + } + err = dmu_object_info(ra->os, drro->drr_object, &doi); + /* + * See receive_read_prefetch for an explanation why we're + * storing this object in the ignore_obj_list. + */ + if (err == ENOENT || + (err == 0 && doi.doi_data_block_size != drro->drr_blksz)) { + struct receive_ign_obj_node *node = + kmem_zalloc(sizeof (*node), + KM_SLEEP); + node->object = drro->drr_object; +#ifdef ZFS_DEBUG + struct receive_ign_obj_node *last_object = + list_tail(&ra->ignore_obj_list); + uint64_t last_objnum = (last_object != NULL ? + last_object->object : 0); + ASSERT3U(node->object, >, last_objnum); +#endif + list_insert_tail(&ra->ignore_obj_list, node); + err = 0; + } + return (err); } case DRR_FREEOBJECTS: { - struct drr_freeobjects *drrfo = - &ra->drr->drr_u.drr_freeobjects; - err = restore_read_payload_and_next_header(ra, 0, NULL); - if (err != 0) - return (err); - return (restore_freeobjects(ra, drrfo)); + err = receive_read_payload_and_next_header(ra, 0, NULL); + return (err); } case DRR_WRITE: { - struct drr_write *drrw = &ra->drr->drr_u.drr_write; + struct drr_write *drrw = &ra->rrd->header.drr_u.drr_write; arc_buf_t *abuf = arc_loan_buf(dmu_objset_spa(ra->os), drrw->drr_length); - err = restore_read_payload_and_next_header(ra, + err = receive_read_payload_and_next_header(ra, drrw->drr_length, abuf->b_data); - if (err != 0) - return (err); - err = restore_write(ra, drrw, abuf); - /* if restore_write() is successful, it consumes the arc_buf */ - if (err != 0) + if (err != 0) { dmu_return_arcbuf(abuf); + return (err); + } + ra->rrd->write_buf = abuf; + receive_read_prefetch(ra, drrw->drr_object, drrw->drr_offset, + drrw->drr_length); return (err); } case DRR_WRITE_BYREF: { - struct drr_write_byref *drrwbr = - &ra->drr->drr_u.drr_write_byref; - err = restore_read_payload_and_next_header(ra, 0, NULL); - if (err != 0) - return (err); - return (restore_write_byref(ra, drrwbr)); + struct drr_write_byref *drrwb = + &ra->rrd->header.drr_u.drr_write_byref; + err = receive_read_payload_and_next_header(ra, 0, NULL); + receive_read_prefetch(ra, drrwb->drr_object, drrwb->drr_offset, + drrwb->drr_length); + return (err); } case DRR_WRITE_EMBEDDED: { struct drr_write_embedded *drrwe = - &ra->drr->drr_u.drr_write_embedded; - err = restore_read_payload_and_next_header(ra, - P2ROUNDUP(drrwe->drr_psize, 8), ra->buf); - if (err != 0) + &ra->rrd->header.drr_u.drr_write_embedded; + uint32_t size = P2ROUNDUP(drrwe->drr_psize, 8); + void *buf = kmem_zalloc(size, KM_SLEEP); + + err = receive_read_payload_and_next_header(ra, size, buf); + if (err != 0) { + kmem_free(buf, size); return (err); - return (restore_write_embedded(ra, drrwe, ra->buf)); + } + + receive_read_prefetch(ra, drrwe->drr_object, drrwe->drr_offset, + drrwe->drr_length); + return (err); } case DRR_FREE: { - struct drr_free *drrf = &ra->drr->drr_u.drr_free; - err = restore_read_payload_and_next_header(ra, 0, NULL); - if (err != 0) - return (err); - return (restore_free(ra, drrf)); + /* + * It might be beneficial to prefetch indirect blocks here, but + * we don't really have the data to decide for sure. + */ + err = receive_read_payload_and_next_header(ra, 0, NULL); + return (err); } case DRR_END: { - struct drr_end *drre = &ra->drr->drr_u.drr_end; + struct drr_end *drre = &ra->rrd->header.drr_u.drr_end; if (!ZIO_CHECKSUM_EQUAL(ra->prev_cksum, drre->drr_checksum)) return (SET_ERROR(EINVAL)); return (0); } case DRR_SPILL: { - struct drr_spill *drrs = &ra->drr->drr_u.drr_spill; - err = restore_read_payload_and_next_header(ra, - drrs->drr_length, ra->buf); + struct drr_spill *drrs = &ra->rrd->header.drr_u.drr_spill; + void *buf = kmem_zalloc(drrs->drr_length, KM_SLEEP); + err = receive_read_payload_and_next_header(ra, drrs->drr_length, + buf); if (err != 0) - return (err); - return (restore_spill(ra, drrs, ra->buf)); + kmem_free(buf, drrs->drr_length); + return (err); + } + default: + return (SET_ERROR(EINVAL)); + } +} + +/* + * Commit the records to the pool. + */ +static int +receive_process_record(struct receive_writer_arg *rwa, + struct receive_record_arg *rrd) +{ + int err; + + switch (rrd->header.drr_type) { + case DRR_OBJECT: + { + struct drr_object *drro = &rrd->header.drr_u.drr_object; + err = receive_object(rwa, drro, rrd->payload); + kmem_free(rrd->payload, rrd->payload_size); + rrd->payload = NULL; + return (err); + } + case DRR_FREEOBJECTS: + { + struct drr_freeobjects *drrfo = + &rrd->header.drr_u.drr_freeobjects; + return (receive_freeobjects(rwa, drrfo)); + } + case DRR_WRITE: + { + struct drr_write *drrw = &rrd->header.drr_u.drr_write; + err = receive_write(rwa, drrw, rrd->write_buf); + /* if receive_write() is successful, it consumes the arc_buf */ + if (err != 0) + dmu_return_arcbuf(rrd->write_buf); + rrd->write_buf = NULL; + rrd->payload = NULL; + return (err); + } + case DRR_WRITE_BYREF: + { + struct drr_write_byref *drrwbr = + &rrd->header.drr_u.drr_write_byref; + return (receive_write_byref(rwa, drrwbr)); + } + case DRR_WRITE_EMBEDDED: + { + struct drr_write_embedded *drrwe = + &rrd->header.drr_u.drr_write_embedded; + err = receive_write_embedded(rwa, drrwe, rrd->payload); + kmem_free(rrd->payload, rrd->payload_size); + rrd->payload = NULL; + return (err); + } + case DRR_FREE: + { + struct drr_free *drrf = &rrd->header.drr_u.drr_free; + return (receive_free(rwa, drrf)); + } + case DRR_SPILL: + { + struct drr_spill *drrs = &rrd->header.drr_u.drr_spill; + err = receive_spill(rwa, drrs, rrd->payload); + kmem_free(rrd->payload, rrd->payload_size); + rrd->payload = NULL; + return (err); } default: return (SET_ERROR(EINVAL)); @@ -2007,6 +2322,51 @@ restore_process_record(struct restorearg *ra) } /* + * dmu_recv_stream's worker thread; pull records off the queue, and then call + * receive_process_record When we're done, signal the main thread and exit. + */ +static void +receive_writer_thread(void *arg) +{ + struct receive_writer_arg *rwa = arg; + struct receive_record_arg *rrd; + for (rrd = bqueue_dequeue(&rwa->q); !rrd->eos_marker; + rrd = bqueue_dequeue(&rwa->q)) { + /* + * If there's an error, the main thread will stop putting things + * on the queue, but we need to clear everything in it before we + * can exit. + */ + if (rwa->err == 0) { + rwa->err = receive_process_record(rwa, rrd); + } else if (rrd->write_buf != NULL) { + dmu_return_arcbuf(rrd->write_buf); + rrd->write_buf = NULL; + rrd->payload = NULL; + } else if (rrd->payload != NULL) { + kmem_free(rrd->payload, rrd->payload_size); + rrd->payload = NULL; + } + kmem_free(rrd, sizeof (*rrd)); + } + kmem_free(rrd, sizeof (*rrd)); + mutex_enter(&rwa->mutex); + rwa->done = B_TRUE; + cv_signal(&rwa->cv); + mutex_exit(&rwa->mutex); + thread_exit(); +} + +/* + * Read in the stream's records, one by one, and apply them to the pool. There + * are two threads involved; the thread that calls this function will spin up a + * worker thread, read the records off the stream one by one, and issue + * prefetches for any necessary indirect blocks. It will then push the records + * onto an internal blocking queue. The worker thread will pull the records off + * the queue, and actually write the data into the DMU. This way, the worker + * thread doesn't have to wait for reads to complete, since everything it needs + * (the indirect blocks) will be prefetched. + * * NB: callers *must* call dmu_recv_end() if this succeeds. */ int @@ -2014,7 +2374,8 @@ dmu_recv_stream(dmu_recv_cookie_t *drc, struct file *fp, offset_t *voffp, int cleanup_fd, uint64_t *action_handlep) { int err = 0; - struct restorearg ra = { 0 }; + struct receive_arg ra = { 0 }; + struct receive_writer_arg rwa = { 0 }; int featureflags; ra.byteswap = drc->drc_byteswap; @@ -2022,10 +2383,8 @@ dmu_recv_stream(dmu_recv_cookie_t *drc, struct file *fp, offset_t *voffp, ra.td = curthread; ra.fp = fp; ra.voff = *voffp; - ra.bufsize = SPA_MAXBLOCKSIZE; - ra.drr = kmem_alloc(sizeof (*ra.drr), KM_SLEEP); - ra.buf = kmem_alloc(ra.bufsize, KM_SLEEP); - ra.next_drr = kmem_alloc(sizeof (*ra.next_drr), KM_SLEEP); + list_create(&ra.ignore_obj_list, sizeof (struct receive_ign_obj_node), + offsetof(struct receive_ign_obj_node, node)); /* these were verified in dmu_recv_begin */ ASSERT3U(DMU_GET_STREAM_HDRTYPE(drc->drc_drrb->drr_versioninfo), ==, @@ -2056,48 +2415,92 @@ dmu_recv_stream(dmu_recv_cookie_t *drc, struct file *fp, offset_t *voffp, } if (*action_handlep == 0) { - ra.guid_to_ds_map = + rwa.guid_to_ds_map = kmem_alloc(sizeof (avl_tree_t), KM_SLEEP); - avl_create(ra.guid_to_ds_map, guid_compare, + avl_create(rwa.guid_to_ds_map, guid_compare, sizeof (guid_map_entry_t), offsetof(guid_map_entry_t, avlnode)); err = zfs_onexit_add_cb(minor, - free_guid_map_onexit, ra.guid_to_ds_map, + free_guid_map_onexit, rwa.guid_to_ds_map, action_handlep); if (ra.err != 0) goto out; } else { err = zfs_onexit_cb_data(minor, *action_handlep, - (void **)&ra.guid_to_ds_map); + (void **)&rwa.guid_to_ds_map); if (ra.err != 0) goto out; } - drc->drc_guid_to_ds_map = ra.guid_to_ds_map; + drc->drc_guid_to_ds_map = rwa.guid_to_ds_map; } - err = restore_read_payload_and_next_header(&ra, 0, NULL); - if (err != 0) + err = receive_read_payload_and_next_header(&ra, 0, NULL); + if (err) goto out; - for (;;) { - void *tmp; + (void) bqueue_init(&rwa.q, zfs_recv_queue_length, + offsetof(struct receive_record_arg, node)); + cv_init(&rwa.cv, NULL, CV_DEFAULT, NULL); + mutex_init(&rwa.mutex, NULL, MUTEX_DEFAULT, NULL); + rwa.os = ra.os; + rwa.byteswap = drc->drc_byteswap; + + (void) thread_create(NULL, 0, receive_writer_thread, &rwa, 0, curproc, + TS_RUN, minclsyspri); + /* + * We're reading rwa.err without locks, which is safe since we are the + * only reader, and the worker thread is the only writer. It's ok if we + * miss a write for an iteration or two of the loop, since the writer + * thread will keep freeing records we send it until we send it an eos + * marker. + * + * We can leave this loop in 3 ways: First, if rwa.err is + * non-zero. In that case, the writer thread will free the rrd we just + * pushed. Second, if we're interrupted; in that case, either it's the + * first loop and ra.rrd was never allocated, or it's later, and ra.rrd + * has been handed off to the writer thread who will free it. Finally, + * if receive_read_record fails or we're at the end of the stream, then + * we free ra.rrd and exit. + */ + while (rwa.err == 0) { if (issig(JUSTLOOKING) && issig(FORREAL)) { err = SET_ERROR(EINTR); break; } - tmp = ra.next_drr; - ra.next_drr = ra.drr; - ra.drr = tmp; + ASSERT3P(ra.rrd, ==, NULL); + ra.rrd = ra.next_rrd; + ra.next_rrd = NULL; + /* Allocates and loads header into ra.next_rrd */ + err = receive_read_record(&ra); - /* process ra.drr, read in ra.next_drr */ - err = restore_process_record(&ra); - if (err != 0) - break; - if (ra.drr->drr_type == DRR_END) + if (ra.rrd->header.drr_type == DRR_END || err != 0) { + kmem_free(ra.rrd, sizeof (*ra.rrd)); + ra.rrd = NULL; break; + } + + bqueue_enqueue(&rwa.q, ra.rrd, + sizeof (struct receive_record_arg) + ra.rrd->payload_size); + ra.rrd = NULL; + } + if (ra.next_rrd == NULL) + ra.next_rrd = kmem_zalloc(sizeof (*ra.next_rrd), KM_SLEEP); + ra.next_rrd->eos_marker = B_TRUE; + bqueue_enqueue(&rwa.q, ra.next_rrd, 1); + + mutex_enter(&rwa.mutex); + while (!rwa.done) { + cv_wait(&rwa.cv, &rwa.mutex); } + mutex_exit(&rwa.mutex); + + cv_destroy(&rwa.cv); + mutex_destroy(&rwa.mutex); + bqueue_destroy(&rwa.q); + if (err == 0) + err = rwa.err; out: if ((featureflags & DMU_BACKUP_FEATURE_DEDUP) && (cleanup_fd != -1)) @@ -2111,10 +2514,13 @@ out: dmu_recv_cleanup_ds(drc); } - kmem_free(ra.drr, sizeof (*ra.drr)); - kmem_free(ra.buf, ra.bufsize); - kmem_free(ra.next_drr, sizeof (*ra.next_drr)); *voffp = ra.voff; + for (struct receive_ign_obj_node *n = + list_remove_head(&ra.ignore_obj_list); n != NULL; + n = list_remove_head(&ra.ignore_obj_list)) { + kmem_free(n, sizeof (*n)); + } + list_destroy(&ra.ignore_obj_list); return (err); } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_traverse.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_traverse.c index e246c49..151d04c 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_traverse.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_traverse.c @@ -158,7 +158,7 @@ resume_skip_check(traverse_data_t *td, const dnode_phys_t *dnp, * If we already visited this bp & everything below, * don't bother doing it again. */ - if (zbookmark_is_before(dnp, zb, td->td_resume)) + if (zbookmark_subtree_completed(dnp, zb, td->td_resume)) return (RESUME_SKIP_ALL); /* @@ -425,6 +425,17 @@ traverse_dnode(traverse_data_t *td, const dnode_phys_t *dnp, int j, err = 0; zbookmark_phys_t czb; + if (td->td_flags & TRAVERSE_PRE) { + SET_BOOKMARK(&czb, objset, object, ZB_DNODE_LEVEL, + ZB_DNODE_BLKID); + err = td->td_func(td->td_spa, NULL, NULL, &czb, dnp, + td->td_arg); + if (err == TRAVERSE_VISIT_NO_CHILDREN) + return (0); + if (err != 0) + return (err); + } + for (j = 0; j < dnp->dn_nblkptr; j++) { SET_BOOKMARK(&czb, objset, object, dnp->dn_nlevels - 1, j); err = traverse_visitbp(td, dnp, &dnp->dn_blkptr[j], &czb); @@ -432,10 +443,21 @@ traverse_dnode(traverse_data_t *td, const dnode_phys_t *dnp, break; } - if (err == 0 && dnp->dn_flags & DNODE_FLAG_SPILL_BLKPTR) { + if (err == 0 && (dnp->dn_flags & DNODE_FLAG_SPILL_BLKPTR)) { SET_BOOKMARK(&czb, objset, object, 0, DMU_SPILL_BLKID); err = traverse_visitbp(td, dnp, &dnp->dn_spill, &czb); } + + if (err == 0 && (td->td_flags & TRAVERSE_POST)) { + SET_BOOKMARK(&czb, objset, object, ZB_DNODE_LEVEL, + ZB_DNODE_BLKID); + err = td->td_func(td->td_spa, NULL, NULL, &czb, dnp, + td->td_arg); + if (err == TRAVERSE_VISIT_NO_CHILDREN) + return (0); + if (err != 0) + return (err); + } return (err); } @@ -448,6 +470,8 @@ traverse_prefetcher(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, arc_flags_t aflags = ARC_FLAG_NOWAIT | ARC_FLAG_PREFETCH; ASSERT(pfd->pd_bytes_fetched >= 0); + if (bp == NULL) + return (0); if (pfd->pd_cancel) return (SET_ERROR(EINTR)); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_tx.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_tx.c index dff9fab..65a017f 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_tx.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_tx.c @@ -315,7 +315,8 @@ dmu_tx_count_write(dmu_tx_hold_t *txh, uint64_t off, uint64_t len) dmu_buf_impl_t *db; rw_enter(&dn->dn_struct_rwlock, RW_READER); - err = dbuf_hold_impl(dn, 0, start, FALSE, FTAG, &db); + err = dbuf_hold_impl(dn, 0, start, + FALSE, FALSE, FTAG, &db); rw_exit(&dn->dn_struct_rwlock); if (err) { @@ -516,7 +517,8 @@ dmu_tx_count_free(dmu_tx_hold_t *txh, uint64_t off, uint64_t len) blkoff = P2PHASE(blkid, epb); tochk = MIN(epb - blkoff, nblks); - err = dbuf_hold_impl(dn, 1, blkid >> epbs, FALSE, FTAG, &dbuf); + err = dbuf_hold_impl(dn, 1, blkid >> epbs, + FALSE, FALSE, FTAG, &dbuf); if (err) { txh->txh_tx->tx_err = err; break; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_zfetch.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_zfetch.c index 77100ef..65ce914 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_zfetch.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_zfetch.c @@ -305,7 +305,8 @@ dmu_zfetch_fetch(dnode_t *dn, uint64_t blkid, uint64_t nblks) fetchsz = dmu_zfetch_fetchsz(dn, blkid, nblks); for (i = 0; i < fetchsz; i++) { - dbuf_prefetch(dn, blkid + i, ZIO_PRIORITY_ASYNC_READ); + dbuf_prefetch(dn, 0, blkid + i, ZIO_PRIORITY_ASYNC_READ, + ARC_FLAG_PREFETCH); } return (fetchsz); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode.c index 5b953fc..0fdcde4 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode.c @@ -1116,7 +1116,7 @@ dnode_hold_impl(objset_t *os, uint64_t object, int flag, drop_struct_lock = TRUE; } - blk = dbuf_whichblock(mdn, object * sizeof (dnode_phys_t)); + blk = dbuf_whichblock(mdn, 0, object * sizeof (dnode_phys_t)); db = dbuf_hold(mdn, blk, FTAG); if (drop_struct_lock) @@ -1413,7 +1413,7 @@ dnode_set_blksz(dnode_t *dn, uint64_t size, int ibs, dmu_tx_t *tx) goto fail; /* resize the old block */ - err = dbuf_hold_impl(dn, 0, 0, TRUE, FTAG, &db); + err = dbuf_hold_impl(dn, 0, 0, TRUE, FALSE, FTAG, &db); if (err == 0) dbuf_new_size(db, size, tx); else if (err != ENOENT) @@ -1586,8 +1586,8 @@ dnode_free_range(dnode_t *dn, uint64_t off, uint64_t len, dmu_tx_t *tx) ASSERT3U(blkoff + head, ==, blksz); if (len < head) head = len; - if (dbuf_hold_impl(dn, 0, dbuf_whichblock(dn, off), TRUE, - FTAG, &db) == 0) { + if (dbuf_hold_impl(dn, 0, dbuf_whichblock(dn, 0, off), + TRUE, FALSE, FTAG, &db) == 0) { caddr_t data; /* don't dirty if it isn't on disk and isn't dirty */ @@ -1624,8 +1624,8 @@ dnode_free_range(dnode_t *dn, uint64_t off, uint64_t len, dmu_tx_t *tx) if (tail) { if (len < tail) tail = len; - if (dbuf_hold_impl(dn, 0, dbuf_whichblock(dn, off+len), - TRUE, FTAG, &db) == 0) { + if (dbuf_hold_impl(dn, 0, dbuf_whichblock(dn, 0, off+len), + TRUE, FALSE, FTAG, &db) == 0) { /* don't dirty if not on disk and not dirty */ if (db->db_last_dirty || (db->db_blkptr && !BP_IS_HOLE(db->db_blkptr))) { @@ -1854,7 +1854,7 @@ dnode_willuse_space(dnode_t *dn, int64_t space, dmu_tx_t *tx) */ static int dnode_next_offset_level(dnode_t *dn, int flags, uint64_t *offset, - int lvl, uint64_t blkfill, uint64_t txg) + int lvl, uint64_t blkfill, uint64_t txg) { dmu_buf_impl_t *db = NULL; void *data = NULL; @@ -1876,8 +1876,8 @@ dnode_next_offset_level(dnode_t *dn, int flags, uint64_t *offset, epb = dn->dn_phys->dn_nblkptr; data = dn->dn_phys->dn_blkptr; } else { - uint64_t blkid = dbuf_whichblock(dn, *offset) >> (epbs * lvl); - error = dbuf_hold_impl(dn, lvl, blkid, TRUE, FTAG, &db); + uint64_t blkid = dbuf_whichblock(dn, lvl, *offset); + error = dbuf_hold_impl(dn, lvl, blkid, TRUE, FALSE, FTAG, &db); if (error) { if (error != ENOENT) return (error); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode_sync.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode_sync.c index 0633604..0787885 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode_sync.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dnode_sync.c @@ -188,7 +188,7 @@ free_verify(dmu_buf_impl_t *db, uint64_t start, uint64_t end, dmu_tx_t *tx) rw_enter(&dn->dn_struct_rwlock, RW_READER); err = dbuf_hold_impl(dn, db->db_level-1, - (db->db_blkid << epbs) + i, TRUE, FTAG, &child); + (db->db_blkid << epbs) + i, TRUE, FALSE, FTAG, &child); rw_exit(&dn->dn_struct_rwlock); if (err == ENOENT) continue; @@ -284,7 +284,7 @@ free_children(dmu_buf_impl_t *db, uint64_t blkid, uint64_t nblks, continue; rw_enter(&dn->dn_struct_rwlock, RW_READER); VERIFY0(dbuf_hold_impl(dn, db->db_level - 1, - i, B_TRUE, FTAG, &subdb)); + i, TRUE, FALSE, FTAG, &subdb)); rw_exit(&dn->dn_struct_rwlock); ASSERT3P(bp, ==, subdb->db_blkptr); @@ -357,7 +357,7 @@ dnode_sync_free_range_impl(dnode_t *dn, uint64_t blkid, uint64_t nblks, continue; rw_enter(&dn->dn_struct_rwlock, RW_READER); VERIFY0(dbuf_hold_impl(dn, dnlevel - 1, i, - TRUE, FTAG, &db)); + TRUE, FALSE, FTAG, &db)); rw_exit(&dn->dn_struct_rwlock); free_children(db, blkid, nblks, tx); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c index 551e35b..f4fdaf9 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c @@ -21,7 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. * Portions Copyright (c) 2011 Martin Matuska <mm@FreeBSD.org> - * Copyright (c) 2011, 2014 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2014, Joyent, Inc. All rights reserved. * Copyright (c) 2014 RackTop Systems. * Copyright (c) 2014 Spectra Logic Corporation, All rights reserved. @@ -130,8 +130,10 @@ dsl_dataset_block_born(dsl_dataset_t *ds, const blkptr_t *bp, dmu_tx_t *tx) dsl_dataset_phys(ds)->ds_compressed_bytes += compressed; dsl_dataset_phys(ds)->ds_uncompressed_bytes += uncompressed; dsl_dataset_phys(ds)->ds_unique_bytes += used; - if (BP_GET_LSIZE(bp) > SPA_OLD_MAXBLOCKSIZE) - ds->ds_need_large_blocks = B_TRUE; + if (BP_GET_LSIZE(bp) > SPA_OLD_MAXBLOCKSIZE) { + ds->ds_feature_activation_needed[SPA_FEATURE_LARGE_BLOCKS] = + B_TRUE; + } mutex_exit(&ds->ds_lock); dsl_dir_diduse_space(ds->ds_dir, DD_USED_HEAD, delta, compressed, uncompressed, tx); @@ -433,19 +435,23 @@ dsl_dataset_hold_obj(dsl_pool_t *dp, uint64_t dsobj, void *tag, offsetof(dmu_sendarg_t, dsa_link)); if (doi.doi_type == DMU_OTN_ZAP_METADATA) { - int zaperr = zap_contains(mos, dsobj, - DS_FIELD_LARGE_BLOCKS); - if (zaperr != ENOENT) { - VERIFY0(zaperr); - ds->ds_large_blocks = B_TRUE; + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (!(spa_feature_table[f].fi_flags & + ZFEATURE_FLAG_PER_DATASET)) + continue; + err = zap_contains(mos, dsobj, + spa_feature_table[f].fi_guid); + if (err == 0) { + ds->ds_feature_inuse[f] = B_TRUE; + } else { + ASSERT3U(err, ==, ENOENT); + err = 0; + } } } - if (err == 0) { - err = dsl_dir_hold_obj(dp, - dsl_dataset_phys(ds)->ds_dir_obj, NULL, ds, - &ds->ds_dir); - } + err = dsl_dir_hold_obj(dp, + dsl_dataset_phys(ds)->ds_dir_obj, NULL, ds, &ds->ds_dir); if (err != 0) { mutex_destroy(&ds->ds_lock); mutex_destroy(&ds->ds_opening_lock); @@ -540,6 +546,7 @@ dsl_dataset_hold(dsl_pool_t *dp, const char *name, const char *snapname; uint64_t obj; int err = 0; + dsl_dataset_t *ds; err = dsl_dir_hold(dp, name, FTAG, &dd, &snapname); if (err != 0) @@ -548,36 +555,37 @@ dsl_dataset_hold(dsl_pool_t *dp, const char *name, ASSERT(dsl_pool_config_held(dp)); obj = dsl_dir_phys(dd)->dd_head_dataset_obj; if (obj != 0) - err = dsl_dataset_hold_obj(dp, obj, tag, dsp); + err = dsl_dataset_hold_obj(dp, obj, tag, &ds); else err = SET_ERROR(ENOENT); /* we may be looking for a snapshot */ if (err == 0 && snapname != NULL) { - dsl_dataset_t *ds; + dsl_dataset_t *snap_ds; if (*snapname++ != '@') { - dsl_dataset_rele(*dsp, tag); + dsl_dataset_rele(ds, tag); dsl_dir_rele(dd, FTAG); return (SET_ERROR(ENOENT)); } dprintf("looking for snapshot '%s'\n", snapname); - err = dsl_dataset_snap_lookup(*dsp, snapname, &obj); + err = dsl_dataset_snap_lookup(ds, snapname, &obj); if (err == 0) - err = dsl_dataset_hold_obj(dp, obj, tag, &ds); - dsl_dataset_rele(*dsp, tag); + err = dsl_dataset_hold_obj(dp, obj, tag, &snap_ds); + dsl_dataset_rele(ds, tag); if (err == 0) { - mutex_enter(&ds->ds_lock); - if (ds->ds_snapname[0] == 0) - (void) strlcpy(ds->ds_snapname, snapname, - sizeof (ds->ds_snapname)); - mutex_exit(&ds->ds_lock); - *dsp = ds; + mutex_enter(&snap_ds->ds_lock); + if (snap_ds->ds_snapname[0] == 0) + (void) strlcpy(snap_ds->ds_snapname, snapname, + sizeof (snap_ds->ds_snapname)); + mutex_exit(&snap_ds->ds_lock); + ds = snap_ds; } } - + if (err == 0) + *dsp = ds; dsl_dir_rele(dd, FTAG); return (err); } @@ -699,6 +707,34 @@ dsl_dataset_tryown(dsl_dataset_t *ds, void *tag) return (gotit); } +static void +dsl_dataset_activate_feature(uint64_t dsobj, spa_feature_t f, dmu_tx_t *tx) +{ + spa_t *spa = dmu_tx_pool(tx)->dp_spa; + objset_t *mos = dmu_tx_pool(tx)->dp_meta_objset; + uint64_t zero = 0; + + VERIFY(spa_feature_table[f].fi_flags & ZFEATURE_FLAG_PER_DATASET); + + spa_feature_incr(spa, f, tx); + dmu_object_zapify(mos, dsobj, DMU_OT_DSL_DATASET, tx); + + VERIFY0(zap_add(mos, dsobj, spa_feature_table[f].fi_guid, + sizeof (zero), 1, &zero, tx)); +} + +void +dsl_dataset_deactivate_feature(uint64_t dsobj, spa_feature_t f, dmu_tx_t *tx) +{ + spa_t *spa = dmu_tx_pool(tx)->dp_spa; + objset_t *mos = dmu_tx_pool(tx)->dp_meta_objset; + + VERIFY(spa_feature_table[f].fi_flags & ZFEATURE_FLAG_PER_DATASET); + + VERIFY0(zap_remove(mos, dsobj, spa_feature_table[f].fi_guid, tx)); + spa_feature_decr(spa, f, tx); +} + uint64_t dsl_dataset_create_sync_dd(dsl_dir_t *dd, dsl_dataset_t *origin, uint64_t flags, dmu_tx_t *tx) @@ -759,8 +795,10 @@ dsl_dataset_create_sync_dd(dsl_dir_t *dd, dsl_dataset_t *origin, dsphys->ds_flags |= dsl_dataset_phys(origin)->ds_flags & (DS_FLAG_INCONSISTENT | DS_FLAG_CI_DATASET); - if (origin->ds_large_blocks) - dsl_dataset_activate_large_blocks_sync_impl(dsobj, tx); + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (origin->ds_feature_inuse[f]) + dsl_dataset_activate_feature(dsobj, f, tx); + } dmu_buf_will_dirty(origin->ds_dbuf, tx); dsl_dataset_phys(origin)->ds_num_children++; @@ -1322,8 +1360,10 @@ dsl_dataset_snapshot_sync_impl(dsl_dataset_t *ds, const char *snapname, dsphys->ds_bp = dsl_dataset_phys(ds)->ds_bp; dmu_buf_rele(dbuf, FTAG); - if (ds->ds_large_blocks) - dsl_dataset_activate_large_blocks_sync_impl(dsobj, tx); + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (ds->ds_feature_inuse[f]) + dsl_dataset_activate_feature(dsobj, f, tx); + } ASSERT3U(ds->ds_prev != 0, ==, dsl_dataset_phys(ds)->ds_prev_snap_obj != 0); @@ -1615,9 +1655,13 @@ dsl_dataset_sync(dsl_dataset_t *ds, zio_t *zio, dmu_tx_t *tx) dmu_objset_sync(ds->ds_objset, zio, tx); - if (ds->ds_need_large_blocks && !ds->ds_large_blocks) { - dsl_dataset_activate_large_blocks_sync_impl(ds->ds_object, tx); - ds->ds_large_blocks = B_TRUE; + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (ds->ds_feature_activation_needed[f]) { + if (ds->ds_feature_inuse[f]) + continue; + dsl_dataset_activate_feature(ds->ds_object, f, tx); + ds->ds_feature_inuse[f] = B_TRUE; + } } } @@ -2781,6 +2825,40 @@ dsl_dataset_clone_swap_sync_impl(dsl_dataset_t *clone, dsl_dataset_phys(clone)->ds_unique_bytes <= origin_head->ds_quota); ASSERT3P(clone->ds_prev, ==, origin_head->ds_prev); + /* + * Swap per-dataset feature flags. + */ + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (!(spa_feature_table[f].fi_flags & + ZFEATURE_FLAG_PER_DATASET)) { + ASSERT(!clone->ds_feature_inuse[f]); + ASSERT(!origin_head->ds_feature_inuse[f]); + continue; + } + + boolean_t clone_inuse = clone->ds_feature_inuse[f]; + boolean_t origin_head_inuse = origin_head->ds_feature_inuse[f]; + + if (clone_inuse) { + dsl_dataset_deactivate_feature(clone->ds_object, f, tx); + clone->ds_feature_inuse[f] = B_FALSE; + } + if (origin_head_inuse) { + dsl_dataset_deactivate_feature(origin_head->ds_object, + f, tx); + origin_head->ds_feature_inuse[f] = B_FALSE; + } + if (clone_inuse) { + dsl_dataset_activate_feature(origin_head->ds_object, + f, tx); + origin_head->ds_feature_inuse[f] = B_TRUE; + } + if (origin_head_inuse) { + dsl_dataset_activate_feature(clone->ds_object, f, tx); + clone->ds_feature_inuse[f] = B_TRUE; + } + } + dmu_buf_will_dirty(clone->ds_dbuf, tx); dmu_buf_will_dirty(origin_head->ds_dbuf, tx); @@ -3335,77 +3413,6 @@ dsl_dataset_space_wouldfree(dsl_dataset_t *firstsnap, return (err); } -static int -dsl_dataset_activate_large_blocks_check(void *arg, dmu_tx_t *tx) -{ - const char *dsname = arg; - dsl_dataset_t *ds; - dsl_pool_t *dp = dmu_tx_pool(tx); - int error = 0; - - if (!spa_feature_is_enabled(dp->dp_spa, SPA_FEATURE_LARGE_BLOCKS)) - return (SET_ERROR(ENOTSUP)); - - ASSERT(spa_feature_is_enabled(dp->dp_spa, - SPA_FEATURE_EXTENSIBLE_DATASET)); - - error = dsl_dataset_hold(dp, dsname, FTAG, &ds); - if (error != 0) - return (error); - - if (ds->ds_large_blocks) - error = EALREADY; - dsl_dataset_rele(ds, FTAG); - - return (error); -} - -void -dsl_dataset_activate_large_blocks_sync_impl(uint64_t dsobj, dmu_tx_t *tx) -{ - spa_t *spa = dmu_tx_pool(tx)->dp_spa; - objset_t *mos = dmu_tx_pool(tx)->dp_meta_objset; - uint64_t zero = 0; - - spa_feature_incr(spa, SPA_FEATURE_LARGE_BLOCKS, tx); - dmu_object_zapify(mos, dsobj, DMU_OT_DSL_DATASET, tx); - - VERIFY0(zap_add(mos, dsobj, DS_FIELD_LARGE_BLOCKS, - sizeof (zero), 1, &zero, tx)); -} - -static void -dsl_dataset_activate_large_blocks_sync(void *arg, dmu_tx_t *tx) -{ - const char *dsname = arg; - dsl_dataset_t *ds; - - VERIFY0(dsl_dataset_hold(dmu_tx_pool(tx), dsname, FTAG, &ds)); - - dsl_dataset_activate_large_blocks_sync_impl(ds->ds_object, tx); - ASSERT(!ds->ds_large_blocks); - ds->ds_large_blocks = B_TRUE; - dsl_dataset_rele(ds, FTAG); -} - -int -dsl_dataset_activate_large_blocks(const char *dsname) -{ - int error; - - error = dsl_sync_task(dsname, - dsl_dataset_activate_large_blocks_check, - dsl_dataset_activate_large_blocks_sync, (void *)dsname, - 1, ZFS_SPACE_CHECK_RESERVED); - - /* - * EALREADY indicates that this dataset already supports large blocks. - */ - if (error == EALREADY) - error = 0; - return (error); -} - /* * Return TRUE if 'earlier' is an earlier snapshot in 'later's timeline. * For example, they could both be snapshots of the same filesystem, and @@ -3450,7 +3457,6 @@ dsl_dataset_is_before(dsl_dataset_t *later, dsl_dataset_t *earlier, return (ret); } - void dsl_dataset_zapify(dsl_dataset_t *ds, dmu_tx_t *tx) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_destroy.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_destroy.c index 7f90469..c7a623c 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_destroy.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_destroy.c @@ -20,7 +20,7 @@ */ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2014 by Delphix. All rights reserved. + * Copyright (c) 2012, 2015 by Delphix. All rights reserved. * Copyright (c) 2013 Steven Hartland. All rights reserved. * Copyright (c) 2013 by Joyent, Inc. All rights reserved. */ @@ -267,9 +267,11 @@ dsl_destroy_snapshot_sync_impl(dsl_dataset_t *ds, boolean_t defer, dmu_tx_t *tx) obj = ds->ds_object; - if (ds->ds_large_blocks) { - ASSERT0(zap_contains(mos, obj, DS_FIELD_LARGE_BLOCKS)); - spa_feature_decr(dp->dp_spa, SPA_FEATURE_LARGE_BLOCKS, tx); + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (ds->ds_feature_inuse[f]) { + dsl_dataset_deactivate_feature(obj, f, tx); + ds->ds_feature_inuse[f] = B_FALSE; + } } if (dsl_dataset_phys(ds)->ds_prev_snap_obj != 0) { ASSERT3P(ds->ds_prev, ==, NULL); @@ -552,7 +554,7 @@ kill_blkptr(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, struct killarg *ka = arg; dmu_tx_t *tx = ka->tx; - if (BP_IS_HOLE(bp) || BP_IS_EMBEDDED(bp)) + if (bp == NULL || BP_IS_HOLE(bp) || BP_IS_EMBEDDED(bp)) return (0); if (zb->zb_level == ZB_ZIL_LEVEL) { @@ -736,12 +738,16 @@ dsl_destroy_head_sync_impl(dsl_dataset_t *ds, dmu_tx_t *tx) ASSERT0(ds->ds_reserved); } - if (ds->ds_large_blocks) - spa_feature_decr(dp->dp_spa, SPA_FEATURE_LARGE_BLOCKS, tx); + obj = ds->ds_object; - dsl_scan_ds_destroyed(ds, tx); + for (spa_feature_t f = 0; f < SPA_FEATURES; f++) { + if (ds->ds_feature_inuse[f]) { + dsl_dataset_deactivate_feature(obj, f, tx); + ds->ds_feature_inuse[f] = B_FALSE; + } + } - obj = ds->ds_object; + dsl_scan_ds_destroyed(ds, tx); if (dsl_dataset_phys(ds)->ds_prev_snap_obj != 0) { /* This is a clone */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_pool.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_pool.c index d58886b..189ca19 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_pool.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_pool.c @@ -415,7 +415,14 @@ dsl_pool_close(dsl_pool_t *dp) txg_list_destroy(&dp->dp_sync_tasks); txg_list_destroy(&dp->dp_dirty_dirs); - arc_flush(dp->dp_spa); + /* + * We can't set retry to TRUE since we're explicitly specifying + * a spa to flush. This is good enough; any missed buffers for + * this spa won't cause trouble, and they'll eventually fall + * out of the ARC just like any other unused buffer. + */ + arc_flush(dp->dp_spa, FALSE); + txg_fini(dp); dsl_scan_fini(dp); dmu_buf_user_evict_wait(); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c index d08b5fb..406af3b 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c @@ -600,7 +600,8 @@ dsl_scan_check_resume(dsl_scan_t *scn, const dnode_phys_t *dnp, * If we already visited this bp & everything below (in * a prior txg sync), don't bother doing it again. */ - if (zbookmark_is_before(dnp, zb, &scn->scn_phys.scn_bookmark)) + if (zbookmark_subtree_completed(dnp, zb, + &scn->scn_phys.scn_bookmark)) return (B_TRUE); /* diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/multilist.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/multilist.c new file mode 100644 index 0000000..8296057 --- /dev/null +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/multilist.c @@ -0,0 +1,366 @@ +/* + * CDDL HEADER START + * + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + * + * CDDL HEADER END + */ +/* + * Copyright (c) 2013, 2014 by Delphix. All rights reserved. + */ + +#include <sys/zfs_context.h> +#include <sys/multilist.h> + +/* needed for spa_get_random() */ +#include <sys/spa.h> + +/* + * Given the object contained on the list, return a pointer to the + * object's multilist_node_t structure it contains. + */ +static multilist_node_t * +multilist_d2l(multilist_t *ml, void *obj) +{ + return ((multilist_node_t *)((char *)obj + ml->ml_offset)); +} + +/* + * Initialize a new mutlilist using the parameters specified. + * + * - 'size' denotes the size of the structure containing the + * multilist_node_t. + * - 'offset' denotes the byte offset of the mutlilist_node_t within + * the structure that contains it. + * - 'num' specifies the number of internal sublists to create. + * - 'index_func' is used to determine which sublist to insert into + * when the multilist_insert() function is called; as well as which + * sublist to remove from when multilist_remove() is called. The + * requirements this function must meet, are the following: + * + * - It must always return the same value when called on the same + * object (to ensure the object is removed from the list it was + * inserted into). + * + * - It must return a value in the range [0, number of sublists). + * The multilist_get_num_sublists() function may be used to + * determine the number of sublists in the multilist. + * + * Also, in order to reduce internal contention between the sublists + * during insertion and removal, this function should choose evenly + * between all available sublists when inserting. This isn't a hard + * requirement, but a general rule of thumb in order to garner the + * best multi-threaded performance out of the data structure. + */ +void +multilist_create(multilist_t *ml, size_t size, size_t offset, unsigned int num, + multilist_sublist_index_func_t *index_func) +{ + ASSERT3P(ml, !=, NULL); + ASSERT3U(size, >, 0); + ASSERT3U(size, >=, offset + sizeof (multilist_node_t)); + ASSERT3U(num, >, 0); + ASSERT3P(index_func, !=, NULL); + + ml->ml_offset = offset; + ml->ml_num_sublists = num; + ml->ml_index_func = index_func; + + ml->ml_sublists = kmem_zalloc(sizeof (multilist_sublist_t) * + ml->ml_num_sublists, KM_SLEEP); + + ASSERT3P(ml->ml_sublists, !=, NULL); + + for (int i = 0; i < ml->ml_num_sublists; i++) { + multilist_sublist_t *mls = &ml->ml_sublists[i]; + mutex_init(&mls->mls_lock, NULL, MUTEX_DEFAULT, NULL); + list_create(&mls->mls_list, size, offset); + } +} + +/* + * Destroy the given multilist object, and free up any memory it holds. + */ +void +multilist_destroy(multilist_t *ml) +{ + ASSERT(multilist_is_empty(ml)); + + for (int i = 0; i < ml->ml_num_sublists; i++) { + multilist_sublist_t *mls = &ml->ml_sublists[i]; + + ASSERT(list_is_empty(&mls->mls_list)); + + list_destroy(&mls->mls_list); + mutex_destroy(&mls->mls_lock); + } + + ASSERT3P(ml->ml_sublists, !=, NULL); + kmem_free(ml->ml_sublists, + sizeof (multilist_sublist_t) * ml->ml_num_sublists); + + ml->ml_num_sublists = 0; + ml->ml_offset = 0; +} + +/* + * Insert the given object into the multilist. + * + * This function will insert the object specified into the sublist + * determined using the function given at multilist creation time. + * + * The sublist locks are automatically acquired if not already held, to + * ensure consistency when inserting and removing from multiple threads. + */ +void +multilist_insert(multilist_t *ml, void *obj) +{ + unsigned int sublist_idx = ml->ml_index_func(ml, obj); + multilist_sublist_t *mls; + boolean_t need_lock; + + DTRACE_PROBE3(multilist__insert, multilist_t *, ml, + unsigned int, sublist_idx, void *, obj); + + ASSERT3U(sublist_idx, <, ml->ml_num_sublists); + + mls = &ml->ml_sublists[sublist_idx]; + + /* + * Note: Callers may already hold the sublist lock by calling + * multilist_sublist_lock(). Here we rely on MUTEX_HELD() + * returning TRUE if and only if the current thread holds the + * lock. While it's a little ugly to make the lock recursive in + * this way, it works and allows the calling code to be much + * simpler -- otherwise it would have to pass around a flag + * indicating that it already has the lock. + */ + need_lock = !MUTEX_HELD(&mls->mls_lock); + + if (need_lock) + mutex_enter(&mls->mls_lock); + + ASSERT(!multilist_link_active(multilist_d2l(ml, obj))); + + multilist_sublist_insert_head(mls, obj); + + if (need_lock) + mutex_exit(&mls->mls_lock); +} + +/* + * Remove the given object from the multilist. + * + * This function will remove the object specified from the sublist + * determined using the function given at multilist creation time. + * + * The necessary sublist locks are automatically acquired, to ensure + * consistency when inserting and removing from multiple threads. + */ +void +multilist_remove(multilist_t *ml, void *obj) +{ + unsigned int sublist_idx = ml->ml_index_func(ml, obj); + multilist_sublist_t *mls; + boolean_t need_lock; + + DTRACE_PROBE3(multilist__remove, multilist_t *, ml, + unsigned int, sublist_idx, void *, obj); + + ASSERT3U(sublist_idx, <, ml->ml_num_sublists); + + mls = &ml->ml_sublists[sublist_idx]; + /* See comment in multilist_insert(). */ + need_lock = !MUTEX_HELD(&mls->mls_lock); + + if (need_lock) + mutex_enter(&mls->mls_lock); + + ASSERT(multilist_link_active(multilist_d2l(ml, obj))); + + multilist_sublist_remove(mls, obj); + + if (need_lock) + mutex_exit(&mls->mls_lock); +} + +/* + * Check to see if this multilist object is empty. + * + * This will return TRUE if it finds all of the sublists of this + * multilist to be empty, and FALSE otherwise. Each sublist lock will be + * automatically acquired as necessary. + * + * If concurrent insertions and removals are occurring, the semantics + * of this function become a little fuzzy. Instead of locking all + * sublists for the entire call time of the function, each sublist is + * only locked as it is individually checked for emptiness. Thus, it's + * possible for this function to return TRUE with non-empty sublists at + * the time the function returns. This would be due to another thread + * inserting into a given sublist, after that specific sublist was check + * and deemed empty, but before all sublists have been checked. + */ +int +multilist_is_empty(multilist_t *ml) +{ + for (int i = 0; i < ml->ml_num_sublists; i++) { + multilist_sublist_t *mls = &ml->ml_sublists[i]; + /* See comment in multilist_insert(). */ + boolean_t need_lock = !MUTEX_HELD(&mls->mls_lock); + + if (need_lock) + mutex_enter(&mls->mls_lock); + + if (!list_is_empty(&mls->mls_list)) { + if (need_lock) + mutex_exit(&mls->mls_lock); + + return (FALSE); + } + + if (need_lock) + mutex_exit(&mls->mls_lock); + } + + return (TRUE); +} + +/* Return the number of sublists composing this multilist */ +unsigned int +multilist_get_num_sublists(multilist_t *ml) +{ + return (ml->ml_num_sublists); +} + +/* Return a randomly selected, valid sublist index for this multilist */ +unsigned int +multilist_get_random_index(multilist_t *ml) +{ + return (spa_get_random(ml->ml_num_sublists)); +} + +/* Lock and return the sublist specified at the given index */ +multilist_sublist_t * +multilist_sublist_lock(multilist_t *ml, unsigned int sublist_idx) +{ + multilist_sublist_t *mls; + + ASSERT3U(sublist_idx, <, ml->ml_num_sublists); + mls = &ml->ml_sublists[sublist_idx]; + mutex_enter(&mls->mls_lock); + + return (mls); +} + +void +multilist_sublist_unlock(multilist_sublist_t *mls) +{ + mutex_exit(&mls->mls_lock); +} + +/* + * We're allowing any object to be inserted into this specific sublist, + * but this can lead to trouble if multilist_remove() is called to + * remove this object. Specifically, if calling ml_index_func on this + * object returns an index for sublist different than what is passed as + * a parameter here, any call to multilist_remove() with this newly + * inserted object is undefined! (the call to multilist_remove() will + * remove the object from a list that it isn't contained in) + */ +void +multilist_sublist_insert_head(multilist_sublist_t *mls, void *obj) +{ + ASSERT(MUTEX_HELD(&mls->mls_lock)); + list_insert_head(&mls->mls_list, obj); +} + +/* please see comment above multilist_sublist_insert_head */ +void +multilist_sublist_insert_tail(multilist_sublist_t *mls, void *obj) +{ + ASSERT(MUTEX_HELD(&mls->mls_lock)); + list_insert_tail(&mls->mls_list, obj); +} + +/* + * Move the object one element forward in the list. + * + * This function will move the given object forward in the list (towards + * the head) by one object. So, in essence, it will swap its position in + * the list with its "prev" pointer. If the given object is already at the + * head of the list, it cannot be moved forward any more than it already + * is, so no action is taken. + * + * NOTE: This function **must not** remove any object from the list other + * than the object given as the parameter. This is relied upon in + * arc_evict_state_impl(). + */ +void +multilist_sublist_move_forward(multilist_sublist_t *mls, void *obj) +{ + void *prev = list_prev(&mls->mls_list, obj); + + ASSERT(MUTEX_HELD(&mls->mls_lock)); + ASSERT(!list_is_empty(&mls->mls_list)); + + /* 'obj' must be at the head of the list, nothing to do */ + if (prev == NULL) + return; + + list_remove(&mls->mls_list, obj); + list_insert_before(&mls->mls_list, prev, obj); +} + +void +multilist_sublist_remove(multilist_sublist_t *mls, void *obj) +{ + ASSERT(MUTEX_HELD(&mls->mls_lock)); + list_remove(&mls->mls_list, obj); +} + +void * +multilist_sublist_head(multilist_sublist_t *mls) +{ + ASSERT(MUTEX_HELD(&mls->mls_lock)); + return (list_head(&mls->mls_list)); +} + +void * +multilist_sublist_tail(multilist_sublist_t *mls) +{ + ASSERT(MUTEX_HELD(&mls->mls_lock)); + return (list_tail(&mls->mls_list)); +} + +void * +multilist_sublist_next(multilist_sublist_t *mls, void *obj) +{ + ASSERT(MUTEX_HELD(&mls->mls_lock)); + return (list_next(&mls->mls_list, obj)); +} + +void * +multilist_sublist_prev(multilist_sublist_t *mls, void *obj) +{ + ASSERT(MUTEX_HELD(&mls->mls_lock)); + return (list_prev(&mls->mls_list, obj)); +} + +void +multilist_link_init(multilist_node_t *link) +{ + list_link_init(link); +} + +int +multilist_link_active(multilist_node_t *link) +{ + return (list_link_active(link)); +} diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c index 40efaba..a5389c3 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c @@ -1943,7 +1943,7 @@ static int spa_load_verify_cb(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, const zbookmark_phys_t *zb, const dnode_phys_t *dnp, void *arg) { - if (BP_IS_HOLE(bp) || BP_IS_EMBEDDED(bp)) + if (bp == NULL || BP_IS_HOLE(bp) || BP_IS_EMBEDDED(bp)) return (0); /* * Note: normally this routine will not be called if diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/space_map.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/space_map.c index aeac124..1ea829f 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/space_map.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/space_map.c @@ -80,8 +80,8 @@ space_map_load(space_map_t *sm, range_tree_t *rt, maptype_t maptype) mutex_exit(sm->sm_lock); if (end > bufsize) { - dmu_prefetch(sm->sm_os, space_map_object(sm), bufsize, - end - bufsize); + dmu_prefetch(sm->sm_os, space_map_object(sm), 0, bufsize, + end - bufsize, ZIO_PRIORITY_SYNC_READ); } mutex_enter(sm->sm_lock); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/arc.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/arc.h index 4d13cb1..a26d8f8 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/arc.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/arc.h @@ -37,6 +37,12 @@ extern "C" { #include <sys/dmu.h> #include <sys/spa.h> +/* + * Used by arc_flush() to inform arc_evict_state() that it should evict + * all available buffers from the arc state being passed in. + */ +#define ARC_EVICT_ALL -1ULL + typedef struct arc_buf_hdr arc_buf_hdr_t; typedef struct arc_buf arc_buf_t; typedef void arc_done_func_t(zio_t *zio, arc_buf_t *buf, void *priv); @@ -154,7 +160,7 @@ void arc_freed(spa_t *spa, const blkptr_t *bp); void arc_set_callback(arc_buf_t *buf, arc_evict_func_t *func, void *priv); boolean_t arc_clear_callback(arc_buf_t *buf); -void arc_flush(spa_t *spa); +void arc_flush(spa_t *spa, boolean_t retry); void arc_tempreserve_clear(uint64_t reserve); int arc_tempreserve_space(uint64_t reserve, uint64_t txg); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/bqueue.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/bqueue.h new file mode 100644 index 0000000..63722df --- /dev/null +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/bqueue.h @@ -0,0 +1,54 @@ +/* + * CDDL HEADER START + * + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + * + * CDDL HEADER END + */ +/* + * Copyright (c) 2014 by Delphix. All rights reserved. + */ + +#ifndef _BQUEUE_H +#define _BQUEUE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <sys/zfs_context.h> + +typedef struct bqueue { + list_t bq_list; + kmutex_t bq_lock; + kcondvar_t bq_add_cv; + kcondvar_t bq_pop_cv; + uint64_t bq_size; + uint64_t bq_maxsize; + size_t bq_node_offset; +} bqueue_t; + +typedef struct bqueue_node { + list_node_t bqn_node; + uint64_t bqn_size; +} bqueue_node_t; + + +int bqueue_init(bqueue_t *, uint64_t, size_t); +void bqueue_destroy(bqueue_t *); +void bqueue_enqueue(bqueue_t *, void *, uint64_t); +void *bqueue_dequeue(bqueue_t *); +boolean_t bqueue_empty(bqueue_t *); + +#ifdef __cplusplus +} +#endif + +#endif /* _BQUEUE_H */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dbuf.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dbuf.h index 2e07185..482ccb0 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dbuf.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dbuf.h @@ -245,8 +245,7 @@ typedef struct dbuf_hash_table { kmutex_t hash_mutexes[DBUF_MUTEXES]; } dbuf_hash_table_t; - -uint64_t dbuf_whichblock(struct dnode *di, uint64_t offset); +uint64_t dbuf_whichblock(struct dnode *di, int64_t level, uint64_t offset); dmu_buf_impl_t *dbuf_create_tlib(struct dnode *dn, char *data); void dbuf_create_bonus(struct dnode *dn); @@ -258,10 +257,12 @@ void dbuf_rm_spill(struct dnode *dn, dmu_tx_t *tx); dmu_buf_impl_t *dbuf_hold(struct dnode *dn, uint64_t blkid, void *tag); dmu_buf_impl_t *dbuf_hold_level(struct dnode *dn, int level, uint64_t blkid, void *tag); -int dbuf_hold_impl(struct dnode *dn, uint8_t level, uint64_t blkid, int create, +int dbuf_hold_impl(struct dnode *dn, uint8_t level, uint64_t blkid, + boolean_t fail_sparse, boolean_t fail_uncached, void *tag, dmu_buf_impl_t **dbp); -void dbuf_prefetch(struct dnode *dn, uint64_t blkid, zio_priority_t prio); +void dbuf_prefetch(struct dnode *dn, int64_t level, uint64_t blkid, + zio_priority_t prio, arc_flags_t aflags); void dbuf_add_ref(dmu_buf_impl_t *db, void *tag); boolean_t dbuf_try_add_ref(dmu_buf_t *db, objset_t *os, uint64_t obj, diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu.h index 3c5cfbe..f6c72b0 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu.h @@ -45,6 +45,7 @@ #include <sys/zfs_context.h> #include <sys/cred.h> #include <sys/fs/zfs.h> +#include <sys/zio_priority.h> #ifdef __cplusplus extern "C" { @@ -748,8 +749,8 @@ extern int zfs_max_recordsize; /* * Asynchronously try to read in the data. */ -void dmu_prefetch(objset_t *os, uint64_t object, uint64_t offset, - uint64_t len); +void dmu_prefetch(objset_t *os, uint64_t object, int64_t level, uint64_t offset, + uint64_t len, enum zio_priority pri); typedef struct dmu_object_info { /* All sizes are in bytes unless otherwise indicated. */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dsl_dataset.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dsl_dataset.h index 7d490ec..001bff5 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dsl_dataset.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dsl_dataset.h @@ -20,7 +20,7 @@ */ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2013 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. * Copyright (c) 2013, Joyent, Inc. All rights reserved. * Copyright (c) 2013 Steven Hartland. All rights reserved. * Copyright (c) 2014 Spectra Logic Corporation, All rights reserved. @@ -38,6 +38,7 @@ #include <sys/zfs_context.h> #include <sys/dsl_deadlist.h> #include <sys/refcount.h> +#include <zfeature_common.h> #ifdef __cplusplus extern "C" { @@ -145,8 +146,6 @@ typedef struct dsl_dataset { /* only used in syncing context, only valid for non-snapshots: */ struct dsl_dataset *ds_prev; uint64_t ds_bookmarks; /* DMU_OTN_ZAP_METADATA */ - boolean_t ds_large_blocks; - boolean_t ds_need_large_blocks; /* has internal locking: */ dsl_deadlist_t ds_deadlist; @@ -185,6 +184,18 @@ typedef struct dsl_dataset { kmutex_t ds_sendstream_lock; list_t ds_sendstreams; + /* + * For ZFEATURE_FLAG_PER_DATASET features, set if this dataset + * uses this feature. + */ + uint8_t ds_feature_inuse[SPA_FEATURES]; + + /* + * Set if we need to activate the feature on this dataset this txg + * (used only in syncing context). + */ + uint8_t ds_feature_activation_needed[SPA_FEATURES]; + /* Protected by ds_lock; keep at end of struct for better locality */ char ds_snapname[MAXNAMELEN]; } dsl_dataset_t; @@ -264,8 +275,6 @@ int dsl_dataset_space_written(dsl_dataset_t *oldsnap, dsl_dataset_t *new, int dsl_dataset_space_wouldfree(dsl_dataset_t *firstsnap, dsl_dataset_t *last, uint64_t *usedp, uint64_t *compp, uint64_t *uncompp); boolean_t dsl_dataset_is_dirty(dsl_dataset_t *ds); -int dsl_dataset_activate_large_blocks(const char *dsname); -void dsl_dataset_activate_large_blocks_sync_impl(uint64_t dsobj, dmu_tx_t *tx); int dsl_dsobj_to_dsname(char *pname, uint64_t obj, char *buf); @@ -305,6 +314,9 @@ void dsl_dataset_set_refreservation_sync_impl(dsl_dataset_t *ds, void dsl_dataset_zapify(dsl_dataset_t *ds, dmu_tx_t *tx); int dsl_dataset_rollback(const char *fsname, void *owner, nvlist_t *result); +void dsl_dataset_deactivate_feature(uint64_t dsobj, + spa_feature_t f, dmu_tx_t *tx); + #ifdef ZFS_DEBUG #define dprintf_ds(ds, fmt, ...) do { \ if (zfs_flags & ZFS_DEBUG_DPRINTF) { \ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/multilist.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/multilist.h new file mode 100644 index 0000000..5ebb7fe --- /dev/null +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/multilist.h @@ -0,0 +1,106 @@ +/* + * CDDL HEADER START + * + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + * + * CDDL HEADER END + */ +/* + * Copyright (c) 2013, 2014 by Delphix. All rights reserved. + */ + +#ifndef _SYS_MULTILIST_H +#define _SYS_MULTILIST_H + +#include <sys/zfs_context.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef list_node_t multilist_node_t; +typedef struct multilist multilist_t; +typedef struct multilist_sublist multilist_sublist_t; +typedef unsigned int multilist_sublist_index_func_t(multilist_t *, void *); + +struct multilist_sublist { + /* + * The mutex used internally to implement thread safe insertions + * and removals to this individual sublist. It can also be locked + * by a consumer using multilist_sublist_{lock,unlock}, which is + * useful if a consumer needs to traverse the list in a thread + * safe manner. + */ + kmutex_t mls_lock; + /* + * The actual list object containing all objects in this sublist. + */ + list_t mls_list; + /* + * Pad to cache line (64 bytes), in an effort to try and prevent + * cache line contention. + */ + uint8_t mls_pad[24]; +}; + +struct multilist { + /* + * This is used to get to the multilist_node_t structure given + * the void *object contained on the list. + */ + size_t ml_offset; + /* + * The number of sublists used internally by this multilist. + */ + uint64_t ml_num_sublists; + /* + * The array of pointers to the actual sublists. + */ + multilist_sublist_t *ml_sublists; + /* + * Pointer to function which determines the sublist to use + * when inserting and removing objects from this multilist. + * Please see the comment above multilist_create for details. + */ + multilist_sublist_index_func_t *ml_index_func; +}; + +void multilist_destroy(multilist_t *); +void multilist_create(multilist_t *, size_t, size_t, unsigned int, + multilist_sublist_index_func_t *); + +void multilist_insert(multilist_t *, void *); +void multilist_remove(multilist_t *, void *); +int multilist_is_empty(multilist_t *); + +unsigned int multilist_get_num_sublists(multilist_t *); +unsigned int multilist_get_random_index(multilist_t *); + +multilist_sublist_t *multilist_sublist_lock(multilist_t *, unsigned int); +void multilist_sublist_unlock(multilist_sublist_t *); + +void multilist_sublist_insert_head(multilist_sublist_t *, void *); +void multilist_sublist_insert_tail(multilist_sublist_t *, void *); +void multilist_sublist_move_forward(multilist_sublist_t *mls, void *obj); +void multilist_sublist_remove(multilist_sublist_t *, void *); + +void *multilist_sublist_head(multilist_sublist_t *); +void *multilist_sublist_tail(multilist_sublist_t *); +void *multilist_sublist_next(multilist_sublist_t *, void *); +void *multilist_sublist_prev(multilist_sublist_t *, void *); + +void multilist_link_init(multilist_node_t *); +int multilist_link_active(multilist_node_t *); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_MULTILIST_H */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio.h index 36739cd..342c9cd 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio.h @@ -29,6 +29,7 @@ #ifndef _ZIO_H #define _ZIO_H +#include <sys/zio_priority.h> #include <sys/zfs_context.h> #include <sys/spa.h> #include <sys/txg.h> @@ -144,18 +145,6 @@ enum zio_compress { #define ZIO_FAILURE_MODE_CONTINUE 1 #define ZIO_FAILURE_MODE_PANIC 2 -typedef enum zio_priority { - ZIO_PRIORITY_SYNC_READ, - ZIO_PRIORITY_SYNC_WRITE, /* ZIL */ - ZIO_PRIORITY_ASYNC_READ, /* prefetch */ - ZIO_PRIORITY_ASYNC_WRITE, /* spa_sync() */ - ZIO_PRIORITY_SCRUB, /* asynchronous scrub/resilver reads */ - ZIO_PRIORITY_TRIM, /* free requests used for TRIM */ - ZIO_PRIORITY_NUM_QUEUEABLE, - - ZIO_PRIORITY_NOW /* non-queued I/Os (e.g. ioctl) */ -} zio_priority_t; - enum zio_flag { /* * Flags inherited by gang, ddt, and vdev children, @@ -260,6 +249,7 @@ extern const char *zio_type_name[ZIO_TYPES]; * Root blocks (objset_phys_t) are object 0, level -1: <objset, 0, -1, 0>. * ZIL blocks are bookmarked <objset, 0, -2, blkid == ZIL sequence number>. * dmu_sync()ed ZIL data blocks are bookmarked <objset, object, -2, blkid>. + * dnode visit bookmarks are <objset, object id of dnode, -3, 0>. * * Note: this structure is called a bookmark because its original purpose * was to remember where to resume a pool-wide traverse. @@ -292,6 +282,9 @@ typedef struct zbookmark_phys { #define ZB_ZIL_OBJECT (0ULL) #define ZB_ZIL_LEVEL (-2LL) +#define ZB_DNODE_LEVEL (-3LL) +#define ZB_DNODE_BLKID (0ULL) + #define ZB_IS_ZERO(zb) \ ((zb)->zb_objset == 0 && (zb)->zb_object == 0 && \ (zb)->zb_level == 0 && (zb)->zb_blkid == 0) @@ -633,8 +626,10 @@ extern void zfs_ereport_post_checksum(spa_t *spa, vdev_t *vd, extern void spa_handle_ignored_writes(spa_t *spa); /* zbookmark_phys functions */ -boolean_t zbookmark_is_before(const struct dnode_phys *dnp, - const zbookmark_phys_t *zb1, const zbookmark_phys_t *zb2); +boolean_t zbookmark_subtree_completed(const struct dnode_phys *dnp, + const zbookmark_phys_t *subtree_root, const zbookmark_phys_t *last_block); +int zbookmark_compare(uint16_t dbss1, uint8_t ibs1, uint16_t dbss2, + uint8_t ibs2, const zbookmark_phys_t *zb1, const zbookmark_phys_t *zb2); #ifdef __cplusplus } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio_checksum.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio_checksum.h index a921a2f..0c293ab 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio_checksum.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio_checksum.h @@ -44,7 +44,7 @@ typedef struct zio_checksum_info { zio_checksum_func_t *ci_func[2]; /* checksum function per byteorder */ int ci_correctable; /* number of correctable bits */ int ci_eck; /* uses zio embedded checksum? */ - int ci_dedup; /* strong enough for dedup? */ + boolean_t ci_dedup; /* strong enough for dedup? */ char *ci_name; /* descriptive name */ } zio_checksum_info_t; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio_priority.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio_priority.h new file mode 100644 index 0000000..32e90e2 --- /dev/null +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio_priority.h @@ -0,0 +1,41 @@ +/* + * CDDL HEADER START + * + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + * + * CDDL HEADER END + */ +/* + * Copyright (c) 2014 by Delphix. All rights reserved. + */ +#ifndef _ZIO_PRIORITY_H +#define _ZIO_PRIORITY_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum zio_priority { + ZIO_PRIORITY_SYNC_READ, + ZIO_PRIORITY_SYNC_WRITE, /* ZIL */ + ZIO_PRIORITY_ASYNC_READ, /* prefetch */ + ZIO_PRIORITY_ASYNC_WRITE, /* spa_sync() */ + ZIO_PRIORITY_SCRUB, /* asynchronous scrub/resilver reads */ + ZIO_PRIORITY_TRIM, /* free requests used for TRIM */ + ZIO_PRIORITY_NUM_QUEUEABLE, + + ZIO_PRIORITY_NOW /* non-queued i/os (e.g. free) */ +} zio_priority_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _ZIO_PRIORITY_H */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap.c index 36969e8..44919d2 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap.c @@ -162,8 +162,9 @@ zap_table_grow(zap_t *zap, zap_table_phys_t *tbl, newblk = zap_allocate_blocks(zap, tbl->zt_numblks * 2); tbl->zt_nextblk = newblk; ASSERT0(tbl->zt_blks_copied); - dmu_prefetch(zap->zap_objset, zap->zap_object, - tbl->zt_blk << bs, tbl->zt_numblks << bs); + dmu_prefetch(zap->zap_objset, zap->zap_object, 0, + tbl->zt_blk << bs, tbl->zt_numblks << bs, + ZIO_PRIORITY_SYNC_READ); } /* @@ -939,7 +940,8 @@ fzap_prefetch(zap_name_t *zn) if (zap_idx_to_blk(zap, idx, &blk) != 0) return; bs = FZAP_BLOCK_SHIFT(zap); - dmu_prefetch(zap->zap_objset, zap->zap_object, blk << bs, 1 << bs); + dmu_prefetch(zap->zap_objset, zap->zap_object, 0, blk << bs, 1 << bs, + ZIO_PRIORITY_SYNC_READ); } /* @@ -1310,9 +1312,10 @@ fzap_get_stats(zap_t *zap, zap_stats_t *zs) } else { int b; - dmu_prefetch(zap->zap_objset, zap->zap_object, + dmu_prefetch(zap->zap_objset, zap->zap_object, 0, zap_f_phys(zap)->zap_ptrtbl.zt_blk << bs, - zap_f_phys(zap)->zap_ptrtbl.zt_numblks << bs); + zap_f_phys(zap)->zap_ptrtbl.zt_numblks << bs, + ZIO_PRIORITY_SYNC_READ); for (b = 0; b < zap_f_phys(zap)->zap_ptrtbl.zt_numblks; b++) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfeature.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfeature.c index 7540320..80a3f0b 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfeature.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfeature.c @@ -20,7 +20,7 @@ */ /* - * Copyright (c) 2013 by Delphix. All rights reserved. + * Copyright (c) 2011, 2015 by Delphix. All rights reserved. */ #include <sys/zfs_context.h> @@ -245,7 +245,7 @@ feature_get_refcount_from_disk(spa_t *spa, zfeature_info_t *feature, { int err; uint64_t refcount; - uint64_t zapobj = feature->fi_can_readonly ? + uint64_t zapobj = (feature->fi_flags & ZFEATURE_FLAG_READONLY_COMPAT) ? spa->spa_feat_for_write_obj : spa->spa_feat_for_read_obj; /* @@ -296,7 +296,7 @@ feature_sync(spa_t *spa, zfeature_info_t *feature, uint64_t refcount, dmu_tx_t *tx) { ASSERT(VALID_FEATURE_OR_NONE(feature->fi_feature)); - uint64_t zapobj = feature->fi_can_readonly ? + uint64_t zapobj = (feature->fi_flags & ZFEATURE_FLAG_READONLY_COMPAT) ? spa->spa_feat_for_write_obj : spa->spa_feat_for_read_obj; VERIFY0(zap_update(spa->spa_meta_objset, zapobj, feature->fi_guid, @@ -322,7 +322,7 @@ feature_sync(spa_t *spa, zfeature_info_t *feature, uint64_t refcount, if (refcount == 0) spa_deactivate_mos_feature(spa, feature->fi_guid); - else if (feature->fi_mos) + else if (feature->fi_flags & ZFEATURE_FLAG_MOS) spa_activate_mos_feature(spa, feature->fi_guid, tx); } @@ -333,8 +333,9 @@ feature_sync(spa_t *spa, zfeature_info_t *feature, uint64_t refcount, void feature_enable_sync(spa_t *spa, zfeature_info_t *feature, dmu_tx_t *tx) { - uint64_t initial_refcount = feature->fi_activate_on_enable ? 1 : 0; - uint64_t zapobj = feature->fi_can_readonly ? + uint64_t initial_refcount = + (feature->fi_flags & ZFEATURE_FLAG_ACTIVATE_ON_ENABLE) ? 1 : 0; + uint64_t zapobj = (feature->fi_flags & ZFEATURE_FLAG_READONLY_COMPAT) ? spa->spa_feat_for_write_obj : spa->spa_feat_for_read_obj; ASSERT(0 != zapobj); @@ -379,7 +380,7 @@ feature_do_action(spa_t *spa, spa_feature_t fid, feature_action_t action, { uint64_t refcount; zfeature_info_t *feature = &spa_feature_table[fid]; - uint64_t zapobj = feature->fi_can_readonly ? + uint64_t zapobj = (feature->fi_flags & ZFEATURE_FLAG_READONLY_COMPAT) ? spa->spa_feat_for_write_obj : spa->spa_feat_for_read_obj; ASSERT(VALID_FEATURE_FID(fid)); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c index c2dd020..693ba41 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c @@ -21,6 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2013 by Delphix. All rights reserved. + * Copyright 2015, OmniTI Computer Consulting, Inc. All rights reserved. */ /* @@ -1149,10 +1150,11 @@ zfsctl_shares_lookup(ap) ZFS_EXIT(zfsvfs); return (SET_ERROR(ENOTSUP)); } - if ((error = zfs_zget(zfsvfs, zfsvfs->z_shares_dir, &dzp)) == 0) + if ((error = zfs_zget(zfsvfs, zfsvfs->z_shares_dir, &dzp)) == 0) { error = VOP_LOOKUP(ZTOV(dzp), vpp, cnp); + VN_RELE(ZTOV(dzp)); + } - VN_RELE(ZTOV(dzp)); ZFS_EXIT(zfsvfs); return (error); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c index 2a583d4..2e51916 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c @@ -5190,6 +5190,7 @@ zfs_ioc_smb_acl(zfs_cmd_t *zc) if ((error = get_nvlist(zc->zc_nvlist_src, zc->zc_nvlist_src_size, zc->zc_iflags, &nvlist)) != 0) { VN_RELE(vp); + VN_RELE(ZTOV(sharedir)); ZFS_EXIT(zfsvfs); return (error); } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c index 8a08c8d..ed56d17 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c @@ -22,7 +22,7 @@ * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2011 Pawel Jakub Dawidek <pawel@dawidek.net>. * All rights reserved. - * Copyright (c) 2013 by Delphix. All rights reserved. + * Copyright (c) 2012, 2014 by Delphix. All rights reserved. */ /* Portions Copyright 2010 Robert Milkowski */ @@ -950,7 +950,7 @@ zfsvfs_create(const char *osname, zfsvfs_t **zfvp) error = zap_lookup(os, MASTER_NODE_OBJ, ZFS_SA_ATTRS, 8, 1, &sa_obj); if (error) - return (error); + goto out; } else { /* * Pre SA versions file systems should never touch diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c index 1038a87..45a2bd7 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c @@ -2675,7 +2675,8 @@ zfs_readdir(vnode_t *vp, uio_t *uio, cred_t *cr, int *eofp, int *ncookies, u_lon /* Prefetch znode */ if (prefetch) - dmu_prefetch(os, objnum, 0, 0); + dmu_prefetch(os, objnum, 0, 0, 0, + ZIO_PRIORITY_SYNC_READ); skip_entry: /* diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c index 48de571..867b798 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c @@ -94,6 +94,9 @@ extern vmem_t *zio_alloc_arena; #define ZIO_PIPELINE_CONTINUE 0x100 #define ZIO_PIPELINE_STOP 0x101 +#define BP_SPANB(indblkshift, level) \ + (((uint64_t)1) << ((level) * ((indblkshift) - SPA_BLKPTRSHIFT))) +#define COMPARE_META_LEVEL 0x80000000ul /* * The following actions directly effect the spa's sync-to-convergence logic. * The values below define the sync pass when we start performing the action. @@ -3461,37 +3464,127 @@ static zio_pipe_stage_t *zio_pipeline[] = { zio_done }; -/* dnp is the dnode for zb1->zb_object */ -boolean_t -zbookmark_is_before(const dnode_phys_t *dnp, const zbookmark_phys_t *zb1, - const zbookmark_phys_t *zb2) -{ - uint64_t zb1nextL0, zb2thisobj; - ASSERT(zb1->zb_objset == zb2->zb_objset); - ASSERT(zb2->zb_level == 0); - /* The objset_phys_t isn't before anything. */ - if (dnp == NULL) - return (B_FALSE); - zb1nextL0 = (zb1->zb_blkid + 1) << - ((zb1->zb_level) * (dnp->dn_indblkshift - SPA_BLKPTRSHIFT)); +/* + * Compare two zbookmark_phys_t's to see which we would reach first in a + * pre-order traversal of the object tree. + * + * This is simple in every case aside from the meta-dnode object. For all other + * objects, we traverse them in order (object 1 before object 2, and so on). + * However, all of these objects are traversed while traversing object 0, since + * the data it points to is the list of objects. Thus, we need to convert to a + * canonical representation so we can compare meta-dnode bookmarks to + * non-meta-dnode bookmarks. + * + * We do this by calculating "equivalents" for each field of the zbookmark. + * zbookmarks outside of the meta-dnode use their own object and level, and + * calculate the level 0 equivalent (the first L0 blkid that is contained in the + * blocks this bookmark refers to) by multiplying their blkid by their span + * (the number of L0 blocks contained within one block at their level). + * zbookmarks inside the meta-dnode calculate their object equivalent + * (which is L0equiv * dnodes per data block), use 0 for their L0equiv, and use + * level + 1<<31 (any value larger than a level could ever be) for their level. + * This causes them to always compare before a bookmark in their object + * equivalent, compare appropriately to bookmarks in other objects, and to + * compare appropriately to other bookmarks in the meta-dnode. + */ +int +zbookmark_compare(uint16_t dbss1, uint8_t ibs1, uint16_t dbss2, uint8_t ibs2, + const zbookmark_phys_t *zb1, const zbookmark_phys_t *zb2) +{ + /* + * These variables represent the "equivalent" values for the zbookmark, + * after converting zbookmarks inside the meta dnode to their + * normal-object equivalents. + */ + uint64_t zb1obj, zb2obj; + uint64_t zb1L0, zb2L0; + uint64_t zb1level, zb2level; - zb2thisobj = zb2->zb_object ? zb2->zb_object : - zb2->zb_blkid << (DNODE_BLOCK_SHIFT - DNODE_SHIFT); + if (zb1->zb_object == zb2->zb_object && + zb1->zb_level == zb2->zb_level && + zb1->zb_blkid == zb2->zb_blkid) + return (0); + + /* + * BP_SPANB calculates the span in blocks. + */ + zb1L0 = (zb1->zb_blkid) * BP_SPANB(ibs1, zb1->zb_level); + zb2L0 = (zb2->zb_blkid) * BP_SPANB(ibs2, zb2->zb_level); if (zb1->zb_object == DMU_META_DNODE_OBJECT) { - uint64_t nextobj = zb1nextL0 * - (dnp->dn_datablkszsec << SPA_MINBLOCKSHIFT) >> DNODE_SHIFT; - return (nextobj <= zb2thisobj); + zb1obj = zb1L0 * (dbss1 << (SPA_MINBLOCKSHIFT - DNODE_SHIFT)); + zb1L0 = 0; + zb1level = zb1->zb_level + COMPARE_META_LEVEL; + } else { + zb1obj = zb1->zb_object; + zb1level = zb1->zb_level; } - if (zb1->zb_object < zb2thisobj) - return (B_TRUE); - if (zb1->zb_object > zb2thisobj) - return (B_FALSE); - if (zb2->zb_object == DMU_META_DNODE_OBJECT) + if (zb2->zb_object == DMU_META_DNODE_OBJECT) { + zb2obj = zb2L0 * (dbss2 << (SPA_MINBLOCKSHIFT - DNODE_SHIFT)); + zb2L0 = 0; + zb2level = zb2->zb_level + COMPARE_META_LEVEL; + } else { + zb2obj = zb2->zb_object; + zb2level = zb2->zb_level; + } + + /* Now that we have a canonical representation, do the comparison. */ + if (zb1obj != zb2obj) + return (zb1obj < zb2obj ? -1 : 1); + else if (zb1L0 != zb2L0) + return (zb1L0 < zb2L0 ? -1 : 1); + else if (zb1level != zb2level) + return (zb1level > zb2level ? -1 : 1); + /* + * This can (theoretically) happen if the bookmarks have the same object + * and level, but different blkids, if the block sizes are not the same. + * There is presently no way to change the indirect block sizes + */ + return (0); +} + +/* + * This function checks the following: given that last_block is the place that + * our traversal stopped last time, does that guarantee that we've visited + * every node under subtree_root? Therefore, we can't just use the raw output + * of zbookmark_compare. We have to pass in a modified version of + * subtree_root; by incrementing the block id, and then checking whether + * last_block is before or equal to that, we can tell whether or not having + * visited last_block implies that all of subtree_root's children have been + * visited. + */ +boolean_t +zbookmark_subtree_completed(const dnode_phys_t *dnp, + const zbookmark_phys_t *subtree_root, const zbookmark_phys_t *last_block) +{ + zbookmark_phys_t mod_zb = *subtree_root; + mod_zb.zb_blkid++; + ASSERT(last_block->zb_level == 0); + + /* The objset_phys_t isn't before anything. */ + if (dnp == NULL) return (B_FALSE); - return (zb1nextL0 <= zb2->zb_blkid); + + /* + * We pass in 1ULL << (DNODE_BLOCK_SHIFT - SPA_MINBLOCKSHIFT) for the + * data block size in sectors, because that variable is only used if + * the bookmark refers to a block in the meta-dnode. Since we don't + * know without examining it what object it refers to, and there's no + * harm in passing in this value in other cases, we always pass it in. + * + * We pass in 0 for the indirect block size shift because zb2 must be + * level 0. The indirect block size is only used to calculate the span + * of the bookmark, but since the bookmark must be level 0, the span is + * always 1, so the math works out. + * + * If you make changes to how the zbookmark_compare code works, be sure + * to make sure that this code still works afterwards. + */ + return (zbookmark_compare(dnp->dn_datablkszsec, dnp->dn_indblkshift, + 1ULL << (DNODE_BLOCK_SHIFT - SPA_MINBLOCKSHIFT), 0, &mod_zb, + last_block) <= 0); } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio_inject.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio_inject.c index 991a0a3..0a7f4e4 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio_inject.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio_inject.c @@ -438,7 +438,11 @@ zio_inject_fault(char *name, int flags, int *id, zinject_record_t *record) * fault injection isn't a performance critical path. */ if (flags & ZINJECT_FLUSH_ARC) - arc_flush(NULL); + /* + * We must use FALSE to ensure arc_flush returns, since + * we're not preventing concurrent ARC insertions. + */ + arc_flush(NULL, FALSE); return (0); } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zvol.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zvol.c index 55de1b4..2c90810 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zvol.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zvol.c @@ -358,7 +358,7 @@ zvol_map_block(spa_t *spa, zilog_t *zilog, const blkptr_t *bp, zvol_extent_t *ze; int bs = ma->ma_zv->zv_volblocksize; - if (BP_IS_HOLE(bp) || + if (bp == NULL || BP_IS_HOLE(bp) || zb->zb_object != ZVOL_OBJ || zb->zb_level != 0) return (0); diff --git a/sys/compat/cloudabi/cloudabi_proc.c b/sys/compat/cloudabi/cloudabi_proc.c index 9c735fa..d917337 100644 --- a/sys/compat/cloudabi/cloudabi_proc.c +++ b/sys/compat/cloudabi/cloudabi_proc.c @@ -46,14 +46,19 @@ cloudabi_sys_proc_exec(struct thread *td, struct cloudabi_sys_proc_exec_args *uap) { struct image_args args; + struct vmspace *oldvmspace; int error; + error = pre_execve(td, &oldvmspace); + if (error != 0) + return (error); error = exec_copyin_data_fds(td, &args, uap->data, uap->datalen, uap->fds, uap->fdslen); if (error == 0) { args.fd = uap->fd; error = kern_execve(td, &args, NULL); } + post_execve(td, error, oldvmspace); return (error); } diff --git a/sys/conf/Makefile.arm b/sys/conf/Makefile.arm index 86b11c6..af5f7da 100644 --- a/sys/conf/Makefile.arm +++ b/sys/conf/Makefile.arm @@ -66,10 +66,6 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\ ${KERNEL_KO}.bin; \ rm ${FULLKERNEL}.noheader -.if defined(MFS_IMAGE) -SYSTEM_LD_TAIL += ;sh ${S}/tools/embed_mfs.sh ${KERNEL_KO}.bin ${MFS_IMAGE}; -.endif - FILES_CPU_FUNC = \ $S/$M/$M/cpufunc_asm_arm9.S \ $S/$M/$M/cpufunc_asm_arm10.S \ diff --git a/sys/conf/NOTES b/sys/conf/NOTES index b0619cb..7bc2048 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -2981,9 +2981,10 @@ options MAXFILES=999 # Random number generator # Only ONE of the below two may be used; they are mutually exclusive. -# If neither is present, then the Fortuna algorithm is used. -options RANDOM_YARROW # Yarrow CSPRNG (old default) -#options RANDOM_DUMMY # Dummy CSPRNG that always blocks +# If neither is present, then the Fortuna algorithm is selected. +#options RANDOM_YARROW # Yarrow CSPRNG (old default) +#options RANDOM_LOADABLE # Allow the algorithm to be loaded as + # a module. # For developers. options RANDOM_DEBUG # Extra debugging messages diff --git a/sys/conf/files b/sys/conf/files index 531647f..dfe9763 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -83,7 +83,7 @@ cam/ctl/ctl_backend_ramdisk.c optional ctl cam/ctl/ctl_cmd_table.c optional ctl cam/ctl/ctl_frontend.c optional ctl cam/ctl/ctl_frontend_cam_sim.c optional ctl -cam/ctl/ctl_frontend_internal.c optional ctl +cam/ctl/ctl_frontend_ioctl.c optional ctl cam/ctl/ctl_frontend_iscsi.c optional ctl cam/ctl/ctl_scsi_all.c optional ctl cam/ctl/ctl_tpc.c optional ctl @@ -145,6 +145,7 @@ cddl/contrib/opensolaris/uts/common/fs/zfs/blkptr.c optional zfs compile-with cddl/contrib/opensolaris/uts/common/fs/zfs/bplist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bpobj.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c optional zfs compile-with "${ZFS_C}" +cddl/contrib/opensolaris/uts/common/fs/zfs/bqueue.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt_zap.c optional zfs compile-with "${ZFS_C}" @@ -174,6 +175,7 @@ cddl/contrib/opensolaris/uts/common/fs/zfs/gzip.c optional zfs compile-with "$ cddl/contrib/opensolaris/uts/common/fs/zfs/lz4.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/metaslab.c optional zfs compile-with "${ZFS_C}" +cddl/contrib/opensolaris/uts/common/fs/zfs/multilist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/range_tree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/rrwlock.c optional zfs compile-with "${ZFS_C}" @@ -548,14 +550,14 @@ crypto/des/des_ecb.c optional crypto | ipsec | netsmb crypto/des/des_setkey.c optional crypto | ipsec | netsmb crypto/rc4/rc4.c optional netgraph_mppc_encryption | kgssapi crypto/rijndael/rijndael-alg-fst.c optional crypto | geom_bde | \ - ipsec | random random_yarrow | random !random_yarrow !random_dummy | wlan_ccmp -crypto/rijndael/rijndael-api-fst.c optional geom_bde | random random_yarrow | random !random_yarrow !random_dummy + ipsec | random !random_loadable | wlan_ccmp +crypto/rijndael/rijndael-api-fst.c optional geom_bde | random !random_loadable crypto/rijndael/rijndael-api.c optional crypto | ipsec | wlan_ccmp crypto/sha1.c optional carp | crypto | ipsec | \ netgraph_mppc_encryption | sctp -crypto/sha2/sha2.c optional crypto | geom_bde | ipsec | random random_yarrow | random !random_yarrow !random_dummy | \ +crypto/sha2/sha2.c optional crypto | geom_bde | ipsec | random !random_loadable | \ sctp | zfs -crypto/sha2/sha256c.c optional crypto | geom_bde | ipsec | random random_yarrow | random !random_yarrow !random_dummy | \ +crypto/sha2/sha256c.c optional crypto | geom_bde | ipsec | random !random_loadable | \ sctp | zfs crypto/siphash/siphash.c optional inet | inet6 crypto/siphash/siphash_test.c optional inet | inet6 @@ -2312,12 +2314,14 @@ rt2860.fw optional rt2860fw | ralfw \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2860.fw" -dev/random/randomdev_none.c optional !random -dev/random/randomdev.c optional random -dev/random/random_harvestq.c optional random random_yarrow | random !random_dummy +dev/random/random_infra.c optional random +dev/random/random_harvestq.c optional random +dev/random/randomdev.c optional random random_yarrow | \ + random !random_yarrow !random_loadable dev/random/yarrow.c optional random random_yarrow -dev/random/fortuna.c optional random !random_yarrow !random_dummy -dev/random/hash.c optional random random_yarrow | random !random_dummy +dev/random/fortuna.c optional random !random_yarrow !random_loadable +dev/random/hash.c optional random random_yarrow | \ + random !random_yarrow !random_loadable dev/rc/rc.c optional rc dev/re/if_re.c optional re dev/rl/if_rl.c optional rl pci diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64 index 2ffe102..8451e00 100644 --- a/sys/conf/files.amd64 +++ b/sys/conf/files.amd64 @@ -40,7 +40,7 @@ ia32_genassym.o standard \ # ia32_assym.h standard \ dependency "$S/kern/genassym.sh ia32_genassym.o" \ - compile-with "env NM='${NM}' sh $S/kern/genassym.sh ia32_genassym.o > ${.TARGET}" \ + compile-with "env NM='${NM}' NMFLAGS='${NMFLAGS}' sh $S/kern/genassym.sh ia32_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "ia32_assym.h" # diff --git a/sys/conf/kern.post.mk b/sys/conf/kern.post.mk index 28ea453..137e72c 100644 --- a/sys/conf/kern.post.mk +++ b/sys/conf/kern.post.mk @@ -121,7 +121,7 @@ gdbinit: .endif .endif -${FULLKERNEL}: ${SYSTEM_DEP} vers.o ${MFS_IMAGE} +${FULLKERNEL}: ${SYSTEM_DEP} vers.o @rm -f ${.TARGET} @echo linking ${.TARGET} ${SYSTEM_LD} @@ -133,9 +133,6 @@ ${FULLKERNEL}: ${SYSTEM_DEP} vers.o ${MFS_IMAGE} ${OBJCOPY} --strip-debug ${.TARGET} .endif ${SYSTEM_LD_TAIL} -.if defined(MFS_IMAGE) - sh ${S}/tools/embed_mfs.sh ${FULLKERNEL} ${MFS_IMAGE} -.endif .if !exists(${.OBJDIR}/.depend) ${SYSTEM_OBJS}: assym.s vnode_if.h ${BEFORE_DEPEND:M*.h} ${MFILES:T:S/.m$/.h/} @@ -177,7 +174,7 @@ hack.So: Makefile ./assym.s: assym.s assym.s: $S/kern/genassym.sh genassym.o - NM='${NM}' sh $S/kern/genassym.sh genassym.o > ${.TARGET} + NM='${NM}' NMFLAGS='${NMFLAGS}' sh $S/kern/genassym.sh genassym.o > ${.TARGET} genassym.o: $S/$M/$M/genassym.c ${CC} -c ${CFLAGS:N-fno-common} $S/$M/$M/genassym.c @@ -301,6 +298,27 @@ vnode_if_newproto.h: vnode_if_typedef.h: ${AWK} -f $S/tools/vnode_if.awk $S/kern/vnode_if.src -q +.if ${MFS_IMAGE:Uno} != "no" +# Generate an object file from the file system image to embed in the kernel +# via linking. Make sure the contents are in the mfs section and rename the +# start/end/size variables to __start_mfs, __stop_mfs, and mfs_size, +# respectively. +embedfs_${MFS_IMAGE:T:R}.o: ${MFS_IMAGE} + ${OBJCOPY} --input-target binary \ + --output-target ${EMBEDFS_FORMAT.${MACHINE_ARCH}} \ + --binary-architecture ${EMBEDFS_ARCH.${MACHINE_ARCH}} \ + ${MFS_IMAGE} ${.TARGET} + ${OBJCOPY} \ + --rename-section .data=mfs,contents,alloc,load,readonly,data \ + --redefine-sym \ + _binary_${MFS_IMAGE:C,[^[:alnum:]],_,g}_size=__mfs_root_size \ + --redefine-sym \ + _binary_${MFS_IMAGE:C,[^[:alnum:]],_,g}_start=mfs_root \ + --redefine-sym \ + _binary_${MFS_IMAGE:C,[^[:alnum:]],_,g}_end=mfs_root_end \ + ${.TARGET} +.endif + # XXX strictly, everything depends on Makefile because changes to ${PROF} # only appear there, but we don't handle that. diff --git a/sys/conf/kern.pre.mk b/sys/conf/kern.pre.mk index cf1b127..3783881 100644 --- a/sys/conf/kern.pre.mk +++ b/sys/conf/kern.pre.mk @@ -191,6 +191,9 @@ SYSTEM_DEP= Makefile ${SYSTEM_OBJS} SYSTEM_OBJS= locore.o ${MDOBJS} ${OBJS} SYSTEM_OBJS+= ${SYSTEM_CFILES:.c=.o} SYSTEM_OBJS+= hack.So +.if ${MFS_IMAGE:Uno} != "no" +SYSTEM_OBJS+= embedfs_${MFS_IMAGE:T:R}.o +.endif SYSTEM_LD= @${LD} -Bdynamic -T ${LDSCRIPT} ${_LDFLAGS} --no-warn-mismatch \ --warn-common --export-dynamic --dynamic-linker /red/herring \ -o ${.TARGET} -X ${SYSTEM_OBJS} vers.o @@ -222,6 +225,32 @@ MKMODULESENV+= DEBUG_FLAGS="${DEBUG}" .endif MKMODULESENV+= _MPATH="${_MPATH}" +# Architecture and output format arguments for objdump to convert image to +# object file +.if ${MFS_IMAGE:Uno} != "no" + +.if !defined(EMBEDFS_FORMAT.${MACHINE_ARCH}) +EMBEDFS_FORMAT.${MACHINE_ARCH}!= awk -F'"' '/OUTPUT_FORMAT/ {print $$2}' ${LDSCRIPT} +.if empty(EMBEDFS_FORMAT.${MACHINE_ARCH}) +.undef EMBEDFS_FORMAT.${MACHINE_ARCH} +.endif +.endif + +.if !defined(EMBEDFS_ARCH.${MACHINE_ARCH}) +EMBEDFS_ARCH.${MACHINE_ARCH}!= sed -n '/OUTPUT_ARCH/s/.*(\(.*\)).*/\1/p' ${LDSCRIPT} +.if empty(EMBEDFS_ARCH.${MACHINE_ARCH}) +.undef EMBEDFS_ARCH.${MACHINE_ARCH} +.endif +.endif + +EMBEDFS_FORMAT.arm?= elf32-littlearm +EMBEDFS_FORMAT.armv6?= elf32-littlearm +EMBEDFS_FORMAT.mips?= elf32-tradbigmips +EMBEDFS_FORMAT.mipsel?= elf32-tradlittlemips +EMBEDFS_FORMAT.mips64?= elf64-tradbigmips +EMBEDFS_FORMAT.mips64el?= elf64-tradlittlemips +.endif + # Detect kernel config options that force stack frames to be turned on. DDB_ENABLED!= grep DDB opt_ddb.h || true ; echo DTR_ENABLED!= grep KDTRACE_FRAME opt_kdtrace.h || true ; echo diff --git a/sys/conf/options b/sys/conf/options index bf6c4a6..30bbc53 100644 --- a/sys/conf/options +++ b/sys/conf/options @@ -711,6 +711,7 @@ DEV_PCI opt_pci.h DEV_PF opt_pf.h DEV_PFLOG opt_pf.h DEV_PFSYNC opt_pf.h +DEV_RANDOM opt_global.h DEV_SPLASH opt_splash.h DEV_VLAN opt_vlan.h @@ -946,13 +947,14 @@ RCTL opt_global.h # The DEBUG option is in global.h as the random harvesting # puts probes all over the place, and it makes little sense # to pollute these headers with an extra include. -# the DUMMY option is in global.h because it is used to -# turn off harvesting all over the kernel. -RANDOM_DEBUG opt_global.h +RANDOM_DEBUG opt_random.h # Which CSPRNG hashes we get. -# These are mutually exclusive. With neither, Fortuna is selected. -RANDOM_DUMMY opt_global.h +# If Yarrow is not chosen, Fortuna is selected. RANDOM_YARROW opt_random.h +# With this, no entropy processor is loaded, but the entropy +# harvesting infrastructure is present. This means an entropy +# processor may be loaded as a module. +RANDOM_LOADABLE opt_random.h # Intel em(4) driver EM_MULTIQUEUE opt_em.h diff --git a/sys/contrib/libnv/nv_impl.h b/sys/contrib/libnv/nv_impl.h index 7928431..b50bdf7 100644 --- a/sys/contrib/libnv/nv_impl.h +++ b/sys/contrib/libnv/nv_impl.h @@ -1,5 +1,6 @@ /*- * Copyright (c) 2013 The FreeBSD Foundation + * Copyright (c) 2013-2015 Mariusz Zaborski <oshogbo@FreeBSD.org> * All rights reserved. * * This software was developed by Pawel Jakub Dawidek under sponsorship from @@ -39,12 +40,14 @@ struct nvpair; typedef struct nvpair nvpair_t; #endif +#define NV_TYPE_NVLIST_ARRAY_NEXT 254 #define NV_TYPE_NVLIST_UP 255 #define NV_TYPE_FIRST NV_TYPE_NULL -#define NV_TYPE_LAST NV_TYPE_BINARY +#define NV_TYPE_LAST NV_TYPE_DESCRIPTOR_ARRAY -#define NV_FLAG_BIG_ENDIAN 0x80 +#define NV_FLAG_BIG_ENDIAN 0x080 +#define NV_FLAG_IN_ARRAY 0x100 #ifdef _KERNEL #define nv_malloc(size) malloc((size), M_NVLIST, M_WAITOK) @@ -86,6 +89,7 @@ typedef struct nvpair nvpair_t; int *nvlist_descriptors(const nvlist_t *nvl, size_t *nitemsp); size_t nvlist_ndescriptors(const nvlist_t *nvl); +void nvlist_set_flags(nvlist_t *nvl, int flags); nvpair_t *nvlist_first_nvpair(const nvlist_t *nvl); nvpair_t *nvlist_next_nvpair(const nvlist_t *nvl, const nvpair_t *nvp); @@ -96,6 +100,7 @@ void nvlist_add_nvpair(nvlist_t *nvl, const nvpair_t *nvp); bool nvlist_move_nvpair(nvlist_t *nvl, nvpair_t *nvp); void nvlist_set_parent(nvlist_t *nvl, nvpair_t *parent); +void nvlist_set_array_next(nvlist_t *nvl, nvpair_t *ele); const nvpair_t *nvlist_get_nvpair(const nvlist_t *nvl, const char *name); @@ -120,18 +125,33 @@ nvpair_t *nvpair_create_stringv(const char *name, const char *valuefmt, va_list nvpair_t *nvpair_create_nvlist(const char *name, const nvlist_t *value); nvpair_t *nvpair_create_descriptor(const char *name, int value); nvpair_t *nvpair_create_binary(const char *name, const void *value, size_t size); +nvpair_t *nvpair_create_bool_array(const char *name, const bool *value, size_t nitems); +nvpair_t *nvpair_create_number_array(const char *name, const uint64_t *value, size_t nitems); +nvpair_t *nvpair_create_string_array(const char *name, const char * const *value, size_t nitems); +nvpair_t *nvpair_create_nvlist_array(const char *name, const nvlist_t * const *value, size_t nitems); +nvpair_t *nvpair_create_descriptor_array(const char *name, const int *value, size_t nitems); nvpair_t *nvpair_move_string(const char *name, char *value); nvpair_t *nvpair_move_nvlist(const char *name, nvlist_t *value); nvpair_t *nvpair_move_descriptor(const char *name, int value); nvpair_t *nvpair_move_binary(const char *name, void *value, size_t size); - -bool nvpair_get_bool(const nvpair_t *nvp); -uint64_t nvpair_get_number(const nvpair_t *nvp); -const char *nvpair_get_string(const nvpair_t *nvp); -const nvlist_t *nvpair_get_nvlist(const nvpair_t *nvp); -int nvpair_get_descriptor(const nvpair_t *nvp); -const void *nvpair_get_binary(const nvpair_t *nvp, size_t *sizep); +nvpair_t *nvpair_move_bool_array(const char *name, bool *value, size_t nitems); +nvpair_t *nvpair_move_nvlist_array(const char *name, nvlist_t **value, size_t nitems); +nvpair_t *nvpair_move_descriptor_array(const char *name, int *value, size_t nitems); +nvpair_t *nvpair_move_number_array(const char *name, uint64_t *value, size_t nitems); +nvpair_t *nvpair_move_string_array(const char *name, char **value, size_t nitems); + +bool nvpair_get_bool(const nvpair_t *nvp); +uint64_t nvpair_get_number(const nvpair_t *nvp); +const char *nvpair_get_string(const nvpair_t *nvp); +const nvlist_t *nvpair_get_nvlist(const nvpair_t *nvp); +int nvpair_get_descriptor(const nvpair_t *nvp); +const void *nvpair_get_binary(const nvpair_t *nvp, size_t *sizep); +const bool *nvpair_get_bool_array(const nvpair_t *nvp, size_t *nitemsp); +const uint64_t *nvpair_get_number_array(const nvpair_t *nvp, size_t *nitemsp); +const char * const *nvpair_get_string_array(const nvpair_t *nvp, size_t *nitemsp); +const nvlist_t * const *nvpair_get_nvlist_array(const nvpair_t *nvp, size_t *nitemsp); +const int *nvpair_get_descriptor_array(const nvpair_t *nvp, size_t *nitemsp); void nvpair_free(nvpair_t *nvp); diff --git a/sys/contrib/libnv/nvlist.c b/sys/contrib/libnv/nvlist.c index edcd074..cf8281e 100644 --- a/sys/contrib/libnv/nvlist.c +++ b/sys/contrib/libnv/nvlist.c @@ -1,5 +1,6 @@ /*- * Copyright (c) 2009-2013 The FreeBSD Foundation + * Copyright (c) 2013-2015 Mariusz Zaborski <oshogbo@FreeBSD.org> * All rights reserved. * * This software was developed by Pawel Jakub Dawidek under sponsorship from @@ -88,7 +89,7 @@ __FBSDID("$FreeBSD$"); #endif #endif -#define NV_FLAG_PRIVATE_MASK (NV_FLAG_BIG_ENDIAN) +#define NV_FLAG_PRIVATE_MASK (NV_FLAG_BIG_ENDIAN | NV_FLAG_IN_ARRAY) #define NV_FLAG_PUBLIC_MASK (NV_FLAG_IGNORE_CASE | NV_FLAG_NO_UNIQUE) #define NV_FLAG_ALL_MASK (NV_FLAG_PRIVATE_MASK | NV_FLAG_PUBLIC_MASK) @@ -98,6 +99,7 @@ struct nvlist { int nvl_error; int nvl_flags; nvpair_t *nvl_parent; + nvpair_t *nvl_array_next; struct nvl_head nvl_head; }; @@ -135,6 +137,7 @@ nvlist_create(int flags) nvl->nvl_error = 0; nvl->nvl_flags = flags; nvl->nvl_parent = NULL; + nvl->nvl_array_next = NULL; TAILQ_INIT(&nvl->nvl_head); nvl->nvl_magic = NVLIST_MAGIC; @@ -157,6 +160,10 @@ nvlist_destroy(nvlist_t *nvl) nvlist_remove_nvpair(nvl, nvp); nvpair_free(nvp); } + if (nvl->nvl_array_next != NULL) + nvpair_free_structure(nvl->nvl_array_next); + nvl->nvl_array_next = NULL; + nvl->nvl_parent = NULL; nvl->nvl_magic = 0; nv_free(nvl); @@ -223,6 +230,59 @@ nvlist_set_parent(nvlist_t *nvl, nvpair_t *parent) nvl->nvl_parent = parent; } +void +nvlist_set_array_next(nvlist_t *nvl, nvpair_t *ele) +{ + + NVLIST_ASSERT(nvl); + + if (ele != NULL) + nvl->nvl_flags |= NV_FLAG_IN_ARRAY; + else + nvl->nvl_flags &= ~NV_FLAG_IN_ARRAY; + + nvl->nvl_array_next = ele; +} + +bool +nvlist_in_array(const nvlist_t *nvl) +{ + + NVLIST_ASSERT(nvl); + + return ((nvl->nvl_flags & NV_FLAG_IN_ARRAY) != 0); +} + +const nvlist_t * +nvlist_get_array_next(const nvlist_t *nvl) +{ + nvpair_t *nvp; + + NVLIST_ASSERT(nvl); + + nvp = nvl->nvl_array_next; + if (nvp == NULL) + return (NULL); + + return (nvpair_get_nvlist(nvp)); +} + +const nvlist_t * +nvlist_get_pararr(const nvlist_t *nvl, void **cookiep) +{ + const nvlist_t *ret; + + ret = nvlist_get_array_next(nvl); + if (ret != NULL) { + if (cookiep != NULL) + *cookiep = NULL; + return (ret); + } + + ret = nvlist_get_parent(nvl, cookiep); + return (ret); +} + bool nvlist_empty(const nvlist_t *nvl) { @@ -239,9 +299,18 @@ nvlist_flags(const nvlist_t *nvl) NVLIST_ASSERT(nvl); PJDLOG_ASSERT(nvl->nvl_error == 0); - PJDLOG_ASSERT((nvl->nvl_flags & ~(NV_FLAG_PUBLIC_MASK)) == 0); - return (nvl->nvl_flags); + return (nvl->nvl_flags & NV_FLAG_PUBLIC_MASK); +} + +void +nvlist_set_flags(nvlist_t *nvl, int flags) +{ + + NVLIST_ASSERT(nvl); + PJDLOG_ASSERT(nvl->nvl_error == 0); + + nvl->nvl_flags = flags; } static void @@ -418,17 +487,129 @@ nvlist_dump(const nvlist_t *nvl, int fd) dprintf(fd, "\n"); break; } + case NV_TYPE_BOOL_ARRAY: + { + const bool *value; + unsigned int ii; + size_t nitems; + + value = nvpair_get_bool_array(nvp, &nitems); + dprintf(fd, " [ "); + for (ii = 0; ii < nitems; ii++) { + dprintf(fd, "%s", value[ii] ? "TRUE" : "FALSE"); + if (ii != nitems - 1) + dprintf(fd, ", "); + } + dprintf(fd, " ]\n"); + break; + } + case NV_TYPE_STRING_ARRAY: + { + const char * const *value; + unsigned int ii; + size_t nitems; + + value = nvpair_get_string_array(nvp, &nitems); + dprintf(fd, " [ "); + for (ii = 0; ii < nitems; ii++) { + if (value[ii] == NULL) + dprintf(fd, "NULL"); + else + dprintf(fd, "\"%s\"", value[ii]); + if (ii != nitems - 1) + dprintf(fd, ", "); + } + dprintf(fd, " ]\n"); + break; + } + case NV_TYPE_NUMBER_ARRAY: + { + const uint64_t *value; + unsigned int ii; + size_t nitems; + + value = nvpair_get_number_array(nvp, &nitems); + dprintf(fd, " [ "); + for (ii = 0; ii < nitems; ii++) { + dprintf(fd, "%ju (%jd) (0x%jx)", + value[ii], value[ii], value[ii]); + if (ii != nitems - 1) + dprintf(fd, ", "); + } + dprintf(fd, " ]\n"); + break; + } + case NV_TYPE_DESCRIPTOR_ARRAY: + { + const int *value; + unsigned int ii; + size_t nitems; + + value = nvpair_get_descriptor_array(nvp, &nitems); + dprintf(fd, " [ "); + for (ii = 0; ii < nitems; ii++) { + dprintf(fd, "%d", value[ii]); + if (ii != nitems - 1) + dprintf(fd, ", "); + } + dprintf(fd, " ]\n"); + break; + } + case NV_TYPE_NVLIST_ARRAY: + { + const nvlist_t * const *value; + unsigned int ii; + size_t nitems; + + value = nvpair_get_nvlist_array(nvp, &nitems); + dprintf(fd, " %zu\n", nitems); + tmpnvl = NULL; + tmpnvp = NULL; + for (ii = 0; ii < nitems; ii++) { + if (nvlist_dump_error_check(value[ii], fd, + level + 1)) { + break; + } + + if (tmpnvl == NULL) { + tmpnvp = nvlist_first_nvpair(value[ii]); + if (tmpnvp != NULL) { + tmpnvl = value[ii]; + } else { + dprintf(fd, "%*s,\n", + (level + 1) * 4, ""); + } + } + } + if (tmpnvp != NULL) { + nvl = tmpnvl; + nvp = tmpnvp; + level++; + continue; + } + break; + } default: PJDLOG_ABORT("Unknown type: %d.", nvpair_type(nvp)); } while ((nvp = nvlist_next_nvpair(nvl, nvp)) == NULL) { - cookie = NULL; - nvl = nvlist_get_parent(nvl, &cookie); - if (nvl == NULL) - return; - nvp = cookie; - level--; + do { + cookie = NULL; + if (nvlist_in_array(nvl)) + dprintf(fd, "%*s,\n", level * 4, ""); + nvl = nvlist_get_pararr(nvl, &cookie); + if (nvl == NULL) + return; + if (nvlist_in_array(nvl) && cookie == NULL) { + nvp = nvlist_first_nvpair(nvl); + } else { + nvp = cookie; + level--; + } + } while (nvp == NULL); + if (nvlist_in_array(nvl) && cookie == NULL) + break; } } } @@ -449,9 +630,11 @@ size_t nvlist_size(const nvlist_t *nvl) { const nvlist_t *tmpnvl; + const nvlist_t * const *nvlarray; const nvpair_t *nvp, *tmpnvp; void *cookie; - size_t size; + size_t size, nitems; + unsigned int ii; NVLIST_ASSERT(nvl); PJDLOG_ASSERT(nvl->nvl_error == 0); @@ -472,16 +655,47 @@ nvlist_size(const nvlist_t *nvl) nvp = tmpnvp; continue; } + } else if (nvpair_type(nvp) == NV_TYPE_NVLIST_ARRAY) { + nvlarray = nvpair_get_nvlist_array(nvp, &nitems); + PJDLOG_ASSERT(nitems > 0); + + size += (nvpair_header_size() + 1) * nitems; + size += sizeof(struct nvlist_header) * nitems; + + tmpnvl = NULL; + tmpnvp = NULL; + for (ii = 0; ii < nitems; ii++) { + PJDLOG_ASSERT(nvlarray[ii]->nvl_error == 0); + tmpnvp = nvlist_first_nvpair(nvlarray[ii]); + if (tmpnvp != NULL) { + tmpnvl = nvlarray[ii]; + break; + } + } + if (tmpnvp != NULL) { + nvp = tmpnvp; + nvl = tmpnvl; + continue; + } + } else { size += nvpair_size(nvp); } while ((nvp = nvlist_next_nvpair(nvl, nvp)) == NULL) { - cookie = NULL; - nvl = nvlist_get_parent(nvl, &cookie); - if (nvl == NULL) - goto out; - nvp = cookie; + do { + cookie = NULL; + nvl = nvlist_get_pararr(nvl, &cookie); + if (nvl == NULL) + goto out; + if (nvlist_in_array(nvl) && cookie == NULL) { + nvp = nvlist_first_nvpair(nvl); + } else { + nvp = cookie; + } + } while (nvp == NULL); + if (nvlist_in_array(nvl) && cookie == NULL) + break; } } @@ -508,13 +722,40 @@ nvlist_xdescriptors(const nvlist_t *nvl, int *descs) *descs = nvpair_get_descriptor(nvp); descs++; break; + case NV_TYPE_DESCRIPTOR_ARRAY: + { + const int *value; + size_t nitems; + unsigned int ii; + + value = nvpair_get_descriptor_array(nvp, + &nitems); + for (ii = 0; ii < nitems; ii++) { + *descs = value[ii]; + descs++; + } + break; + } case NV_TYPE_NVLIST: nvl = nvpair_get_nvlist(nvp); nvp = NULL; break; + case NV_TYPE_NVLIST_ARRAY: + { + const nvlist_t * const *value; + size_t nitems; + + value = nvpair_get_nvlist_array(nvp, &nitems); + PJDLOG_ASSERT(value != NULL); + PJDLOG_ASSERT(nitems > 0); + + nvl = value[0]; + nvp = NULL; + break; + } } } - } while ((nvl = nvlist_get_parent(nvl, (void**)&nvp)) != NULL); + } while ((nvl = nvlist_get_pararr(nvl, (void**)&nvp)) != NULL); return (descs); } @@ -564,9 +805,31 @@ nvlist_ndescriptors(const nvlist_t *nvl) nvl = nvpair_get_nvlist(nvp); nvp = NULL; break; + case NV_TYPE_NVLIST_ARRAY: + { + const nvlist_t * const *value; + size_t nitems; + + value = nvpair_get_nvlist_array(nvp, &nitems); + PJDLOG_ASSERT(value != NULL); + PJDLOG_ASSERT(nitems > 0); + + nvl = value[0]; + nvp = NULL; + break; + } + case NV_TYPE_DESCRIPTOR_ARRAY: + { + size_t nitems; + + (void)nvpair_get_descriptor_array(nvp, + &nitems); + ndescs += nitems; + break; + } } } - } while ((nvl = nvlist_get_parent(nvl, (void**)&nvp)) != NULL); + } while ((nvl = nvlist_get_pararr(nvl, (void**)&nvp)) != NULL); return (ndescs); #else @@ -661,24 +924,86 @@ nvlist_xpack(const nvlist_t *nvl, int64_t *fdidxp, size_t *sizep) case NV_TYPE_DESCRIPTOR: ptr = nvpair_pack_descriptor(nvp, ptr, fdidxp, &left); break; + case NV_TYPE_DESCRIPTOR_ARRAY: + ptr = nvpair_pack_descriptor_array(nvp, ptr, fdidxp, + &left); + break; #endif case NV_TYPE_BINARY: ptr = nvpair_pack_binary(nvp, ptr, &left); break; + case NV_TYPE_BOOL_ARRAY: + ptr = nvpair_pack_bool_array(nvp, ptr, &left); + break; + case NV_TYPE_NUMBER_ARRAY: + ptr = nvpair_pack_number_array(nvp, ptr, &left); + break; + case NV_TYPE_STRING_ARRAY: + ptr = nvpair_pack_string_array(nvp, ptr, &left); + break; + case NV_TYPE_NVLIST_ARRAY: + { + const nvlist_t * const * value; + size_t nitems; + unsigned int ii; + + tmpnvl = NULL; + value = nvpair_get_nvlist_array(nvp, &nitems); + for (ii = 0; ii < nitems; ii++) { + ptr = nvlist_pack_header(value[ii], ptr, &left); + if (ptr == NULL) + goto out; + tmpnvp = nvlist_first_nvpair(value[ii]); + if (tmpnvp != NULL) { + tmpnvl = value[ii]; + break; + } + ptr = nvpair_pack_nvlist_array_next(ptr, &left); + if (ptr == NULL) + goto out; + } + if (tmpnvl != NULL) { + nvl = tmpnvl; + nvp = tmpnvp; + continue; + } + break; + } default: PJDLOG_ABORT("Invalid type (%d).", nvpair_type(nvp)); } if (ptr == NULL) goto fail; while ((nvp = nvlist_next_nvpair(nvl, nvp)) == NULL) { - cookie = NULL; - nvl = nvlist_get_parent(nvl, &cookie); - if (nvl == NULL) - goto out; - nvp = cookie; - ptr = nvpair_pack_nvlist_up(ptr, &left); - if (ptr == NULL) - goto fail; + do { + cookie = NULL; + if (nvlist_in_array(nvl)) { + ptr = nvpair_pack_nvlist_array_next(ptr, + &left); + if (ptr == NULL) + goto fail; + } + nvl = nvlist_get_pararr(nvl, &cookie); + if (nvl == NULL) + goto out; + if (nvlist_in_array(nvl) && cookie == NULL) { + nvp = nvlist_first_nvpair(nvl); + ptr = nvlist_pack_header(nvl, ptr, + &left); + if (ptr == NULL) + goto fail; + } else if (nvpair_type((nvpair_t *)cookie) != + NV_TYPE_NVLIST_ARRAY) { + ptr = nvpair_pack_nvlist_up(ptr, &left); + if (ptr == NULL) + goto fail; + nvp = cookie; + } else { + nvp = cookie; + } + } while (nvp == NULL); + if (nvlist_in_array(nvl) && cookie == NULL) + break; } } @@ -741,6 +1066,7 @@ nvlist_unpack_header(nvlist_t *nvl, const unsigned char *ptr, size_t nfds, bool *isbep, size_t *leftp) { struct nvlist_header nvlhdr; + int inarrayf; if (*leftp < sizeof(nvlhdr)) goto failed; @@ -762,7 +1088,8 @@ nvlist_unpack_header(nvlist_t *nvl, const unsigned char *ptr, size_t nfds, if ((nvlhdr.nvlh_flags & ~NV_FLAG_ALL_MASK) != 0) goto failed; - nvl->nvl_flags = (nvlhdr.nvlh_flags & NV_FLAG_PUBLIC_MASK); + inarrayf = (nvl->nvl_flags & NV_FLAG_IN_ARRAY); + nvl->nvl_flags = (nvlhdr.nvlh_flags & NV_FLAG_PUBLIC_MASK) | inarrayf; ptr += sizeof(nvlhdr); if (isbep != NULL) @@ -780,7 +1107,7 @@ nvlist_xunpack(const void *buf, size_t size, const int *fds, size_t nfds, int flags) { const unsigned char *ptr; - nvlist_t *nvl, *retnvl, *tmpnvl; + nvlist_t *nvl, *retnvl, *tmpnvl, *array; nvpair_t *nvp; size_t left; bool isbe; @@ -790,7 +1117,7 @@ nvlist_xunpack(const void *buf, size_t size, const int *fds, size_t nfds, left = size; ptr = buf; - tmpnvl = NULL; + tmpnvl = array = NULL; nvl = retnvl = nvlist_create(0); if (nvl == NULL) goto failed; @@ -832,6 +1159,10 @@ nvlist_xunpack(const void *buf, size_t size, const int *fds, size_t nfds, ptr = nvpair_unpack_descriptor(isbe, nvp, ptr, &left, fds, nfds); break; + case NV_TYPE_DESCRIPTOR_ARRAY: + ptr = nvpair_unpack_descriptor_array(isbe, nvp, ptr, + &left, fds, nfds); + break; #endif case NV_TYPE_BINARY: ptr = nvpair_unpack_binary(isbe, nvp, ptr, &left); @@ -842,6 +1173,44 @@ nvlist_xunpack(const void *buf, size_t size, const int *fds, size_t nfds, nvl = nvpair_nvlist(nvl->nvl_parent); nvpair_free_structure(nvp); continue; + case NV_TYPE_NVLIST_ARRAY_NEXT: + if (nvl->nvl_array_next == NULL) { + if (nvl->nvl_parent == NULL) + goto failed; + nvl = nvpair_nvlist(nvl->nvl_parent); + } else { + nvl = __DECONST(nvlist_t *, + nvlist_get_array_next(nvl)); + ptr = nvlist_unpack_header(nvl, ptr, nfds, + &isbe, &left); + if (ptr == NULL) + goto failed; + } + nvpair_free_structure(nvp); + continue; + case NV_TYPE_BOOL_ARRAY: + ptr = nvpair_unpack_bool_array(isbe, nvp, ptr, &left); + break; + case NV_TYPE_NUMBER_ARRAY: + ptr = nvpair_unpack_number_array(isbe, nvp, ptr, &left); + break; + case NV_TYPE_STRING_ARRAY: + ptr = nvpair_unpack_string_array(isbe, nvp, ptr, &left); + break; + case NV_TYPE_NVLIST_ARRAY: + ptr = nvpair_unpack_nvlist_array(isbe, nvp, ptr, &left, + &array); + if (ptr == NULL) + goto failed; + tmpnvl = array; + while (array != NULL) { + nvlist_set_parent(array, nvp); + array = __DECONST(nvlist_t *, + nvlist_get_array_next(array)); + } + ptr = nvlist_unpack_header(tmpnvl, ptr, nfds, &isbe, + &left); + break; default: PJDLOG_ABORT("Invalid type (%d).", nvpair_type(nvp)); } @@ -1062,10 +1431,15 @@ NVLIST_EXISTS(bool, BOOL) NVLIST_EXISTS(number, NUMBER) NVLIST_EXISTS(string, STRING) NVLIST_EXISTS(nvlist, NVLIST) +NVLIST_EXISTS(binary, BINARY) +NVLIST_EXISTS(bool_array, BOOL_ARRAY) +NVLIST_EXISTS(number_array, NUMBER_ARRAY) +NVLIST_EXISTS(string_array, STRING_ARRAY) +NVLIST_EXISTS(nvlist_array, NVLIST_ARRAY) #ifndef _KERNEL NVLIST_EXISTS(descriptor, DESCRIPTOR) +NVLIST_EXISTS(descriptor_array, DESCRIPTOR_ARRAY) #endif -NVLIST_EXISTS(binary, BINARY) #undef NVLIST_EXISTS @@ -1198,6 +1572,37 @@ NVLIST_ADD(int, descriptor); #undef NVLIST_ADD +#define NVLIST_ADD_ARRAY(vtype, type) \ +void \ +nvlist_add_##type##_array(nvlist_t *nvl, const char *name, vtype value, \ + size_t nitems) \ +{ \ + nvpair_t *nvp; \ + \ + if (nvlist_error(nvl) != 0) { \ + ERRNO_SET(nvlist_error(nvl)); \ + return; \ + } \ + \ + nvp = nvpair_create_##type##_array(name, value, nitems); \ + if (nvp == NULL) { \ + nvl->nvl_error = ERRNO_OR_DEFAULT(ENOMEM); \ + ERRNO_SET(nvl->nvl_error); \ + } else { \ + (void)nvlist_move_nvpair(nvl, nvp); \ + } \ +} + +NVLIST_ADD_ARRAY(const bool *, bool) +NVLIST_ADD_ARRAY(const uint64_t *, number) +NVLIST_ADD_ARRAY(const char * const *, string) +NVLIST_ADD_ARRAY(const nvlist_t * const *, nvlist) +#ifndef _KERNEL +NVLIST_ADD_ARRAY(const int *, descriptor) +#endif + +#undef NVLIST_ADD_ARRAY + bool nvlist_move_nvpair(nvlist_t *nvl, nvpair_t *nvp) { @@ -1306,6 +1711,131 @@ nvlist_move_binary(nvlist_t *nvl, const char *name, void *value, size_t size) } } +void +nvlist_move_bool_array(nvlist_t *nvl, const char *name, bool *value, + size_t nitems) +{ + nvpair_t *nvp; + + if (nvlist_error(nvl) != 0) { + nv_free(value); + ERRNO_SET(nvlist_error(nvl)); + return; + } + + nvp = nvpair_move_bool_array(name, value, nitems); + if (nvp == NULL) { + nvl->nvl_error = ERRNO_OR_DEFAULT(ENOMEM); + ERRNO_SET(nvl->nvl_error); + } else { + (void)nvlist_move_nvpair(nvl, nvp); + } +} + +void +nvlist_move_string_array(nvlist_t *nvl, const char *name, char **value, + size_t nitems) +{ + nvpair_t *nvp; + size_t i; + + if (nvlist_error(nvl) != 0) { + if (value != NULL) { + for (i = 0; i < nitems; i++) + nv_free(value[i]); + nv_free(value); + } + ERRNO_SET(nvlist_error(nvl)); + return; + } + + nvp = nvpair_move_string_array(name, value, nitems); + if (nvp == NULL) { + nvl->nvl_error = ERRNO_OR_DEFAULT(ENOMEM); + ERRNO_SET(nvl->nvl_error); + } else { + (void)nvlist_move_nvpair(nvl, nvp); + } +} + +void +nvlist_move_nvlist_array(nvlist_t *nvl, const char *name, nvlist_t **value, + size_t nitems) +{ + nvpair_t *nvp; + size_t i; + + if (nvlist_error(nvl) != 0) { + if (value != NULL) { + for (i = 0; i < nitems; i++) { + if (nvlist_get_pararr(value[i], NULL) == NULL) + nvlist_destroy(value[i]); + } + } + nv_free(value); + ERRNO_SET(nvlist_error(nvl)); + return; + } + + nvp = nvpair_move_nvlist_array(name, value, nitems); + if (nvp == NULL) { + nvl->nvl_error = ERRNO_OR_DEFAULT(ENOMEM); + ERRNO_SET(nvl->nvl_error); + } else { + (void)nvlist_move_nvpair(nvl, nvp); + } +} + +void +nvlist_move_number_array(nvlist_t *nvl, const char *name, uint64_t *value, + size_t nitems) +{ + nvpair_t *nvp; + + if (nvlist_error(nvl) != 0) { + nv_free(value); + ERRNO_SET(nvlist_error(nvl)); + return; + } + + nvp = nvpair_move_number_array(name, value, nitems); + if (nvp == NULL) { + nvl->nvl_error = ERRNO_OR_DEFAULT(ENOMEM); + ERRNO_SET(nvl->nvl_error); + } else { + (void)nvlist_move_nvpair(nvl, nvp); + } +} + +#ifndef _KERNEL +void +nvlist_move_descriptor_array(nvlist_t *nvl, const char *name, int *value, + size_t nitems) +{ + nvpair_t *nvp; + size_t i; + + if (nvlist_error(nvl) != 0) { + if (value != 0) { + for (i = 0; i < nitems; i++) + close(value[i]); + nv_free(value); + } + + ERRNO_SET(nvlist_error(nvl)); + return; + } + + nvp = nvpair_move_descriptor_array(name, value, nitems); + if (nvp == NULL) { + nvl->nvl_error = ERRNO_OR_DEFAULT(ENOMEM); + ERRNO_SET(nvl->nvl_error); + } else { + (void)nvlist_move_nvpair(nvl, nvp); + } +} +#endif + const nvpair_t * nvlist_get_nvpair(const nvlist_t *nvl, const char *name) { @@ -1347,6 +1877,29 @@ nvlist_get_binary(const nvlist_t *nvl, const char *name, size_t *sizep) return (nvpair_get_binary(nvp, sizep)); } +#define NVLIST_GET_ARRAY(ftype, type, TYPE) \ +ftype \ +nvlist_get_##type##_array(const nvlist_t *nvl, const char *name, \ + size_t *nitems) \ +{ \ + const nvpair_t *nvp; \ + \ + nvp = nvlist_find(nvl, NV_TYPE_##TYPE##_ARRAY, name); \ + if (nvp == NULL) \ + nvlist_report_missing(NV_TYPE_##TYPE##_ARRAY, name); \ + return (nvpair_get_##type##_array(nvp, nitems)); \ +} + +NVLIST_GET_ARRAY(const bool *, bool, BOOL) +NVLIST_GET_ARRAY(const uint64_t *, number, NUMBER) +NVLIST_GET_ARRAY(const char * const *, string, STRING) +NVLIST_GET_ARRAY(const nvlist_t * const *, nvlist, NVLIST) +#ifndef _KERNEL +NVLIST_GET_ARRAY(const int *, descriptor, DESCRIPTOR) +#endif + +#undef NVLIST_GET_ARRAY + #define NVLIST_TAKE(ftype, type, TYPE) \ ftype \ nvlist_take_##type(nvlist_t *nvl, const char *name) \ @@ -1389,6 +1942,31 @@ nvlist_take_binary(nvlist_t *nvl, const char *name, size_t *sizep) return (value); } +#define NVLIST_TAKE_ARRAY(ftype, type, TYPE) \ +ftype \ +nvlist_take_##type##_array(nvlist_t *nvl, const char *name, \ + size_t *nitems) \ +{ \ + nvpair_t *nvp; \ + ftype value; \ + \ + nvp = nvlist_find(nvl, NV_TYPE_##TYPE##_ARRAY, name); \ + if (nvp == NULL) \ + nvlist_report_missing(NV_TYPE_##TYPE##_ARRAY, name); \ + value = (ftype)(intptr_t)nvpair_get_##type##_array(nvp, nitems);\ + nvlist_remove_nvpair(nvl, nvp); \ + nvpair_free_structure(nvp); \ + return (value); \ +} + +NVLIST_TAKE_ARRAY(bool *, bool, BOOL) +NVLIST_TAKE_ARRAY(uint64_t *, number, NUMBER) +NVLIST_TAKE_ARRAY(char **, string, STRING) +NVLIST_TAKE_ARRAY(nvlist_t **, nvlist, NVLIST) +#ifndef _KERNEL +NVLIST_TAKE_ARRAY(int *, descriptor, DESCRIPTOR) +#endif + void nvlist_remove_nvpair(nvlist_t *nvl, nvpair_t *nvp) { @@ -1420,10 +1998,15 @@ NVLIST_FREE(bool, BOOL) NVLIST_FREE(number, NUMBER) NVLIST_FREE(string, STRING) NVLIST_FREE(nvlist, NVLIST) +NVLIST_FREE(binary, BINARY) +NVLIST_FREE(bool_array, BOOL_ARRAY) +NVLIST_FREE(number_array, NUMBER_ARRAY) +NVLIST_FREE(string_array, STRING_ARRAY) +NVLIST_FREE(nvlist_array, NVLIST_ARRAY) #ifndef _KERNEL NVLIST_FREE(descriptor, DESCRIPTOR) +NVLIST_FREE(descriptor_array, DESCRIPTOR_ARRAY) #endif -NVLIST_FREE(binary, BINARY) #undef NVLIST_FREE diff --git a/sys/contrib/libnv/nvlist_impl.h b/sys/contrib/libnv/nvlist_impl.h index 18ccebf..9952db8 100644 --- a/sys/contrib/libnv/nvlist_impl.h +++ b/sys/contrib/libnv/nvlist_impl.h @@ -1,5 +1,6 @@ /*- * Copyright (c) 2013 The FreeBSD Foundation + * Copyright (c) 2013-2015 Mariusz Zaborski <oshogbo@FreeBSD.org> * All rights reserved. * * This software was developed by Pawel Jakub Dawidek under sponsorship from diff --git a/sys/contrib/libnv/nvpair.c b/sys/contrib/libnv/nvpair.c index 7146767..1e3bd0e 100644 --- a/sys/contrib/libnv/nvpair.c +++ b/sys/contrib/libnv/nvpair.c @@ -1,5 +1,6 @@ /*- * Copyright (c) 2009-2013 The FreeBSD Foundation + * Copyright (c) 2013-2015 Mariusz Zaborski <oshogbo@FreeBSD.org> * All rights reserved. * * This software was developed by Pawel Jakub Dawidek under sponsorship from @@ -86,6 +87,7 @@ struct nvpair { int nvp_type; uint64_t nvp_data; size_t nvp_datasize; + size_t nvp_nitems; /* Used only for array types. */ nvlist_t *nvp_list; TAILQ_ENTRY(nvpair) nvp_next; }; @@ -99,6 +101,7 @@ struct nvpair_header { uint8_t nvph_type; uint16_t nvph_namesize; uint64_t nvph_datasize; + uint64_t nvph_nitems; } __packed; @@ -109,6 +112,36 @@ nvpair_assert(const nvpair_t *nvp) NVPAIR_ASSERT(nvp); } +static nvpair_t * +nvpair_allocv(const char *name, int type, uint64_t data, size_t datasize, + size_t nitems) +{ + nvpair_t *nvp; + size_t namelen; + + PJDLOG_ASSERT(type >= NV_TYPE_FIRST && type <= NV_TYPE_LAST); + + namelen = strlen(name); + if (namelen >= NV_NAME_MAX) { + ERRNO_SET(ENAMETOOLONG); + return (NULL); + } + + nvp = nv_calloc(1, sizeof(*nvp) + namelen + 1); + if (nvp != NULL) { + nvp->nvp_name = (char *)(nvp + 1); + memcpy(nvp->nvp_name, name, namelen); + nvp->nvp_name[namelen] = '\0'; + nvp->nvp_type = type; + nvp->nvp_data = data; + nvp->nvp_datasize = datasize; + nvp->nvp_nitems = nitems; + nvp->nvp_magic = NVPAIR_MAGIC; + } + + return (nvp); +} + nvlist_t * nvpair_nvlist(const nvpair_t *nvp) { @@ -162,6 +195,19 @@ nvpair_remove_nvlist(nvpair_t *nvp) nvlist_set_parent(nvl, NULL); } +static void +nvpair_remove_nvlist_array(nvpair_t *nvp) +{ + nvlist_t **nvlarray; + size_t count, i; + + /* XXX: DECONST is bad, mkay? */ + nvlarray = __DECONST(nvlist_t **, + nvpair_get_nvlist_array(nvp, &count)); + for (i = 0; i < count; i++) + nvlist_set_array_next(nvlarray[i], NULL); +} + void nvpair_remove(struct nvl_head *head, nvpair_t *nvp, const nvlist_t *nvl) { @@ -171,6 +217,8 @@ nvpair_remove(struct nvl_head *head, nvpair_t *nvp, const nvlist_t *nvl) if (nvpair_type(nvp) == NV_TYPE_NVLIST) nvpair_remove_nvlist(nvp); + else if (nvpair_type(nvp) == NV_TYPE_NVLIST_ARRAY) + nvpair_remove_nvlist_array(nvp); TAILQ_REMOVE(head, nvp, nvp_next); nvp->nvp_list = NULL; @@ -204,16 +252,36 @@ nvpair_clone(const nvpair_t *nvp) case NV_TYPE_NVLIST: newnvp = nvpair_create_nvlist(name, nvpair_get_nvlist(nvp)); break; + case NV_TYPE_BINARY: + data = nvpair_get_binary(nvp, &datasize); + newnvp = nvpair_create_binary(name, data, datasize); + break; + case NV_TYPE_BOOL_ARRAY: + data = nvpair_get_bool_array(nvp, &datasize); + newnvp = nvpair_create_bool_array(name, data, datasize); + break; + case NV_TYPE_NUMBER_ARRAY: + data = nvpair_get_number_array(nvp, &datasize); + newnvp = nvpair_create_number_array(name, data, datasize); + break; + case NV_TYPE_STRING_ARRAY: + data = nvpair_get_string_array(nvp, &datasize); + newnvp = nvpair_create_string_array(name, data, datasize); + break; + case NV_TYPE_NVLIST_ARRAY: + data = nvpair_get_nvlist_array(nvp, &datasize); + newnvp = nvpair_create_nvlist_array(name, data, datasize); + break; #ifndef _KERNEL case NV_TYPE_DESCRIPTOR: newnvp = nvpair_create_descriptor(name, nvpair_get_descriptor(nvp)); break; -#endif - case NV_TYPE_BINARY: - data = nvpair_get_binary(nvp, &datasize); - newnvp = nvpair_create_binary(name, data, datasize); + case NV_TYPE_DESCRIPTOR_ARRAY: + data = nvpair_get_descriptor_array(nvp, &datasize); + newnvp = nvpair_create_descriptor_array(name, data, datasize); break; +#endif default: PJDLOG_ABORT("Unknown type: %d.", nvpair_type(nvp)); } @@ -250,6 +318,7 @@ nvpair_pack_header(const nvpair_t *nvp, unsigned char *ptr, size_t *leftp) PJDLOG_ASSERT(namesize > 0 && namesize <= UINT16_MAX); nvphdr.nvph_namesize = namesize; nvphdr.nvph_datasize = nvp->nvp_datasize; + nvphdr.nvph_nitems = nvp->nvp_nitems; PJDLOG_ASSERT(*leftp >= sizeof(nvphdr)); memcpy(ptr, &nvphdr, sizeof(nvphdr)); ptr += sizeof(nvphdr); @@ -336,6 +405,32 @@ nvpair_pack_nvlist_up(unsigned char *ptr, size_t *leftp) nvphdr.nvph_type = NV_TYPE_NVLIST_UP; nvphdr.nvph_namesize = namesize; nvphdr.nvph_datasize = 0; + nvphdr.nvph_nitems = 0; + PJDLOG_ASSERT(*leftp >= sizeof(nvphdr)); + memcpy(ptr, &nvphdr, sizeof(nvphdr)); + ptr += sizeof(nvphdr); + *leftp -= sizeof(nvphdr); + + PJDLOG_ASSERT(*leftp >= namesize); + memcpy(ptr, name, namesize); + ptr += namesize; + *leftp -= namesize; + + return (ptr); +} + +unsigned char * +nvpair_pack_nvlist_array_next(unsigned char *ptr, size_t *leftp) +{ + struct nvpair_header nvphdr; + size_t namesize; + const char *name = ""; + + namesize = 1; + nvphdr.nvph_type = NV_TYPE_NVLIST_ARRAY_NEXT; + nvphdr.nvph_namesize = namesize; + nvphdr.nvph_datasize = 0; + nvphdr.nvph_nitems = 0; PJDLOG_ASSERT(*leftp >= sizeof(nvphdr)); memcpy(ptr, &nvphdr, sizeof(nvphdr)); ptr += sizeof(nvphdr); @@ -396,6 +491,106 @@ nvpair_pack_binary(const nvpair_t *nvp, unsigned char *ptr, size_t *leftp) return (ptr); } +unsigned char * +nvpair_pack_bool_array(const nvpair_t *nvp, unsigned char *ptr, size_t *leftp) +{ + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_BOOL_ARRAY); + PJDLOG_ASSERT(*leftp >= nvp->nvp_datasize); + + memcpy(ptr, (const void *)(intptr_t)nvp->nvp_data, nvp->nvp_datasize); + ptr += nvp->nvp_datasize; + *leftp -= nvp->nvp_datasize; + + return (ptr); +} + +unsigned char * +nvpair_pack_number_array(const nvpair_t *nvp, unsigned char *ptr, size_t *leftp) +{ + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_NUMBER_ARRAY); + PJDLOG_ASSERT(*leftp >= nvp->nvp_datasize); + + memcpy(ptr, (const void *)(intptr_t)nvp->nvp_data, nvp->nvp_datasize); + ptr += nvp->nvp_datasize; + *leftp -= nvp->nvp_datasize; + + return (ptr); +} + +unsigned char * +nvpair_pack_string_array(const nvpair_t *nvp, unsigned char *ptr, size_t *leftp) +{ + unsigned int ii; + size_t size, len; + const char * const *array; + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_STRING_ARRAY); + PJDLOG_ASSERT(*leftp >= nvp->nvp_datasize); + + size = 0; + array = nvpair_get_string_array(nvp, NULL); + PJDLOG_ASSERT(array != NULL); + + for (ii = 0; ii < nvp->nvp_nitems; ii++) { + len = strlen(array[ii]) + 1; + PJDLOG_ASSERT(*leftp >= len); + + memcpy(ptr, (const void *)array[ii], len); + size += len; + ptr += len; + *leftp -= len; + } + + PJDLOG_ASSERT(size == nvp->nvp_datasize); + + return (ptr); +} + +#ifndef _KERNEL +unsigned char * +nvpair_pack_descriptor_array(const nvpair_t *nvp, unsigned char *ptr, + int64_t *fdidxp, size_t *leftp) +{ + int64_t value; + const int *array; + unsigned int ii; + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_DESCRIPTOR_ARRAY); + PJDLOG_ASSERT(*leftp >= nvp->nvp_datasize); + + array = nvpair_get_descriptor_array(nvp, NULL); + PJDLOG_ASSERT(array != NULL); + + for (ii = 0; ii < nvp->nvp_nitems; ii++) { + PJDLOG_ASSERT(*leftp >= sizeof(value)); + + value = array[ii]; + if (value != -1) { + /* + * If there is a real descriptor here, we change its + * number to position in the array of descriptors send + * via control message. + */ + PJDLOG_ASSERT(fdidxp != NULL); + + value = *fdidxp; + (*fdidxp)++; + } + memcpy(ptr, &value, sizeof(value)); + ptr += sizeof(value); + *leftp -= sizeof(value); + } + + return (ptr); +} +#endif + void nvpair_init_datasize(nvpair_t *nvp) { @@ -430,7 +625,8 @@ nvpair_unpack_header(bool isbe, nvpair_t *nvp, const unsigned char *ptr, goto failed; #endif if (nvphdr.nvph_type > NV_TYPE_LAST && - nvphdr.nvph_type != NV_TYPE_NVLIST_UP) { + nvphdr.nvph_type != NV_TYPE_NVLIST_UP && + nvphdr.nvph_type != NV_TYPE_NVLIST_ARRAY_NEXT) { goto failed; } @@ -467,6 +663,7 @@ nvpair_unpack_header(bool isbe, nvpair_t *nvp, const unsigned char *ptr, nvp->nvp_type = nvphdr.nvph_type; nvp->nvp_data = 0; nvp->nvp_datasize = nvphdr.nvph_datasize; + nvp->nvp_nitems = nvphdr.nvph_nitems; return (ptr); failed: @@ -540,6 +737,7 @@ nvpair_unpack_number(bool isbe, nvpair_t *nvp, const unsigned char *ptr, nvp->nvp_data = be64dec(ptr); else nvp->nvp_data = le64dec(ptr); + ptr += sizeof(uint64_t); *leftp -= sizeof(uint64_t); @@ -670,6 +868,234 @@ nvpair_unpack_binary(bool isbe __unused, nvpair_t *nvp, } const unsigned char * +nvpair_unpack_bool_array(bool isbe __unused, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp) +{ + uint8_t *value; + size_t size; + unsigned int i; + + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_BOOL_ARRAY); + + size = sizeof(*value) * nvp->nvp_nitems; + if (nvp->nvp_datasize != size || *leftp < size || + nvp->nvp_nitems == 0 || size < nvp->nvp_nitems) { + ERRNO_SET(EINVAL); + return (NULL); + } + + value = nv_malloc(size); + if (value == NULL) + return (NULL); + + for (i = 0; i < nvp->nvp_nitems; i++) { + value[i] = *(const uint8_t *)ptr; + + ptr += sizeof(*value); + *leftp -= sizeof(*value); + } + + nvp->nvp_data = (uint64_t)(uintptr_t)value; + + return (ptr); +} + +const unsigned char * +nvpair_unpack_number_array(bool isbe, nvpair_t *nvp, const unsigned char *ptr, + size_t *leftp) +{ + uint64_t *value; + size_t size; + unsigned int i; + + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_NUMBER_ARRAY); + + size = sizeof(*value) * nvp->nvp_nitems; + if (nvp->nvp_datasize != size || *leftp < size || + nvp->nvp_nitems == 0 || size < nvp->nvp_nitems) { + ERRNO_SET(EINVAL); + return (NULL); + } + + value = nv_malloc(size); + if (value == NULL) + return (NULL); + + for (i = 0; i < nvp->nvp_nitems; i++) { + if (isbe) + value[i] = be64dec(ptr); + else + value[i] = le64dec(ptr); + + ptr += sizeof(*value); + *leftp -= sizeof(*value); + } + + nvp->nvp_data = (uint64_t)(uintptr_t)value; + + return (ptr); +} + +const unsigned char * +nvpair_unpack_string_array(bool isbe __unused, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp) +{ + ssize_t size; + size_t len; + const char *tmp; + char **value; + unsigned int ii, j; + + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_STRING_ARRAY); + + if (*leftp < nvp->nvp_datasize || nvp->nvp_datasize == 0 || + nvp->nvp_nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + size = nvp->nvp_datasize; + tmp = (const char *)ptr; + for (ii = 0; ii < nvp->nvp_nitems; ii++) { + len = strnlen(tmp, size - 1) + 1; + size -= len; + if (size < 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + tmp += len; + } + if (size != 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + value = nv_malloc(sizeof(*value) * nvp->nvp_nitems); + if (value == NULL) + return (NULL); + + for (ii = 0; ii < nvp->nvp_nitems; ii++) { + value[ii] = nv_strdup((const char *)ptr); + if (value[ii] == NULL) + goto out; + len = strlen(value[ii]) + 1; + ptr += len; + *leftp -= len; + } + nvp->nvp_data = (uint64_t)(uintptr_t)value; + + return (ptr); +out: + for (j = 0; j < ii; j++) + nv_free(value[j]); + nv_free(value); + return (NULL); +} + +#ifndef _KERNEL +const unsigned char * +nvpair_unpack_descriptor_array(bool isbe, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp, const int *fds, size_t nfds) +{ + int64_t idx; + size_t size; + unsigned int ii; + int *array; + + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_DESCRIPTOR_ARRAY); + + size = sizeof(idx) * nvp->nvp_nitems; + if (nvp->nvp_datasize != size || *leftp < size || + nvp->nvp_nitems == 0 || size < nvp->nvp_nitems) { + ERRNO_SET(EINVAL); + return (NULL); + } + + array = (int *)nv_malloc(size); + if (array == NULL) + return (NULL); + + for (ii = 0; ii < nvp->nvp_nitems; ii++) { + if (isbe) + idx = be64dec(ptr); + else + idx = le64dec(ptr); + + if (idx < 0) { + ERRNO_SET(EINVAL); + nv_free(array); + return (NULL); + } + + if ((size_t)idx >= nfds) { + ERRNO_SET(EINVAL); + nv_free(array); + return (NULL); + } + + array[ii] = (uint64_t)fds[idx]; + + ptr += sizeof(idx); + *leftp -= sizeof(idx); + } + + nvp->nvp_data = (uint64_t)(uintptr_t)array; + + return (ptr); +} +#endif + +const unsigned char * +nvpair_unpack_nvlist_array(bool isbe __unused, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp, nvlist_t **firstel) +{ + nvlist_t **value; + nvpair_t *tmpnvp; + unsigned int ii, j; + size_t sizeup; + + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_NVLIST_ARRAY); + + sizeup = sizeof(struct nvpair_header) * nvp->nvp_nitems; + if (nvp->nvp_nitems == 0 || sizeup < nvp->nvp_nitems || + sizeup > *leftp) { + ERRNO_SET(EINVAL); + return (NULL); + } + + value = nv_malloc(nvp->nvp_nitems * sizeof(*value)); + if (value == NULL) + return (NULL); + + for (ii = 0; ii < nvp->nvp_nitems; ii++) { + value[ii] = nvlist_create(0); + if (value[ii] == NULL) + goto fail; + if (ii > 0) { + tmpnvp = nvpair_allocv(" ", NV_TYPE_NVLIST, + (uint64_t)(uintptr_t)value[ii], 0, 0); + if (tmpnvp == NULL) + goto fail; + nvlist_set_array_next(value[ii - 1], tmpnvp); + } + } + nvlist_set_flags(value[nvp->nvp_nitems - 1], NV_FLAG_IN_ARRAY); + + nvp->nvp_data = (uint64_t)(uintptr_t)value; + *firstel = value[0]; + + return (ptr); +fail: + ERRNO_SAVE(); + for (j = 0; j < ii; j++) + nvlist_destroy(value[j]); + nv_free(value); + ERRNO_RESTORE(); + + return (NULL); +} + +const unsigned char * nvpair_unpack(bool isbe, const unsigned char *ptr, size_t *leftp, nvpair_t **nvpp) { @@ -717,34 +1143,6 @@ nvpair_name(const nvpair_t *nvp) return (nvp->nvp_name); } -static nvpair_t * -nvpair_allocv(const char *name, int type, uint64_t data, size_t datasize) -{ - nvpair_t *nvp; - size_t namelen; - - PJDLOG_ASSERT(type >= NV_TYPE_FIRST && type <= NV_TYPE_LAST); - - namelen = strlen(name); - if (namelen >= NV_NAME_MAX) { - ERRNO_SET(ENAMETOOLONG); - return (NULL); - } - - nvp = nv_calloc(1, sizeof(*nvp) + namelen + 1); - if (nvp != NULL) { - nvp->nvp_name = (char *)(nvp + 1); - memcpy(nvp->nvp_name, name, namelen); - nvp->nvp_name[namelen] = '\0'; - nvp->nvp_type = type; - nvp->nvp_data = data; - nvp->nvp_datasize = datasize; - nvp->nvp_magic = NVPAIR_MAGIC; - } - - return (nvp); -} - nvpair_t * nvpair_create_stringf(const char *name, const char *valuefmt, ...) { @@ -778,7 +1176,7 @@ nvpair_t * nvpair_create_null(const char *name) { - return (nvpair_allocv(name, NV_TYPE_NULL, 0, 0)); + return (nvpair_allocv(name, NV_TYPE_NULL, 0, 0, 0)); } nvpair_t * @@ -786,14 +1184,14 @@ nvpair_create_bool(const char *name, bool value) { return (nvpair_allocv(name, NV_TYPE_BOOL, value ? 1 : 0, - sizeof(uint8_t))); + sizeof(uint8_t), 0)); } nvpair_t * nvpair_create_number(const char *name, uint64_t value) { - return (nvpair_allocv(name, NV_TYPE_NUMBER, value, sizeof(value))); + return (nvpair_allocv(name, NV_TYPE_NUMBER, value, sizeof(value), 0)); } nvpair_t * @@ -814,7 +1212,7 @@ nvpair_create_string(const char *name, const char *value) size = strlen(value) + 1; nvp = nvpair_allocv(name, NV_TYPE_STRING, (uint64_t)(uintptr_t)data, - size); + size, 0); if (nvp == NULL) nv_free(data); @@ -836,7 +1234,8 @@ nvpair_create_nvlist(const char *name, const nvlist_t *value) if (nvl == NULL) return (NULL); - nvp = nvpair_allocv(name, NV_TYPE_NVLIST, (uint64_t)(uintptr_t)nvl, 0); + nvp = nvpair_allocv(name, NV_TYPE_NVLIST, (uint64_t)(uintptr_t)nvl, 0, + 0); if (nvp == NULL) nvlist_destroy(nvl); else @@ -861,7 +1260,7 @@ nvpair_create_descriptor(const char *name, int value) return (NULL); nvp = nvpair_allocv(name, NV_TYPE_DESCRIPTOR, (uint64_t)value, - sizeof(int64_t)); + sizeof(int64_t), 0); if (nvp == NULL) { ERRNO_SAVE(); close(value); @@ -889,7 +1288,7 @@ nvpair_create_binary(const char *name, const void *value, size_t size) memcpy(data, value, size); nvp = nvpair_allocv(name, NV_TYPE_BINARY, (uint64_t)(uintptr_t)data, - size); + size, 0); if (nvp == NULL) nv_free(data); @@ -897,6 +1296,226 @@ nvpair_create_binary(const char *name, const void *value, size_t size) } nvpair_t * +nvpair_create_bool_array(const char *name, const bool *value, size_t nitems) +{ + nvpair_t *nvp; + size_t size; + void *data; + + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + size = sizeof(value[0]) * nitems; + data = nv_malloc(size); + if (data == NULL) + return (NULL); + + memcpy(data, value, size); + nvp = nvpair_allocv(name, NV_TYPE_BOOL_ARRAY, (uint64_t)(uintptr_t)data, + size, nitems); + if (nvp == NULL) { + ERRNO_SAVE(); + nv_free(data); + ERRNO_RESTORE(); + } + + return (nvp); +} + +nvpair_t * +nvpair_create_number_array(const char *name, const uint64_t *value, + size_t nitems) +{ + nvpair_t *nvp; + size_t size; + void *data; + + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + size = sizeof(value[0]) * nitems; + data = nv_malloc(size); + if (data == NULL) + return (NULL); + + memcpy(data, value, size); + nvp = nvpair_allocv(name, NV_TYPE_NUMBER_ARRAY, + (uint64_t)(uintptr_t)data, size, nitems); + if (nvp == NULL) { + ERRNO_SAVE(); + nv_free(data); + ERRNO_RESTORE(); + } + + return (nvp); +} + +nvpair_t * +nvpair_create_string_array(const char *name, const char * const *value, + size_t nitems) +{ + nvpair_t *nvp; + unsigned int ii; + size_t datasize, size; + char **data; + + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + nvp = NULL; + datasize = 0; + data = nv_malloc(sizeof(value[0]) * nitems); + if (data == NULL) + return (NULL); + + for (ii = 0; ii < nitems; ii++) { + if (value[ii] == NULL) { + ERRNO_SET(EINVAL); + goto fail; + } + + size = strlen(value[ii]) + 1; + datasize += size; + data[ii] = nv_strdup(value[ii]); + if (data[ii] == NULL) + goto fail; + } + nvp = nvpair_allocv(name, NV_TYPE_STRING_ARRAY, + (uint64_t)(uintptr_t)data, datasize, nitems); + +fail: + if (nvp == NULL) { + ERRNO_SAVE(); + for (; ii > 0; ii--) + nv_free(data[ii - 1]); + nv_free(data); + ERRNO_RESTORE(); + } + + return (nvp); +} + +nvpair_t * +nvpair_create_nvlist_array(const char *name, const nvlist_t * const *value, + size_t nitems) +{ + unsigned int ii; + nvlist_t **nvls; + nvpair_t *nvp; + int flags; + + nvp = NULL; + nvls = NULL; + ii = 0; + + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + nvls = nv_malloc(sizeof(value[0]) * nitems); + if (nvls == NULL) + return (NULL); + + for (ii = 0; ii < nitems; ii++) { + if (value[ii] == NULL) { + ERRNO_SET(EINVAL); + goto fail; + } + + nvls[ii] = nvlist_clone(value[ii]); + if (nvls[ii] == NULL) + goto fail; + + if (ii > 0) { + nvp = nvpair_allocv(" ", NV_TYPE_NVLIST, + (uint64_t)(uintptr_t)nvls[ii], 0, 0); + if (nvp == NULL) + goto fail; + nvlist_set_array_next(nvls[ii - 1], nvp); + } + } + flags = nvlist_flags(nvls[nitems - 1]) | NV_FLAG_IN_ARRAY; + nvlist_set_flags(nvls[nitems - 1], flags); + + nvp = nvpair_allocv(name, NV_TYPE_NVLIST_ARRAY, + (uint64_t)(uintptr_t)nvls, 0, nitems); + +fail: + if (nvp == NULL) { + ERRNO_SAVE(); + for (; ii > 0; ii--) + nvlist_destroy(nvls[ii - 1]); + + nv_free(nvls); + ERRNO_RESTORE(); + } else { + for (ii = 0; ii < nitems; ii++) + nvlist_set_parent(nvls[ii], nvp); + } + + return (nvp); +} + +#ifndef _KERNEL +nvpair_t * +nvpair_create_descriptor_array(const char *name, const int *value, + size_t nitems) +{ + unsigned int ii; + nvpair_t *nvp; + int *fds; + + if (value == NULL) { + ERRNO_SET(EINVAL); + return (NULL); + } + + nvp = NULL; + + fds = nv_malloc(sizeof(value[0]) * nitems); + if (fds == NULL) + return (NULL); + for (ii = 0; ii < nitems; ii++) { + if (value[ii] == -1) { + fds[ii] = -1; + } else { + if (!fd_is_valid(value[ii])) { + ERRNO_SET(EBADF); + goto fail; + } + + fds[ii] = fcntl(value[ii], F_DUPFD_CLOEXEC, 0); + if (fds[ii] == -1) + goto fail; + } + } + + nvp = nvpair_allocv(name, NV_TYPE_DESCRIPTOR_ARRAY, + (uint64_t)(uintptr_t)fds, sizeof(int64_t) * nitems, nitems); + +fail: + if (nvp == NULL) { + ERRNO_SAVE(); + for (; ii > 0; ii--) { + if (fds[ii - 1] != -1) + close(fds[ii - 1]); + } + nv_free(fds); + ERRNO_RESTORE(); + } + + return (nvp); +} +#endif + +nvpair_t * nvpair_move_string(const char *name, char *value) { nvpair_t *nvp; @@ -907,7 +1526,7 @@ nvpair_move_string(const char *name, char *value) } nvp = nvpair_allocv(name, NV_TYPE_STRING, (uint64_t)(uintptr_t)value, - strlen(value) + 1); + strlen(value) + 1, 0); if (nvp == NULL) { ERRNO_SAVE(); nv_free(value); @@ -934,7 +1553,7 @@ nvpair_move_nvlist(const char *name, nvlist_t *value) } nvp = nvpair_allocv(name, NV_TYPE_NVLIST, (uint64_t)(uintptr_t)value, - 0); + 0, 0); if (nvp == NULL) nvlist_destroy(value); else @@ -955,7 +1574,7 @@ nvpair_move_descriptor(const char *name, int value) } nvp = nvpair_allocv(name, NV_TYPE_DESCRIPTOR, (uint64_t)value, - sizeof(int64_t)); + sizeof(int64_t), 0); if (nvp == NULL) { ERRNO_SAVE(); close(value); @@ -977,7 +1596,83 @@ nvpair_move_binary(const char *name, void *value, size_t size) } nvp = nvpair_allocv(name, NV_TYPE_BINARY, (uint64_t)(uintptr_t)value, - size); + size, 0); + if (nvp == NULL) { + ERRNO_SAVE(); + nv_free(value); + ERRNO_RESTORE(); + } + + return (nvp); +} + +nvpair_t * +nvpair_move_bool_array(const char *name, bool *value, size_t nitems) +{ + nvpair_t *nvp; + + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + nvp = nvpair_allocv(name, NV_TYPE_BOOL_ARRAY, + (uint64_t)(uintptr_t)value, sizeof(value[0]) * nitems, nitems); + if (nvp == NULL) { + ERRNO_SAVE(); + nv_free(value); + ERRNO_RESTORE(); + } + + return (nvp); +} + +nvpair_t * +nvpair_move_string_array(const char *name, char **value, size_t nitems) +{ + nvpair_t *nvp; + size_t i, size; + + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + size = 0; + for (i = 0; i < nitems; i++) { + if (value[i] == NULL) { + ERRNO_SET(EINVAL); + return (NULL); + } + + size += strlen(value[i]) + 1; + } + + nvp = nvpair_allocv(name, NV_TYPE_STRING_ARRAY, + (uint64_t)(uintptr_t)value, size, nitems); + if (nvp == NULL) { + ERRNO_SAVE(); + for (i = 0; i < nitems; i++) + nv_free(value[i]); + nv_free(value); + ERRNO_RESTORE(); + } + + return (nvp); +} + +nvpair_t * +nvpair_move_number_array(const char *name, uint64_t *value, size_t nitems) +{ + nvpair_t *nvp; + + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + nvp = nvpair_allocv(name, NV_TYPE_NUMBER_ARRAY, + (uint64_t)(uintptr_t)value, sizeof(value[0]) * nitems, nitems); if (nvp == NULL) { ERRNO_SAVE(); nv_free(value); @@ -987,6 +1682,95 @@ nvpair_move_binary(const char *name, void *value, size_t size) return (nvp); } +nvpair_t * +nvpair_move_nvlist_array(const char *name, nvlist_t **value, size_t nitems) +{ + unsigned int ii; + nvpair_t *nvp; + int flags; + + nvp = NULL; + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + for (ii = 0; ii < nitems; ii++) { + if (value == NULL || nvlist_error(value[ii]) != 0 || + nvlist_get_pararr(value[ii], NULL) != NULL) { + ERRNO_SET(EINVAL); + goto fail; + } + if (ii > 0) { + nvp = nvpair_allocv(" ", NV_TYPE_NVLIST, + (uint64_t)(uintptr_t)value[ii], 0, 0); + if (nvp == NULL) + goto fail; + nvlist_set_array_next(value[ii - 1], nvp); + } + } + flags = nvlist_flags(value[nitems - 1]) | NV_FLAG_IN_ARRAY; + nvlist_set_flags(value[nitems - 1], flags); + + nvp = nvpair_allocv(name, NV_TYPE_NVLIST_ARRAY, + (uint64_t)(uintptr_t)value, 0, nitems); +fail: + if (nvp == NULL) { + ERRNO_SAVE(); + for (ii = 0; ii < nitems; ii++) { + if (value[ii] != NULL && + nvlist_get_pararr(value[ii], NULL) != NULL) { + nvlist_destroy(value[ii]); + } + nv_free(value); + } + ERRNO_RESTORE(); + } else { + for (ii = 0; ii < nitems; ii++) + nvlist_set_parent(value[ii], nvp); + } + + return (nvp); +} + +#ifndef _KERNEL +nvpair_t * +nvpair_move_descriptor_array(const char *name, int *value, size_t nitems) +{ + nvpair_t *nvp; + size_t i; + + nvp = NULL; + if (value == NULL || nitems == 0) { + ERRNO_SET(EINVAL); + return (NULL); + } + + for (i = 0; i < nitems; i++) { + if (value[i] != -1 && !fd_is_valid(value[i])) { + ERRNO_SET(EBADF); + goto fail; + } + } + + nvp = nvpair_allocv(name, NV_TYPE_DESCRIPTOR_ARRAY, + (uint64_t)(uintptr_t)value, sizeof(value[0]) * nitems, nitems); + +fail: + if (nvp == NULL) { + ERRNO_SAVE(); + for (i = 0; i < nitems; i++) { + if (fd_is_valid(value[i])) + close(value[i]); + } + nv_free(value); + ERRNO_RESTORE(); + } + + return (nvp); +} +#endif + bool nvpair_get_bool(const nvpair_t *nvp) { @@ -1046,12 +1830,81 @@ nvpair_get_binary(const nvpair_t *nvp, size_t *sizep) if (sizep != NULL) *sizep = nvp->nvp_datasize; + return ((const void *)(intptr_t)nvp->nvp_data); } +const bool * +nvpair_get_bool_array(const nvpair_t *nvp, size_t *nitems) +{ + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_BOOL_ARRAY); + + if (nitems != NULL) + *nitems = nvp->nvp_nitems; + + return ((const bool *)(intptr_t)nvp->nvp_data); +} + +const uint64_t * +nvpair_get_number_array(const nvpair_t *nvp, size_t *nitems) +{ + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_NUMBER_ARRAY); + + if (nitems != NULL) + *nitems = nvp->nvp_nitems; + + return ((const uint64_t *)(intptr_t)nvp->nvp_data); +} + +const char * const * +nvpair_get_string_array(const nvpair_t *nvp, size_t *nitems) +{ + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_STRING_ARRAY); + + if (nitems != NULL) + *nitems = nvp->nvp_nitems; + + return ((const char * const *)(intptr_t)nvp->nvp_data); +} + +const nvlist_t * const * +nvpair_get_nvlist_array(const nvpair_t *nvp, size_t *nitems) +{ + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_NVLIST_ARRAY); + + if (nitems != NULL) + *nitems = nvp->nvp_nitems; + + return ((const nvlist_t * const *)((intptr_t)nvp->nvp_data)); +} + +#ifndef _KERNEL +const int * +nvpair_get_descriptor_array(const nvpair_t *nvp, size_t *nitems) +{ + + NVPAIR_ASSERT(nvp); + PJDLOG_ASSERT(nvp->nvp_type == NV_TYPE_DESCRIPTOR_ARRAY); + + if (nitems != NULL) + *nitems = nvp->nvp_nitems; + + return ((const int *)(intptr_t)nvp->nvp_data); +} +#endif + void nvpair_free(nvpair_t *nvp) { + size_t i; NVPAIR_ASSERT(nvp); PJDLOG_ASSERT(nvp->nvp_list == NULL); @@ -1062,6 +1915,10 @@ nvpair_free(nvpair_t *nvp) case NV_TYPE_DESCRIPTOR: close((int)nvp->nvp_data); break; + case NV_TYPE_DESCRIPTOR_ARRAY: + for (i = 0; i < nvp->nvp_nitems; i++) + close(((int *)(intptr_t)nvp->nvp_data)[i]); + break; #endif case NV_TYPE_NVLIST: nvlist_destroy((nvlist_t *)(intptr_t)nvp->nvp_data); @@ -1072,6 +1929,23 @@ nvpair_free(nvpair_t *nvp) case NV_TYPE_BINARY: nv_free((void *)(intptr_t)nvp->nvp_data); break; + case NV_TYPE_NVLIST_ARRAY: + for (i = 0; i < nvp->nvp_nitems; i++) { + nvlist_destroy( + ((nvlist_t **)(intptr_t)nvp->nvp_data)[i]); + } + nv_free(((nvlist_t **)(intptr_t)nvp->nvp_data)); + break; + case NV_TYPE_NUMBER_ARRAY: + nv_free((uint64_t *)(intptr_t)nvp->nvp_data); + break; + case NV_TYPE_BOOL_ARRAY: + nv_free((bool *)(intptr_t)nvp->nvp_data); + break; + case NV_TYPE_STRING_ARRAY: + for (i = 0; i < nvp->nvp_nitems; i++) + nv_free(((char **)(intptr_t)nvp->nvp_data)[i]); + break; } nv_free(nvp); } @@ -1106,6 +1980,16 @@ nvpair_type_string(int type) return ("DESCRIPTOR"); case NV_TYPE_BINARY: return ("BINARY"); + case NV_TYPE_BOOL_ARRAY: + return ("BOOL ARRAY"); + case NV_TYPE_NUMBER_ARRAY: + return ("NUMBER ARRAY"); + case NV_TYPE_STRING_ARRAY: + return ("STRING ARRAY"); + case NV_TYPE_NVLIST_ARRAY: + return ("NVLIST ARRAY"); + case NV_TYPE_DESCRIPTOR_ARRAY: + return ("DESCRIPTOR ARRAY"); default: return ("<UNKNOWN>"); } diff --git a/sys/contrib/libnv/nvpair_impl.h b/sys/contrib/libnv/nvpair_impl.h index fed7725..0350b1c 100644 --- a/sys/contrib/libnv/nvpair_impl.h +++ b/sys/contrib/libnv/nvpair_impl.h @@ -1,5 +1,6 @@ /*- * Copyright (c) 2009-2013 The FreeBSD Foundation + * Copyright (c) 2013-2015 Mariusz Zaborski <oshogbo@FreeBSD.org> * All rights reserved. * * This software was developed by Pawel Jakub Dawidek under sponsorship from @@ -71,6 +72,15 @@ unsigned char *nvpair_pack_descriptor(const nvpair_t *nvp, unsigned char *ptr, unsigned char *nvpair_pack_binary(const nvpair_t *nvp, unsigned char *ptr, size_t *leftp); unsigned char *nvpair_pack_nvlist_up(unsigned char *ptr, size_t *leftp); +unsigned char *nvpair_pack_bool_array(const nvpair_t *nvp, unsigned char *ptr, + size_t *leftp); +unsigned char *nvpair_pack_number_array(const nvpair_t *nvp, unsigned char *ptr, + size_t *leftp); +unsigned char *nvpair_pack_string_array(const nvpair_t *nvp, unsigned char *ptr, + size_t *leftp); +unsigned char *nvpair_pack_descriptor_array(const nvpair_t *nvp, + unsigned char *ptr, int64_t *fdidxp, size_t *leftp); +unsigned char *nvpair_pack_nvlist_array_next(unsigned char *ptr, size_t *leftp); /* Unpack data functions. */ const unsigned char *nvpair_unpack_header(bool isbe, nvpair_t *nvp, @@ -89,5 +99,15 @@ const unsigned char *nvpair_unpack_descriptor(bool isbe, nvpair_t *nvp, const unsigned char *ptr, size_t *leftp, const int *fds, size_t nfds); const unsigned char *nvpair_unpack_binary(bool isbe, nvpair_t *nvp, const unsigned char *ptr, size_t *leftp); +const unsigned char *nvpair_unpack_bool_array(bool isbe, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp); +const unsigned char *nvpair_unpack_number_array(bool isbe, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp); +const unsigned char *nvpair_unpack_string_array(bool isbe, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp); +const unsigned char *nvpair_unpack_descriptor_array(bool isbe, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp, const int *fds, size_t nfds); +const unsigned char *nvpair_unpack_nvlist_array(bool isbe, nvpair_t *nvp, + const unsigned char *ptr, size_t *leftp, nvlist_t **firstel); #endif /* !_NVPAIR_IMPL_H_ */ diff --git a/sys/dev/ata/ata-all.c b/sys/dev/ata/ata-all.c index 52db44d..118e38e 100644 --- a/sys/dev/ata/ata-all.c +++ b/sys/dev/ata/ata-all.c @@ -64,18 +64,15 @@ static void ata_cam_end_transaction(device_t dev, struct ata_request *request); static void ata_cam_request_sense(device_t dev, struct ata_request *request); static int ata_check_ids(device_t dev, union ccb *ccb); static void ata_conn_event(void *context, int dummy); -static void ata_init(void); static void ata_interrupt_locked(void *data); static int ata_module_event_handler(module_t mod, int what, void *arg); static void ata_periodic_poll(void *data); static int ata_str2mode(const char *str); -static void ata_uninit(void); /* global vars */ MALLOC_DEFINE(M_ATA, "ata_generic", "ATA driver generic layer"); int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data) = NULL; devclass_t ata_devclass; -uma_zone_t ata_request_zone; int ata_dma_check_80pin = 1; /* sysctl vars */ @@ -650,12 +647,7 @@ ata_cam_begin_transaction(device_t dev, union ccb *ccb) struct ata_channel *ch = device_get_softc(dev); struct ata_request *request; - if (!(request = ata_alloc_request())) { - device_printf(dev, "FAILURE - out of memory in start\n"); - ccb->ccb_h.status = CAM_REQ_INVALID; - xpt_done(ccb); - return; - } + request = &ch->request; bzero(request, sizeof(*request)); /* setup request */ @@ -794,7 +786,6 @@ ata_cam_process_sense(device_t dev, struct ata_request *request) ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL; } - ata_free_request(request); xpt_done(ccb); /* Do error recovery if needed. */ if (fatalerr) @@ -865,10 +856,8 @@ ata_cam_end_transaction(device_t dev, struct ata_request *request) if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) ata_cam_request_sense(dev, request); - else { - ata_free_request(request); + else xpt_done(ccb); - } /* Do error recovery if needed. */ if (fatalerr) ata_reinit(dev); @@ -1148,18 +1137,3 @@ static moduledata_t ata_moduledata = { "ata", ata_module_event_handler, NULL }; DECLARE_MODULE(ata, ata_moduledata, SI_SUB_CONFIGURE, SI_ORDER_SECOND); MODULE_VERSION(ata, 1); MODULE_DEPEND(ata, cam, 1, 1, 1); - -static void -ata_init(void) -{ - ata_request_zone = uma_zcreate("ata_request", sizeof(struct ata_request), - NULL, NULL, NULL, NULL, 0, 0); -} -SYSINIT(ata_register, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_init, NULL); - -static void -ata_uninit(void) -{ - uma_zdestroy(ata_request_zone); -} -SYSUNINIT(ata_unregister, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_uninit, NULL); diff --git a/sys/dev/ata/ata-all.h b/sys/dev/ata/ata-all.h index 19cb7ef..cf8ed78 100644 --- a/sys/dev/ata/ata-all.h +++ b/sys/dev/ata/ata-all.h @@ -450,6 +450,7 @@ struct ata_channel { struct ata_cam_device curr[16]; /* Current settings */ int requestsense; /* CCB waiting for SENSE. */ struct callout poll_callout; /* Periodic status poll. */ + struct ata_request request; }; /* disk bay/enclosure related */ @@ -507,14 +508,6 @@ int ata_sata_getrev(device_t dev, int target); int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); void ata_pm_identify(device_t dev); -/* macros for alloc/free of struct ata_request */ -extern uma_zone_t ata_request_zone; -#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) -#define ata_free_request(request) { \ - if (!(request->flags & ATA_R_DANGER2)) \ - uma_zfree(ata_request_zone, request); \ - } - MALLOC_DECLARE(M_ATA); /* misc newbus defines */ diff --git a/sys/dev/ath/if_ath.c b/sys/dev/ath/if_ath.c index 2c935a2b..26bf591 100644 --- a/sys/dev/ath/if_ath.c +++ b/sys/dev/ath/if_ath.c @@ -1473,7 +1473,7 @@ ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, const uint8_t bssid[IEEE80211_ADDR_LEN], const uint8_t mac0[IEEE80211_ADDR_LEN]) { - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_vap *avp; struct ieee80211vap *vap; uint8_t mac[IEEE80211_ADDR_LEN]; @@ -1732,7 +1732,7 @@ ath_vap_delete(struct ieee80211vap *vap) { struct ieee80211com *ic = vap->iv_ic; struct ifnet *ifp = ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; struct ath_vap *avp = ATH_VAP(vap); @@ -2340,7 +2340,7 @@ ath_fatal_proc(void *arg, int pending) static void ath_bmiss_vap(struct ieee80211vap *vap) { - struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; /* * Workaround phantom bmiss interrupts by sanity-checking @@ -2361,8 +2361,6 @@ ath_bmiss_vap(struct ieee80211vap *vap) ATH_UNLOCK(sc); if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { - struct ifnet *ifp = vap->iv_ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; u_int64_t lastrx = sc->sc_lastrx; u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); /* XXX should take a locked ref to iv_bss */ @@ -2851,8 +2849,8 @@ ath_stop(struct ifnet *ifp) int ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type) { - struct ath_softc *sc = ifp->if_softc; struct ieee80211com *ic = ifp->if_l2com; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; HAL_STATUS status; int i; @@ -3045,7 +3043,7 @@ ath_reset_vap(struct ieee80211vap *vap, u_long cmd) { struct ieee80211com *ic = vap->iv_ic; struct ifnet *ifp = ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; switch (cmd) { @@ -3248,7 +3246,7 @@ static int ath_transmit(struct ifnet *ifp, struct mbuf *m) { struct ieee80211com *ic = ifp->if_l2com; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ieee80211_node *ni; struct mbuf *next; struct ath_buf *bf; @@ -3538,8 +3536,7 @@ ath_media_change(struct ifnet *ifp) static void ath_key_update_begin(struct ieee80211vap *vap) { - struct ifnet *ifp = vap->iv_ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); taskqueue_block(sc->sc_tq); @@ -3548,8 +3545,7 @@ ath_key_update_begin(struct ieee80211vap *vap) static void ath_key_update_end(struct ieee80211vap *vap) { - struct ifnet *ifp = vap->iv_ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); taskqueue_unblock(sc->sc_tq); @@ -4156,7 +4152,7 @@ static struct ieee80211_node * ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) { struct ieee80211com *ic = vap->iv_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; struct ath_node *an; @@ -4183,7 +4179,7 @@ static void ath_node_cleanup(struct ieee80211_node *ni) { struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, ni->ni_macaddr, ":", ATH_NODE(ni)); @@ -4198,7 +4194,7 @@ static void ath_node_free(struct ieee80211_node *ni) { struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, ni->ni_macaddr, ":", ATH_NODE(ni)); @@ -4210,7 +4206,7 @@ static void ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) { struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; *rssi = ic->ic_node_getrssi(ni); @@ -4422,7 +4418,7 @@ ath_txq_update(struct ath_softc *sc, int ac) int ath_wme_update(struct ieee80211com *ic) { - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; return !ath_txq_update(sc, WME_AC_BE) || !ath_txq_update(sc, WME_AC_BK) || @@ -5797,7 +5793,7 @@ static void ath_scan_start(struct ieee80211com *ic) { struct ifnet *ifp = ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; u_int32_t rfilt; @@ -5821,8 +5817,7 @@ ath_scan_start(struct ieee80211com *ic) static void ath_scan_end(struct ieee80211com *ic) { - struct ifnet *ifp = ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; u_int32_t rfilt; @@ -5862,8 +5857,7 @@ ath_scan_end(struct ieee80211com *ic) static void ath_update_chw(struct ieee80211com *ic) { - struct ifnet *ifp = ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__); ath_set_channel(ic); @@ -5873,8 +5867,7 @@ ath_update_chw(struct ieee80211com *ic) static void ath_set_channel(struct ieee80211com *ic) { - struct ifnet *ifp = ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; ATH_LOCK(sc); ath_power_set_power_state(sc, HAL_PM_AWAKE); @@ -5916,7 +5909,7 @@ static int ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) { struct ieee80211com *ic = vap->iv_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_vap *avp = ATH_VAP(vap); struct ath_hal *ah = sc->sc_ah; struct ieee80211_node *ni = NULL; @@ -6252,7 +6245,7 @@ static void ath_setup_stationkey(struct ieee80211_node *ni) { struct ieee80211vap *vap = ni->ni_vap; - struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; ieee80211_keyix keyix, rxkeyix; /* XXX should take a locked ref to vap->iv_bss */ @@ -6285,7 +6278,7 @@ ath_newassoc(struct ieee80211_node *ni, int isnew) { struct ath_node *an = ATH_NODE(ni); struct ieee80211vap *vap = ni->ni_vap; - struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; const struct ieee80211_txparam *tp = ni->ni_txparms; an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); @@ -6337,7 +6330,7 @@ static int ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, int nchans, struct ieee80211_channel chans[]) { - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; HAL_STATUS status; @@ -6361,7 +6354,7 @@ static void ath_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, struct ieee80211_channel chans[]) { - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", @@ -6693,8 +6686,8 @@ ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { #define IS_RUNNING(ifp) \ ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) - struct ath_softc *sc = ifp->if_softc; struct ieee80211com *ic = ifp->if_l2com; + struct ath_softc *sc = ic->ic_softc; struct ifreq *ifr = (struct ifreq *)data; const HAL_RATE_TABLE *rt; int error = 0; @@ -6864,7 +6857,7 @@ ath_node_powersave(struct ieee80211_node *ni, int enable) #ifdef ATH_SW_PSQ struct ath_node *an = ATH_NODE(ni); struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_vap *avp = ATH_VAP(ni->ni_vap); /* XXX and no TXQ locks should be held here */ @@ -6931,7 +6924,7 @@ ath_node_set_tim(struct ieee80211_node *ni, int enable) { #ifdef ATH_SW_PSQ struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_node *an = ATH_NODE(ni); struct ath_vap *avp = ATH_VAP(ni->ni_vap); int changed = 0; @@ -7136,7 +7129,7 @@ ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m) struct ath_node *an; struct ath_vap *avp; struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; int tid; /* Just paranoia */ diff --git a/sys/dev/ath/if_ath_keycache.c b/sys/dev/ath/if_ath_keycache.c index fe99f10..b8a77e8 100644 --- a/sys/dev/ath/if_ath_keycache.c +++ b/sys/dev/ath/if_ath_keycache.c @@ -425,7 +425,7 @@ int ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) { - struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; /* * Group key allocation must be handled specially for @@ -493,7 +493,7 @@ ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, int ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) { - struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; struct ath_hal *ah = sc->sc_ah; const struct ieee80211_cipher *cip = k->wk_cipher; u_int keyix = k->wk_keyix; @@ -538,7 +538,7 @@ int ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, const u_int8_t mac[IEEE80211_ADDR_LEN]) { - struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; return ath_keyset(sc, vap, k, vap->iv_bss); } diff --git a/sys/dev/ath/if_ath_rx.c b/sys/dev/ath/if_ath_rx.c index 2779b7a..e391dd7 100644 --- a/sys/dev/ath/if_ath_rx.c +++ b/sys/dev/ath/if_ath_rx.c @@ -330,7 +330,7 @@ ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) { struct ieee80211vap *vap = ni->ni_vap; - struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; + struct ath_softc *sc = vap->iv_ic->ic_softc; uint64_t tsf_beacon_old, tsf_beacon; uint64_t nexttbtt; int64_t tsf_delta; diff --git a/sys/dev/ath/if_ath_tdma.c b/sys/dev/ath/if_ath_tdma.c index fd23db1..d4c9ccd 100644 --- a/sys/dev/ath/if_ath_tdma.c +++ b/sys/dev/ath/if_ath_tdma.c @@ -359,7 +359,7 @@ ath_tdma_update(struct ieee80211_node *ni, #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) struct ieee80211vap *vap = ni->ni_vap; struct ieee80211com *ic = ni->ni_ic; - struct ath_softc *sc = ic->ic_ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_hal *ah = sc->sc_ah; const HAL_RATE_TABLE *rt = sc->sc_currates; u_int64_t tsf, rstamp, nextslot, nexttbtt, nexttbtt_full; diff --git a/sys/dev/ath/if_ath_tx.c b/sys/dev/ath/if_ath_tx.c index c15b158..916d4cb 100644 --- a/sys/dev/ath/if_ath_tx.c +++ b/sys/dev/ath/if_ath_tx.c @@ -2341,7 +2341,7 @@ ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, { struct ieee80211com *ic = ni->ni_ic; struct ifnet *ifp = ic->ic_ifp; - struct ath_softc *sc = ifp->if_softc; + struct ath_softc *sc = ic->ic_softc; struct ath_buf *bf; struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); int error = 0; @@ -5731,7 +5731,7 @@ int ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, int dialogtoken, int baparamset, int batimeout) { - struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; + struct ath_softc *sc = ni->ni_ic->ic_softc; int tid = tap->txa_tid; struct ath_node *an = ATH_NODE(ni); struct ath_tid *atid = &an->an_tid[tid]; @@ -5809,7 +5809,7 @@ int ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, int status, int code, int batimeout) { - struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; + struct ath_softc *sc = ni->ni_ic->ic_softc; int tid = tap->txa_tid; struct ath_node *an = ATH_NODE(ni); struct ath_tid *atid = &an->an_tid[tid]; @@ -5856,7 +5856,7 @@ ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, void ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) { - struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; + struct ath_softc *sc = ni->ni_ic->ic_softc; int tid = tap->txa_tid; struct ath_node *an = ATH_NODE(ni); struct ath_tid *atid = &an->an_tid[tid]; @@ -5991,7 +5991,7 @@ void ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, int status) { - struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; + struct ath_softc *sc = ni->ni_ic->ic_softc; int tid = tap->txa_tid; struct ath_node *an = ATH_NODE(ni); struct ath_tid *atid = &an->an_tid[tid]; @@ -6064,7 +6064,7 @@ void ath_addba_response_timeout(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) { - struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; + struct ath_softc *sc = ni->ni_ic->ic_softc; int tid = tap->txa_tid; struct ath_node *an = ATH_NODE(ni); struct ath_tid *atid = &an->an_tid[tid]; diff --git a/sys/dev/bxe/ecore_hsi.h b/sys/dev/bxe/ecore_hsi.h index 005bb2e..f78f4ea 100644 --- a/sys/dev/bxe/ecore_hsi.h +++ b/sys/dev/bxe/ecore_hsi.h @@ -2536,9 +2536,9 @@ struct shmem2_region { #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 #define SHMEM_EEE_SUPPORTED_SHIFT 16 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 - #define SHMEM_EEE_100M_ADV (1<<0) - #define SHMEM_EEE_1G_ADV (1<<1) - #define SHMEM_EEE_10G_ADV (1<<2) + #define SHMEM_EEE_100M_ADV (1U<<0) + #define SHMEM_EEE_1G_ADV (1U<<1) + #define SHMEM_EEE_10G_ADV (1U<<2) #define SHMEM_EEE_ADV_STATUS_SHIFT 20 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 diff --git a/sys/dev/e1000/e1000_80003es2lan.c b/sys/dev/e1000/e1000_80003es2lan.c index 076e02b..b948bb4 100644 --- a/sys/dev/e1000/e1000_80003es2lan.c +++ b/sys/dev/e1000/e1000_80003es2lan.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2013, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_80003es2lan.h b/sys/dev/e1000/e1000_80003es2lan.h index 3807e46..89b1551 100644 --- a/sys/dev/e1000/e1000_80003es2lan.h +++ b/sys/dev/e1000/e1000_80003es2lan.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2013, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82540.c b/sys/dev/e1000/e1000_82540.c index 141b92e..68f92c6 100644 --- a/sys/dev/e1000/e1000_82540.c +++ b/sys/dev/e1000/e1000_82540.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82541.c b/sys/dev/e1000/e1000_82541.c index 781aa93..69fcee4 100644 --- a/sys/dev/e1000/e1000_82541.c +++ b/sys/dev/e1000/e1000_82541.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82541.h b/sys/dev/e1000/e1000_82541.h index 3b6b961..1eebfad 100644 --- a/sys/dev/e1000/e1000_82541.h +++ b/sys/dev/e1000/e1000_82541.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2008, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82542.c b/sys/dev/e1000/e1000_82542.c index 19d5402..a6b3616 100644 --- a/sys/dev/e1000/e1000_82542.c +++ b/sys/dev/e1000/e1000_82542.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82543.c b/sys/dev/e1000/e1000_82543.c index 1c01658..3350f17 100644 --- a/sys/dev/e1000/e1000_82543.c +++ b/sys/dev/e1000/e1000_82543.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82543.h b/sys/dev/e1000/e1000_82543.h index 60e5c15..0fa813b 100644 --- a/sys/dev/e1000/e1000_82543.h +++ b/sys/dev/e1000/e1000_82543.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2008, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82571.c b/sys/dev/e1000/e1000_82571.c index e209d43..a64ef56 100644 --- a/sys/dev/e1000/e1000_82571.c +++ b/sys/dev/e1000/e1000_82571.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82571.h b/sys/dev/e1000/e1000_82571.h index c76f16f..cda87a2 100644 --- a/sys/dev/e1000/e1000_82571.h +++ b/sys/dev/e1000/e1000_82571.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82575.c b/sys/dev/e1000/e1000_82575.c index d79db67..8981ae3 100644 --- a/sys/dev/e1000/e1000_82575.c +++ b/sys/dev/e1000/e1000_82575.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_82575.h b/sys/dev/e1000/e1000_82575.h index 6569b98..503fdce 100644 --- a/sys/dev/e1000/e1000_82575.h +++ b/sys/dev/e1000/e1000_82575.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_api.c b/sys/dev/e1000/e1000_api.c index 374ffa6..5db22db 100644 --- a/sys/dev/e1000/e1000_api.c +++ b/sys/dev/e1000/e1000_api.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_api.h b/sys/dev/e1000/e1000_api.h index a2ffa16..e87acc8 100644 --- a/sys/dev/e1000/e1000_api.h +++ b/sys/dev/e1000/e1000_api.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_defines.h b/sys/dev/e1000/e1000_defines.h index 5deada2..9472ca4 100644 --- a/sys/dev/e1000/e1000_defines.h +++ b/sys/dev/e1000/e1000_defines.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_hw.h b/sys/dev/e1000/e1000_hw.h index faf64a3..3ec921e 100644 --- a/sys/dev/e1000/e1000_hw.h +++ b/sys/dev/e1000/e1000_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_i210.c b/sys/dev/e1000/e1000_i210.c index f12c13f..563f11a 100644 --- a/sys/dev/e1000/e1000_i210.c +++ b/sys/dev/e1000/e1000_i210.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_i210.h b/sys/dev/e1000/e1000_i210.h index 2a20ca1..f940915 100644 --- a/sys/dev/e1000/e1000_i210.h +++ b/sys/dev/e1000/e1000_i210.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_ich8lan.c b/sys/dev/e1000/e1000_ich8lan.c index 204c39c..23e7b95 100644 --- a/sys/dev/e1000/e1000_ich8lan.c +++ b/sys/dev/e1000/e1000_ich8lan.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_ich8lan.h b/sys/dev/e1000/e1000_ich8lan.h index f045ebd..9cb79c0 100644 --- a/sys/dev/e1000/e1000_ich8lan.h +++ b/sys/dev/e1000/e1000_ich8lan.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_mac.c b/sys/dev/e1000/e1000_mac.c index b888b34..1c86307 100644 --- a/sys/dev/e1000/e1000_mac.c +++ b/sys/dev/e1000/e1000_mac.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_mac.h b/sys/dev/e1000/e1000_mac.h index 2c1bfe3..1daed9b 100644 --- a/sys/dev/e1000/e1000_mac.h +++ b/sys/dev/e1000/e1000_mac.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_manage.c b/sys/dev/e1000/e1000_manage.c index 8087e65..f319c8b 100644 --- a/sys/dev/e1000/e1000_manage.c +++ b/sys/dev/e1000/e1000_manage.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_manage.h b/sys/dev/e1000/e1000_manage.h index 51f17671..303e99e 100644 --- a/sys/dev/e1000/e1000_manage.h +++ b/sys/dev/e1000/e1000_manage.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_mbx.c b/sys/dev/e1000/e1000_mbx.c index 55477b2..d9fb9ac 100644 --- a/sys/dev/e1000/e1000_mbx.c +++ b/sys/dev/e1000/e1000_mbx.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_mbx.h b/sys/dev/e1000/e1000_mbx.h index d2aea5c4..fadd849 100644 --- a/sys/dev/e1000/e1000_mbx.h +++ b/sys/dev/e1000/e1000_mbx.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_nvm.c b/sys/dev/e1000/e1000_nvm.c index f702f71..0a1a18d 100644 --- a/sys/dev/e1000/e1000_nvm.c +++ b/sys/dev/e1000/e1000_nvm.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_nvm.h b/sys/dev/e1000/e1000_nvm.h index 34077b2..31f2180 100644 --- a/sys/dev/e1000/e1000_nvm.h +++ b/sys/dev/e1000/e1000_nvm.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2013, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_osdep.c b/sys/dev/e1000/e1000_osdep.c index 75a7b79..2987cda 100644 --- a/sys/dev/e1000/e1000_osdep.c +++ b/sys/dev/e1000/e1000_osdep.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_osdep.h b/sys/dev/e1000/e1000_osdep.h index 1324110..fc46f48 100644 --- a/sys/dev/e1000/e1000_osdep.h +++ b/sys/dev/e1000/e1000_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_phy.c b/sys/dev/e1000/e1000_phy.c index f27889c..adb6732 100644 --- a/sys/dev/e1000/e1000_phy.c +++ b/sys/dev/e1000/e1000_phy.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_phy.h b/sys/dev/e1000/e1000_phy.h index 0e5b2e6..d3d563f 100644 --- a/sys/dev/e1000/e1000_phy.h +++ b/sys/dev/e1000/e1000_phy.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_regs.h b/sys/dev/e1000/e1000_regs.h index 952a7dc..da93d75 100644 --- a/sys/dev/e1000/e1000_regs.h +++ b/sys/dev/e1000/e1000_regs.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_vf.c b/sys/dev/e1000/e1000_vf.c index 2cabac9..4af985b 100644 --- a/sys/dev/e1000/e1000_vf.c +++ b/sys/dev/e1000/e1000_vf.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/e1000_vf.h b/sys/dev/e1000/e1000_vf.h index 2a780741..e6f834e 100644 --- a/sys/dev/e1000/e1000_vf.h +++ b/sys/dev/e1000/e1000_vf.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2014, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index 830325b..e36a3d8 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -364,8 +364,14 @@ MODULE_DEPEND(em, netmap, 1, 1, 1); #define CSUM_TSO 0 #endif +#define TSO_WORKAROUND 4 + static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); +static int em_disable_crc_stripping = 0; +SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, + &em_disable_crc_stripping, 0, "Disable CRC Stripping"); + static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, @@ -1872,13 +1878,15 @@ em_xmit(struct tx_ring *txr, struct mbuf **m_headp) struct ether_header *eh; struct ip *ip = NULL; struct tcphdr *tp = NULL; - u32 txd_upper = 0, txd_lower = 0, txd_used = 0; + u32 txd_upper = 0, txd_lower = 0; int ip_off, poff; int nsegs, i, j, first, last = 0; - int error, do_tso, tso_desc = 0, remap = 1; + int error; + bool do_tso, tso_desc, remap = TRUE; m_head = *m_headp; - do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0); + do_tso = (m_head->m_pkthdr.csum_flags & CSUM_TSO); + tso_desc = FALSE; ip_off = poff = 0; /* @@ -1914,74 +1922,82 @@ em_xmit(struct tx_ring *txr, struct mbuf **m_headp) * for IPv6 yet. */ ip_off = sizeof(struct ether_header); - m_head = m_pullup(m_head, ip_off); - if (m_head == NULL) { - *m_headp = NULL; - return (ENOBUFS); + if (m_head->m_len < ip_off) { + m_head = m_pullup(m_head, ip_off); + if (m_head == NULL) { + *m_headp = NULL; + return (ENOBUFS); + } } eh = mtod(m_head, struct ether_header *); if (eh->ether_type == htons(ETHERTYPE_VLAN)) { ip_off = sizeof(struct ether_vlan_header); - m_head = m_pullup(m_head, ip_off); + if (m_head->m_len < ip_off) { + m_head = m_pullup(m_head, ip_off); + if (m_head == NULL) { + *m_headp = NULL; + return (ENOBUFS); + } + } + } + if (m_head->m_len < ip_off + sizeof(struct ip)) { + m_head = m_pullup(m_head, ip_off + sizeof(struct ip)); if (m_head == NULL) { *m_headp = NULL; return (ENOBUFS); } } - m_head = m_pullup(m_head, ip_off + sizeof(struct ip)); - if (m_head == NULL) { - *m_headp = NULL; - return (ENOBUFS); - } ip = (struct ip *)(mtod(m_head, char *) + ip_off); poff = ip_off + (ip->ip_hl << 2); - if (do_tso) { - m_head = m_pullup(m_head, poff + sizeof(struct tcphdr)); - if (m_head == NULL) { - *m_headp = NULL; - return (ENOBUFS); + + if (do_tso || (m_head->m_pkthdr.csum_flags & CSUM_TCP)) { + if (m_head->m_len < poff + sizeof(struct tcphdr)) { + m_head = m_pullup(m_head, poff + + sizeof(struct tcphdr)); + if (m_head == NULL) { + *m_headp = NULL; + return (ENOBUFS); + } } tp = (struct tcphdr *)(mtod(m_head, char *) + poff); /* * TSO workaround: * pull 4 more bytes of data into it. */ - m_head = m_pullup(m_head, poff + (tp->th_off << 2) + 4); - if (m_head == NULL) { - *m_headp = NULL; - return (ENOBUFS); + if (m_head->m_len < poff + (tp->th_off << 2)) { + m_head = m_pullup(m_head, poff + + (tp->th_off << 2) + + TSO_WORKAROUND); + if (m_head == NULL) { + *m_headp = NULL; + return (ENOBUFS); + } } ip = (struct ip *)(mtod(m_head, char *) + ip_off); - ip->ip_len = 0; - ip->ip_sum = 0; - /* - * The pseudo TCP checksum does not include TCP payload - * length so driver should recompute the checksum here - * what hardware expect to see. This is adherence of - * Microsoft's Large Send specification. - */ tp = (struct tcphdr *)(mtod(m_head, char *) + poff); - tp->th_sum = in_pseudo(ip->ip_src.s_addr, - ip->ip_dst.s_addr, htons(IPPROTO_TCP)); - } else if (m_head->m_pkthdr.csum_flags & CSUM_TCP) { - m_head = m_pullup(m_head, poff + sizeof(struct tcphdr)); - if (m_head == NULL) { - *m_headp = NULL; - return (ENOBUFS); + if (do_tso) { + ip->ip_len = htons(m_head->m_pkthdr.tso_segsz + + (ip->ip_hl << 2) + + (tp->th_off << 2)); + ip->ip_sum = 0; + /* + * The pseudo TCP checksum does not include TCP + * payload length so driver should recompute + * the checksum here what hardware expect to + * see. This is adherence of Microsoft's Large + * Send specification. + */ + tp->th_sum = in_pseudo(ip->ip_src.s_addr, + ip->ip_dst.s_addr, htons(IPPROTO_TCP)); } - tp = (struct tcphdr *)(mtod(m_head, char *) + poff); - m_head = m_pullup(m_head, poff + (tp->th_off << 2)); - if (m_head == NULL) { - *m_headp = NULL; - return (ENOBUFS); - } - ip = (struct ip *)(mtod(m_head, char *) + ip_off); - tp = (struct tcphdr *)(mtod(m_head, char *) + poff); } else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) { - m_head = m_pullup(m_head, poff + sizeof(struct udphdr)); - if (m_head == NULL) { - *m_headp = NULL; - return (ENOBUFS); + if (m_head->m_len < poff + sizeof(struct udphdr)) { + m_head = m_pullup(m_head, poff + + sizeof(struct udphdr)); + if (m_head == NULL) { + *m_headp = NULL; + return (ENOBUFS); + } } ip = (struct ip *)(mtod(m_head, char *) + ip_off); } @@ -2027,7 +2043,7 @@ retry: *m_headp = m; /* Try it again, but only once */ - remap = 0; + remap = FALSE; goto retry; } else if (error != 0) { adapter->no_tx_dma_setup++; @@ -2042,13 +2058,13 @@ retry: * it follows a TSO burst, then we need to add a * sentinel descriptor to prevent premature writeback. */ - if ((do_tso == 0) && (txr->tx_tso == TRUE)) { + if ((!do_tso) && (txr->tx_tso == TRUE)) { if (nsegs == 1) tso_desc = TRUE; txr->tx_tso = FALSE; } - if (nsegs > (txr->tx_avail - 2)) { + if (nsegs > (txr->tx_avail - EM_MAX_SCATTER)) { txr->no_desc_avail++; bus_dmamap_unload(txr->txtag, map); return (ENOBUFS); @@ -2088,23 +2104,23 @@ retry: ** If this is the last descriptor, we want to ** split it so we have a small final sentinel */ - if (tso_desc && (j == (nsegs -1)) && (seg_len > 8)) { - seg_len -= 4; + if (tso_desc && (j == (nsegs - 1)) && (seg_len > 8)) { + seg_len -= TSO_WORKAROUND; ctxd->buffer_addr = htole64(seg_addr); ctxd->lower.data = htole32( - adapter->txd_cmd | txd_lower | seg_len); - ctxd->upper.data = - htole32(txd_upper); + adapter->txd_cmd | txd_lower | seg_len); + ctxd->upper.data = htole32(txd_upper); if (++i == adapter->num_tx_desc) i = 0; + /* Now make the sentinel */ - ++txd_used; /* using an extra txd */ + txr->tx_avail--; ctxd = &txr->tx_base[i]; tx_buffer = &txr->tx_buffers[i]; ctxd->buffer_addr = htole64(seg_addr + seg_len); ctxd->lower.data = htole32( - adapter->txd_cmd | txd_lower | 4); + adapter->txd_cmd | txd_lower | TSO_WORKAROUND); ctxd->upper.data = htole32(txd_upper); last = i; @@ -2114,8 +2130,7 @@ retry: ctxd->buffer_addr = htole64(seg_addr); ctxd->lower.data = htole32( adapter->txd_cmd | txd_lower | seg_len); - ctxd->upper.data = - htole32(txd_upper); + ctxd->upper.data = htole32(txd_upper); last = i; if (++i == adapter->num_tx_desc) i = 0; @@ -2126,8 +2141,6 @@ retry: txr->next_avail_desc = i; txr->tx_avail -= nsegs; - if (tso_desc) /* TSO used an extra for sentinel */ - txr->tx_avail -= txd_used; tx_buffer->m_head = m_head; /* @@ -3030,6 +3043,11 @@ em_setup_interface(device_t dev, struct adapter *adapter) if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); if_setioctlfn(ifp, em_ioctl); if_setgetcounterfn(ifp, em_get_counter); + /* TSO parameters */ + ifp->if_hw_tsomax = EM_TSO_SIZE; + ifp->if_hw_tsomaxsegcount = EM_MAX_SCATTER; + ifp->if_hw_tsomaxsegsize = EM_TSO_SEG_SIZE; + #ifdef EM_MULTIQUEUE /* Multiqueue stack interface */ if_settransmitfn(ifp, em_mq_start); @@ -4514,7 +4532,8 @@ em_initialize_receive_unit(struct adapter *adapter) (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); /* Strip the CRC */ - rctl |= E1000_RCTL_SECRC; + if (!em_disable_crc_stripping) + rctl |= E1000_RCTL_SECRC; /* Make sure VLAN Filters are off */ rctl &= ~E1000_RCTL_VFE; @@ -4888,8 +4907,8 @@ em_enable_intr(struct adapter *adapter) u32 ims_mask = IMS_ENABLE_MASK; if (hw->mac.type == e1000_82574) { - E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); - ims_mask |= EM_MSIX_MASK; + E1000_WRITE_REG(hw, EM_EIAC, adapter->ims); + ims_mask |= adapter->ims; } E1000_WRITE_REG(hw, E1000_IMS, ims_mask); } diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h index be18a6c..8725de3 100644 --- a/sys/dev/e1000/if_em.h +++ b/sys/dev/e1000/if_em.h @@ -266,7 +266,7 @@ #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) -#define EM_MAX_SCATTER 32 +#define EM_MAX_SCATTER 64 #define EM_VFTA_SIZE 128 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c index 9eacc78..a3ea8d0 100644 --- a/sys/dev/e1000/if_igb.c +++ b/sys/dev/e1000/if_igb.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2013, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/if_igb.h b/sys/dev/e1000/if_igb.h index f2d0926..a4222e3 100644 --- a/sys/dev/e1000/if_igb.h +++ b/sys/dev/e1000/if_igb.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2013, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/e1000/if_lem.c b/sys/dev/e1000/if_lem.c index f34010e..7476be5 100644 --- a/sys/dev/e1000/if_lem.c +++ b/sys/dev/e1000/if_lem.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -97,7 +97,7 @@ /********************************************************************* * Legacy Em Driver version: *********************************************************************/ -char lem_driver_version[] = "1.0.6"; +char lem_driver_version[] = "1.1.0"; /********************************************************************* * PCI Device ID Table @@ -2913,10 +2913,6 @@ lem_free_transmit_structures(struct adapter *adapter) bus_dma_tag_destroy(adapter->txtag); adapter->txtag = NULL; } -#if __FreeBSD_version >= 800000 - if (adapter->br != NULL) - buf_ring_free(adapter->br, M_DEVBUF); -#endif } /********************************************************************* diff --git a/sys/dev/e1000/if_lem.h b/sys/dev/e1000/if_lem.h index 41447d1..4c43bdd 100644 --- a/sys/dev/e1000/if_lem.h +++ b/sys/dev/e1000/if_lem.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2015, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -296,9 +296,6 @@ struct em_int_delay_info { /* Our adapter structure */ struct adapter { if_t ifp; -#if __FreeBSD_version >= 800000 - struct buf_ring *br; -#endif struct e1000_hw hw; /* FreeBSD operating-system-specific structures. */ diff --git a/sys/dev/gpio/gpiobus.c b/sys/dev/gpio/gpiobus.c index e741d28..6cafdaf 100644 --- a/sys/dev/gpio/gpiobus.c +++ b/sys/dev/gpio/gpiobus.c @@ -155,12 +155,16 @@ gpiobus_attach_bus(device_t dev) int gpiobus_detach_bus(device_t dev) { + int err; #ifdef FDT ofw_gpiobus_unregister_provider(dev); #endif + err = bus_generic_detach(dev); + if (err != 0) + return (err); - return (bus_generic_detach(dev)); + return (device_delete_children(dev)); } int @@ -338,11 +342,14 @@ gpiobus_detach(device_t dev) if ((err = device_get_children(dev, &devlist, &ndevs)) != 0) return (err); for (i = 0; i < ndevs; i++) { - device_delete_child(dev, devlist[i]); devi = GPIOBUS_IVAR(devlist[i]); gpiobus_free_ivars(devi); + resource_list_free(&devi->rl); + free(devi, M_DEVBUF); + device_delete_child(dev, devlist[i]); } free(devlist, M_TEMP); + rman_fini(&sc->sc_intr_rman); if (sc->sc_pins) { for (i = 0; i < sc->sc_npins; i++) { if (sc->sc_pins[i].name != NULL) @@ -442,7 +449,7 @@ gpiobus_add_child(device_t dev, u_int order, const char *name, int unit) devi = malloc(sizeof(struct gpiobus_ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (devi == NULL) { device_delete_child(dev, child); - return (0); + return (NULL); } resource_list_init(&devi->rl); device_set_ivars(child, devi); @@ -461,8 +468,11 @@ gpiobus_hinted_child(device_t bus, const char *dname, int dunit) child = BUS_ADD_CHILD(bus, 0, dname, dunit); devi = GPIOBUS_IVAR(child); resource_int_value(dname, dunit, "pins", &pins); - if (gpiobus_parse_pins(sc, child, pins)) + if (gpiobus_parse_pins(sc, child, pins)) { + resource_list_free(&devi->rl); + free(devi, M_DEVBUF); device_delete_child(bus, child); + } if (resource_int_value(dname, dunit, "irq", &irq) == 0) { if (bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1) != 0) device_printf(bus, diff --git a/sys/dev/gpio/gpioled.c b/sys/dev/gpio/gpioled.c index 01710c2..e699128 100644 --- a/sys/dev/gpio/gpioled.c +++ b/sys/dev/gpio/gpioled.c @@ -255,3 +255,4 @@ static driver_t gpioled_driver = { }; DRIVER_MODULE(gpioled, gpiobus, gpioled_driver, gpioled_devclass, 0, 0); +MODULE_DEPEND(gpioled, gpiobus, 1, 1, 1); diff --git a/sys/dev/md/md.c b/sys/dev/md/md.c index a82d81d..c19f7fe 100644 --- a/sys/dev/md/md.c +++ b/sys/dev/md/md.c @@ -89,6 +89,7 @@ #include <sys/vnode.h> #include <geom/geom.h> +#include <geom/geom_int.h> #include <vm/vm.h> #include <vm/vm_param.h> @@ -121,9 +122,12 @@ SYSCTL_INT(_vm, OID_AUTO, md_malloc_wait, CTLFLAG_RW, &md_malloc_wait, 0, #define MD_ROOT_FSTYPE "ufs" #endif -#if defined(MD_ROOT) && defined(MD_ROOT_SIZE) +#if defined(MD_ROOT) /* * Preloaded image gets put here. + */ +#if defined(MD_ROOT_SIZE) +/* * Applications that patch the object with the image can determine * the size looking at the start and end markers (strings), * so we want them contiguous. @@ -135,6 +139,14 @@ static struct { .start = "MFS Filesystem goes here", .end = "MFS Filesystem had better STOP here", }; +const int mfs_root_size = sizeof(mfs_root.start); +#else +extern volatile u_char __weak_symbol mfs_root; +extern volatile u_char __weak_symbol mfs_root_end; +__GLOBL(mfs_root); +__GLOBL(mfs_root_end); +#define mfs_root_size ((uintptr_t)(&mfs_root_end - &mfs_root)) +#endif #endif static g_init_t g_md_init; @@ -1552,6 +1564,9 @@ md_preloaded(u_char *image, size_t length, const char *name) if (name != NULL) { printf("%s%d: Preloaded image <%s> %zd bytes at %p\n", MD_NAME, sc->unit, name, length, image); + } else { + printf("%s%d: Embedded image %zd bytes at %p\n", + MD_NAME, sc->unit, length, image); } } @@ -1571,10 +1586,13 @@ g_md_init(struct g_class *mp __unused) sx_init(&md_sx, "MD config lock"); g_topology_unlock(); md_uh = new_unrhdr(0, INT_MAX, NULL); -#ifdef MD_ROOT_SIZE - sx_xlock(&md_sx); - md_preloaded(mfs_root.start, sizeof(mfs_root.start), NULL); - sx_xunlock(&md_sx); +#ifdef MD_ROOT + if (mfs_root_size != 0) { + sx_xlock(&md_sx); + md_preloaded(__DEVOLATILE(u_char *, &mfs_root), mfs_root_size, + NULL); + sx_xunlock(&md_sx); + } #endif /* XXX: are preload_* static or do they need Giant ? */ while ((mod = preload_search_next_name(mod)) != NULL) { @@ -1660,9 +1678,11 @@ g_md_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp, "read-only"); sbuf_printf(sb, "%s<type>%s</type>\n", indent, type); - if (mp->type == MD_VNODE && mp->vnode != NULL) - sbuf_printf(sb, "%s<file>%s</file>\n", - indent, mp->file); + if (mp->type == MD_VNODE && mp->vnode != NULL) { + sbuf_printf(sb, "%s<file>", indent); + g_conf_printf_escaped(sb, "%s", mp->file); + sbuf_printf(sb, "</file>\n"); + } } } } diff --git a/sys/dev/random/fortuna.c b/sys/dev/random/fortuna.c index 2aafba4..0b03931 100644 --- a/sys/dev/random/fortuna.c +++ b/sys/dev/random/fortuna.c @@ -58,6 +58,7 @@ __FBSDID("$FreeBSD$"); #include <dev/random/fortuna.h> #else /* !_KERNEL */ #include <inttypes.h> +#include <stdbool.h> #include <stdio.h> #include <stdlib.h> #include <string.h> @@ -124,9 +125,7 @@ static uint8_t zero_region[RANDOM_ZERO_BLOCKSIZE]; static void random_fortuna_pre_read(void); static void random_fortuna_read(uint8_t *, u_int); -static void random_fortuna_write(uint8_t *, u_int); -static void random_fortuna_reseed(void); -static int random_fortuna_seeded(void); +static bool random_fortuna_seeded(void); static void random_fortuna_process_event(struct harvest_event *); static void random_fortuna_init_alg(void *); static void random_fortuna_deinit_alg(void *); @@ -139,8 +138,6 @@ struct random_algorithm random_alg_context = { .ra_deinit_alg = random_fortuna_deinit_alg, .ra_pre_read = random_fortuna_pre_read, .ra_read = random_fortuna_read, - .ra_write = random_fortuna_write, - .ra_reseed = random_fortuna_reseed, .ra_seeded = random_fortuna_seeded, .ra_event_processor = random_fortuna_process_event, .ra_poolcount = RANDOM_FORTUNA_NPOOLS, @@ -420,43 +417,7 @@ random_fortuna_read(uint8_t *buf, u_int bytecount) RANDOM_RESEED_UNLOCK(); } -/* Internal function to hand external entropy to the PRNG. */ -void -random_fortuna_write(uint8_t *buf, u_int count) -{ - static u_int destination = 0; - struct harvest_event event; - struct randomdev_hash hash; - uint32_t entropy_data[RANDOM_KEYSIZE_WORDS], timestamp; - int i; - - /* Extra timing here is helpful to scrape scheduler timing entropy */ - randomdev_hash_init(&hash); - timestamp = (uint32_t)get_cyclecount(); - randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); - randomdev_hash_iterate(&hash, buf, count); - timestamp = (uint32_t)get_cyclecount(); - randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); - randomdev_hash_finish(&hash, entropy_data); - explicit_bzero(&hash, sizeof(hash)); - for (i = 0; i < RANDOM_KEYSIZE_WORDS; i += sizeof(event.he_entropy)/sizeof(event.he_entropy[0])) { - event.he_somecounter = (uint32_t)get_cyclecount(); - event.he_size = sizeof(event.he_entropy); - event.he_bits = event.he_size/8; - event.he_source = RANDOM_CACHED; - event.he_destination = destination++; /* Harmless cheating */ - memcpy(event.he_entropy, entropy_data + i, sizeof(event.he_entropy)); - random_fortuna_process_event(&event); - } - explicit_bzero(entropy_data, sizeof(entropy_data)); -} - -void -random_fortuna_reseed(void) -{ -} - -int +bool random_fortuna_seeded(void) { diff --git a/sys/dev/random/other_algorithm.c b/sys/dev/random/other_algorithm.c new file mode 100644 index 0000000..740e879 --- /dev/null +++ b/sys/dev/random/other_algorithm.c @@ -0,0 +1,209 @@ +/*- + * Copyright (c) 2015 Mark R V Murray + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/*- + * This is a skeleton for folks who wish to build a loadable module + * containing an alternative entropy-processing algorithm for random(4). + * + * The functions below should be completed with the appropriate code, + * and the nearby yarrow.c and fortuna.c may be consulted for examples + * of working code. + * + * The author is willing to provide reasonable help to those wishing to + * write such a module for themselves. Please use the markm@ FreeBSD + * email address, and ensure that you are developing this on a suitably + * supported branch (This is currently 11-CURRENT, and will be no + * older than 11-STABLE in the future). + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/kernel.h> +#include <sys/lock.h> +#include <sys/malloc.h> +#include <sys/mutex.h> +#include <sys/random.h> +#include <sys/sysctl.h> +#include <sys/systm.h> + +#include <machine/cpu.h> + +#include <crypto/rijndael/rijndael-api-fst.h> +#include <crypto/sha2/sha2.h> + +#include <dev/random/hash.h> +#include <dev/random/randomdev.h> +#include <dev/random/random_harvestq.h> +#include <dev/random/uint128.h> +#include <dev/random/other_algorithm.h> + +static void random_other_pre_read(void); +static void random_other_read(uint8_t *, u_int); +static bool random_other_seeded(void); +static void random_other_process_event(struct harvest_event *); +static void random_other_init_alg(void *); +static void random_other_deinit_alg(void *); + +/* + * RANDOM_OTHER_NPOOLS is used when reading hardware random + * number sources to ensure that each pool gets one read sample + * per loop iteration. Yarrow has 2 such pools (FAST and SLOW), + * and fortuna has 32 (0-31). The RNG used prior to Yarrow and + * ported from Linux had just 1 pool. + */ +#define RANDOM_OTHER_NPOOLS 1 + +struct random_algorithm random_alg_context = { + .ra_ident = "other", + .ra_init_alg = random_other_init_alg, + .ra_deinit_alg = random_other_deinit_alg, + .ra_pre_read = random_other_pre_read, + .ra_read = random_other_read, + .ra_seeded = random_other_seeded, + .ra_event_processor = random_other_process_event, + .ra_poolcount = RANDOM_OTHER_NPOOLS, +}; + +/* Use a mutex to protect your reseed variables? */ +static mtx_t other_mtx; + +/* + * void random_other_init_alg(void *unused __unused) + * + * Do algorithm-specific initialisation here. + */ +void +random_other_init_alg(void *unused __unused) +{ + + RANDOM_RESEED_INIT_LOCK(); + /* + * Do set-up work here! + */ +} + +/* + * void random_other_deinit_alg(void *unused __unused) + * + * Do algorithm-specific deinitialisation here. + */ +static void +random_other_deinit_alg(void *unused __unused) +{ + + /* + * Do tear-down work here! + */ + RANDOM_RESEED_DEINIT_LOCK(); +} + +/* + * void random_other_pre_read(void) + * + * Do any pre-read preparation you need to. This will be called + * before >=1 calls to random_other_read() corresponding to one + * read(2). + * + * This routine will be called periodically while the generator is + * still blocked and a read is being attempted, giving you an + * opportunity to unblock. + */ +static void +random_other_pre_read(void) +{ + + RANDOM_RESEED_LOCK(); + /* + * Do pre-read housekeeping work here! + * You may use this as a chance to unblock the generator. + */ + RANDOM_RESEED_UNLOCK(); +} + +/* + * void random_other_read(uint8_t *buf, u_int count) + * + * Generate <count> bytes of output into <*buf>. + * You may use the fact that <count> will be a multiple of + * RANDOM_BLOCKSIZE for optimization purposes. + * + * This function will always be called with your generator + * unblocked and ready. If you are not ready to generate + * output here, then feel free to KASSERT() or panic(). + */ +static void +random_other_read(uint8_t *buf, u_int count) +{ + + RANDOM_RESEED_LOCK(); + /* + * Do random-number generation work here! + */ + RANDOM_RESEED_UNLOCK(); +} + +/* + * bool random_other_seeded(void) + * + * Return true if your generator is ready to generate + * output, and false otherwise. + */ +static bool +random_other_seeded(void) +{ + bool seeded = false; + + /* + * Find out if your generator is seeded here! + */ + return (seeded); +} + +/* + * void random_other_process_event(struct harvest_event *event) + * + * Process one stochastic event <*event> into your entropy + * processor. + * + * The structure of the event may change, so it is easier to + * just grab the whole thing into your accumulation system. + * You may pick-and-choose bits, but please don't complain + * when/if these change. + */ +static void +random_other_process_event(struct harvest_event *event) +{ + + RANDOM_RESEED_LOCK(); + /* + * Do entropy accumulation work here! + * You may use this as a chance to unblock the generator. + */ + RANDOM_RESEED_UNLOCK(); +} diff --git a/sys/dev/random/other_algorithm.h b/sys/dev/random/other_algorithm.h new file mode 100644 index 0000000..8ca2bb8 --- /dev/null +++ b/sys/dev/random/other_algorithm.h @@ -0,0 +1,62 @@ +/*- + * Copyright (c) 2015 Mark R V Murray + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/*- + * This is a skeleton for folks who wish to build a loadable module + * containing an alternative entropy-processing algorithm for random(4). + * + * The functions below should be completed with the appropriate code, + * and the nearby yarrow.c and fortuna.c may be consulted for examples + * of working code. + * + * The author is willing to provide reasonable help to those wishing to + * write such a module for themselves. Please use the markm@ FreeBSD + * email address, and ensure that you are developing this on a suitably + * supported branch (This is currently 11-CURRENT, and will be no + * older than 11-STABLE in the future). + */ + +#ifndef SYS_DEV_RANDOM_OTHER_H_INCLUDED +#define SYS_DEV_RANDOM_OTHER_H_INCLUDED + +#ifdef _KERNEL +typedef struct mtx mtx_t; +#define RANDOM_RESEED_INIT_LOCK(x) mtx_init(&other_mtx, "reseed mutex", NULL, MTX_DEF) +#define RANDOM_RESEED_DEINIT_LOCK(x) mtx_destroy(&other_mtx) +#define RANDOM_RESEED_LOCK(x) mtx_lock(&other_mtx) +#define RANDOM_RESEED_UNLOCK(x) mtx_unlock(&other_mtx) +#define RANDOM_RESEED_ASSERT_LOCK_OWNED(x) mtx_assert(&other_mtx, MA_OWNED) +#else +#define RANDOM_RESEED_INIT_LOCK(x) mtx_init(&other_mtx, mtx_plain) +#define RANDOM_RESEED_DEINIT_LOCK(x) mtx_destroy(&other_mtx) +#define RANDOM_RESEED_LOCK(x) mtx_lock(&other_mtx) +#define RANDOM_RESEED_UNLOCK(x) mtx_unlock(&other_mtx) +#define RANDOM_RESEED_ASSERT_LOCK_OWNED(x) +#endif + +#endif /* SYS_DEV_RANDOM_OTHER_H_INCLUDED */ diff --git a/sys/dev/random/random_harvestq.c b/sys/dev/random/random_harvestq.c index 34a809b..255136c 100644 --- a/sys/dev/random/random_harvestq.c +++ b/sys/dev/random/random_harvestq.c @@ -47,12 +47,21 @@ __FBSDID("$FreeBSD$"); #include <sys/sysctl.h> #include <sys/unistd.h> +#if defined(RANDOM_LOADABLE) +#include <sys/lock.h> +#include <sys/sx.h> +#endif + +#include <machine/atomic.h> #include <machine/cpu.h> #include <dev/random/randomdev.h> #include <dev/random/random_harvestq.h> static void random_kthread(void); +static void random_sources_feed(void); + +static u_int read_rate; /* List for the dynamic sysctls */ static struct sysctl_ctx_list random_clist; @@ -66,7 +75,7 @@ static struct sysctl_ctx_list random_clist; #define RANDOM_RING_MAX 1024 #define RANDOM_ACCUM_MAX 8 -/* 1 to let the kernel thread run, 0 to terminate */ +/* 1 to let the kernel thread run, 0 to terminate, -1 to mark completion */ volatile int random_kthread_control; /* @@ -123,13 +132,18 @@ static struct kproc_desc random_proc_kp = { &harvest_context.hc_kthread_proc, }; - /* Pass the given event straight through to Fortuna/Yarrow/Whatever. */ static __inline void random_harvestq_fast_process_event(struct harvest_event *event) { - if (random_alg_context.ra_event_processor) - random_alg_context.ra_event_processor(event); +#if defined(RANDOM_LOADABLE) + RANDOM_CONFIG_S_LOCK(); + if (p_random_alg_context) +#endif + p_random_alg_context->ra_event_processor(event); +#if defined(RANDOM_LOADABLE) + RANDOM_CONFIG_S_UNLOCK(); +#endif } static void @@ -163,12 +177,58 @@ random_kthread(void) /* XXX: FIX!! This is a *great* place to pass hardware/live entropy to random(9) */ tsleep_sbt(&harvest_context.hc_kthread_proc, 0, "-", SBT_1S/10, 0, C_PREL(1)); } + random_kthread_control = -1; wakeup(&harvest_context.hc_kthread_proc); kproc_exit(0); /* NOTREACHED */ } +/* This happens well after SI_SUB_RANDOM */ SYSINIT(random_device_h_proc, SI_SUB_CREATE_INIT, SI_ORDER_ANY, kproc_start, &random_proc_kp); +/* + * Run through all fast sources reading entropy for the given + * number of rounds, which should be a multiple of the number + * of entropy accumulation pools in use; 2 for Yarrow and 32 + * for Fortuna. + */ +static void +random_sources_feed(void) +{ + uint32_t entropy[HARVESTSIZE]; + struct random_sources *rrs; + u_int i, n, local_read_rate; + + /* + * Step over all of live entropy sources, and feed their output + * to the system-wide RNG. + */ +#if defined(RANDOM_LOADABLE) + RANDOM_CONFIG_S_LOCK(); + if (p_random_alg_context) { + /* It's an indenting error. Yeah, Yeah. */ +#endif + local_read_rate = atomic_readandclear_32(&read_rate); + LIST_FOREACH(rrs, &source_list, rrs_entries) { + for (i = 0; i < p_random_alg_context->ra_poolcount*(local_read_rate + 1); i++) { + n = rrs->rrs_source->rs_read(entropy, sizeof(entropy)); + KASSERT((n > 0 && n <= sizeof(entropy)), ("very bad return from rs_read (= %d) in %s", n, __func__)); + random_harvest_direct(entropy, n, (n*8)/2, rrs->rrs_source->rs_source); + } + } + explicit_bzero(entropy, sizeof(entropy)); +#if defined(RANDOM_LOADABLE) + } + RANDOM_CONFIG_S_UNLOCK(); +#endif +} + +void +read_rate_increment(u_int chunk) +{ + + atomic_add_32(&read_rate, chunk); +} + /* ARGSUSED */ RANDOM_CHECK_UINT(harvestmask, 0, RANDOM_HARVEST_EVERYTHING_MASK); @@ -317,7 +377,8 @@ random_harvestq_deinit(void *unused __unused) /* Command the hash/reseed thread to end and wait for it to finish */ random_kthread_control = 0; - tsleep(&harvest_context.hc_kthread_proc, 0, "harvqterm", 0); + while (random_kthread_control >= 0) + tsleep(&harvest_context.hc_kthread_proc, 0, "harvqterm", hz/5); sysctl_ctx_free(&random_clist); } SYSUNINIT(random_device_h_init, SI_SUB_RANDOM, SI_ORDER_SECOND, random_harvestq_deinit, NULL); @@ -412,3 +473,5 @@ random_harvest_direct(const void *entropy, u_int size, u_int bits, enum random_e random_harvestq_fast_process_event(&event); explicit_bzero(&event, sizeof(event)); } + +MODULE_VERSION(random_harvestq, 1); diff --git a/sys/dev/random/random_harvestq.h b/sys/dev/random/random_harvestq.h index f1de86f..421b592 100644 --- a/sys/dev/random/random_harvestq.h +++ b/sys/dev/random/random_harvestq.h @@ -43,6 +43,8 @@ struct harvest_event { uint8_t he_source; /* origin of the entropy */ } __packed; +void read_rate_increment(u_int); + #define RANDOM_HARVESTQ_BOOT_ENTROPY_FILE "/boot/entropy" #define RANDOM_HARVEST_INIT_LOCK(x) mtx_init(&harvest_context.hc_mtx, "entropy harvest mutex", NULL, MTX_SPIN) diff --git a/sys/dev/random/random_infra.c b/sys/dev/random/random_infra.c new file mode 100644 index 0000000..d31b84b --- /dev/null +++ b/sys/dev/random/random_infra.c @@ -0,0 +1,128 @@ +/*- + * Copyright (c) 2015 Mark R V Murray + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/random.h> +#include <sys/sysctl.h> + +#if defined(RANDOM_LOADABLE) +#include <sys/lock.h> +#include <sys/sx.h> +#endif + +#include <dev/random/randomdev.h> + +/* Set up the sysctl root node for the entropy device */ +SYSCTL_NODE(_kern, OID_AUTO, random, CTLFLAG_RW, 0, "Cryptographically Secure Random Number Generator"); + +MALLOC_DEFINE(M_ENTROPY, "entropy", "Entropy harvesting buffers and data structures"); + +struct sources_head source_list = LIST_HEAD_INITIALIZER(source_list); + +#if defined(RANDOM_LOADABLE) +struct random_algorithm *p_random_alg_context = NULL; +#else /* !defined(RANDOM_LOADABLE) */ +struct random_algorithm *p_random_alg_context = &random_alg_context; +#endif /* defined(RANDOM_LOADABLE) */ + +#if defined(RANDOM_LOADABLE) + +struct random_readers { + int (*read_random_uio)(struct uio *, bool); + u_int (*read_random)(void *, u_int); +} random_reader_context = { + (int (*)(struct uio *, bool))nullop, + (u_int (*)(void *, u_int))nullop, +}; + +struct sx randomdev_config_lock; + +static void +random_infra_sysinit(void *dummy __unused) +{ + + RANDOM_CONFIG_INIT_LOCK(); +} +SYSINIT(random_device_h_init, SI_SUB_RANDOM, SI_ORDER_FIRST, random_infra_sysinit, NULL); + +void +random_infra_init(int (*p_random_read_uio)(struct uio *, bool), u_int (*p_random_read)(void *, u_int)) +{ + + RANDOM_CONFIG_X_LOCK(); + random_reader_context.read_random_uio = p_random_read_uio; + random_reader_context.read_random = p_random_read; + RANDOM_CONFIG_X_UNLOCK(); +} + +void +random_infra_uninit(void) +{ + + RANDOM_CONFIG_X_LOCK(); + random_reader_context.read_random_uio = (int (*)(struct uio *, bool))nullop; + random_reader_context.read_random = (u_int (*)(void *, u_int))nullop; + RANDOM_CONFIG_X_UNLOCK(); +} + +static void +random_infra_sysuninit(void *dummy __unused) +{ + + RANDOM_CONFIG_DEINIT_LOCK(); +} +SYSUNINIT(random_device_h_init, SI_SUB_RANDOM, SI_ORDER_FIRST, random_infra_sysuninit, NULL); + +int +read_random_uio(struct uio *uio, bool nonblock) +{ + int retval; + + RANDOM_CONFIG_S_LOCK(); + retval = random_reader_context.read_random_uio(uio, nonblock); + RANDOM_CONFIG_S_UNLOCK(); + return (retval); +} + +u_int +read_random(void *buf, u_int len) +{ + u_int retval; + + RANDOM_CONFIG_S_LOCK(); + retval = random_reader_context.read_random(buf, len); + RANDOM_CONFIG_S_UNLOCK(); + return (retval); +} + +#endif /* defined(RANDOM_LOADABLE) */ diff --git a/sys/dev/random/randomdev.c b/sys/dev/random/randomdev.c index 5c20c5d..f20a462 100644 --- a/sys/dev/random/randomdev.c +++ b/sys/dev/random/randomdev.c @@ -56,14 +56,18 @@ __FBSDID("$FreeBSD$"); #include <dev/random/randomdev.h> #include <dev/random/random_harvestq.h> -#include "opt_random.h" +#define RANDOM_UNIT 0 -#if defined(RANDOM_DUMMY) && defined(RANDOM_YARROW) -#error "Cannot define both RANDOM_DUMMY and RANDOM_YARROW" +#if defined(RANDOM_LOADABLE) +#define READ_RANDOM_UIO _read_random_uio +#define READ_RANDOM _read_random +static int READ_RANDOM_UIO(struct uio *, bool); +static u_int READ_RANDOM(void *, u_int); +#else +#define READ_RANDOM_UIO read_random_uio +#define READ_RANDOM read_random #endif -#define RANDOM_UNIT 0 - /* Return the largest number >= x that is a multiple of m */ #define CEIL_TO_MULTIPLE(x, m) ((((x) + (m) - 1)/(m))*(m)) @@ -84,68 +88,31 @@ static struct cdevsw random_cdevsw = { /* For use with make_dev(9)/destroy_dev(9). */ static struct cdev *random_dev; -/* Set up the sysctl root node for the entropy device */ -SYSCTL_NODE(_kern, OID_AUTO, random, CTLFLAG_RW, 0, "Cryptographically Secure Random Number Generator"); - -MALLOC_DEFINE(M_ENTROPY, "entropy", "Entropy harvesting buffers and data structures"); - -#if defined(RANDOM_DUMMY) - -/*- - * Dummy "always block" pseudo algorithm, used when there is no real - * random(4) driver to provide a CSPRNG. - */ - -static u_int -dummy_random_zero(void) -{ - - return (0); -} - -static void -dummy_random(void) -{ -} - -struct random_algorithm random_alg_context = { - .ra_ident = "Dummy", - .ra_init_alg = NULL, - .ra_deinit_alg = NULL, - .ra_pre_read = dummy_random, - .ra_read = (random_alg_read_t *)dummy_random_zero, - .ra_write = (random_alg_write_t *)dummy_random_zero, - .ra_reseed = dummy_random, - .ra_seeded = (random_alg_seeded_t *)dummy_random_zero, - .ra_event_processor = NULL, - .ra_poolcount = 0, -}; - -#else /* !defined(RANDOM_DUMMY) */ - -LIST_HEAD(sources_head, random_sources); -static struct sources_head source_list = LIST_HEAD_INITIALIZER(source_list); -static u_int read_rate; - static void random_alg_context_ra_init_alg(void *data) { - random_alg_context.ra_init_alg(data); + p_random_alg_context = &random_alg_context; + p_random_alg_context->ra_init_alg(data); +#if defined(RANDOM_LOADABLE) + random_infra_init(READ_RANDOM_UIO, READ_RANDOM); +#endif } static void random_alg_context_ra_deinit_alg(void *data) { - random_alg_context.ra_deinit_alg(data); +#if defined(RANDOM_LOADABLE) + random_infra_uninit(); +#endif + p_random_alg_context->ra_deinit_alg(data); + p_random_alg_context = NULL; } SYSINIT(random_device, SI_SUB_RANDOM, SI_ORDER_THIRD, random_alg_context_ra_init_alg, NULL); SYSUNINIT(random_device, SI_SUB_RANDOM, SI_ORDER_THIRD, random_alg_context_ra_deinit_alg, NULL); -#endif /* defined(RANDOM_DUMMY) */ - static struct selinfo rsel; /* @@ -156,28 +123,28 @@ static int randomdev_read(struct cdev *dev __unused, struct uio *uio, int flags) { - return (read_random_uio(uio, (flags & O_NONBLOCK) != 0)); + return (READ_RANDOM_UIO(uio, (flags & O_NONBLOCK) != 0)); } int -read_random_uio(struct uio *uio, bool nonblock) +READ_RANDOM_UIO(struct uio *uio, bool nonblock) { uint8_t *random_buf; int error, spamcount; ssize_t read_len, total_read, c; random_buf = malloc(PAGE_SIZE, M_ENTROPY, M_WAITOK); - random_alg_context.ra_pre_read(); + p_random_alg_context->ra_pre_read(); error = 0; spamcount = 0; /* (Un)Blocking logic */ - while (!random_alg_context.ra_seeded()) { + while (!p_random_alg_context->ra_seeded()) { if (nonblock) { error = EWOULDBLOCK; break; } /* keep tapping away at the pre-read until we seed/unblock. */ - random_alg_context.ra_pre_read(); + p_random_alg_context->ra_pre_read(); /* Only bother the console every 10 seconds or so */ if (spamcount == 0) printf("random: %s unblock wait\n", __func__); @@ -187,10 +154,7 @@ read_random_uio(struct uio *uio, bool nonblock) break; } if (error == 0) { -#if !defined(RANDOM_DUMMY) - /* XXX: FIX!! Next line as an atomic operation? */ - read_rate += (uio->uio_resid + sizeof(uint32_t))/sizeof(uint32_t); -#endif + read_rate_increment((uio->uio_resid + sizeof(uint32_t))/sizeof(uint32_t)); total_read = 0; while (uio->uio_resid && !error) { read_len = uio->uio_resid; @@ -203,7 +167,7 @@ read_random_uio(struct uio *uio, bool nonblock) read_len = CEIL_TO_MULTIPLE(read_len, RANDOM_BLOCKSIZE); /* Work in chunks page-sized or less */ read_len = MIN(read_len, PAGE_SIZE); - random_alg_context.ra_read(random_buf, read_len); + p_random_alg_context->ra_read(random_buf, read_len); c = MIN(uio->uio_resid, read_len); error = uiomove(random_buf, c, uio); total_read += c; @@ -224,19 +188,16 @@ read_random_uio(struct uio *uio, bool nonblock) * RANDOM_BLOCKSIZE bytes. */ u_int -read_random(void *random_buf, u_int len) +READ_RANDOM(void *random_buf, u_int len) { u_int read_len; uint8_t local_buf[len + RANDOM_BLOCKSIZE]; KASSERT(random_buf != NULL, ("No suitable random buffer in %s", __func__)); - random_alg_context.ra_pre_read(); + p_random_alg_context->ra_pre_read(); /* (Un)Blocking logic; if not seeded, return nothing. */ - if (random_alg_context.ra_seeded()) { -#if !defined(RANDOM_DUMMY) - /* XXX: FIX!! Next line as an atomic operation? */ - read_rate += (len + sizeof(uint32_t))/sizeof(uint32_t); -#endif + if (p_random_alg_context->ra_seeded()) { + read_rate_increment((len + sizeof(uint32_t))/sizeof(uint32_t)); if (len > 0) { /* * Belt-and-braces. @@ -244,7 +205,7 @@ read_random(void *random_buf, u_int len) * which is what the underlying generator is expecting. */ read_len = CEIL_TO_MULTIPLE(len, RANDOM_BLOCKSIZE); - random_alg_context.ra_read(local_buf, read_len); + p_random_alg_context->ra_read(local_buf, read_len); memcpy(random_buf, local_buf, len); } } else @@ -252,6 +213,37 @@ read_random(void *random_buf, u_int len) return (len); } +static __inline void +randomdev_accumulate(uint8_t *buf, u_int count) +{ + static u_int destination = 0; + static struct harvest_event event; + static struct randomdev_hash hash; + static uint32_t entropy_data[RANDOM_KEYSIZE_WORDS]; + uint32_t timestamp; + int i; + + /* Extra timing here is helpful to scrape scheduler jitter entropy */ + randomdev_hash_init(&hash); + timestamp = (uint32_t)get_cyclecount(); + randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); + randomdev_hash_iterate(&hash, buf, count); + timestamp = (uint32_t)get_cyclecount(); + randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); + randomdev_hash_finish(&hash, entropy_data); + explicit_bzero(&hash, sizeof(hash)); + for (i = 0; i < RANDOM_KEYSIZE_WORDS; i += sizeof(event.he_entropy)/sizeof(event.he_entropy[0])) { + event.he_somecounter = (uint32_t)get_cyclecount(); + event.he_size = sizeof(event.he_entropy); + event.he_bits = event.he_size/8; + event.he_source = RANDOM_CACHED; + event.he_destination = destination++; /* Harmless cheating */ + memcpy(event.he_entropy, entropy_data + i, sizeof(event.he_entropy)); + p_random_alg_context->ra_event_processor(&event); + } + explicit_bzero(entropy_data, sizeof(entropy_data)); +} + /* ARGSUSED */ static int randomdev_write(struct cdev *dev __unused, struct uio *uio, int flags __unused) @@ -267,7 +259,7 @@ randomdev_write(struct cdev *dev __unused, struct uio *uio, int flags __unused) error = uiomove(random_buf, c, uio); if (error) break; - random_alg_context.ra_write(random_buf, c); + randomdev_accumulate(random_buf, c); tsleep(&random_alg_context, 0, "randwr", hz/10); } if (nbytes != uio->uio_resid && (error == ERESTART || error == EINTR)) @@ -283,7 +275,7 @@ randomdev_poll(struct cdev *dev __unused, int events, struct thread *td __unused { if (events & (POLLIN | POLLRDNORM)) { - if (random_alg_context.ra_seeded()) + if (p_random_alg_context->ra_seeded()) events &= (POLLIN | POLLRDNORM); else selrecord(td, &rsel); @@ -325,9 +317,6 @@ randomdev_ioctl(struct cdev *dev __unused, u_long cmd, caddr_t addr __unused, void random_source_register(struct random_source *rsource) { -#if defined(RANDOM_DUMMY) - (void)rsource; -#else /* !defined(RANDOM_DUMMY) */ struct random_sources *rrs; KASSERT(rsource != NULL, ("invalid input to %s", __func__)); @@ -337,15 +326,11 @@ random_source_register(struct random_source *rsource) printf("random: registering fast source %s\n", rsource->rs_ident); LIST_INSERT_HEAD(&source_list, rrs, rrs_entries); -#endif /* defined(RANDOM_DUMMY) */ } void random_source_deregister(struct random_source *rsource) { -#if defined(RANDOM_DUMMY) - (void)rsource; -#else /* !defined(RANDOM_DUMMY) */ struct random_sources *rrs = NULL; KASSERT(rsource != NULL, ("invalid input to %s", __func__)); @@ -356,41 +341,6 @@ random_source_deregister(struct random_source *rsource) } if (rrs != NULL) free(rrs, M_ENTROPY); -#endif /* defined(RANDOM_DUMMY) */ -} - -#if !defined(RANDOM_DUMMY) -/* - * Run through all fast sources reading entropy for the given - * number of rounds, which should be a multiple of the number - * of entropy accumulation pools in use; 2 for Yarrow and 32 - * for Fortuna. - * - * BEWARE!!! - * This function runs inside the RNG thread! Don't do anything silly! - */ -void -random_sources_feed(void) -{ - uint32_t entropy[HARVESTSIZE]; - struct random_sources *rrs; - u_int i, n, local_read_rate; - - /* - * Step over all of live entropy sources, and feed their output - * to the system-wide RNG. - */ - /* XXX: FIX!! Next lines as an atomic operation? */ - local_read_rate = read_rate; - read_rate = RANDOM_ALG_READ_RATE_MINIMUM; - LIST_FOREACH(rrs, &source_list, rrs_entries) { - for (i = 0; i < random_alg_context.ra_poolcount*local_read_rate; i++) { - n = rrs->rrs_source->rs_read(entropy, sizeof(entropy)); - KASSERT((n > 0 && n <= sizeof(entropy)), ("very bad return from rs_read (= %d) in %s", n, __func__)); - random_harvest_direct(entropy, n, (n*8)/2, rrs->rrs_source->rs_source); - } - } - explicit_bzero(entropy, sizeof(entropy)); } static int @@ -414,7 +364,6 @@ random_source_handler(SYSCTL_HANDLER_ARGS) SYSCTL_PROC(_kern_random, OID_AUTO, random_sources, CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0, random_source_handler, "A", "List of active fast entropy sources."); -#endif /* !defined(RANDOM_DUMMY) */ /* ARGSUSED */ static int @@ -449,3 +398,5 @@ static moduledata_t randomdev_mod = { DECLARE_MODULE(random_device, randomdev_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST); MODULE_VERSION(random_device, 1); +MODULE_DEPEND(random_device, crypto, 1, 1, 1); +MODULE_DEPEND(random_device, random_harvestq, 1, 1, 1); diff --git a/sys/dev/random/randomdev.h b/sys/dev/random/randomdev.h index 799efb1..0f3b359 100644 --- a/sys/dev/random/randomdev.h +++ b/sys/dev/random/randomdev.h @@ -55,16 +55,15 @@ random_check_uint_##name(SYSCTL_HANDLER_ARGS) \ MALLOC_DECLARE(M_ENTROPY); -#define RANDOM_ALG_READ_RATE_MINIMUM 32 - #endif /* _KERNEL */ struct harvest_event; +typedef void random_alg_init_t(void *); +typedef void random_alg_deinit_t(void *); typedef void random_alg_pre_read_t(void); typedef void random_alg_read_t(uint8_t *, u_int); -typedef void random_alg_write_t(uint8_t *, u_int); -typedef int random_alg_seeded_t(void); +typedef bool random_alg_seeded_t(void); typedef void random_alg_reseed_t(void); typedef void random_alg_eventprocessor_t(struct harvest_event *); @@ -81,13 +80,11 @@ struct random_algorithm { void (*ra_deinit_alg)(void *); random_alg_pre_read_t *ra_pre_read; random_alg_read_t *ra_read; - random_alg_write_t *ra_write; - random_alg_reseed_t *ra_reseed; random_alg_seeded_t *ra_seeded; random_alg_eventprocessor_t *ra_event_processor; }; -extern struct random_algorithm random_alg_context; +extern struct random_algorithm random_alg_context, *p_random_alg_context; #ifdef _KERNEL @@ -97,22 +94,33 @@ extern struct random_algorithm random_alg_context; * upon request. */ struct random_source { - const char *rs_ident; - enum random_entropy_source rs_source; - random_source_read_t *rs_read; + const char *rs_ident; + enum random_entropy_source rs_source; + random_source_read_t *rs_read; }; -#if !defined(RANDOM_DUMMY) struct random_sources { - LIST_ENTRY(random_sources) rrs_entries; - struct random_source *rrs_source; + LIST_ENTRY(random_sources) rrs_entries; + struct random_source *rrs_source; }; -#endif /* !defined(RANDOM_DUMMY) */ + +LIST_HEAD(sources_head, random_sources); +extern struct sources_head source_list; void random_source_register(struct random_source *); void random_source_deregister(struct random_source *); -void random_sources_feed(void); +#if defined(RANDOM_LOADABLE) +extern struct sx randomdev_config_lock; +#define RANDOM_CONFIG_INIT_LOCK(x) sx_init(&randomdev_config_lock, "configuration change lock") +#define RANDOM_CONFIG_X_LOCK(x) sx_xlock(&randomdev_config_lock) +#define RANDOM_CONFIG_X_UNLOCK(x) sx_xunlock(&randomdev_config_lock) +#define RANDOM_CONFIG_S_LOCK(x) sx_slock(&randomdev_config_lock) +#define RANDOM_CONFIG_S_UNLOCK(x) sx_sunlock(&randomdev_config_lock) +#define RANDOM_CONFIG_DEINIT_LOCK(x) sx_destroy(&randomdev_config_lock) +void random_infra_init(int (*)(struct uio *, bool), u_int (*)(void *, u_int)); +void random_infra_uninit(void); +#endif #endif /* _KERNEL */ diff --git a/sys/dev/random/randomdev_none.c b/sys/dev/random/randomdev_none.c deleted file mode 100644 index ee5cbf2..0000000 --- a/sys/dev/random/randomdev_none.c +++ /dev/null @@ -1,72 +0,0 @@ -/*- - * Copyright (c) 2015 Mark R V Murray - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/malloc.h> -#include <sys/random.h> -#include <sys/systm.h> - -#include <dev/random/randomdev.h> - -#include "opt_random.h" - -#if defined(RANDOM_DUMMY) || defined(RANDOM_YARROW) -#error "Cannot define any of RANDOM_DUMMY and RANDOM_YARROW without 'device random'" -#endif - -/*- - * Dummy "not even here" device. Stub out all routines that the kernel would need. - */ - -/* ARGSUSED */ -u_int -read_random(void *random_buf __unused, u_int len __unused) -{ - - return (0); -} - -/* ARGSUSED */ -void -random_harvest_direct(const void *entropy __unused, u_int count __unused, u_int bits __unused, enum random_entropy_source origin __unused) -{ -} - -/* ARGSUSED */ -void -random_harvest_queue(const void *entropy __unused, u_int count __unused, u_int bits __unused, enum random_entropy_source origin __unused) -{ -} - -/* ARGSUSED */ -void -random_harvest_fast(const void *entropy __unused, u_int count __unused, u_int bits __unused, enum random_entropy_source origin __unused) -{ -} diff --git a/sys/dev/random/unit_test.c b/sys/dev/random/unit_test.c index 7ae5716..fac4c8d 100644 --- a/sys/dev/random/unit_test.c +++ b/sys/dev/random/unit_test.c @@ -46,6 +46,7 @@ Where <alg> is YARROW or FORTUNA. #include <sys/types.h> #include <inttypes.h> +#include <stdbool.h> #include <stdio.h> #include <stdlib.h> #include <threads.h> @@ -172,35 +173,6 @@ RunHarvester(void *arg __unused) } static int -WriteCSPRNG(void *threadid) -{ - uint8_t *buf; - int i; - - printf("Thread #1 starts\n"); - - for (i = 0; ; i++) { - if (stopseeding) - break; - buf = malloc(4096); - if (i % 1000 == 0) - printf("Thread write 1 - %d\n", i); - if (buf != NULL) { - printf("Thread 1 writing.\n"); - random_alg_context.ra_write(buf, i); - free(buf); - } - usleep(1000000); - } - - printf("Thread #1 ends\n"); - - thrd_exit(0); - - return (0); -} - -static int ReadCSPRNG(void *threadid) { size_t tid, zsize; @@ -271,7 +243,7 @@ main(int argc, char *argv[]) for (t = 0; t < NUM_THREADS; t++) { printf("In main: creating thread %ld\n", t); - rc = thrd_create(&threads[t], (t == 0 ? RunHarvester : (t == 1 ? WriteCSPRNG : ReadCSPRNG)), NULL); + rc = thrd_create(&threads[t], (t == 0 ? RunHarvester : ReadCSPRNG), NULL); if (rc != thrd_success) { printf("ERROR; return code from thrd_create() is %d\n", rc); exit(-1); diff --git a/sys/dev/random/yarrow.c b/sys/dev/random/yarrow.c index d6ebd46..2ef15a4 100644 --- a/sys/dev/random/yarrow.c +++ b/sys/dev/random/yarrow.c @@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$"); #include <dev/random/yarrow.h> #else /* !_KERNEL */ #include <inttypes.h> +#include <stdbool.h> #include <stdio.h> #include <stdlib.h> #include <stdint.h> @@ -92,7 +93,7 @@ static struct yarrow_state { u_int ysp_thresh; /* pool reseed threshhold */ struct randomdev_hash ysp_hash; /* accumulated entropy */ } ys_pool[RANDOM_YARROW_NPOOLS];/* pool[0] is fast, pool[1] is slow */ - int ys_seeded; + bool ys_seeded; /* Reseed lock */ mtx_t ys_mtx; } yarrow_state; @@ -108,9 +109,7 @@ RANDOM_CHECK_UINT(slowoverthresh, 1, 5); static void random_yarrow_pre_read(void); static void random_yarrow_read(uint8_t *, u_int); -static void random_yarrow_write(uint8_t *, u_int); -static void random_yarrow_reseed(void); -static int random_yarrow_seeded(void); +static bool random_yarrow_seeded(void); static void random_yarrow_process_event(struct harvest_event *); static void random_yarrow_init_alg(void *); static void random_yarrow_deinit_alg(void *); @@ -123,8 +122,6 @@ struct random_algorithm random_alg_context = { .ra_deinit_alg = random_yarrow_deinit_alg, .ra_pre_read = random_yarrow_pre_read, .ra_read = random_yarrow_read, - .ra_write = random_yarrow_write, - .ra_reseed = random_yarrow_reseed, .ra_seeded = random_yarrow_seeded, .ra_event_processor = random_yarrow_process_event, .ra_poolcount = RANDOM_YARROW_NPOOLS, @@ -141,7 +138,7 @@ random_yarrow_init_alg(void *unused __unused) RANDOM_RESEED_INIT_LOCK(); /* Start unseeded, therefore blocked. */ - yarrow_state.ys_seeded = 0; + yarrow_state.ys_seeded = false; #ifdef _KERNEL /* * Yarrow parameters. Do not adjust these unless you have @@ -266,12 +263,14 @@ random_yarrow_reseed_internal(u_int fastslow) RANDOM_RESEED_ASSERT_LOCK_OWNED(); #ifdef RANDOM_DEBUG /* WARNING! This is dangerously tedious to do with mutexes held! */ - printf("random: %s %s seeded = %d\n", __func__, (fastslow == RANDOM_YARROW_FAST ? "RANDOM_YARROW_FAST" : "RANDOM_YARROW_SLOW"), yarrow_state.ys_seeded); - printf("random: %s - fast - thresh %d,1 - ", __func__, yarrow_state.ys_pool[RANDOM_YARROW_FAST].ysp_thresh); + printf("random: %s ", __func__); + printf("type/pool = %s ", fastslow == RANDOM_YARROW_FAST ? "RANDOM_YARROW_FAST" : "RANDOM_YARROW_SLOW"); + printf("seeded = %s\n", yarrow_state.ys_seeded ? "true" : "false"); + printf("random: fast - thresh %d,1 - ", yarrow_state.ys_pool[RANDOM_YARROW_FAST].ysp_thresh); for (i = RANDOM_START; i < ENTROPYSOURCE; i++) printf(" %d", yarrow_state.ys_pool[RANDOM_YARROW_FAST].ysp_source_bits[i]); printf("\n"); - printf("random: %s - slow - thresh %d,%d - ", __func__, yarrow_state.ys_pool[RANDOM_YARROW_SLOW].ysp_thresh, yarrow_state.ys_slowoverthresh); + printf("random: slow - thresh %d,%d - ", yarrow_state.ys_pool[RANDOM_YARROW_SLOW].ysp_thresh, yarrow_state.ys_slowoverthresh); for (i = RANDOM_START; i < ENTROPYSOURCE; i++) printf(" %d", yarrow_state.ys_pool[RANDOM_YARROW_SLOW].ysp_source_bits[i]); printf("\n"); @@ -338,7 +337,7 @@ random_yarrow_reseed_internal(u_int fastslow) #endif /* Unblock the device if it was blocked due to being unseeded */ if (!yarrow_state.ys_seeded) { - yarrow_state.ys_seeded = 1; + yarrow_state.ys_seeded = true; randomdev_unblock(); } } @@ -395,47 +394,7 @@ random_yarrow_read(uint8_t *buf, u_int bytecount) RANDOM_RESEED_UNLOCK(); } -/* Internal function to hand external entropy to the PRNG. */ -void -random_yarrow_write(uint8_t *buf, u_int count) -{ - static u_int destination = 0; - static struct harvest_event event; - struct randomdev_hash hash; - uint32_t entropy_data[RANDOM_KEYSIZE_WORDS], timestamp; - int i; - - /* Extra timing here is helpful to scrape scheduler timing entropy */ - randomdev_hash_init(&hash); - timestamp = (uint32_t)get_cyclecount(); - randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); - randomdev_hash_iterate(&hash, buf, count); - timestamp = (uint32_t)get_cyclecount(); - randomdev_hash_iterate(&hash, ×tamp, sizeof(timestamp)); - randomdev_hash_finish(&hash, entropy_data); - explicit_bzero(&hash, sizeof(hash)); - for (i = 0; i < RANDOM_KEYSIZE_WORDS; i += sizeof(event.he_entropy)/sizeof(event.he_entropy[0])) { - event.he_somecounter = (uint32_t)get_cyclecount(); - event.he_size = sizeof(event.he_entropy); - event.he_bits = event.he_size/8; - event.he_source = RANDOM_CACHED; - event.he_destination = destination++; /* Harmless cheating */ - memcpy(event.he_entropy, entropy_data + i, sizeof(event.he_entropy)); - random_yarrow_process_event(&event); - } - explicit_bzero(entropy_data, sizeof(entropy_data)); -} - -void -random_yarrow_reseed(void) -{ - - RANDOM_RESEED_LOCK(); - random_yarrow_reseed_internal(RANDOM_YARROW_SLOW); - RANDOM_RESEED_UNLOCK(); -} - -int +bool random_yarrow_seeded(void) { diff --git a/sys/dev/usb/controller/dwc_otg.c b/sys/dev/usb/controller/dwc_otg.c index bd3e51b..e018ab5 100644 --- a/sys/dev/usb/controller/dwc_otg.c +++ b/sys/dev/usb/controller/dwc_otg.c @@ -1,7 +1,7 @@ /* $FreeBSD$ */ /*- * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. - * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. + * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -597,14 +597,18 @@ dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) } static uint8_t -dwc_otg_host_check_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) +dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { uint32_t temp; temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); - if (td->ep_type == UE_INTERRUPT || - td->ep_type == UE_ISOCHRONOUS) { + if (td->ep_type == UE_ISOCHRONOUS) { + /* + * NOTE: USB INTERRUPT transactions are executed like + * USB CONTROL transactions! See the setup standard + * chain function for more information. + */ if (!(temp & GINTSTS_PTXFEMP)) { DPRINTF("Periodic TX FIFO is not empty\n"); if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { @@ -631,8 +635,10 @@ dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t is_out) { uint8_t x; + uint8_t y; + uint8_t z; - if (td->channel < DWC_OTG_MAX_CHANNELS) + if (td->channel[0] < DWC_OTG_MAX_CHANNELS) return (0); /* already allocated */ /* check if device is suspended */ @@ -641,20 +647,42 @@ dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, /* compute needed TX FIFO size */ if (is_out != 0) { - if (dwc_otg_host_check_fifo_empty(sc, td) != 0) + if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) return (1); /* busy - cannot transfer data */ } - - for (x = 0; x != sc->sc_host_ch_max; x++) { + z = td->max_packet_count; + for (x = y = 0; x != sc->sc_host_ch_max; x++) { /* check if channel is allocated */ if (sc->sc_chan_state[x].allocated != 0) continue; /* check if channel is still enabled */ if (sc->sc_chan_state[x].wait_halted != 0) continue; + /* store channel number */ + td->channel[y++] = x; + /* check if we got all channels */ + if (y == z) + break; + } + if (y != z) { + /* reset channel variable */ + td->channel[0] = DWC_OTG_MAX_CHANNELS; + td->channel[1] = DWC_OTG_MAX_CHANNELS; + td->channel[2] = DWC_OTG_MAX_CHANNELS; + /* wait a bit */ + dwc_otg_enable_sof_irq(sc); + return (1); /* busy - not enough channels */ + } + + for (y = 0; y != z; y++) { + x = td->channel[y]; + /* set allocated */ sc->sc_chan_state[x].allocated = 1; + /* set wait halted */ + sc->sc_chan_state[x].wait_halted = 1; + /* clear interrupts */ dwc_otg_clear_hcint(sc, x); @@ -663,29 +691,22 @@ dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, /* set active channel */ sc->sc_active_rx_ep |= (1 << x); - - /* set channel */ - td->channel = x; - - return (0); /* allocated */ } - /* wait a bit */ - dwc_otg_enable_sof_irq(sc); - return (1); /* busy */ + return (0); /* allocated */ } static void -dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) +dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) { uint32_t hcchar; uint8_t x; - if (td->channel >= DWC_OTG_MAX_CHANNELS) + if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) return; /* already freed */ /* free channel */ - x = td->channel; - td->channel = DWC_OTG_MAX_CHANNELS; + x = td->channel[index]; + td->channel[index] = DWC_OTG_MAX_CHANNELS; DPRINTF("CH=%d\n", x); @@ -704,26 +725,42 @@ dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) /* clear active channel */ sc->sc_active_rx_ep &= ~(1 << x); + /* check if already halted */ + if (sc->sc_chan_state[x].wait_halted == 0) + return; + /* disable host channel */ hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); if (hcchar & HCCHAR_CHENA) { DPRINTF("Halting channel %d\n", x); DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), hcchar | HCCHAR_CHDIS); - sc->sc_chan_state[x].wait_halted = 1; /* don't write HCCHAR until the channel is halted */ + } else { + sc->sc_chan_state[x].wait_halted = 0; } } static void +dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) +{ + uint8_t x; + for (x = 0; x != td->max_packet_count; x++) + dwc_otg_host_channel_free_sub(sc, td, x); +} + +static void dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { + uint8_t x; /* dump any pending messages */ - if (sc->sc_last_rx_status != 0) { - if (td->channel < DWC_OTG_MAX_CHANNELS && - td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { - dwc_otg_common_rx_ack(sc); - } + if (sc->sc_last_rx_status == 0) + return; + for (x = 0; x != td->max_packet_count; x++) { + if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || + td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) + continue; + dwc_otg_common_rx_ack(sc); } } @@ -737,13 +774,13 @@ dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) dwc_otg_host_dump_rx(sc, td); - if (td->channel < DWC_OTG_MAX_CHANNELS) { - hcint = sc->sc_chan_state[td->channel].hcint; + if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { + hcint = sc->sc_chan_state[td->channel[0]].hcint; DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", - td->channel, td->state, hcint, - DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), - DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); + td->channel[0], td->state, hcint, + DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), + DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); } else { hcint = 0; goto check_state; @@ -753,12 +790,12 @@ dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) HCINT_ACK | HCINT_NYET)) { /* give success bits priority over failure bits */ } else if (hcint & HCINT_STALL) { - DPRINTF("CH=%d STALL\n", td->channel); + DPRINTF("CH=%d STALL\n", td->channel[0]); td->error_stall = 1; td->error_any = 1; goto complete; } else if (hcint & HCINT_ERRORS) { - DPRINTF("CH=%d ERROR\n", td->channel); + DPRINTF("CH=%d ERROR\n", td->channel[0]); td->errcnt++; if (td->hcsplt != 0 || td->errcnt >= 3) { td->error_any = 1; @@ -863,23 +900,23 @@ send_pkt: usbd_copy_out(td->pc, 0, &req, sizeof(req)); - DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), + DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); - DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); + DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); hcchar = td->hcchar; hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; /* must enable channel before writing data to FIFO */ - DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); + DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); /* transfer data into FIFO */ bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, - DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); + DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); /* wait until next slot before trying complete split */ td->tt_complete_slot = sc->sc_last_frame_num + 1; @@ -916,17 +953,17 @@ send_cpkt: td->hcsplt |= HCSPLT_COMPSPLT; td->state = DWC_CHAN_ST_WAIT_C_ANE; - DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), + DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); - DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); + DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); hcchar = td->hcchar; hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; /* must enable channel before writing data to FIFO */ - DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); + DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); busy: return (1); /* busy */ @@ -1060,50 +1097,51 @@ dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *t static uint8_t dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { + uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; + if (td->ep_type == UE_ISOCHRONOUS) { /* non TT isochronous traffic */ - if ((td->tmr_val != 0) || - (sc->sc_last_frame_num & (td->tmr_res - 1))) { + if (frame_num & (td->tmr_res - 1)) goto busy; - } - td->tmr_val = 1; /* executed */ + if ((frame_num ^ td->tmr_val) & td->tmr_res) + goto busy; + td->tmr_val = td->tmr_res + sc->sc_last_frame_num; td->toggle = 0; - + return (0); } else if (td->ep_type == UE_INTERRUPT) { if (!td->tt_scheduled) goto busy; td->tt_scheduled = 0; + return (0); } else if (td->did_nak != 0) { - uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; /* check if we should pause sending queries for 125us */ if (td->tmr_res == frame_num) { /* wait a bit */ dwc_otg_enable_sof_irq(sc); goto busy; } - /* query for data one more time */ - td->tmr_res = frame_num; - td->did_nak = 0; } else if (td->set_toggle) { td->set_toggle = 0; td->toggle = 1; } + /* query for data one more time */ + td->tmr_res = frame_num; + td->did_nak = 0; return (0); busy: return (1); } static uint8_t -dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) +dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, + uint8_t channel) { uint32_t count; - uint8_t channel; /* check endpoint status */ if (sc->sc_last_rx_status == 0) goto busy; - channel = td->channel; if (channel >= DWC_OTG_MAX_CHANNELS) goto busy; @@ -1128,21 +1166,22 @@ dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) /* get the packet byte count */ count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); - /* check for isochronous transfer or high-speed bandwidth endpoint */ - if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { - if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { + /* check for ISOCHRONOUS endpoint */ + if (td->ep_type == UE_ISOCHRONOUS) { + if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != + GRXSTSRD_DPID_DATA0) { + /* more data to be received */ td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; } else { + /* all data received */ td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; - /* verify the packet byte count */ - if (count < td->max_packet_size) { + if (count != td->remainder) { /* we have a short packet */ td->short_pkt = 1; td->got_short = 1; } } - td->toggle = 0; } else { /* verify the packet byte count */ if (count != td->max_packet_size) { @@ -1194,15 +1233,17 @@ complete: static uint8_t dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) { - uint32_t hcint; + uint32_t hcint = 0; uint32_t hcchar; uint8_t delta; uint8_t channel; + uint8_t x; - channel = td->channel; - - if (channel < DWC_OTG_MAX_CHANNELS) { - hcint = sc->sc_chan_state[channel].hcint; + for (x = 0; x != td->max_packet_count; x++) { + channel = td->channel[x]; + if (channel >= DWC_OTG_MAX_CHANNELS) + continue; + hcint |= sc->sc_chan_state[channel].hcint; DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", channel, td->state, hcint, @@ -1230,19 +1271,17 @@ dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) } /* check channels for data, if any */ - if (dwc_otg_host_data_rx_sub(sc, td)) + if (dwc_otg_host_data_rx_sub(sc, td, channel)) goto complete; /* refresh interrupt status */ - hcint = sc->sc_chan_state[channel].hcint; + hcint |= sc->sc_chan_state[channel].hcint; if (hcint & (HCINT_ERRORS | HCINT_RETRY | HCINT_ACK | HCINT_NYET)) { if (!(hcint & HCINT_ERRORS)) td->errcnt = 0; } - } else { - hcint = 0; } switch (td->state) { @@ -1269,6 +1308,8 @@ dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) td->toggle ^= 1; goto receive_pkt; } + } else if (td->ep_type == UE_ISOCHRONOUS) { + goto complete; } td->did_nak = 1; td->tt_scheduled = 0; @@ -1292,12 +1333,12 @@ dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) if (td->ep_type == UE_ISOCHRONOUS) { /* check if we are complete */ - if ((td->remainder == 0) || - (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { + if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { goto complete; + } else { + /* get more packets */ + goto busy; } - /* get another packet */ - goto receive_pkt; } else { /* check if we are complete */ if ((td->remainder == 0) || (td->got_short != 0)) { @@ -1365,8 +1406,7 @@ receive_pkt: } /* complete split */ td->hcsplt |= HCSPLT_COMPSPLT; - } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && - dwc_otg_host_rate_check(sc, td)) { + } else if (dwc_otg_host_rate_check(sc, td)) { td->state = DWC_CHAN_ST_WAIT_C_PKT; goto busy; } @@ -1377,8 +1417,6 @@ receive_pkt: goto busy; } - channel = td->channel; - /* set toggle, if any */ if (td->set_toggle) { td->set_toggle = 0; @@ -1387,28 +1425,31 @@ receive_pkt: td->state = DWC_CHAN_ST_WAIT_ANE; - /* receive one packet */ - DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), - (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | - (1 << HCTSIZ_PKTCNT_SHIFT) | - (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : - (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); + for (x = 0; x != td->max_packet_count; x++) { + channel = td->channel[x]; - DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); + /* receive one packet */ + DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), + (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | + (1 << HCTSIZ_PKTCNT_SHIFT) | + (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : + (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); - hcchar = td->hcchar; - hcchar |= HCCHAR_EPDIR_IN; + DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); - /* receive complete split ASAP */ - if ((sc->sc_last_frame_num & 1) != 0 && - (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) - hcchar |= HCCHAR_ODDFRM; - else - hcchar &= ~HCCHAR_ODDFRM; + hcchar = td->hcchar; + hcchar |= HCCHAR_EPDIR_IN; - /* must enable channel before data can be received */ - DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); + /* receive complete split ASAP */ + if ((sc->sc_last_frame_num & 1) != 0 && + td->ep_type == UE_ISOCHRONOUS) + hcchar |= HCCHAR_ODDFRM; + else + hcchar &= ~HCCHAR_ODDFRM; + /* must enable channel before data can be received */ + DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); + } /* wait until next slot before trying complete split */ td->tt_complete_slot = sc->sc_last_frame_num + 1; @@ -1437,7 +1478,7 @@ receive_spkt: goto busy; } - channel = td->channel; + channel = td->channel[0]; td->hcsplt &= ~HCSPLT_COMPSPLT; td->state = DWC_CHAN_ST_WAIT_S_ANE; @@ -1450,7 +1491,7 @@ receive_spkt: /* send after next SOF event */ if ((sc->sc_last_frame_num & 1) == 0 && - (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) + td->ep_type == UE_ISOCHRONOUS) td->hcchar |= HCCHAR_ODDFRM; else td->hcchar &= ~HCCHAR_ODDFRM; @@ -1605,10 +1646,12 @@ dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) uint32_t hcchar; uint8_t delta; uint8_t channel; + uint8_t x; dwc_otg_host_dump_rx(sc, td); - channel = td->channel; + /* check that last channel is complete */ + channel = td->channel[td->npkt]; if (channel < DWC_OTG_MAX_CHANNELS) { hcint = sc->sc_chan_state[channel].hcint; @@ -1658,7 +1701,11 @@ dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) td->offset += td->tx_bytes; td->remainder -= td->tx_bytes; td->toggle ^= 1; - td->did_nak = 0; + /* check if next response will be a NAK */ + if (hcint & HCINT_NYET) + td->did_nak = 1; + else + td->did_nak = 0; td->tt_scheduled = 0; /* check remainder */ @@ -1715,33 +1762,13 @@ dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) goto send_cpkt; case DWC_CHAN_ST_TX_WAIT_ISOC: - - /* Check if isochronous OUT traffic is complete */ + /* Check if ISOCHRONOUS OUT traffic is complete */ if ((hcint & HCINT_HCH_DONE_MASK) == 0) break; td->offset += td->tx_bytes; td->remainder -= td->tx_bytes; - - if (td->hcsplt != 0 || td->remainder == 0) - goto complete; - - /* check for next packet */ - if (td->max_packet_count > 1) - td->tt_xactpos++; - - /* free existing channel, if any */ - dwc_otg_host_channel_free(sc, td); - - td->state = DWC_CHAN_ST_TX_PKT_ISOC; - - /* FALLTHROUGH */ - - case DWC_CHAN_ST_TX_PKT_ISOC: - if (dwc_otg_host_channel_alloc(sc, td, 1)) - break; - channel = td->channel; - goto send_isoc_pkt; + goto complete; default: break; } @@ -1775,8 +1802,6 @@ send_pkt: goto busy; } - channel = td->channel; - /* set toggle, if any */ if (td->set_toggle) { td->set_toggle = 0; @@ -1784,8 +1809,7 @@ send_pkt: } if (td->ep_type == UE_ISOCHRONOUS) { -send_isoc_pkt: - /* Isochronous OUT transfers don't have any ACKs */ + /* ISOCHRONOUS OUT transfers don't have any ACKs */ td->state = DWC_CHAN_ST_TX_WAIT_ISOC; td->hcsplt &= ~HCSPLT_COMPSPLT; if (td->hcsplt != 0) { @@ -1799,123 +1823,110 @@ send_isoc_pkt: /* Update transaction position */ td->hcsplt &= ~HCSPLT_XACTPOS_MASK; td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); - } else { - /* send one packet at a time */ - count = td->max_packet_size; - if (td->remainder < count) { - /* we have a short packet */ - td->short_pkt = 1; - count = td->remainder; - } } } else if (td->hcsplt != 0) { - td->hcsplt &= ~HCSPLT_COMPSPLT; - /* Wait for ACK/NAK/ERR from TT */ td->state = DWC_CHAN_ST_WAIT_S_ANE; - - /* send one packet at a time */ - count = td->max_packet_size; - if (td->remainder < count) { - /* we have a short packet */ - td->short_pkt = 1; - count = td->remainder; - } } else { /* Wait for ACK/NAK/STALL from device */ td->state = DWC_CHAN_ST_WAIT_ANE; + } + + td->tx_bytes = 0; + + for (x = 0; x != td->max_packet_count; x++) { + uint32_t rem_bytes; + + channel = td->channel[x]; /* send one packet at a time */ count = td->max_packet_size; - if (td->remainder < count) { + rem_bytes = td->remainder - td->tx_bytes; + if (rem_bytes < count) { /* we have a short packet */ td->short_pkt = 1; - count = td->remainder; - } - } - - /* check for High-Speed multi-packets */ - if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { - if (td->npkt == 0) { - if (td->remainder >= (3 * td->max_packet_size)) - td->npkt = 3; - else if (td->remainder >= (2 * td->max_packet_size)) - td->npkt = 2; - else - td->npkt = 1; - - if (td->npkt > td->max_packet_count) - td->npkt = td->max_packet_count; - - td->tt_xactpos = 1; /* overload */ + count = rem_bytes; } - if (td->tt_xactpos == td->npkt) { - if (td->npkt == 1) { + if (count == rem_bytes) { + /* last packet */ + switch (x) { + case 0: DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | - (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); - } else if (td->npkt == 2) { + (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : + (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); + break; + case 1: DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); - } else { + break; + default: DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); + break; } - td->npkt = 0; - } else { + } else if (td->ep_type == UE_ISOCHRONOUS && + td->max_packet_count > 1) { + /* ISOCHRONOUS multi packet */ DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), (count << HCTSIZ_XFERSIZE_SHIFT) | (1 << HCTSIZ_PKTCNT_SHIFT) | (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); + } else { + /* TODO: HCTSIZ_DOPNG */ + /* standard BULK/INTERRUPT/CONTROL packet */ + DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), + (count << HCTSIZ_XFERSIZE_SHIFT) | + (1 << HCTSIZ_PKTCNT_SHIFT) | + (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : + (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); } - } else { - /* TODO: HCTSIZ_DOPNG */ - DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), - (count << HCTSIZ_XFERSIZE_SHIFT) | - (1 << HCTSIZ_PKTCNT_SHIFT) | - (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : - (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); - } + DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); - DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); + hcchar = td->hcchar; + hcchar &= ~HCCHAR_EPDIR_IN; - hcchar = td->hcchar; - hcchar &= ~HCCHAR_EPDIR_IN; + /* send after next SOF event */ + if ((sc->sc_last_frame_num & 1) == 0 && + td->ep_type == UE_ISOCHRONOUS) + hcchar |= HCCHAR_ODDFRM; + else + hcchar &= ~HCCHAR_ODDFRM; - /* send after next SOF event */ - if ((sc->sc_last_frame_num & 1) == 0 && - (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) - hcchar |= HCCHAR_ODDFRM; - else - hcchar &= ~HCCHAR_ODDFRM; + /* must enable before writing data to FIFO */ + DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); - /* must enable before writing data to FIFO */ - DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); + if (count != 0) { + /* clear topmost word before copy */ + sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; - if (count != 0) { + /* copy out data */ + usbd_copy_out(td->pc, td->offset + td->tx_bytes, + sc->sc_tx_bounce_buffer, count); - /* clear topmost word before copy */ - sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; + /* transfer data into FIFO */ + bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, + DOTG_DFIFO(channel), + sc->sc_tx_bounce_buffer, (count + 3) / 4); + } - /* copy out data */ - usbd_copy_out(td->pc, td->offset, - sc->sc_tx_bounce_buffer, count); + /* store number of bytes transmitted */ + td->tx_bytes += count; - /* transfer data into FIFO */ - bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, - DOTG_DFIFO(channel), - sc->sc_tx_bounce_buffer, (count + 3) / 4); + /* store last packet index */ + td->npkt = x; + + /* check for last packet */ + if (count == rem_bytes) + break; } - - /* store number of bytes transmitted */ - td->tx_bytes = count; goto busy; send_cpkt: @@ -1941,7 +1952,7 @@ send_cpkt: goto busy; } - channel = td->channel; + channel = td->channel[0]; td->hcsplt |= HCSPLT_COMPSPLT; td->state = DWC_CHAN_ST_WAIT_C_ANE; @@ -1956,7 +1967,7 @@ send_cpkt: /* receive complete split ASAP */ if ((sc->sc_last_frame_num & 1) != 0 && - (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) + td->ep_type == UE_ISOCHRONOUS) hcchar |= HCCHAR_ODDFRM; else hcchar &= ~HCCHAR_ODDFRM; @@ -2383,9 +2394,6 @@ dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) continue; - /* execute more frames */ - td->tmr_val = 0; - sc->sc_needsof = 1; if (td->hcsplt == 0 || td->tt_scheduled != 0) @@ -2417,9 +2425,6 @@ dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) continue; - /* execute more frames */ - td->tmr_val = 0; - sc->sc_needsof = 1; if (td->hcsplt == 0 || td->tt_scheduled != 0) @@ -2513,10 +2518,10 @@ dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); - /* put non-TT BULK transfers last */ + /* put non-TT non-ISOCHRONOUS transfers last */ TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { td = xfer->td_transfer_cache; - if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) + if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) continue; TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); TAILQ_INSERT_TAIL(&head, xfer, wait_entry); @@ -2551,11 +2556,19 @@ static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) { struct usb_xfer *xfer; - uint32_t count = 0; + uint32_t count; uint32_t temp; uint8_t got_rx_status; uint8_t x; + if (sc->sc_flags.status_device_mode == 0) { + /* + * Update host transfer schedule, so that new + * transfers can be issued: + */ + dwc_otg_update_host_transfer_schedule_locked(sc); + } + count = 0; repeat: if (++count == 16) { /* give other interrupts a chance */ @@ -2659,12 +2672,6 @@ repeat: sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } - - if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { - /* update host transfer schedule, so that new transfers can be issued */ - if (dwc_otg_update_host_transfer_schedule_locked(sc)) - goto repeat; - } } static void @@ -2944,12 +2951,6 @@ dwc_otg_interrupt(void *arg) /* complete FIFOs, if any */ dwc_otg_interrupt_complete_locked(sc); - - if (sc->sc_flags.status_device_mode == 0) { - /* update host transfer schedule, so that new transfers can be issued */ - if (dwc_otg_update_host_transfer_schedule_locked(sc)) - dwc_otg_interrupt_poll_locked(sc); - } } USB_BUS_SPIN_UNLOCK(&sc->sc_bus); USB_BUS_UNLOCK(&sc->sc_bus); @@ -2982,7 +2983,9 @@ dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) td->set_toggle = 0; td->got_short = 0; td->did_nak = 0; - td->channel = DWC_OTG_MAX_CHANNELS; + td->channel[0] = DWC_OTG_MAX_CHANNELS; + td->channel[1] = DWC_OTG_MAX_CHANNELS; + td->channel[2] = DWC_OTG_MAX_CHANNELS; td->state = 0; td->errcnt = 0; td->tt_scheduled = 0; @@ -3247,8 +3250,10 @@ dwc_otg_setup_standard_chain(struct usb_xfer *xfer) td->tmr_val = sc->sc_tmr_val + ival; td->tmr_res = ival; } else if (td->ep_type == UE_ISOCHRONOUS) { - td->tmr_val = 0; td->tmr_res = 1; + td->tmr_val = sc->sc_last_frame_num; + if (td->hcchar & HCCHAR_EPDIR_IN) + td->tmr_val++; } else { td->tmr_val = 0; td->tmr_res = (uint8_t)sc->sc_last_frame_num; @@ -3258,10 +3263,8 @@ dwc_otg_setup_standard_chain(struct usb_xfer *xfer) hcsplt = 0; if (td->ep_type == UE_INTERRUPT) { uint32_t ival; -#if 0 hcchar |= ((xfer->max_packet_count & 3) << HCCHAR_MC_SHIFT); -#endif ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; if (ival == 0) ival = 1; @@ -3272,8 +3275,11 @@ dwc_otg_setup_standard_chain(struct usb_xfer *xfer) } else if (td->ep_type == UE_ISOCHRONOUS) { hcchar |= ((xfer->max_packet_count & 3) << HCCHAR_MC_SHIFT); - td->tmr_val = 0; td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); + td->tmr_val = sc->sc_last_frame_num; + if (td->hcchar & HCCHAR_EPDIR_IN) + td->tmr_val += td->tmr_res; + } else { td->tmr_val = 0; td->tmr_res = (uint8_t)sc->sc_last_frame_num; @@ -3330,6 +3336,19 @@ dwc_otg_start_standard_chain(struct usb_xfer *xfer) dwc_otg_xfer_do_fifo(sc, xfer); if (dwc_otg_xfer_do_complete_locked(sc, xfer)) goto done; + } else { + struct dwc_otg_td *td = xfer->td_transfer_cache; + if (td->ep_type == UE_ISOCHRONOUS && + (td->hcchar & HCCHAR_EPDIR_IN) == 0) { + /* + * Need to start ISOCHRONOUS OUT transfer ASAP + * because execution is delayed by one 125us + * microframe: + */ + dwc_otg_xfer_do_fifo(sc, xfer); + if (dwc_otg_xfer_do_complete_locked(sc, xfer)) + goto done; + } } /* put transfer on interrupt queue */ @@ -3950,11 +3969,6 @@ dwc_otg_do_poll(struct usb_bus *bus) USB_BUS_SPIN_LOCK(&sc->sc_bus); dwc_otg_interrupt_poll_locked(sc); dwc_otg_interrupt_complete_locked(sc); - if (sc->sc_flags.status_device_mode == 0) { - /* update host transfer schedule, so that new transfers can be issued */ - if (dwc_otg_update_host_transfer_schedule_locked(sc)) - dwc_otg_interrupt_poll_locked(sc); - } USB_BUS_SPIN_UNLOCK(&sc->sc_bus); USB_BUS_UNLOCK(&sc->sc_bus); } @@ -4728,6 +4742,9 @@ dwc_otg_xfer_setup(struct usb_setup_params *parm) /* init TD */ td->max_packet_size = xfer->max_packet_size; td->max_packet_count = xfer->max_packet_count; + /* range check */ + if (td->max_packet_count == 0 || td->max_packet_count > 3) + td->max_packet_count = 1; td->ep_no = ep_no; td->ep_type = ep_type; td->obj_next = last_obj; @@ -4766,12 +4783,13 @@ dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, return; } } else { - if (udev->speed == USB_SPEED_HIGH) { - if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { - /* high bandwidth endpoint - not tested */ - DPRINTF("High Bandwidth Endpoint - not tested\n"); - return; - } + if (udev->speed == USB_SPEED_HIGH && + (edesc->wMaxPacketSize[1] & 0x18) != 0 && + (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { + /* not supported */ + DPRINTFN(-1, "Non-isochronous high bandwidth " + "endpoint not supported\n"); + return; } } if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) diff --git a/sys/dev/usb/controller/dwc_otg.h b/sys/dev/usb/controller/dwc_otg.h index 39c9529..f5e9887 100644 --- a/sys/dev/usb/controller/dwc_otg.h +++ b/sys/dev/usb/controller/dwc_otg.h @@ -69,7 +69,7 @@ struct dwc_otg_td { uint8_t tmr_val; uint8_t ep_no; uint8_t ep_type; - uint8_t channel; + uint8_t channel[3]; uint8_t tt_index; /* TT data */ uint8_t tt_start_slot; /* TT data */ uint8_t tt_complete_slot; /* TT data */ @@ -80,8 +80,7 @@ struct dwc_otg_td { #define DWC_CHAN_ST_WAIT_S_ANE 2 #define DWC_CHAN_ST_WAIT_C_ANE 3 #define DWC_CHAN_ST_WAIT_C_PKT 4 -#define DWC_CHAN_ST_TX_PKT_ISOC 5 -#define DWC_CHAN_ST_TX_WAIT_ISOC 6 +#define DWC_CHAN_ST_TX_WAIT_ISOC 5 uint8_t error_any:1; uint8_t error_stall:1; uint8_t alt_next:1; diff --git a/sys/dev/usb/controller/usb_controller.c b/sys/dev/usb/controller/usb_controller.c index 92ea6c5..9f7ce24 100644 --- a/sys/dev/usb/controller/usb_controller.c +++ b/sys/dev/usb/controller/usb_controller.c @@ -231,7 +231,8 @@ usb_detach(device_t dev) /* Get rid of USB callback processes */ usb_proc_free(USB_BUS_GIANT_PROC(bus)); - usb_proc_free(USB_BUS_NON_GIANT_PROC(bus)); + usb_proc_free(USB_BUS_NON_GIANT_ISOC_PROC(bus)); + usb_proc_free(USB_BUS_NON_GIANT_BULK_PROC(bus)); /* Get rid of USB explore process */ @@ -395,7 +396,8 @@ usb_bus_explore(struct usb_proc_msg *pm) */ usb_proc_rewakeup(USB_BUS_CONTROL_XFER_PROC(bus)); usb_proc_rewakeup(USB_BUS_GIANT_PROC(bus)); - usb_proc_rewakeup(USB_BUS_NON_GIANT_PROC(bus)); + usb_proc_rewakeup(USB_BUS_NON_GIANT_ISOC_PROC(bus)); + usb_proc_rewakeup(USB_BUS_NON_GIANT_BULK_PROC(bus)); #endif USB_BUS_UNLOCK(bus); @@ -860,9 +862,13 @@ usb_attach_sub(device_t dev, struct usb_bus *bus) &bus->bus_mtx, device_get_nameunit(dev), USB_PRI_MED)) { device_printf(dev, "WARNING: Creation of USB Giant " "callback process failed.\n"); - } else if (usb_proc_create(USB_BUS_NON_GIANT_PROC(bus), + } else if (usb_proc_create(USB_BUS_NON_GIANT_ISOC_PROC(bus), + &bus->bus_mtx, device_get_nameunit(dev), USB_PRI_HIGHEST)) { + device_printf(dev, "WARNING: Creation of USB non-Giant ISOC " + "callback process failed.\n"); + } else if (usb_proc_create(USB_BUS_NON_GIANT_BULK_PROC(bus), &bus->bus_mtx, device_get_nameunit(dev), USB_PRI_HIGH)) { - device_printf(dev, "WARNING: Creation of USB non-Giant " + device_printf(dev, "WARNING: Creation of USB non-Giant BULK " "callback process failed.\n"); } else if (usb_proc_create(USB_BUS_EXPLORE_PROC(bus), &bus->bus_mtx, device_get_nameunit(dev), USB_PRI_MED)) { diff --git a/sys/dev/usb/usb_bus.h b/sys/dev/usb/usb_bus.h index bdd1681..3ceeb1e 100644 --- a/sys/dev/usb/usb_bus.h +++ b/sys/dev/usb/usb_bus.h @@ -57,19 +57,26 @@ struct usb_bus { struct root_hold_token *bus_roothold; #endif +/* convenience macros */ +#define USB_BUS_TT_PROC(bus) USB_BUS_NON_GIANT_ISOC_PROC(bus) +#define USB_BUS_CS_PROC(bus) USB_BUS_NON_GIANT_ISOC_PROC(bus) + #if USB_HAVE_PER_BUS_PROCESS #define USB_BUS_GIANT_PROC(bus) (&(bus)->giant_callback_proc) -#define USB_BUS_NON_GIANT_PROC(bus) (&(bus)->non_giant_callback_proc) +#define USB_BUS_NON_GIANT_ISOC_PROC(bus) (&(bus)->non_giant_isoc_callback_proc) +#define USB_BUS_NON_GIANT_BULK_PROC(bus) (&(bus)->non_giant_bulk_callback_proc) #define USB_BUS_EXPLORE_PROC(bus) (&(bus)->explore_proc) #define USB_BUS_CONTROL_XFER_PROC(bus) (&(bus)->control_xfer_proc) - /* - * There are two callback processes. One for Giant locked - * callbacks. One for non-Giant locked callbacks. This should - * avoid congestion and reduce response time in most cases. + * There are three callback processes. One for Giant locked + * callbacks. One for non-Giant locked non-periodic callbacks + * and one for non-Giant locked periodic callbacks. This + * should avoid congestion and reduce response time in most + * cases. */ struct usb_process giant_callback_proc; - struct usb_process non_giant_callback_proc; + struct usb_process non_giant_isoc_callback_proc; + struct usb_process non_giant_bulk_callback_proc; /* Explore process */ struct usb_process explore_proc; diff --git a/sys/dev/usb/usb_device.c b/sys/dev/usb/usb_device.c index 5ffc07f..13e2c14 100644 --- a/sys/dev/usb/usb_device.c +++ b/sys/dev/usb/usb_device.c @@ -2181,7 +2181,7 @@ usb_free_device(struct usb_device *udev, uint8_t flag) * anywhere: */ USB_BUS_LOCK(udev->bus); - usb_proc_mwait(USB_BUS_NON_GIANT_PROC(udev->bus), + usb_proc_mwait(USB_BUS_CS_PROC(udev->bus), &udev->cs_msg[0], &udev->cs_msg[1]); USB_BUS_UNLOCK(udev->bus); diff --git a/sys/dev/usb/usb_hub.c b/sys/dev/usb/usb_hub.c index 2f1459c..a54fa2e 100644 --- a/sys/dev/usb/usb_hub.c +++ b/sys/dev/usb/usb_hub.c @@ -346,7 +346,7 @@ uhub_tt_buffer_reset_async_locked(struct usb_device *child, struct usb_endpoint } up->req_reset_tt = req; /* get reset transfer started */ - usb_proc_msignal(USB_BUS_NON_GIANT_PROC(udev->bus), + usb_proc_msignal(USB_BUS_TT_PROC(udev->bus), &hub->tt_msg[0], &hub->tt_msg[1]); } #endif @@ -1579,7 +1579,7 @@ uhub_detach(device_t dev) #if USB_HAVE_TT_SUPPORT /* Make sure our TT messages are not queued anywhere */ USB_BUS_LOCK(bus); - usb_proc_mwait(USB_BUS_NON_GIANT_PROC(bus), + usb_proc_mwait(USB_BUS_TT_PROC(bus), &hub->tt_msg[0], &hub->tt_msg[1]); USB_BUS_UNLOCK(bus); #endif diff --git a/sys/dev/usb/usb_pf.c b/sys/dev/usb/usb_pf.c index 468eafb..82ad8e4 100644 --- a/sys/dev/usb/usb_pf.c +++ b/sys/dev/usb/usb_pf.c @@ -221,7 +221,13 @@ usbpf_clone_destroy(struct if_clone *ifc, struct ifnet *ifp) ubus = ifp->if_softc; unit = ifp->if_dunit; + /* + * Lock USB before clearing the "ifp" pointer, to avoid + * clearing the pointer in the middle of a TAP operation: + */ + USB_BUS_LOCK(ubus); ubus->ifp = NULL; + USB_BUS_UNLOCK(ubus); bpfdetach(ifp); if_detach(ifp); if_free(ifp); diff --git a/sys/dev/usb/usb_process.h b/sys/dev/usb/usb_process.h index c12cdc4..dd20afd 100644 --- a/sys/dev/usb/usb_process.h +++ b/sys/dev/usb/usb_process.h @@ -34,6 +34,7 @@ #endif /* defines */ +#define USB_PRI_HIGHEST PI_SWI(SWI_TTY) #define USB_PRI_HIGH PI_SWI(SWI_NET) #define USB_PRI_MED PI_SWI(SWI_CAMBIO) diff --git a/sys/dev/usb/usb_transfer.c b/sys/dev/usb/usb_transfer.c index 5650790..783a96c 100644 --- a/sys/dev/usb/usb_transfer.c +++ b/sys/dev/usb/usb_transfer.c @@ -872,6 +872,19 @@ done: } } +static uint8_t +usbd_transfer_setup_has_bulk(const struct usb_config *setup_start, + uint16_t n_setup) +{ + while (n_setup--) { + uint8_t type = setup_start[n_setup].type; + if (type == UE_BULK || type == UE_BULK_INTR || + type == UE_TYPE_ANY) + return (1); + } + return (0); +} + /*------------------------------------------------------------------------* * usbd_transfer_setup - setup an array of USB transfers * @@ -1013,9 +1026,12 @@ usbd_transfer_setup(struct usb_device *udev, else if (xfer_mtx == &Giant) info->done_p = USB_BUS_GIANT_PROC(udev->bus); + else if (usbd_transfer_setup_has_bulk(setup_start, n_setup)) + info->done_p = + USB_BUS_NON_GIANT_BULK_PROC(udev->bus); else info->done_p = - USB_BUS_NON_GIANT_PROC(udev->bus); + USB_BUS_NON_GIANT_ISOC_PROC(udev->bus); } /* reset sizes */ @@ -2280,10 +2296,8 @@ usbd_callback_ss_done_defer(struct usb_xfer *xfer) * will have a Lock Order Reversal, LOR, if we try to * proceed ! */ - if (usb_proc_msignal(info->done_p, - &info->done_m[0], &info->done_m[1])) { - /* ignore */ - } + (void) usb_proc_msignal(info->done_p, + &info->done_m[0], &info->done_m[1]); } else { /* clear second recurse flag */ pq->recurse_2 = 0; @@ -2307,23 +2321,26 @@ usbd_callback_wrapper(struct usb_xfer_queue *pq) struct usb_xfer_root *info = xfer->xroot; USB_BUS_LOCK_ASSERT(info->bus, MA_OWNED); - if (!mtx_owned(info->xfer_mtx) && !SCHEDULER_STOPPED()) { + if ((pq->recurse_3 != 0 || mtx_owned(info->xfer_mtx) == 0) && + SCHEDULER_STOPPED() == 0) { /* * Cases that end up here: * * 5) HW interrupt done callback or other source. + * 6) HW completed transfer during callback */ - DPRINTFN(3, "case 5\n"); + DPRINTFN(3, "case 5 and 6\n"); /* * We have to postpone the callback due to the fact we * will have a Lock Order Reversal, LOR, if we try to - * proceed ! + * proceed! + * + * Postponing the callback also ensures that other USB + * transfer queues get a chance. */ - if (usb_proc_msignal(info->done_p, - &info->done_m[0], &info->done_m[1])) { - /* ignore */ - } + (void) usb_proc_msignal(info->done_p, + &info->done_m[0], &info->done_m[1]); return; } /* @@ -2381,8 +2398,11 @@ usbd_callback_wrapper(struct usb_xfer_queue *pq) } #if USB_HAVE_PF - if (xfer->usb_state != USB_ST_SETUP) + if (xfer->usb_state != USB_ST_SETUP) { + USB_BUS_LOCK(info->bus); usbpf_xfertap(xfer, USBPF_XFERTAP_DONE); + USB_BUS_UNLOCK(info->bus); + } #endif /* call processing routine */ (xfer->callback) (xfer, xfer->error); @@ -2694,7 +2714,7 @@ usbd_pipe_start(struct usb_xfer_queue *pq) } else if (udev->ctrl_xfer[1]) { info = udev->ctrl_xfer[1]->xroot; usb_proc_msignal( - USB_BUS_NON_GIANT_PROC(info->bus), + USB_BUS_CS_PROC(info->bus), &udev->cs_msg[0], &udev->cs_msg[1]); } else { /* should not happen */ @@ -3019,9 +3039,11 @@ usb_command_wrapper(struct usb_xfer_queue *pq, struct usb_xfer *xfer) if (!pq->recurse_1) { - do { + /* clear third recurse flag */ + pq->recurse_3 = 0; - /* set both recurse flags */ + do { + /* set two first recurse flags */ pq->recurse_1 = 1; pq->recurse_2 = 1; @@ -3040,6 +3062,12 @@ usb_command_wrapper(struct usb_xfer_queue *pq, struct usb_xfer *xfer) (pq->command) (pq); DPRINTFN(6, "cb %p (leave)\n", pq->curr); + /* + * Set third recurse flag to indicate + * recursion happened: + */ + pq->recurse_3 = 1; + } while (!pq->recurse_2); /* clear first recurse flag */ @@ -3315,7 +3343,8 @@ usbd_transfer_poll(struct usb_xfer **ppxfer, uint16_t max) USB_BUS_CONTROL_XFER_PROC(udev->bus)->up_msleep = 0; USB_BUS_EXPLORE_PROC(udev->bus)->up_msleep = 0; USB_BUS_GIANT_PROC(udev->bus)->up_msleep = 0; - USB_BUS_NON_GIANT_PROC(udev->bus)->up_msleep = 0; + USB_BUS_NON_GIANT_ISOC_PROC(udev->bus)->up_msleep = 0; + USB_BUS_NON_GIANT_BULK_PROC(udev->bus)->up_msleep = 0; /* poll USB hardware */ (udev->bus->methods->xfer_poll) (udev->bus); diff --git a/sys/dev/usb/usbdi.h b/sys/dev/usb/usbdi.h index 09b0ca7..ecd5a81 100644 --- a/sys/dev/usb/usbdi.h +++ b/sys/dev/usb/usbdi.h @@ -128,6 +128,8 @@ struct usb_xfer_queue { void (*command) (struct usb_xfer_queue *pq); uint8_t recurse_1:1; uint8_t recurse_2:1; + uint8_t recurse_3:1; + uint8_t reserved:5; }; /* diff --git a/sys/dev/vt/hw/efifb/efifb.c b/sys/dev/vt/hw/efifb/efifb.c index ec029c8..4184f77 100644 --- a/sys/dev/vt/hw/efifb/efifb.c +++ b/sys/dev/vt/hw/efifb/efifb.c @@ -96,7 +96,6 @@ vt_efifb_probe(struct vt_device *vd) static int vt_efifb_init(struct vt_device *vd) { - int depth, d; struct fb_info *info; struct efi_fb *efifb; caddr_t kmdp; @@ -116,16 +115,13 @@ vt_efifb_init(struct vt_device *vd) info->fb_height = efifb->fb_height; info->fb_width = efifb->fb_width; - depth = fls(efifb->fb_mask_red); - d = fls(efifb->fb_mask_green); - depth = d > depth ? d : depth; - d = fls(efifb->fb_mask_blue); - depth = d > depth ? d : depth; - d = fls(efifb->fb_mask_reserved); - depth = d > depth ? d : depth; - info->fb_depth = depth; + info->fb_depth = fls(efifb->fb_mask_red | efifb->fb_mask_green | + efifb->fb_mask_blue | efifb->fb_mask_reserved); + /* Round to a multiple of the bits in a byte. */ + info->fb_bpp = (info->fb_depth + NBBY - 1) & ~(NBBY - 1); - info->fb_stride = efifb->fb_stride * (depth / 8); + /* Stride in bytes, not pixels */ + info->fb_stride = efifb->fb_stride * (info->fb_bpp / NBBY); vt_generate_cons_palette(info->fb_cmap, COLOR_FORMAT_RGB, efifb->fb_mask_red, ffs(efifb->fb_mask_red) - 1, @@ -137,16 +133,6 @@ vt_efifb_init(struct vt_device *vd) info->fb_vbase = (intptr_t)pmap_mapdev_attr(info->fb_pbase, info->fb_size, VM_MEMATTR_WRITE_COMBINING); - /* Get pixel storage size. */ - info->fb_bpp = info->fb_stride / info->fb_width * 8; - - /* - * Early FB driver work with static window buffer, so reduce to minimal - * size, buffer or screen. - */ - info->fb_width = MIN(info->fb_width, VT_FB_DEFAULT_WIDTH); - info->fb_height = MIN(info->fb_height, VT_FB_DEFAULT_HEIGHT); - vt_fb_init(vd); return (CN_INTERNAL); diff --git a/sys/dev/vt/hw/vga/vt_vga.c b/sys/dev/vt/hw/vga/vt_vga.c index 0b7ebe4..4661f35 100644 --- a/sys/dev/vt/hw/vga/vt_vga.c +++ b/sys/dev/vt/hw/vga/vt_vga.c @@ -883,9 +883,9 @@ vga_bitblt_text_txtmode(struct vt_device *vd, const struct vt_window *vw, /* Convert colors to VGA attributes. */ attr = bg << 4 | fg; - MEM_WRITE1(sc, 0x18000 + (row * 80 + col) * 2 + 0, + MEM_WRITE1(sc, (row * 80 + col) * 2 + 0, ch); - MEM_WRITE1(sc, 0x18000 + (row * 80 + col) * 2 + 1, + MEM_WRITE1(sc, (row * 80 + col) * 2 + 1, attr); } } @@ -1226,8 +1226,6 @@ vga_init(struct vt_device *vd) # error "Architecture not yet supported!" #endif - bus_space_map(sc->vga_fb_tag, VGA_MEM_BASE, VGA_MEM_SIZE, 0, - &sc->vga_fb_handle); bus_space_map(sc->vga_reg_tag, VGA_REG_BASE, VGA_REG_SIZE, 0, &sc->vga_reg_handle); @@ -1236,9 +1234,13 @@ vga_init(struct vt_device *vd) vd->vd_flags |= VDF_TEXTMODE; vd->vd_width = 80; vd->vd_height = 25; + bus_space_map(sc->vga_fb_tag, VGA_TXT_BASE, VGA_TXT_SIZE, 0, + &sc->vga_fb_handle); } else { vd->vd_width = VT_VGA_WIDTH; vd->vd_height = VT_VGA_HEIGHT; + bus_space_map(sc->vga_fb_tag, VGA_MEM_BASE, VGA_MEM_SIZE, 0, + &sc->vga_fb_handle); } if (vga_initialize(vd, textmode) != 0) return (CN_DEAD); diff --git a/sys/dev/vt/hw/vga/vt_vga_reg.h b/sys/dev/vt/hw/vga/vt_vga_reg.h index 5bfb8ce..cf33a37 100644 --- a/sys/dev/vt/hw/vga/vt_vga_reg.h +++ b/sys/dev/vt/hw/vga/vt_vga_reg.h @@ -49,6 +49,8 @@ #define VGA_MEM_BASE 0xA0000 #define VGA_MEM_SIZE 0x10000 +#define VGA_TXT_BASE 0xB8000 +#define VGA_TXT_SIZE 0x08000 #define VGA_REG_BASE 0x3c0 #define VGA_REG_SIZE 0x10+0x0c diff --git a/sys/dev/vt/vt_core.c b/sys/dev/vt/vt_core.c index 99da892..702df42 100644 --- a/sys/dev/vt/vt_core.c +++ b/sys/dev/vt/vt_core.c @@ -264,8 +264,9 @@ vt_update_static(void *dummy) if (!vty_enabled(VTY_VT)) return; if (main_vd->vd_driver != NULL) - printf("VT: running with driver \"%s\".\n", - main_vd->vd_driver->vd_name); + printf("VT(%s): %s %ux%u\n", main_vd->vd_driver->vd_name, + (main_vd->vd_flags & VDF_TEXTMODE) ? "text" : "resolution", + main_vd->vd_width, main_vd->vd_height); else printf("VT: init without driver.\n"); diff --git a/sys/dev/xen/netfront/netfront.c b/sys/dev/xen/netfront/netfront.c index 2f972b8..302c017 100644 --- a/sys/dev/xen/netfront/netfront.c +++ b/sys/dev/xen/netfront/netfront.c @@ -280,8 +280,6 @@ struct netfront_info { struct callout xn_stat_ch; u_long rx_pfn_array[NET_RX_RING_SIZE]; - multicall_entry_t rx_mcl[NET_RX_RING_SIZE+1]; - mmu_update_t rx_mmu[NET_RX_RING_SIZE]; struct ifmedia sc_media; bool xn_resume; @@ -882,13 +880,6 @@ refill: gnttab_grant_foreign_transfer_ref(ref, otherend_id, pfn); sc->rx_pfn_array[nr_flips] = pfn; - if (!xen_feature(XENFEAT_auto_translated_physmap)) { - /* Remove this page before passing - * back to Xen. - */ - MULTI_update_va_mapping(&sc->rx_mcl[i], - vaddr, 0, 0); - } nr_flips++; } else { gnttab_grant_foreign_access_ref(ref, @@ -918,25 +909,6 @@ refill: reservation.extent_order = 0; reservation.address_bits = 0; reservation.domid = DOMID_SELF; - - if (!xen_feature(XENFEAT_auto_translated_physmap)) { - /* After all PTEs have been zapped, flush the TLB. */ - sc->rx_mcl[i-1].args[MULTI_UVMFLAGS_INDEX] = - UVMF_TLB_FLUSH|UVMF_ALL; - - /* Give away a batch of pages. */ - sc->rx_mcl[i].op = __HYPERVISOR_memory_op; - sc->rx_mcl[i].args[0] = XENMEM_decrease_reservation; - sc->rx_mcl[i].args[1] = (u_long)&reservation; - /* Zap PTEs and give away pages in one big multicall. */ - (void)HYPERVISOR_multicall(sc->rx_mcl, i+1); - - if (__predict_false(sc->rx_mcl[i].result != i || - HYPERVISOR_memory_op(XENMEM_decrease_reservation, - &reservation) != i)) - panic("%s: unable to reduce memory " - "reservation\n", __func__); - } } else { wmb(); } @@ -961,7 +933,6 @@ xn_rxeof(struct netfront_info *np) struct netif_rx_response *rx = &rinfo.rx; struct netif_extra_info *extras = rinfo.extras; RING_IDX i, rp; - multicall_entry_t *mcl; struct mbuf *m; struct mbufq rxq, errq; int err, pages_flipped = 0, work_to_do; @@ -1022,19 +993,6 @@ xn_rxeof(struct netfront_info *np) #ifdef notyet balloon_update_driver_allowance(-pages_flipped); #endif - /* Do all the remapping work, and M->P updates, in one big - * hypercall. - */ - if (!!xen_feature(XENFEAT_auto_translated_physmap)) { - mcl = np->rx_mcl + pages_flipped; - mcl->op = __HYPERVISOR_mmu_update; - mcl->args[0] = (u_long)np->rx_mmu; - mcl->args[1] = pages_flipped; - mcl->args[2] = 0; - mcl->args[3] = DOMID_SELF; - (void)HYPERVISOR_multicall(np->rx_mcl, - pages_flipped + 1); - } } mbufq_drain(&errq); @@ -1273,8 +1231,6 @@ xennet_get_responses(struct netfront_info *np, int *pages_flipped_p) { int pages_flipped = *pages_flipped_p; - struct mmu_update *mmu; - struct multicall_entry *mcl; struct netif_rx_response *rx = &rinfo->rx; struct netif_extra_info *extras = rinfo->extras; struct mbuf *m, *m0, *m_prev; @@ -1346,22 +1302,6 @@ xennet_get_responses(struct netfront_info *np, goto next; } - if (!xen_feature( XENFEAT_auto_translated_physmap)) { - /* Remap the page. */ - void *vaddr = mtod(m, void *); - uint32_t pfn; - - mcl = np->rx_mcl + pages_flipped; - mmu = np->rx_mmu + pages_flipped; - - MULTI_update_va_mapping(mcl, (u_long)vaddr, - (((vm_paddr_t)mfn) << PAGE_SHIFT) | PG_RW | - PG_V | PG_M | PG_A, 0); - pfn = (uintptr_t)m->m_ext.ext_arg1; - mmu->ptr = ((vm_paddr_t)mfn << PAGE_SHIFT) | - MMU_MACHPHYS_UPDATE; - mmu->val = pfn; - } pages_flipped++; } else { ret = gnttab_end_foreign_access_ref(ref); diff --git a/sys/fs/nfsserver/nfs_nfsdstate.c b/sys/fs/nfsserver/nfs_nfsdstate.c index d1ade4a..c0e05b9 100644 --- a/sys/fs/nfsserver/nfs_nfsdstate.c +++ b/sys/fs/nfsserver/nfs_nfsdstate.c @@ -401,9 +401,12 @@ nfsrv_setclient(struct nfsrv_descript *nd, struct nfsclient **new_clpp, } /* For NFSv4.1, mark that we found a confirmed clientid. */ - if ((nd->nd_flag & ND_NFSV41) != 0) + if ((nd->nd_flag & ND_NFSV41) != 0) { + clientidp->lval[0] = clp->lc_clientid.lval[0]; + clientidp->lval[1] = clp->lc_clientid.lval[1]; + confirmp->lval[0] = 0; /* Ignored by client */ confirmp->lval[1] = 1; - else { + } else { /* * id and verifier match, so update the net address info * and get rid of any existing callback authentication diff --git a/sys/kern/genassym.sh b/sys/kern/genassym.sh index 1cbc32b..521c7a2 100644 --- a/sys/kern/genassym.sh +++ b/sys/kern/genassym.sh @@ -10,7 +10,7 @@ usage() work() { - ${NM:='nm'} "$1" | ${AWK:='awk'} ' + ${NM:='nm'} ${NMFLAGS} "$1" | ${AWK:='awk'} ' / C .*sign$/ { sign = substr($1, length($1) - 3, 4) sub("^0*", "", sign) diff --git a/sys/kern/kern_exit.c b/sys/kern/kern_exit.c index 3310d1d..d84c26f 100644 --- a/sys/kern/kern_exit.c +++ b/sys/kern/kern_exit.c @@ -981,6 +981,10 @@ proc_to_reap(struct thread *td, struct proc *p, idtype_t idtype, id_t id, switch (idtype) { case P_ALL: + if (p->p_procdesc != NULL) { + PROC_UNLOCK(p); + return (0); + } break; case P_PID: if (p->p_pid != (pid_t)id) { diff --git a/sys/kern/kern_tc.c b/sys/kern/kern_tc.c index d09f0b6..432e38a 100644 --- a/sys/kern/kern_tc.c +++ b/sys/kern/kern_tc.c @@ -133,6 +133,8 @@ SYSCTL_PROC(_kern_timecounter, OID_AUTO, alloweddeviation, sysctl_kern_timecounter_adjprecision, "I", "Allowed time interval deviation in percents"); +static int tc_chosen; /* Non-zero if a specific tc was chosen via sysctl. */ + static void tc_windup(void); static void cpu_tick_calibrate(int); @@ -1197,10 +1199,13 @@ tc_init(struct timecounter *tc) "quality", CTLFLAG_RD, &(tc->tc_quality), 0, "goodness of time counter"); /* - * Never automatically use a timecounter with negative quality. + * Do not automatically switch if the current tc was specifically + * chosen. Never automatically use a timecounter with negative quality. * Even though we run on the dummy counter, switching here may be - * worse since this timecounter may not be monotonous. + * worse since this timecounter may not be monotonic. */ + if (tc_chosen) + return; if (tc->tc_quality < 0) return; if (tc->tc_quality < timecounter->tc_quality) @@ -1433,9 +1438,12 @@ sysctl_kern_timecounter_hardware(SYSCTL_HANDLER_ARGS) strlcpy(newname, tc->tc_name, sizeof(newname)); error = sysctl_handle_string(oidp, &newname[0], sizeof(newname), req); - if (error != 0 || req->newptr == NULL || - strcmp(newname, tc->tc_name) == 0) + if (error != 0 || req->newptr == NULL) return (error); + /* Record that the tc in use now was specifically chosen. */ + tc_chosen = 1; + if (strcmp(newname, tc->tc_name) == 0) + return (0); for (newtc = timecounters; newtc != NULL; newtc = newtc->tc_next) { if (strcmp(newname, newtc->tc_name) != 0) continue; @@ -1464,7 +1472,7 @@ SYSCTL_PROC(_kern_timecounter, OID_AUTO, hardware, CTLTYPE_STRING | CTLFLAG_RW, "Timecounter hardware selected"); -/* Report or change the active timecounter hardware. */ +/* Report the available timecounter hardware. */ static int sysctl_kern_timecounter_choice(SYSCTL_HANDLER_ARGS) { diff --git a/sys/modules/Makefile b/sys/modules/Makefile index bd52356..21009a9 100644 --- a/sys/modules/Makefile +++ b/sys/modules/Makefile @@ -296,6 +296,9 @@ SUBDIR= \ ${_qlxgbe} \ ral \ ${_ralfw} \ + ${_random_fortuna} \ + ${_random_yarrow} \ + ${_random_other} \ rc4 \ ${_rdma} \ ${_rdrand_rng} \ @@ -398,6 +401,9 @@ _autofs= autofs .if exists(${.CURDIR}/../opencrypto) _crypto= crypto _cryptodev= cryptodev +_random_fortuna=random_fortuna +_random_yarrow= random_yarrow +_random_other= random_other .endif .endif diff --git a/sys/modules/am335x_dmtpps/Makefile b/sys/modules/am335x_dmtpps/Makefile new file mode 100644 index 0000000..4d9deac --- /dev/null +++ b/sys/modules/am335x_dmtpps/Makefile @@ -0,0 +1,8 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../arm/ti/am335x + +KMOD= am335x_dmtpps +SRCS= am335x_dmtpps.c + +.include <bsd.kmod.mk> diff --git a/sys/modules/ctl/Makefile b/sys/modules/ctl/Makefile index e97ec38..c74f000 100644 --- a/sys/modules/ctl/Makefile +++ b/sys/modules/ctl/Makefile @@ -11,7 +11,7 @@ SRCS+= ctl_backend_ramdisk.c SRCS+= ctl_cmd_table.c SRCS+= ctl_frontend.c SRCS+= ctl_frontend_cam_sim.c -SRCS+= ctl_frontend_internal.c +SRCS+= ctl_frontend_ioctl.c SRCS+= ctl_frontend_iscsi.c SRCS+= ctl_scsi_all.c SRCS+= ctl_tpc.c diff --git a/sys/modules/gpio/gpiobus/Makefile b/sys/modules/gpio/gpiobus/Makefile index e868cba..2a3f86d 100644 --- a/sys/modules/gpio/gpiobus/Makefile +++ b/sys/modules/gpio/gpiobus/Makefile @@ -32,8 +32,9 @@ .PATH: ${.CURDIR}/../../../dev/gpio/ KMOD= gpiobus -SRCS= gpiobus.c -SRCS+= device_if.h bus_if.h gpio_if.h gpiobus_if.h opt_platform.h +SRCS= gpiobus.c gpioc.c +SRCS+= gpio_if.c gpio_if.h gpiobus_if.c gpiobus_if.h +SRCS+= device_if.h bus_if.h opt_platform.h CFLAGS+= -I. -I${.CURDIR}/../../../dev/gpio/ diff --git a/sys/modules/random_fortuna/Makefile b/sys/modules/random_fortuna/Makefile new file mode 100644 index 0000000..d28ae4d --- /dev/null +++ b/sys/modules/random_fortuna/Makefile @@ -0,0 +1,11 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/random + +KMOD = random_fortuna +SRCS = randomdev.c hash.c fortuna.c +SRCS += opt_param.h bus_if.h device_if.h +SRCS += opt_ddb.h +CFLAGS += -DRANDOM_LOADABLE + +.include <bsd.kmod.mk> diff --git a/sys/modules/random_other/Makefile b/sys/modules/random_other/Makefile new file mode 100644 index 0000000..6ce586b --- /dev/null +++ b/sys/modules/random_other/Makefile @@ -0,0 +1,11 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/random + +KMOD = random_OTHER +SRCS = randomdev.c hash.c other_algorithm.c +SRCS += opt_param.h bus_if.h device_if.h +SRCS += opt_ddb.h +CFLAGS += -DRANDOM_LOADABLE + +.include <bsd.kmod.mk> diff --git a/sys/modules/random_yarrow/Makefile b/sys/modules/random_yarrow/Makefile new file mode 100644 index 0000000..1750af4 --- /dev/null +++ b/sys/modules/random_yarrow/Makefile @@ -0,0 +1,11 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/random + +KMOD = random_yarrow +SRCS = randomdev.c hash.c yarrow.c +SRCS += opt_param.h bus_if.h device_if.h +SRCS += opt_ddb.h +CFLAGS += -DRANDOM_LOADABLE + +.include <bsd.kmod.mk> diff --git a/sys/net/ieee8023ad_lacp.c b/sys/net/ieee8023ad_lacp.c index 64aafb1..1af4ffc 100644 --- a/sys/net/ieee8023ad_lacp.c +++ b/sys/net/ieee8023ad_lacp.c @@ -522,7 +522,7 @@ lacp_port_create(struct lagg_port *lgp) int error; boolean_t active = TRUE; /* XXX should be configurable */ - boolean_t fast = FALSE; /* XXX should be configurable */ + boolean_t fast = FALSE; /* Configurable via ioctl */ link_init_sdl(ifp, (struct sockaddr *)&sdl, IFT_ETHER); sdl.sdl_alen = ETHER_ADDR_LEN; diff --git a/sys/net/ieee8023ad_lacp.h b/sys/net/ieee8023ad_lacp.h index e814f83..8f0f51a 100644 --- a/sys/net/ieee8023ad_lacp.h +++ b/sys/net/ieee8023ad_lacp.h @@ -251,6 +251,7 @@ struct lacp_softc { u_int32_t lsc_tx_test; } lsc_debug; u_int32_t lsc_strict_mode; + boolean_t lsc_fast_timeout; /* if set, fast timeout */ }; #define LACP_TYPE_ACTORINFO 1 diff --git a/sys/net/if_lagg.c b/sys/net/if_lagg.c index dcd005a..b623493 100644 --- a/sys/net/if_lagg.c +++ b/sys/net/if_lagg.c @@ -1257,6 +1257,8 @@ lagg_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) ro->ro_opts |= LAGG_OPT_LACP_RXTEST; if (lsc->lsc_strict_mode != 0) ro->ro_opts |= LAGG_OPT_LACP_STRICT; + if (lsc->lsc_fast_timeout != 0) + ro->ro_opts |= LAGG_OPT_LACP_TIMEOUT; ro->ro_active = sc->sc_active; } else { @@ -1292,6 +1294,8 @@ lagg_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) case -LAGG_OPT_LACP_RXTEST: case LAGG_OPT_LACP_STRICT: case -LAGG_OPT_LACP_STRICT: + case LAGG_OPT_LACP_TIMEOUT: + case -LAGG_OPT_LACP_TIMEOUT: valid = lacp = 1; break; default: @@ -1320,6 +1324,7 @@ lagg_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) sc->sc_opts &= ~ro->ro_opts; } else { struct lacp_softc *lsc; + struct lacp_port *lp; lsc = (struct lacp_softc *)sc->sc_psc; @@ -1342,6 +1347,20 @@ lagg_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) case -LAGG_OPT_LACP_STRICT: lsc->lsc_strict_mode = 0; break; + case LAGG_OPT_LACP_TIMEOUT: + LACP_LOCK(lsc); + LIST_FOREACH(lp, &lsc->lsc_ports, lp_next) + lp->lp_state |= LACP_STATE_TIMEOUT; + LACP_UNLOCK(lsc); + lsc->lsc_fast_timeout = 1; + break; + case -LAGG_OPT_LACP_TIMEOUT: + LACP_LOCK(lsc); + LIST_FOREACH(lp, &lsc->lsc_ports, lp_next) + lp->lp_state &= ~LACP_STATE_TIMEOUT; + LACP_UNLOCK(lsc); + lsc->lsc_fast_timeout = 0; + break; } } LAGG_WUNLOCK(sc); diff --git a/sys/net/if_lagg.h b/sys/net/if_lagg.h index a45fa16..bb5ea23 100644 --- a/sys/net/if_lagg.h +++ b/sys/net/if_lagg.h @@ -150,6 +150,7 @@ struct lagg_reqopts { #define LAGG_OPT_LACP_STRICT 0x10 /* LACP strict mode */ #define LAGG_OPT_LACP_TXTEST 0x20 /* LACP debug: txtest */ #define LAGG_OPT_LACP_RXTEST 0x40 /* LACP debug: rxtest */ +#define LAGG_OPT_LACP_TIMEOUT 0x80 /* LACP timeout */ u_int ro_count; /* number of ports */ u_int ro_active; /* active port count */ u_int ro_flapping; /* number of flapping */ diff --git a/sys/netinet/if_ether.c b/sys/netinet/if_ether.c index f90925a..263c197 100644 --- a/sys/netinet/if_ether.c +++ b/sys/netinet/if_ether.c @@ -130,6 +130,13 @@ static void arptimer(void *); static void in_arpinput(struct mbuf *); #endif +static void arp_check_update_lle(struct arphdr *ah, struct in_addr isaddr, + struct ifnet *ifp, int bridged, struct llentry *la); +static void arp_update_lle(struct arphdr *ah, struct ifnet *ifp, + struct llentry *la); +static void arp_mark_lle_reachable(struct llentry *la); + + static const struct netisr_handler arp_nh = { .nh_name = "arp", .nh_handler = arpintr, @@ -302,57 +309,37 @@ arprequest(struct ifnet *ifp, const struct in_addr *sip, } /* - * Resolve an IP address into an ethernet address. - * On input: - * ifp is the interface we use - * is_gw != if @dst represents gateway to some destination - * m is the mbuf. May be NULL if we don't have a packet. - * dst is the next hop, - * desten is where we want the address. - * flags returns lle entry flags. + * Resolve an IP address into an ethernet address - heavy version. + * Used internally by arpresolve(). + * We have already checked than we can't use existing lle without + * modification so we have to acquire LLE_EXCLUSIVE lle lock. * * On success, desten and flags are filled in and the function returns 0; * If the packet must be held pending resolution, we return EWOULDBLOCK * On other errors, we return the corresponding error code. * Note that m_freem() handles NULL. */ -int -arpresolve(struct ifnet *ifp, int is_gw, struct mbuf *m, +static int +arpresolve_full(struct ifnet *ifp, int is_gw, int create, struct mbuf *m, const struct sockaddr *dst, u_char *desten, uint32_t *pflags) { - struct llentry *la = 0; - u_int flags = 0; + struct llentry *la = NULL; struct mbuf *curr = NULL; struct mbuf *next = NULL; - int create, error, renew; + int error, renew; if (pflags != NULL) *pflags = 0; - create = 0; - if (m != NULL) { - if (m->m_flags & M_BCAST) { - /* broadcast */ - (void)memcpy(desten, - ifp->if_broadcastaddr, ifp->if_addrlen); - return (0); - } - if (m->m_flags & M_MCAST) { - /* multicast */ - ETHER_MAP_IP_MULTICAST(&SIN(dst)->sin_addr, desten); - return (0); - } + if (create == 0) { + IF_AFDATA_RLOCK(ifp); + la = lla_lookup(LLTABLE(ifp), LLE_EXCLUSIVE, dst); + IF_AFDATA_RUNLOCK(ifp); } -retry: - IF_AFDATA_RLOCK(ifp); - la = lla_lookup(LLTABLE(ifp), flags, dst); - IF_AFDATA_RUNLOCK(ifp); - if ((la == NULL) && ((flags & LLE_EXCLUSIVE) == 0) - && ((ifp->if_flags & (IFF_NOARP | IFF_STATICARP)) == 0)) { + if (la == NULL && (ifp->if_flags & (IFF_NOARP | IFF_STATICARP)) == 0) { create = 1; - flags |= LLE_EXCLUSIVE; IF_AFDATA_WLOCK(ifp); - la = lla_create(LLTABLE(ifp), flags, dst); + la = lla_create(LLTABLE(ifp), 0, dst); IF_AFDATA_WUNLOCK(ifp); } if (la == NULL) { @@ -382,10 +369,7 @@ retry: if (pflags != NULL) *pflags = la->la_flags; - if (flags & LLE_EXCLUSIVE) - LLE_WUNLOCK(la); - else - LLE_RUNLOCK(la); + LLE_WUNLOCK(la); if (renew == 1) arprequest(ifp, NULL, &SIN(dst)->sin_addr, NULL); @@ -393,20 +377,7 @@ retry: return (0); } - if (la->la_flags & LLE_STATIC) { /* should not happen! */ - log(LOG_DEBUG, "arpresolve: ouch, empty static llinfo for %s\n", - inet_ntoa(SIN(dst)->sin_addr)); - m_freem(m); - error = EINVAL; - goto done; - } - renew = (la->la_asked == 0 || la->la_expire != time_uptime); - if ((renew || m != NULL) && (flags & LLE_EXCLUSIVE) == 0) { - flags |= LLE_EXCLUSIVE; - LLE_RUNLOCK(la); - goto retry; - } /* * There is an arptab entry, but no ethernet address * response yet. Add the mbuf to the list, dropping @@ -431,11 +402,6 @@ retry: } else la->la_hold = m; la->la_numheld++; - if (renew == 0 && (flags & LLE_EXCLUSIVE)) { - flags &= ~LLE_EXCLUSIVE; - LLE_DOWNGRADE(la); - } - } /* * Return EWOULDBLOCK if we have tried less than arp_maxtries. It @@ -462,15 +428,88 @@ retry: arprequest(ifp, NULL, &SIN(dst)->sin_addr, NULL); return (error); } -done: - if (flags & LLE_EXCLUSIVE) - LLE_WUNLOCK(la); - else - LLE_RUNLOCK(la); + + LLE_WUNLOCK(la); return (error); } /* + * Resolve an IP address into an ethernet address. + * On input: + * ifp is the interface we use + * is_gw != 0 if @dst represents gateway to some destination + * m is the mbuf. May be NULL if we don't have a packet. + * dst is the next hop, + * desten is the storage to put LL address. + * flags returns lle entry flags. + * + * On success, desten and flags are filled in and the function returns 0; + * If the packet must be held pending resolution, we return EWOULDBLOCK + * On other errors, we return the corresponding error code. + * Note that m_freem() handles NULL. + */ +int +arpresolve(struct ifnet *ifp, int is_gw, struct mbuf *m, + const struct sockaddr *dst, u_char *desten, uint32_t *pflags) +{ + struct llentry *la = 0; + int renew; + + if (pflags != NULL) + *pflags = 0; + + if (m != NULL) { + if (m->m_flags & M_BCAST) { + /* broadcast */ + (void)memcpy(desten, + ifp->if_broadcastaddr, ifp->if_addrlen); + return (0); + } + if (m->m_flags & M_MCAST) { + /* multicast */ + ETHER_MAP_IP_MULTICAST(&SIN(dst)->sin_addr, desten); + return (0); + } + } + + IF_AFDATA_RLOCK(ifp); + la = lla_lookup(LLTABLE(ifp), 0, dst); + IF_AFDATA_RUNLOCK(ifp); + + if (la == NULL) + return (arpresolve_full(ifp, is_gw, 1, m, dst, desten, pflags)); + + if ((la->la_flags & LLE_VALID) && + ((la->la_flags & LLE_STATIC) || la->la_expire > time_uptime)) { + bcopy(&la->ll_addr, desten, ifp->if_addrlen); + renew = 0; + /* + * If entry has an expiry time and it is approaching, + * see if we need to send an ARP request within this + * arpt_down interval. + */ + if (!(la->la_flags & LLE_STATIC) && + time_uptime + la->la_preempt > la->la_expire) { + renew = 1; + la->la_preempt--; + } + + if (pflags != NULL) + *pflags = la->la_flags; + + LLE_RUNLOCK(la); + + if (renew == 1) + arprequest(ifp, NULL, &SIN(dst)->sin_addr, NULL); + + return (0); + } + LLE_RUNLOCK(la); + + return (arpresolve_full(ifp, is_gw, 0, m, dst, desten, pflags)); +} + +/* * Common length and type checks are done here, * then the protocol-specific routine is called. */ @@ -576,10 +615,10 @@ in_arpinput(struct mbuf *m) struct sockaddr sa; struct in_addr isaddr, itaddr, myaddr; u_int8_t *enaddr = NULL; - int op, flags; + int op; int req_len; int bridged = 0, is_bridge = 0; - int carped, create; + int carped; struct sockaddr_in sin; sin.sin_len = sizeof(struct sockaddr_in); sin.sin_family = AF_INET; @@ -708,6 +747,16 @@ match: "%s!\n", inet_ntoa(isaddr)); goto drop; } + + if (ifp->if_addrlen != ah->ar_hln) { + LLE_WUNLOCK(la); + ARP_LOG(LOG_WARNING, "from %*D: addr len: new %d, " + "i/f %d (ignored)\n", ifp->if_addrlen, + (u_char *) ar_sha(ah), ":", ah->ar_hln, + ifp->if_addrlen); + goto drop; + } + /* * Warn if another host is using the same IP address, but only if the * IP address isn't 0.0.0.0, which is used for DHCP only, in which @@ -730,100 +779,22 @@ match: sin.sin_len = sizeof(struct sockaddr_in); sin.sin_family = AF_INET; sin.sin_addr = isaddr; - create = (itaddr.s_addr == myaddr.s_addr) ? 1 : 0; - flags = LLE_EXCLUSIVE; - IF_AFDATA_LOCK(ifp); - if (create != 0) - la = lla_create(LLTABLE(ifp), 0, (struct sockaddr *)&sin); - else - la = lla_lookup(LLTABLE(ifp), flags, (struct sockaddr *)&sin); - IF_AFDATA_UNLOCK(ifp); - if (la != NULL) { - /* the following is not an error when doing bridging */ - if (!bridged && la->lle_tbl->llt_ifp != ifp) { - if (log_arp_wrong_iface) - ARP_LOG(LOG_WARNING, "%s is on %s " - "but got reply from %*D on %s\n", - inet_ntoa(isaddr), - la->lle_tbl->llt_ifp->if_xname, - ifp->if_addrlen, (u_char *)ar_sha(ah), ":", - ifp->if_xname); - LLE_WUNLOCK(la); - goto reply; - } - if ((la->la_flags & LLE_VALID) && - bcmp(ar_sha(ah), &la->ll_addr, ifp->if_addrlen)) { - if (la->la_flags & LLE_STATIC) { - LLE_WUNLOCK(la); - if (log_arp_permanent_modify) - ARP_LOG(LOG_ERR, - "%*D attempts to modify " - "permanent entry for %s on %s\n", - ifp->if_addrlen, - (u_char *)ar_sha(ah), ":", - inet_ntoa(isaddr), ifp->if_xname); - goto reply; - } - if (log_arp_movements) { - ARP_LOG(LOG_INFO, "%s moved from %*D " - "to %*D on %s\n", - inet_ntoa(isaddr), - ifp->if_addrlen, - (u_char *)&la->ll_addr, ":", - ifp->if_addrlen, (u_char *)ar_sha(ah), ":", - ifp->if_xname); - } - } - - if (ifp->if_addrlen != ah->ar_hln) { - LLE_WUNLOCK(la); - ARP_LOG(LOG_WARNING, "from %*D: addr len: new %d, " - "i/f %d (ignored)\n", ifp->if_addrlen, - (u_char *) ar_sha(ah), ":", ah->ar_hln, - ifp->if_addrlen); - goto drop; - } - (void)memcpy(&la->ll_addr, ar_sha(ah), ifp->if_addrlen); - la->la_flags |= LLE_VALID; - - EVENTHANDLER_INVOKE(lle_event, la, LLENTRY_RESOLVED); - - if (!(la->la_flags & LLE_STATIC)) { - int canceled; - - LLE_ADDREF(la); - la->la_expire = time_uptime + V_arpt_keep; - canceled = callout_reset(&la->lle_timer, - hz * V_arpt_keep, arptimer, la); - if (canceled) - LLE_REMREF(la); - } - la->la_asked = 0; - la->la_preempt = V_arp_maxtries; + IF_AFDATA_RLOCK(ifp); + la = lla_lookup(LLTABLE(ifp), LLE_EXCLUSIVE, (struct sockaddr *)&sin); + IF_AFDATA_RUNLOCK(ifp); + if (la != NULL) + arp_check_update_lle(ah, isaddr, ifp, bridged, la); + else if (itaddr.s_addr == myaddr.s_addr) { /* - * The packets are all freed within the call to the output - * routine. - * - * NB: The lock MUST be released before the call to the - * output routine. + * Reply to our address, but no lle exists yet. + * do we really have to create an entry? */ - if (la->la_hold != NULL) { - struct mbuf *m_hold, *m_hold_next; - - m_hold = la->la_hold; - la->la_hold = NULL; - la->la_numheld = 0; - lltable_fill_sa_entry(la, (struct sockaddr *)&sa); - LLE_WUNLOCK(la); - for (; m_hold != NULL; m_hold = m_hold_next) { - m_hold_next = m_hold->m_nextpkt; - m_hold->m_nextpkt = NULL; - /* Avoid confusing lower layers. */ - m_clrprotoflags(m_hold); - (*ifp->if_output)(ifp, m_hold, &sa, NULL); - } - } else - LLE_WUNLOCK(la); + IF_AFDATA_WLOCK(ifp); + la = lla_create(LLTABLE(ifp), 0, (struct sockaddr *)&sin); + arp_update_lle(ah, ifp, la); + IF_AFDATA_WUNLOCK(ifp); + arp_mark_lle_reachable(la); + LLE_WUNLOCK(la); } reply: if (op != ARPOP_REQUEST) @@ -934,6 +905,140 @@ drop: } #endif +/* + * Checks received arp data against existing @la. + * Updates lle state/performs notification if necessary. + */ +static void +arp_check_update_lle(struct arphdr *ah, struct in_addr isaddr, struct ifnet *ifp, + int bridged, struct llentry *la) +{ + struct sockaddr sa; + struct mbuf *m_hold, *m_hold_next; + + LLE_WLOCK_ASSERT(la); + + /* the following is not an error when doing bridging */ + if (!bridged && la->lle_tbl->llt_ifp != ifp) { + if (log_arp_wrong_iface) + ARP_LOG(LOG_WARNING, "%s is on %s " + "but got reply from %*D on %s\n", + inet_ntoa(isaddr), + la->lle_tbl->llt_ifp->if_xname, + ifp->if_addrlen, (u_char *)ar_sha(ah), ":", + ifp->if_xname); + LLE_WUNLOCK(la); + return; + } + if ((la->la_flags & LLE_VALID) && + bcmp(ar_sha(ah), &la->ll_addr, ifp->if_addrlen)) { + if (la->la_flags & LLE_STATIC) { + LLE_WUNLOCK(la); + if (log_arp_permanent_modify) + ARP_LOG(LOG_ERR, + "%*D attempts to modify " + "permanent entry for %s on %s\n", + ifp->if_addrlen, + (u_char *)ar_sha(ah), ":", + inet_ntoa(isaddr), ifp->if_xname); + return; + } + if (log_arp_movements) { + ARP_LOG(LOG_INFO, "%s moved from %*D " + "to %*D on %s\n", + inet_ntoa(isaddr), + ifp->if_addrlen, + (u_char *)&la->ll_addr, ":", + ifp->if_addrlen, (u_char *)ar_sha(ah), ":", + ifp->if_xname); + } + } + + /* Check if something has changed */ + if (memcmp(&la->ll_addr, ar_sha(ah), ifp->if_addrlen) != 0 || + (la->la_flags & LLE_VALID) == 0) { + /* Perform real LLE update */ + /* use afdata WLOCK to update fields */ + LLE_ADDREF(la); + LLE_WUNLOCK(la); + IF_AFDATA_WLOCK(ifp); + LLE_WLOCK(la); + + /* + * Since we droppped LLE lock, other thread might have deleted + * this lle. Check and return + */ + if ((la->la_flags & LLE_DELETED) != 0) { + IF_AFDATA_WUNLOCK(ifp); + LLE_FREE_LOCKED(la); + return; + } + + /* Update data */ + arp_update_lle(ah, ifp, la); + + IF_AFDATA_WUNLOCK(ifp); + LLE_REMREF(la); + } + + arp_mark_lle_reachable(la); + + /* + * The packets are all freed within the call to the output + * routine. + * + * NB: The lock MUST be released before the call to the + * output routine. + */ + if (la->la_hold != NULL) { + m_hold = la->la_hold; + la->la_hold = NULL; + la->la_numheld = 0; + lltable_fill_sa_entry(la, &sa); + LLE_WUNLOCK(la); + for (; m_hold != NULL; m_hold = m_hold_next) { + m_hold_next = m_hold->m_nextpkt; + m_hold->m_nextpkt = NULL; + /* Avoid confusing lower layers. */ + m_clrprotoflags(m_hold); + (*ifp->if_output)(ifp, m_hold, &sa, NULL); + } + } else + LLE_WUNLOCK(la); +} + +/* + * Updates @la fields used by fast path code. + */ +static void +arp_update_lle(struct arphdr *ah, struct ifnet *ifp, struct llentry *la) +{ + + memcpy(&la->ll_addr, ar_sha(ah), ifp->if_addrlen); + la->la_flags |= LLE_VALID; +} + +static void +arp_mark_lle_reachable(struct llentry *la) +{ + int canceled; + + LLE_WLOCK_ASSERT(la); + + EVENTHANDLER_INVOKE(lle_event, la, LLENTRY_RESOLVED); + + if (!(la->la_flags & LLE_STATIC)) { + LLE_ADDREF(la); + la->la_expire = time_uptime + V_arpt_keep; + canceled = callout_reset(&la->lle_timer, + hz * V_arpt_keep, arptimer, la); + if (canceled) + LLE_REMREF(la); + } + la->la_asked = 0; + la->la_preempt = V_arp_maxtries; +} + void arp_ifinit(struct ifnet *ifp, struct ifaddr *ifa) { diff --git a/sys/netinet/sctp_timer.c b/sys/netinet/sctp_timer.c index 6c8589e..3e72585 100644 --- a/sys/netinet/sctp_timer.c +++ b/sys/netinet/sctp_timer.c @@ -1492,6 +1492,8 @@ sctp_pathmtu_timer(struct sctp_inpcb *inp, #endif if (mtu > next_mtu) { net->mtu = next_mtu; + } else { + net->mtu = mtu; } } } diff --git a/sys/ofed/drivers/infiniband/core/cma.c b/sys/ofed/drivers/infiniband/core/cma.c index f1d26cc..7ee525a 100644 --- a/sys/ofed/drivers/infiniband/core/cma.c +++ b/sys/ofed/drivers/infiniband/core/cma.c @@ -72,6 +72,11 @@ static int def_prec2sl = 3; module_param_named(def_prec2sl, def_prec2sl, int, 0644); MODULE_PARM_DESC(def_prec2sl, "Default value for SL priority with RoCE. Valid values 0 - 7"); +static int unify_tcp_port_space = 1; +module_param(unify_tcp_port_space, int, 0644); +MODULE_PARM_DESC(unify_tcp_port_space, "Unify the host TCP and RDMA port " + "space allocation (default=1)"); + static int debug_level = 0; #define cma_pr(level, priv, format, arg...) \ printk(level "CMA: %p: %s: " format, ((struct rdma_id_priv *) priv) , __func__, ## arg) @@ -957,6 +962,8 @@ static void cma_release_port(struct rdma_id_private *id_priv) kfree(bind_list); } mutex_unlock(&lock); + if (id_priv->sock) + sock_release(id_priv->sock); } static void cma_leave_mc_groups(struct rdma_id_private *id_priv) @@ -2449,6 +2456,42 @@ static int cma_bind_listen(struct rdma_id_private *id_priv) return ret; } +static int cma_get_tcp_port(struct rdma_id_private *id_priv) +{ + int ret; + int size; + struct socket *sock; + + ret = sock_create_kern(AF_INET, SOCK_STREAM, IPPROTO_TCP, &sock); + if (ret) + return ret; +#ifdef __linux__ + ret = sock->ops->bind(sock, + (struct sockaddr *) &id_priv->id.route.addr.src_addr, + ip_addr_size((struct sockaddr *) &id_priv->id.route.addr.src_addr)); +#else + ret = -sobind(sock, + (struct sockaddr *)&id_priv->id.route.addr.src_addr, + curthread); +#endif + if (ret) { + sock_release(sock); + return ret; + } + + size = ip_addr_size((struct sockaddr *) &id_priv->id.route.addr.src_addr); + ret = sock_getname(sock, + (struct sockaddr *) &id_priv->id.route.addr.src_addr, + &size, 0); + if (ret) { + sock_release(sock); + return ret; + } + + id_priv->sock = sock; + return 0; +} + static int cma_get_port(struct rdma_id_private *id_priv) { struct idr *ps; @@ -2460,6 +2503,11 @@ static int cma_get_port(struct rdma_id_private *id_priv) break; case RDMA_PS_TCP: ps = &tcp_ps; + if (unify_tcp_port_space) { + ret = cma_get_tcp_port(id_priv); + if (ret) + goto out; + } break; case RDMA_PS_UDP: ps = &udp_ps; @@ -2480,7 +2528,7 @@ static int cma_get_port(struct rdma_id_private *id_priv) else ret = cma_use_port(ps, id_priv); mutex_unlock(&lock); - +out: return ret; } diff --git a/sys/powerpc/powerpc/trap.c b/sys/powerpc/powerpc/trap.c index 57008e9..d2e5eaa 100644 --- a/sys/powerpc/powerpc/trap.c +++ b/sys/powerpc/powerpc/trap.c @@ -413,8 +413,8 @@ printtrap(u_int vector, struct trapframe *frame, int isfatal, int user) case EXC_DTMISS: printf(" virtual address = 0x%" PRIxPTR "\n", frame->dar); #ifdef AIM - printf(" dsisr = 0x%" PRIxPTR "\n", - frame->cpu.aim.dsisr); + printf(" dsisr = 0x%lx\n", + (u_long)frame->cpu.aim.dsisr); #endif break; case EXC_ISE: @@ -438,7 +438,7 @@ printtrap(u_int vector, struct trapframe *frame, int isfatal, int user) frame->cpu.booke.esr); #endif printf(" srr0 = 0x%" PRIxPTR "\n", frame->srr0); - printf(" srr1 = 0x%" PRIxPTR "\n", frame->srr1); + printf(" srr1 = 0x%lx\n", (u_long)frame->srr1); printf(" lr = 0x%" PRIxPTR "\n", frame->lr); printf(" curthread = %p\n", curthread); if (curthread != NULL) diff --git a/sys/sys/ata.h b/sys/sys/ata.h index 863f0e8..272b46a 100644 --- a/sys/sys/ata.h +++ b/sys/sys/ata.h @@ -399,6 +399,7 @@ struct ata_params { #define ATA_IDLE_CMD 0xe3 /* idle */ #define ATA_READ_BUFFER 0xe4 /* read buffer */ #define ATA_READ_PM 0xe4 /* read portmultiplier */ +#define ATA_CHECK_POWER_MODE 0xe5 /* device power mode */ #define ATA_SLEEP 0xe6 /* sleep */ #define ATA_FLUSHCACHE 0xe7 /* flush cache to disk */ #define ATA_WRITE_PM 0xe8 /* write portmultiplier */ diff --git a/sys/sys/nv.h b/sys/sys/nv.h index fa5d138..a985b6d 100644 --- a/sys/sys/nv.h +++ b/sys/sys/nv.h @@ -1,5 +1,6 @@ /*- * Copyright (c) 2009-2013 The FreeBSD Foundation + * Copyright (c) 2013-2015 Mariusz Zaborski <oshogbo@FreeBSD.org> * All rights reserved. * * This software was developed by Pawel Jakub Dawidek under sponsorship from @@ -59,6 +60,11 @@ typedef struct nvlist nvlist_t; #define NV_TYPE_NVLIST 5 #define NV_TYPE_DESCRIPTOR 6 #define NV_TYPE_BINARY 7 +#define NV_TYPE_BOOL_ARRAY 8 +#define NV_TYPE_NUMBER_ARRAY 9 +#define NV_TYPE_STRING_ARRAY 10 +#define NV_TYPE_NVLIST_ARRAY 11 +#define NV_TYPE_DESCRIPTOR_ARRAY 12 /* * Perform case-insensitive lookups of provided names. @@ -101,6 +107,11 @@ const char *nvlist_next(const nvlist_t *nvl, int *typep, void **cookiep); const nvlist_t *nvlist_get_parent(const nvlist_t *nvl, void **cookiep); +const nvlist_t *nvlist_get_array_next(const nvlist_t *nvl); +bool nvlist_in_array(const nvlist_t *nvl); + +const nvlist_t *nvlist_get_pararr(const nvlist_t *nvl, void **cookiep); + /* * The nvlist_exists functions check if the given name (optionally of the given * type) exists on nvlist. @@ -114,10 +125,15 @@ bool nvlist_exists_bool(const nvlist_t *nvl, const char *name); bool nvlist_exists_number(const nvlist_t *nvl, const char *name); bool nvlist_exists_string(const nvlist_t *nvl, const char *name); bool nvlist_exists_nvlist(const nvlist_t *nvl, const char *name); +bool nvlist_exists_binary(const nvlist_t *nvl, const char *name); +bool nvlist_exists_bool_array(const nvlist_t *nvl, const char *name); +bool nvlist_exists_number_array(const nvlist_t *nvl, const char *name); +bool nvlist_exists_string_array(const nvlist_t *nvl, const char *name); +bool nvlist_exists_nvlist_array(const nvlist_t *nvl, const char *name); #ifndef _KERNEL bool nvlist_exists_descriptor(const nvlist_t *nvl, const char *name); +bool nvlist_exists_descriptor_array(const nvlist_t *nvl, const char *name); #endif -bool nvlist_exists_binary(const nvlist_t *nvl, const char *name); /* * The nvlist_add functions add the given name/value pair. @@ -134,10 +150,15 @@ void nvlist_add_stringf(nvlist_t *nvl, const char *name, const char *valuefmt, . void nvlist_add_stringv(nvlist_t *nvl, const char *name, const char *valuefmt, va_list valueap) __printflike(3, 0); #endif void nvlist_add_nvlist(nvlist_t *nvl, const char *name, const nvlist_t *value); +void nvlist_add_binary(nvlist_t *nvl, const char *name, const void *value, size_t size); +void nvlist_add_bool_array(nvlist_t *nvl, const char *name, const bool *value, size_t nitems); +void nvlist_add_number_array(nvlist_t *nvl, const char *name, const uint64_t *value, size_t nitems); +void nvlist_add_string_array(nvlist_t *nvl, const char *name, const char * const *value, size_t nitems); +void nvlist_add_nvlist_array(nvlist_t *nvl, const char *name, const nvlist_t * const *value, size_t nitems); #ifndef _KERNEL void nvlist_add_descriptor(nvlist_t *nvl, const char *name, int value); +void nvlist_add_descriptor_array(nvlist_t *nvl, const char *name, const int *value, size_t nitems); #endif -void nvlist_add_binary(nvlist_t *nvl, const char *name, const void *value, size_t size); /* * The nvlist_move functions add the given name/value pair. @@ -146,10 +167,15 @@ void nvlist_add_binary(nvlist_t *nvl, const char *name, const void *value, size_ void nvlist_move_string(nvlist_t *nvl, const char *name, char *value); void nvlist_move_nvlist(nvlist_t *nvl, const char *name, nvlist_t *value); +void nvlist_move_binary(nvlist_t *nvl, const char *name, void *value, size_t size); +void nvlist_move_bool_array(nvlist_t *nvl, const char *name, bool *value, size_t nitems); +void nvlist_move_string_array(nvlist_t *nvl, const char *name, char **value, size_t nitems); +void nvlist_move_nvlist_array(nvlist_t *nvl, const char *name, nvlist_t **value, size_t nitems); +void nvlist_move_number_array(nvlist_t *nvl, const char *name, uint64_t *value, size_t nitems); #ifndef _KERNEL void nvlist_move_descriptor(nvlist_t *nvl, const char *name, int value); +void nvlist_move_descriptor_array(nvlist_t *nvl, const char *name, int *value, size_t nitems); #endif -void nvlist_move_binary(nvlist_t *nvl, const char *name, void *value, size_t size); /* * The nvlist_get functions returns value associated with the given name. @@ -157,14 +183,19 @@ void nvlist_move_binary(nvlist_t *nvl, const char *name, void *value, size_t siz * not be freed by the caller. */ -bool nvlist_get_bool(const nvlist_t *nvl, const char *name); -uint64_t nvlist_get_number(const nvlist_t *nvl, const char *name); -const char *nvlist_get_string(const nvlist_t *nvl, const char *name); -const nvlist_t *nvlist_get_nvlist(const nvlist_t *nvl, const char *name); +bool nvlist_get_bool(const nvlist_t *nvl, const char *name); +uint64_t nvlist_get_number(const nvlist_t *nvl, const char *name); +const char *nvlist_get_string(const nvlist_t *nvl, const char *name); +const nvlist_t *nvlist_get_nvlist(const nvlist_t *nvl, const char *name); +const void *nvlist_get_binary(const nvlist_t *nvl, const char *name, size_t *sizep); +const bool *nvlist_get_bool_array(const nvlist_t *nvl, const char *name, size_t *nitemsp); +const uint64_t *nvlist_get_number_array(const nvlist_t *nvl, const char *name, size_t *nitemsp); +const char * const *nvlist_get_string_array(const nvlist_t *nvl, const char *name, size_t *nitemsp); +const nvlist_t * const *nvlist_get_nvlist_array(const nvlist_t *nvl, const char *name, size_t *nitemsp); #ifndef _KERNEL -int nvlist_get_descriptor(const nvlist_t *nvl, const char *name); +int nvlist_get_descriptor(const nvlist_t *nvl, const char *name); +const int *nvlist_get_descriptor_array(const nvlist_t *nvl, const char *name, size_t *nitemsp); #endif -const void *nvlist_get_binary(const nvlist_t *nvl, const char *name, size_t *sizep); /* * The nvlist_take functions returns value associated with the given name and @@ -172,14 +203,19 @@ const void *nvlist_get_binary(const nvlist_t *nvl, const char *name, size_t *siz * The caller is responsible for freeing received data. */ -bool nvlist_take_bool(nvlist_t *nvl, const char *name); -uint64_t nvlist_take_number(nvlist_t *nvl, const char *name); -char *nvlist_take_string(nvlist_t *nvl, const char *name); -nvlist_t *nvlist_take_nvlist(nvlist_t *nvl, const char *name); +bool nvlist_take_bool(nvlist_t *nvl, const char *name); +uint64_t nvlist_take_number(nvlist_t *nvl, const char *name); +char *nvlist_take_string(nvlist_t *nvl, const char *name); +nvlist_t *nvlist_take_nvlist(nvlist_t *nvl, const char *name); +void *nvlist_take_binary(nvlist_t *nvl, const char *name, size_t *sizep); +bool *nvlist_take_bool_array(nvlist_t *nvl, const char *name, size_t *nitemsp); +uint64_t *nvlist_take_number_array(nvlist_t *nvl, const char *name, size_t *nitemsp); +char **nvlist_take_string_array(nvlist_t *nvl, const char *name, size_t *nitemsp); +nvlist_t **nvlist_take_nvlist_array(nvlist_t *nvl, const char *name, size_t *nitemsp); #ifndef _KERNEL int nvlist_take_descriptor(nvlist_t *nvl, const char *name); +int *nvlist_take_descriptor_array(nvlist_t *nvl, const char *name, size_t *nitemsp); #endif -void *nvlist_take_binary(nvlist_t *nvl, const char *name, size_t *sizep); /* * The nvlist_free functions removes the given name/value pair from the nvlist @@ -194,10 +230,16 @@ void nvlist_free_bool(nvlist_t *nvl, const char *name); void nvlist_free_number(nvlist_t *nvl, const char *name); void nvlist_free_string(nvlist_t *nvl, const char *name); void nvlist_free_nvlist(nvlist_t *nvl, const char *name); +void nvlist_free_binary(nvlist_t *nvl, const char *name); +void nvlist_free_bool_array(nvlist_t *nvl, const char *name); +void nvlist_free_number_array(nvlist_t *nvl, const char *name); +void nvlist_free_string_array(nvlist_t *nvl, const char *name); +void nvlist_free_nvlist_array(nvlist_t *nvl, const char *name); +void nvlist_free_binary_array(nvlist_t *nvl, const char *name); #ifndef _KERNEL void nvlist_free_descriptor(nvlist_t *nvl, const char *name); +void nvlist_free_descriptor_array(nvlist_t *nvl, const char *name); #endif -void nvlist_free_binary(nvlist_t *nvl, const char *name); __END_DECLS diff --git a/sys/sys/random.h b/sys/sys/random.h index 78a9955..92eb80f 100644 --- a/sys/sys/random.h +++ b/sys/sys/random.h @@ -33,10 +33,29 @@ #include <sys/types.h> +#include "opt_random.h" + +#if defined(RANDOM_LOADABLE) && defined(RANDOM_YARROW) +#error "Cannot define both RANDOM_LOADABLE and RANDOM_YARROW" +#endif + struct uio; +#if defined(DEV_RANDOM) u_int read_random(void *, u_int); int read_random_uio(struct uio *, bool); +#else +static __inline int +read_random_uio(void *a __unused, u_int b __unused) +{ + return (0); +} +static __inline u_int +read_random(void *a __unused, u_int b __unused) +{ + return (0); +} +#endif /* * Note: if you add or remove members of random_entropy_source, remember to also update the @@ -76,15 +95,15 @@ enum random_entropy_source { #define RANDOM_HARVEST_EVERYTHING_MASK ((1 << (RANDOM_ENVIRONMENTAL_END + 1)) - 1) -#if defined(RANDOM_DUMMY) -#define random_harvest_queue(a, b, c, d) do {} while (0) -#define random_harvest_fast(a, b, c, d) do {} while (0) -#define random_harvest_direct(a, b, c, d) do {} while (0) -#else /* !defined(RANDOM_DUMMY) */ +#if defined(DEV_RANDOM) void random_harvest_queue(const void *, u_int, u_int, enum random_entropy_source); void random_harvest_fast(const void *, u_int, u_int, enum random_entropy_source); void random_harvest_direct(const void *, u_int, u_int, enum random_entropy_source); -#endif /* defined(RANDOM_DUMMY) */ +#else +#define random_harvest_queue(a, b, c, d) do {} while (0) +#define random_harvest_fast(a, b, c, d) do {} while (0) +#define random_harvest_direct(a, b, c, d) do {} while (0) +#endif #endif /* _KERNEL */ diff --git a/sys/sys/socketvar.h b/sys/sys/socketvar.h index 112bb2c..26cf9a6 100644 --- a/sys/sys/socketvar.h +++ b/sys/sys/socketvar.h @@ -78,7 +78,7 @@ struct socket { short so_state; /* (b) internal state flags SS_* */ int so_qstate; /* (e) internal state flags SQ_* */ void *so_pcb; /* protocol control block */ - struct vnet *so_vnet; /* network stack instance */ + struct vnet *so_vnet; /* (a) network stack instance */ struct protosw *so_proto; /* (a) protocol handle */ /* * Variables for connection queuing. diff --git a/sys/sys/timeet.h b/sys/sys/timeet.h index 728578b..3d50e51 100644 --- a/sys/sys/timeet.h +++ b/sys/sys/timeet.h @@ -53,7 +53,7 @@ typedef int et_deregister_cb_t(struct eventtimer *et, void *arg); struct eventtimer { SLIST_ENTRY(eventtimer) et_all; /* Pointer to the next event timer. */ - char *et_name; + const char *et_name; /* Name of the event timer. */ int et_flags; /* Set of capabilities flags: */ diff --git a/sys/sys/timetc.h b/sys/sys/timetc.h index e68e327..8f00e22 100644 --- a/sys/sys/timetc.h +++ b/sys/sys/timetc.h @@ -49,7 +49,7 @@ struct timecounter { /* This mask should mask off any unimplemented bits. */ uint64_t tc_frequency; /* Frequency of the counter in Hz. */ - char *tc_name; + const char *tc_name; /* Name of the timecounter. */ int tc_quality; /* diff --git a/sys/teken/demo/teken_demo.c b/sys/teken/demo/teken_demo.c index 08323dc..42747ce 100644 --- a/sys/teken/demo/teken_demo.c +++ b/sys/teken/demo/teken_demo.c @@ -72,7 +72,7 @@ struct pixel { #define NCOLS 80 #define NROWS 24 -struct pixel buffer[NCOLS][NROWS]; +static struct pixel buffer[NCOLS][NROWS]; static int ptfd; diff --git a/sys/teken/teken.c b/sys/teken/teken.c index 3002a88..8834390 100644 --- a/sys/teken/teken.c +++ b/sys/teken/teken.c @@ -29,12 +29,14 @@ #include <sys/cdefs.h> #if defined(__FreeBSD__) && defined(_KERNEL) #include <sys/param.h> +#include <sys/limits.h> #include <sys/lock.h> #include <sys/systm.h> #define teken_assert(x) MPASS(x) #else /* !(__FreeBSD__ && _KERNEL) */ #include <sys/types.h> #include <assert.h> +#include <limits.h> #include <stdint.h> #include <stdio.h> #include <string.h> @@ -405,18 +407,24 @@ teken_state_numbers(teken_t *t, teken_char_t c) teken_assert(t->t_curnum < T_NUMSIZE); if (c >= '0' && c <= '9') { - /* - * Don't do math with the default value of 1 when a - * custom number is inserted. - */ if (t->t_stateflags & TS_FIRSTDIGIT) { + /* First digit. */ t->t_stateflags &= ~TS_FIRSTDIGIT; - t->t_nums[t->t_curnum] = 0; - } else { - t->t_nums[t->t_curnum] *= 10; + t->t_nums[t->t_curnum] = c - '0'; + } else if (t->t_nums[t->t_curnum] < UINT_MAX / 100) { + /* + * There is no need to continue parsing input + * once the value exceeds the size of the + * terminal. It would only allow for integer + * overflows when performing arithmetic on the + * cursor position. + * + * Ignore any further digits if the value is + * already UINT_MAX / 100. + */ + t->t_nums[t->t_curnum] = + t->t_nums[t->t_curnum] * 10 + c - '0'; } - - t->t_nums[t->t_curnum] += c - '0'; return (1); } else if (c == ';') { if (t->t_stateflags & TS_FIRSTDIGIT) diff --git a/sys/vm/vm_pageout.c b/sys/vm/vm_pageout.c index 91affa0..13916c0 100644 --- a/sys/vm/vm_pageout.c +++ b/sys/vm/vm_pageout.c @@ -566,11 +566,6 @@ vm_pageout_flush(vm_page_t *mc, int count, int flags, int mreq, int *prunlen, if (pageout_status[i] != VM_PAGER_PEND) { vm_object_pip_wakeup(object); vm_page_sunbusy(mt); - if (vm_page_count_severe()) { - vm_page_lock(mt); - vm_page_try_to_cache(mt); - vm_page_unlock(mt); - } } } if (prunlen != NULL) diff --git a/sys/x86/iommu/intel_idpgtbl.c b/sys/x86/iommu/intel_idpgtbl.c index 405976b..d52e8d4 100644 --- a/sys/x86/iommu/intel_idpgtbl.c +++ b/sys/x86/iommu/intel_idpgtbl.c @@ -374,8 +374,9 @@ retry: KASSERT(lvl > 0, ("lost root page table page %p", domain)); /* - * Page table page does not exists, allocate - * it and create pte in the up level. + * Page table page does not exist, allocate + * it and create a pte in the preceeding page level + * to reference the allocated page table page. */ m = dmar_pgalloc(domain->pgtbl_obj, idx, flags | DMAR_PGF_ZERO); diff --git a/sys/x86/x86/busdma_bounce.c b/sys/x86/x86/busdma_bounce.c index dcdeafa..48c500f 100644 --- a/sys/x86/x86/busdma_bounce.c +++ b/sys/x86/x86/busdma_bounce.c @@ -79,7 +79,8 @@ struct bounce_page { vm_offset_t vaddr; /* kva of bounce buffer */ bus_addr_t busaddr; /* Physical address */ vm_offset_t datavaddr; /* kva of client data */ - bus_addr_t dataaddr; /* client physical address */ + vm_page_t datapage; /* physical page of client data */ + vm_offset_t dataoffs; /* page offset of client data */ bus_size_t datacount; /* client data count */ STAILQ_ENTRY(bounce_page) links; }; @@ -658,7 +659,7 @@ bounce_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, { bus_size_t sgsize, max_sgsize; bus_addr_t curaddr; - vm_offset_t vaddr; + vm_offset_t kvaddr, vaddr; int error; if (map == NULL) @@ -681,10 +682,13 @@ bounce_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, /* * Get the physical address for this segment. */ - if (pmap == kernel_pmap) + if (pmap == kernel_pmap) { curaddr = pmap_kextract(vaddr); - else + kvaddr = vaddr; + } else { curaddr = pmap_extract(pmap, vaddr); + kvaddr = 0; + } /* * Compute the segment size, and adjust counts. @@ -696,7 +700,7 @@ bounce_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, bus_dma_run_filter(&dmat->common, curaddr)) { sgsize = roundup2(sgsize, dmat->common.alignment); sgsize = MIN(sgsize, max_sgsize); - curaddr = add_bounce_page(dmat, map, vaddr, curaddr, + curaddr = add_bounce_page(dmat, map, kvaddr, curaddr, sgsize); } else { sgsize = MIN(sgsize, max_sgsize); @@ -757,48 +761,56 @@ bounce_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) { struct bounce_page *bpage; + vm_offset_t datavaddr, tempvaddr; - if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { - /* - * Handle data bouncing. We might also - * want to add support for invalidating - * the caches on broken hardware - */ - CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " - "performing bounce", __func__, dmat, - dmat->common.flags, op); - - if ((op & BUS_DMASYNC_PREWRITE) != 0) { - while (bpage != NULL) { - if (bpage->datavaddr != 0) { - bcopy((void *)bpage->datavaddr, - (void *)bpage->vaddr, - bpage->datacount); - } else { - physcopyout(bpage->dataaddr, - (void *)bpage->vaddr, - bpage->datacount); - } - bpage = STAILQ_NEXT(bpage, links); + if ((bpage = STAILQ_FIRST(&map->bpages)) == NULL) + return; + + /* + * Handle data bouncing. We might also want to add support for + * invalidating the caches on broken hardware. + */ + CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " + "performing bounce", __func__, dmat, dmat->common.flags, op); + + if ((op & BUS_DMASYNC_PREWRITE) != 0) { + while (bpage != NULL) { + tempvaddr = 0; + datavaddr = bpage->datavaddr; + if (datavaddr == 0) { + tempvaddr = + pmap_quick_enter_page(bpage->datapage); + datavaddr = tempvaddr | bpage->dataoffs; } - dmat->bounce_zone->total_bounced++; + + bcopy((void *)datavaddr, + (void *)bpage->vaddr, bpage->datacount); + + if (tempvaddr != 0) + pmap_quick_remove_page(tempvaddr); + bpage = STAILQ_NEXT(bpage, links); } + dmat->bounce_zone->total_bounced++; + } - if ((op & BUS_DMASYNC_POSTREAD) != 0) { - while (bpage != NULL) { - if (bpage->datavaddr != 0) { - bcopy((void *)bpage->vaddr, - (void *)bpage->datavaddr, - bpage->datacount); - } else { - physcopyin((void *)bpage->vaddr, - bpage->dataaddr, - bpage->datacount); - } - bpage = STAILQ_NEXT(bpage, links); + if ((op & BUS_DMASYNC_POSTREAD) != 0) { + while (bpage != NULL) { + tempvaddr = 0; + datavaddr = bpage->datavaddr; + if (datavaddr == 0) { + tempvaddr = + pmap_quick_enter_page(bpage->datapage); + datavaddr = tempvaddr | bpage->dataoffs; } - dmat->bounce_zone->total_bounced++; + + bcopy((void *)bpage->vaddr, + (void *)datavaddr, bpage->datacount); + + if (tempvaddr != 0) + pmap_quick_remove_page(tempvaddr); + bpage = STAILQ_NEXT(bpage, links); } + dmat->bounce_zone->total_bounced++; } } @@ -993,7 +1005,8 @@ add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, bpage->busaddr |= addr & PAGE_MASK; } bpage->datavaddr = vaddr; - bpage->dataaddr = addr; + bpage->datapage = PHYS_TO_VM_PAGE(addr & ~PAGE_MASK); + bpage->dataoffs = addr & PAGE_MASK; bpage->datacount = size; STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); return (bpage->busaddr); diff --git a/sys/xen/gnttab.h b/sys/xen/gnttab.h index d0a44ae..9e82124 100644 --- a/sys/xen/gnttab.h +++ b/sys/xen/gnttab.h @@ -126,10 +126,8 @@ gnttab_set_map_op(struct gnttab_map_grant_ref *map, vm_paddr_t addr, { if (flags & GNTMAP_contains_pte) map->host_addr = addr; - else if (xen_feature(XENFEAT_auto_translated_physmap)) - map->host_addr = vtophys(addr); else - map->host_addr = addr; + map->host_addr = vtophys(addr); map->flags = flags; map->ref = ref; @@ -142,10 +140,8 @@ gnttab_set_unmap_op(struct gnttab_unmap_grant_ref *unmap, vm_paddr_t addr, { if (flags & GNTMAP_contains_pte) unmap->host_addr = addr; - else if (xen_feature(XENFEAT_auto_translated_physmap)) - unmap->host_addr = vtophys(addr); else - unmap->host_addr = addr; + unmap->host_addr = vtophys(addr); unmap->handle = handle; unmap->dev_bus_addr = 0; @@ -155,13 +151,8 @@ static inline void gnttab_set_replace_op(struct gnttab_unmap_and_replace *unmap, vm_paddr_t addr, vm_paddr_t new_addr, grant_handle_t handle) { - if (xen_feature(XENFEAT_auto_translated_physmap)) { - unmap->host_addr = vtophys(addr); - unmap->new_addr = vtophys(new_addr); - } else { - unmap->host_addr = addr; - unmap->new_addr = new_addr; - } + unmap->host_addr = vtophys(addr); + unmap->new_addr = vtophys(new_addr); unmap->handle = handle; } diff --git a/targets/pseudo/toolchain/Makefile.depend b/targets/pseudo/toolchain/Makefile.depend index e2e0202..0b35c07 100644 --- a/targets/pseudo/toolchain/Makefile.depend +++ b/targets/pseudo/toolchain/Makefile.depend @@ -9,7 +9,7 @@ DEP_RELDIR := ${_PARSEDIR:S,${SRCTOP}/,,} .endif DIRDEPS= -.if ${MK_ELFTOOLCHAIN_TOOLS} == "yes" +.if ${MK_TOOLCHAIN} == "yes" DIRDEPS+= \ usr.bin/addr2line \ usr.bin/cxxflit \ diff --git a/tools/build/mk/OptionalObsoleteFiles.inc b/tools/build/mk/OptionalObsoleteFiles.inc index 2ae3054..5192807 100644 --- a/tools/build/mk/OptionalObsoleteFiles.inc +++ b/tools/build/mk/OptionalObsoleteFiles.inc @@ -184,7 +184,7 @@ OLD_DIRS+=usr/share/examples/bhyve .if ${MK_BINUTILS} == no OLD_FILES+=usr/bin/as OLD_FILES+=usr/bin/ld -.if ${MK_ELFTOOLCHAIN_TOOLS} != no && ${MK_ELFCOPY_AS_OBJCOPY} == no +.if ${MK_ELFCOPY_AS_OBJCOPY} == no OLD_FILES+=usr/bin/objcopy .endif OLD_FILES+=usr/bin/objdump @@ -203,7 +203,7 @@ OLD_FILES+=usr/libdata/ldscripts/elf_x86_64_fbsd.xu OLD_FILES+=usr/libdata/ldscripts/elf_x86_64_fbsd.xw OLD_FILES+=usr/share/man/man1/as.1.gz OLD_FILES+=usr/share/man/man1/ld.1.gz -.if ${MK_ELFTOOLCHAIN_TOOLS} != no && ${MK_ELFCOPY_AS_OBJCOPY} == no +.if ${MK_ELFCOPY_AS_OBJCOPY} == no OLD_FILES+=usr/share/man/man1/objcopy.1.gz .endif OLD_FILES+=usr/share/man/man1/objdump.1.gz @@ -1663,29 +1663,6 @@ OLD_FILES+=usr/share/nls/ru_RU.KOI8-R/ee.cat OLD_FILES+=usr/share/nls/uk_UA.KOI8-U/ee.cat .endif -.if ${MK_ELFTOOLCHAIN_TOOLS} == no || \ - (${MK_ELFTOOLCHAIN_TOOLS} != no && ${MK_ELFCOPY_AS_OBJCOPY} != no) -OLD_FILES+=usr/bin/elfcopy -OLD_FILES+=usr/share/man/man1/elfcopy.1.gz -.endif - -.if ${MK_ELFTOOLCHAIN_TOOLS} == no -OLD_FILES+=usr/bin/addr2line -OLD_FILES+=usr/bin/c++filt -OLD_FILES+=usr/bin/nm -OLD_FILES+=usr/bin/readelf -OLD_FILES+=usr/bin/size -OLD_FILES+=usr/bin/strings -OLD_FILES+=usr/bin/strip -OLD_FILES+=usr/share/man/man1/addr2line.1.gz -OLD_FILES+=usr/share/man/man1/c++filt.1.gz -OLD_FILES+=usr/share/man/man1/nm.1.gz -OLD_FILES+=usr/share/man/man1/readelf.1.gz -OLD_FILES+=usr/share/man/man1/size.1.gz -OLD_FILES+=usr/share/man/man1/strings.1.gz -OLD_FILES+=usr/share/man/man1/strip.1.gz -.endif - #.if ${MK_EXAMPLES} == no # to be filled in #.endif @@ -7545,9 +7522,26 @@ OLD_FILES+=usr/share/man/man1/colcrt.1.gz OLD_FILES+=usr/share/man/man1/ul.1.gz .endif -#.if ${MK_TOOLCHAIN} == no -# to be filled in -#.endif +.if ${MK_TOOLCHAIN} == no +OLD_FILES+=usr/bin/addr2line +OLD_FILES+=usr/bin/c++filt +OLD_FILES+=usr/bin/nm +OLD_FILES+=usr/bin/readelf +OLD_FILES+=usr/bin/size +OLD_FILES+=usr/bin/strings +OLD_FILES+=usr/bin/strip +OLD_FILES+=usr/share/man/man1/addr2line.1.gz +OLD_FILES+=usr/share/man/man1/c++filt.1.gz +OLD_FILES+=usr/share/man/man1/nm.1.gz +OLD_FILES+=usr/share/man/man1/readelf.1.gz +OLD_FILES+=usr/share/man/man1/size.1.gz +OLD_FILES+=usr/share/man/man1/strings.1.gz +OLD_FILES+=usr/share/man/man1/strip.1.gz +.endif +.if ${MK_TOOLCHAIN} == no || ${MK_ELFCOPY_AS_OBJCOPY} != no +OLD_FILES+=usr/bin/elfcopy +OLD_FILES+=usr/share/man/man1/elfcopy.1.gz +.endif .if ${MK_UNBOUND} == no OLD_FILES+=etc/rc.d/local_unbound diff --git a/tools/build/options/WITHOUT_ELFTOOLCHAIN_TOOLS b/tools/build/options/WITHOUT_ELFTOOLCHAIN_TOOLS deleted file mode 100644 index e30f48d..0000000 --- a/tools/build/options/WITHOUT_ELFTOOLCHAIN_TOOLS +++ /dev/null @@ -1,10 +0,0 @@ -.\" $FreeBSD$ -Set to avoid building ELF Tool Chain tools -.Xr addr2line 1 , -.Xr c++filt 1 , -.Xr nm 1 , -.Xr readelf 1 , -.Xr size 1 , -.Xr strings 1 , -and -.Xr strip 1 . diff --git a/tools/build/options/WITHOUT_SYSINSTALL b/tools/build/options/WITHOUT_SYSINSTALL deleted file mode 100644 index 60426e3..0000000 --- a/tools/build/options/WITHOUT_SYSINSTALL +++ /dev/null @@ -1,4 +0,0 @@ -.\" $FreeBSD$ -Set to not build -.Xr sysinstall 8 -and related programs. diff --git a/tools/tools/nanobsd/gateworks/common b/tools/tools/nanobsd/gateworks/common index 8cedf38..bc38e99 100644 --- a/tools/tools/nanobsd/gateworks/common +++ b/tools/tools/nanobsd/gateworks/common @@ -147,7 +147,6 @@ WITHOUT_SENDMAIL=true WITHOUT_SHAREDOCS=true WITHOUT_SSP=true WITHOUT_SYSCONS=true -WITHOUT_SYSINSTALL=true WITHOUT_TCSH=true WITHOUT_TFTPD=true WITHOUT_ZFS=true diff --git a/usr.bin/Makefile b/usr.bin/Makefile index 64dffa9..faabe67 100644 --- a/usr.bin/Makefile +++ b/usr.bin/Makefile @@ -218,16 +218,6 @@ SUBDIR+= clang SUBDIR+= ee .endif -.if ${MK_ELFTOOLCHAIN_TOOLS} != "no" -SUBDIR+= addr2line -SUBDIR+= cxxfilt -SUBDIR+= elfcopy -SUBDIR+= nm -SUBDIR+= readelf -SUBDIR+= size -SUBDIR+= strings -.endif - .if ${MK_FILE} != "no" SUBDIR+= file .endif @@ -361,10 +351,13 @@ SUBDIR+= tftp .endif .if ${MK_TOOLCHAIN} != "no" +SUBDIR+= addr2line SUBDIR+= ar SUBDIR+= c89 SUBDIR+= c99 SUBDIR+= ctags +SUBDIR+= cxxfilt +SUBDIR+= elfcopy SUBDIR+= file2c .if ${MACHINE_ARCH} != "aarch64" # ARM64TODO gprof does not build SUBDIR+= gprof @@ -372,8 +365,12 @@ SUBDIR+= gprof SUBDIR+= indent SUBDIR+= lex SUBDIR+= mkstr +SUBDIR+= nm +SUBDIR+= readelf SUBDIR+= rpcgen SUBDIR+= unifdef +SUBDIR+= size +SUBDIR+= strings .if ${MACHINE_ARCH} != "aarch64" # ARM64TODO xlint does not build SUBDIR+= xlint .endif diff --git a/usr.bin/ctlstat/ctlstat.c b/usr.bin/ctlstat/ctlstat.c index 3bfb248..f12dd43 100644 --- a/usr.bin/ctlstat/ctlstat.c +++ b/usr.bin/ctlstat/ctlstat.c @@ -62,7 +62,6 @@ __FBSDID("$FreeBSD$"); #include <cam/ctl/ctl_io.h> #include <cam/ctl/ctl_scsi_all.h> #include <cam/ctl/ctl_util.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_ioctl.h> diff --git a/usr.bin/lorder/lorder.1 b/usr.bin/lorder/lorder.1 index 66e682a..56a4b2a 100644 --- a/usr.bin/lorder/lorder.1 +++ b/usr.bin/lorder/lorder.1 @@ -28,7 +28,7 @@ .\" @(#)lorder.1 8.2 (Berkeley) 4/28/95 .\" $FreeBSD$ .\" -.Dd October 25, 2006 +.Dd August 14, 2015 .Dt LORDER 1 .Os .Sh NAME @@ -68,6 +68,9 @@ Path to the .Xr nm 1 binary, defaults to .Dq Li nm . +.It Ev NMFLAGS +Flags to pass to +.Xr nm 1 . .El .Sh EXAMPLES .Bd -literal -offset indent diff --git a/usr.bin/lorder/lorder.sh b/usr.bin/lorder/lorder.sh index e423d96..8123c96 100644 --- a/usr.bin/lorder/lorder.sh +++ b/usr.bin/lorder/lorder.sh @@ -60,7 +60,7 @@ done # # if the line has " U " it's a globally undefined symbol, put it into # the reference file. -${NM} -go $* | sed " +${NM} ${NMFLAGS} -go $* | sed " / [TDW] / { s/:.* [TDW] / / w $S diff --git a/usr.bin/patch/common.h b/usr.bin/patch/common.h index f33abcf..2cdeaff 100644 --- a/usr.bin/patch/common.h +++ b/usr.bin/patch/common.h @@ -42,12 +42,6 @@ #define BUFFERSIZE 4096 #define LINENUM_MAX LONG_MAX -#define SCCSPREFIX "s." - -#define RCSSUFFIX ",v" -#define CHECKOUT "/usr/bin/co" -#define RCSDIFF "/usr/bin/rcsdiff" - #define ORIGEXT ".orig" #define REJEXT ".rej" diff --git a/usr.bin/patch/inp.c b/usr.bin/patch/inp.c index f4daeae..19536da 100644 --- a/usr.bin/patch/inp.c +++ b/usr.bin/patch/inp.c @@ -137,13 +137,12 @@ reallocate_lines(size_t *lines_allocated) static bool plan_a(const char *filename) { - int ifd, statfailed, pstat; - char *p, *s, lbuf[INITLINELEN]; + int ifd, statfailed; + char *p, *s; struct stat filestat; ptrdiff_t sz; size_t i; size_t iline, lines_allocated; - pid_t pid; #ifdef DEBUGGING if (debug & 8) @@ -169,96 +168,8 @@ plan_a(const char *filename) close(creat(filename, 0666)); statfailed = stat(filename, &filestat); } - if (statfailed && check_only) - fatal("%s not found, -C mode, can't probe further\n", filename); - /* For nonexistent or read-only files, look for RCS versions. */ - - if (statfailed || - /* No one can write to it. */ - (filestat.st_mode & 0222) == 0 || - /* I can't write to it. */ - ((filestat.st_mode & 0022) == 0 && filestat.st_uid != getuid())) { - char *filebase, *filedir; - struct stat cstat; - char *tmp_filename1, *tmp_filename2; - char *argp[4] = { NULL }; - posix_spawn_file_actions_t file_actions; - - tmp_filename1 = strdup(filename); - tmp_filename2 = strdup(filename); - if (tmp_filename1 == NULL || tmp_filename2 == NULL) - fatal("strdupping filename"); - - filebase = basename(tmp_filename1); - filedir = dirname(tmp_filename2); - - memset(argp, 0, sizeof(argp)); - -#define try(f, a1, a2, a3) \ - (snprintf(lbuf, sizeof(lbuf), f, a1, a2, a3), stat(lbuf, &cstat) == 0) - - /* - * else we can't write to it but it's not under a version - * control system, so just proceed. - */ - if (try("%s/RCS/%s%s", filedir, filebase, RCSSUFFIX) || - try("%s/RCS/%s%s", filedir, filebase, "") || - try("%s/%s%s", filedir, filebase, RCSSUFFIX)) { - if (!statfailed) { - if ((filestat.st_mode & 0222) != 0) - /* The owner can write to it. */ - fatal("file %s seems to be locked " - "by somebody else under RCS\n", - filename); - /* - * It might be checked out unlocked. See if - * it's safe to check out the default version - * locked. - */ - if (verbose) - say("Comparing file %s to default " - "RCS version...\n", filename); - - argp[0] = __DECONST(char *, RCSDIFF); - argp[1] = __DECONST(char *, filename); - posix_spawn_file_actions_init(&file_actions); - posix_spawn_file_actions_addopen(&file_actions, - STDOUT_FILENO, _PATH_DEVNULL, O_WRONLY, 0); - if (posix_spawn(&pid, RCSDIFF, &file_actions, - NULL, argp, NULL) == 0) { - pid = waitpid(pid, &pstat, 0); - if (pid == -1 || WEXITSTATUS(pstat) != 0) - fatal("can't check out file %s: " - "differs from default RCS version\n", - filename); - } else - fatal("posix_spawn: %s\n", strerror(errno)); - posix_spawn_file_actions_destroy(&file_actions); - } - - if (verbose) - say("Checking out file %s from RCS...\n", - filename); - - argp[0] = __DECONST(char *, CHECKOUT); - argp[1] = __DECONST(char *, "-l"); - argp[2] = __DECONST(char *, filename); - if (posix_spawn(&pid, CHECKOUT, NULL, NULL, argp, - NULL) == 0) { - pid = waitpid(pid, &pstat, 0); - if (pid == -1 || WEXITSTATUS(pstat) != 0 || - stat(filename, &filestat)) - fatal("can't check out file %s from RCS\n", - filename); - } else - fatal("posix_spawn: %s\n", strerror(errno)); - } else if (statfailed) { - fatal("can't find %s\n", filename); - } - free(tmp_filename1); - free(tmp_filename2); - } - + if (statfailed) + fatal("can't find %s\n", filename); filemode = filestat.st_mode; if (!S_ISREG(filemode)) fatal("%s is not a normal file--can't patch\n", filename); diff --git a/usr.bin/patch/patch.1 b/usr.bin/patch/patch.1 index 25adf5f..e8478fc 100644 --- a/usr.bin/patch/patch.1 +++ b/usr.bin/patch/patch.1 @@ -21,7 +21,7 @@ .\" .\" $OpenBSD: patch.1,v 1.27 2014/04/15 06:26:54 jmc Exp $ .\" $FreeBSD$ -.Dd July 21, 2015 +.Dd August 15, 2015 .Dt PATCH 1 .Os .Sh NAME @@ -175,7 +175,7 @@ for that. .Fl Fl input Ar patchfile .Xc Causes the next argument to be interpreted as the input file name -(i.e. a patchfile). +(i.e., a patchfile). This option may be specified multiple times. .It Fl l , Fl Fl ignore-whitespace Causes the pattern matching to be done loosely, in case the tabs and @@ -245,7 +245,7 @@ option. Tells .Nm that this patch was created with the old and new files swapped. -(Yes, I'm afraid that does happen occasionally, human nature being what it +(Yes, I am afraid that does happen occasionally, human nature being what it is.) .Nm will attempt to swap each hunk around before applying it. @@ -263,7 +263,7 @@ If it can, you will be asked if you want to have the option set. If it cannot, the patch will continue to be applied normally. (Note: this method cannot detect a reversed patch if it is a normal diff -and if the first command is an append (i.e. it should have been a delete) +and if the first command is an append (i.e., it should have been a delete) since appends always succeed, due to the fact that a null context will match anywhere. Luckily, most patches add or change lines rather than delete them, so most @@ -387,7 +387,7 @@ given in the hunk. First .Nm looks for a place where all lines of the context match. -If no such place is found, and it's a context diff, and the maximum fuzz factor +If no such place is found, and it is a context diff, and the maximum fuzz factor is set to 1 or more, then another scan takes place ignoring the first and last line of context. If that fails, and the maximum fuzz factor is set to 2 or more, @@ -483,15 +483,6 @@ file names or, for a non-context diff, the file name, and choose the file name with the fewest path components, the shortest basename, and the shortest total file name length (in that order). .It -If no file exists, -.Nm -checks for the existence of the files in an SCCS or RCS directory -(using the appropriate prefix or suffix) using the criteria specified -above. -If found, -.Nm -will attempt to get or check out the file. -.It If no suitable file was found to patch, the patch file is a context or unified diff, and the old file was zero length, the new file name is created and used. diff --git a/usr.bin/patch/pch.c b/usr.bin/patch/pch.c index 5fadf62..cae7bf4 100644 --- a/usr.bin/patch/pch.c +++ b/usr.bin/patch/pch.c @@ -1501,17 +1501,8 @@ posix_name(const struct file_name *names, bool assume_exists) } if (path == NULL && !assume_exists) { /* - * No files found, look for something we can checkout from - * RCS/SCCS dirs. Same order as above. - */ - for (i = 0; i < MAX_FILE; i++) { - if (names[i].path != NULL && - (path = checked_in(names[i].path)) != NULL) - break; - } - /* - * Still no match? Check to see if the diff could be creating - * a new file. + * No files found, check to see if the diff could be + * creating a new file. */ if (path == NULL && ok_to_create_file && names[NEW_FILE].path != NULL) @@ -1522,7 +1513,7 @@ posix_name(const struct file_name *names, bool assume_exists) } static char * -compare_names(const struct file_name *names, bool assume_exists, int phase) +compare_names(const struct file_name *names, bool assume_exists) { size_t min_components, min_baselen, min_len, tmp; char *best = NULL; @@ -1539,9 +1530,7 @@ compare_names(const struct file_name *names, bool assume_exists, int phase) min_components = min_baselen = min_len = SIZE_MAX; for (i = INDEX_FILE; i >= OLD_FILE; i--) { path = names[i].path; - if (path == NULL || - (phase == 1 && !names[i].exists && !assume_exists) || - (phase == 2 && checked_in(path) == NULL)) + if (path == NULL || (!names[i].exists && !assume_exists)) continue; if ((tmp = num_components(path)) > min_components) continue; @@ -1572,17 +1561,11 @@ best_name(const struct file_name *names, bool assume_exists) { char *best; - best = compare_names(names, assume_exists, 1); - if (best == NULL) { - best = compare_names(names, assume_exists, 2); - /* - * Still no match? Check to see if the diff could be creating - * a new file. - */ - if (best == NULL && ok_to_create_file && - names[NEW_FILE].path != NULL) - best = names[NEW_FILE].path; - } + best = compare_names(names, assume_exists); + + /* No match? Check to see if the diff could be creating a new file. */ + if (best == NULL && ok_to_create_file) + best = names[NEW_FILE].path; return best ? xstrdup(best) : NULL; } diff --git a/usr.bin/patch/util.c b/usr.bin/patch/util.c index 1859e17..39a2eed 100644 --- a/usr.bin/patch/util.c +++ b/usr.bin/patch/util.c @@ -399,36 +399,10 @@ fetchname(const char *at, bool *exists, int strip_leading) return name; } -/* - * Takes the name returned by fetchname and looks in RCS/SCCS directories - * for a checked in version. - */ -char * -checked_in(char *file) -{ - char *filebase, *filedir, tmpbuf[PATH_MAX]; - struct stat filestat; - - filebase = basename(file); - filedir = dirname(file); - -#define try(f, a1, a2, a3) \ -(snprintf(tmpbuf, sizeof tmpbuf, f, a1, a2, a3), stat(tmpbuf, &filestat) == 0) - - if (try("%s/RCS/%s%s", filedir, filebase, RCSSUFFIX) || - try("%s/RCS/%s%s", filedir, filebase, "") || - try("%s/%s%s", filedir, filebase, RCSSUFFIX) || - try("%s/SCCS/%s%s", filedir, SCCSPREFIX, filebase) || - try("%s/%s%s", filedir, SCCSPREFIX, filebase)) - return file; - - return NULL; -} - void version(void) { - printf("patch 2.0-12u10 FreeBSD\n"); + printf("patch 2.0-12u11 FreeBSD\n"); my_exit(EXIT_SUCCESS); } diff --git a/usr.bin/patch/util.h b/usr.bin/patch/util.h index ff2feab..2ef6b2f 100644 --- a/usr.bin/patch/util.h +++ b/usr.bin/patch/util.h @@ -28,7 +28,6 @@ */ char *fetchname(const char *, bool *, int); -char *checked_in(char *); int backup_file(const char *); int move_file(const char *, const char *); int copy_file(const char *, const char *); diff --git a/usr.bin/truss/syscall.h b/usr.bin/truss/syscall.h index a2fa826..db79fef 100644 --- a/usr.bin/truss/syscall.h +++ b/usr.bin/truss/syscall.h @@ -41,7 +41,8 @@ enum Argtype { None = 1, Hex, Octal, Int, LongHex, Name, Ptr, Stat, Ioctl, Quad, Sigset, Sigprocmask, Kevent, Sockdomain, Socktype, Open, Fcntlflag, Rusage, BinString, Shutdown, Resource, Rlimit, Timeval2, Pathconf, Rforkflags, ExitStatus, Waitoptions, Idtype, Procctl, - LinuxSockArgs, Umtxop, Atfd, Atflags, Timespec2, Accessmode }; + LinuxSockArgs, Umtxop, Atfd, Atflags, Timespec2, Accessmode, Long, + Sysarch }; #define ARG_MASK 0xff #define OUT 0x100 diff --git a/usr.bin/truss/syscalls.c b/usr.bin/truss/syscalls.c index 7ecb38b..3132f21 100644 --- a/usr.bin/truss/syscalls.c +++ b/usr.bin/truss/syscalls.c @@ -56,6 +56,7 @@ static const char rcsid[] = #include <sys/event.h> #include <sys/stat.h> #include <sys/resource.h> +#include <machine/sysarch.h> #include <ctype.h> #include <err.h> @@ -113,6 +114,7 @@ static struct syscall syscalls[] = { { .name = "getsid", .ret_type = 1, .nargs = 1, .args = { { Int, 0 } } }, { .name = "getuid", .ret_type = 1, .nargs = 0 }, + { .name = "issetugid", .ret_type = 1, .nargs = 0 }, { .name = "readlink", .ret_type = 1, .nargs = 3, .args = { { Name, 0 }, { Readlinkres | OUT, 1 }, { Int, 2 } } }, { .name = "readlinkat", .ret_type = 1, .nargs = 4, @@ -280,8 +282,22 @@ static struct syscall syscalls[] = { { .name = "kevent", .ret_type = 0, .nargs = 6, .args = { { Int, 0 }, { Kevent, 1 }, { Int, 2 }, { Kevent | OUT, 3 }, { Int, 4 }, { Timespec, 5 } } }, + { .name = "sigpending", .ret_type = 0, .nargs = 1, + .args = { { Sigset | OUT, 0 } } }, { .name = "sigprocmask", .ret_type = 0, .nargs = 3, .args = { { Sigprocmask, 0 }, { Sigset, 1 }, { Sigset | OUT, 2 } } }, + { .name = "sigqueue", .ret_type = 0, .nargs = 3, + .args = { { Int, 0 }, { Signal, 1 }, { LongHex, 2 } } }, + { .name = "sigreturn", .ret_type = 0, .nargs = 1, + .args = { { Ptr, 0 } } }, + { .name = "sigsuspend", .ret_type = 0, .nargs = 1, + .args = { { Sigset | IN, 0 } } }, + { .name = "sigtimedwait", .ret_type = 1, .nargs = 3, + .args = { { Sigset | IN, 0 }, { Ptr, 1 }, { Timespec | IN, 2 } } }, + { .name = "sigwait", .ret_type = 1, .nargs = 2, + .args = { { Sigset | IN, 0 }, { Ptr, 1 } } }, + { .name = "sigwaitinfo", .ret_type = 1, .nargs = 2, + .args = { { Sigset | IN, 0 }, { Ptr, 1 } } }, { .name = "unmount", .ret_type = 1, .nargs = 2, .args = { { Name, 0 }, { Int, 1 } } }, { .name = "socket", .ret_type = 1, .nargs = 3, @@ -317,6 +333,8 @@ static struct syscall syscalls[] = { .args = { { Name | IN, 0 }, { Pathconf, 1 } } }, { .name = "pipe", .ret_type = 1, .nargs = 1, .args = { { Ptr, 0 } } }, + { .name = "pipe2", .ret_type = 1, .nargs = 2, + .args = { { Ptr, 0 }, { Open, 1 } } }, { .name = "truncate", .ret_type = 1, .nargs = 3, .args = { { Name | IN, 0 }, { Int | IN, 1 }, { Quad | IN, 2 } } }, { .name = "ftruncate", .ret_type = 1, .nargs = 3, @@ -345,9 +363,15 @@ static struct syscall syscalls[] = { { Waitoptions, 3 }, { Rusage | OUT, 4 }, { Ptr, 5 } } }, { .name = "procctl", .ret_type = 1, .nargs = 4, .args = { { Idtype, 0 }, { Int, 1 }, { Procctl, 2 }, { Ptr, 3 } } }, + { .name = "sysarch", .ret_type = 1, .nargs = 2, + .args = { { Sysarch, 0 }, { Ptr, 1 } } }, { .name = "_umtx_op", .ret_type = 1, .nargs = 5, .args = { { Ptr, 0 }, { Umtxop, 1 }, { LongHex, 2 }, { Ptr, 3 }, { Ptr, 4 } } }, + { .name = "thr_kill", .ret_type = 0, .nargs = 2, + .args = { { Long, 0 }, { Signal, 1 } } }, + { .name = "thr_self", .ret_type = 0, .nargs = 1, + .args = { { Ptr, 0 } } }, { .name = 0 }, }; @@ -511,6 +535,26 @@ static struct xlat access_modes[] = { X(R_OK) X(W_OK) X(X_OK) XEND }; +static struct xlat sysarch_ops[] = { +#if defined(__i386__) || defined(__amd64__) + X(I386_GET_LDT) X(I386_SET_LDT) X(I386_GET_IOPERM) X(I386_SET_IOPERM) + X(I386_VM86) X(I386_GET_FSBASE) X(I386_SET_FSBASE) X(I386_GET_GSBASE) + X(I386_SET_GSBASE) X(I386_GET_XFPUSTATE) X(AMD64_GET_FSBASE) + X(AMD64_SET_FSBASE) X(AMD64_GET_GSBASE) X(AMD64_SET_GSBASE) + X(AMD64_GET_XFPUSTATE) +#endif + XEND +}; + +static struct xlat linux_socketcall_ops[] = { + X(LINUX_SOCKET) X(LINUX_BIND) X(LINUX_CONNECT) X(LINUX_LISTEN) + X(LINUX_ACCEPT) X(LINUX_GETSOCKNAME) X(LINUX_GETPEERNAME) + X(LINUX_SOCKETPAIR) X(LINUX_SEND) X(LINUX_RECV) X(LINUX_SENDTO) + X(LINUX_RECVFROM) X(LINUX_SHUTDOWN) X(LINUX_SETSOCKOPT) + X(LINUX_GETSOCKOPT) X(LINUX_SENDMSG) X(LINUX_RECVMSG) + XEND +}; + #undef X #undef XEND @@ -721,7 +765,10 @@ print_arg(struct syscall_args *sc, unsigned long *args, long retval, break; case LongHex: asprintf(&tmp, "0x%lx", args[sc->offset]); - break; + break; + case Long: + asprintf(&tmp, "%ld", args[sc->offset]); + break; case Name: { /* NULL-terminated string. */ char *tmp2; @@ -925,71 +972,12 @@ print_arg(struct syscall_args *sc, unsigned long *args, long retval, { struct linux_socketcall_args largs; if (get_struct(pid, (void *)args[sc->offset], (void *)&largs, - sizeof(largs)) == -1) { - err(1, "get_struct %p", (void *)args[sc->offset]); - } - const char *what; - char buf[30]; - - switch (largs.what) { - case LINUX_SOCKET: - what = "LINUX_SOCKET"; - break; - case LINUX_BIND: - what = "LINUX_BIND"; - break; - case LINUX_CONNECT: - what = "LINUX_CONNECT"; - break; - case LINUX_LISTEN: - what = "LINUX_LISTEN"; - break; - case LINUX_ACCEPT: - what = "LINUX_ACCEPT"; - break; - case LINUX_GETSOCKNAME: - what = "LINUX_GETSOCKNAME"; - break; - case LINUX_GETPEERNAME: - what = "LINUX_GETPEERNAME"; - break; - case LINUX_SOCKETPAIR: - what = "LINUX_SOCKETPAIR"; - break; - case LINUX_SEND: - what = "LINUX_SEND"; - break; - case LINUX_RECV: - what = "LINUX_RECV"; - break; - case LINUX_SENDTO: - what = "LINUX_SENDTO"; - break; - case LINUX_RECVFROM: - what = "LINUX_RECVFROM"; - break; - case LINUX_SHUTDOWN: - what = "LINUX_SHUTDOWN"; - break; - case LINUX_SETSOCKOPT: - what = "LINUX_SETSOCKOPT"; - break; - case LINUX_GETSOCKOPT: - what = "LINUX_GETSOCKOPT"; - break; - case LINUX_SENDMSG: - what = "LINUX_SENDMSG"; - break; - case LINUX_RECVMSG: - what = "LINUX_RECVMSG"; - break; - default: - sprintf(buf, "%d", largs.what); - what = buf; - break; - } - asprintf(&tmp, "(0x%lx)%s, 0x%lx", args[sc->offset], what, - (long unsigned int)largs.args); + sizeof(largs)) != -1) + asprintf(&tmp, "{ %s, 0x%lx }", + lookup(linux_socketcall_ops, largs.what, 10), + (long unsigned int)largs.args); + else + asprintf(&tmp, "0x%lx", args[sc->offset]); break; } case Pollfd: { @@ -1089,8 +1077,10 @@ print_arg(struct syscall_args *sc, unsigned long *args, long retval, asprintf(&tmp, "0x%lx", args[sc->offset]); break; } - tmp = malloc(sys_nsig * 8); /* 7 bytes avg per signal name */ + tmp = malloc(sys_nsig * 8 + 2); /* 7 bytes avg per signal name */ used = 0; + tmp[used++] = '{'; + tmp[used++] = ' '; for (i = 1; i < sys_nsig; i++) { if (sigismember(&ss, i)) { signame = strsig(i); @@ -1098,10 +1088,11 @@ print_arg(struct syscall_args *sc, unsigned long *args, long retval, free(signame); } } - if (used) - tmp[used-1] = 0; - else - strcpy(tmp, "0x0"); + if (tmp[used - 1] == '|') + used--; + tmp[used++] = ' '; + tmp[used++] = '}'; + tmp[used++] = '\0'; break; } case Sigprocmask: { @@ -1188,9 +1179,22 @@ print_arg(struct syscall_args *sc, unsigned long *args, long retval, case Sockdomain: tmp = strdup(xlookup(sockdomain_arg, args[sc->offset])); break; - case Socktype: - tmp = strdup(xlookup(socktype_arg, args[sc->offset])); + case Socktype: { + FILE *fp; + size_t len; + int type, flags; + + flags = args[sc->offset] & (SOCK_CLOEXEC | SOCK_NONBLOCK); + type = args[sc->offset] & ~flags; + fp = open_memstream(&tmp, &len); + fputs(xlookup(socktype_arg, type), fp); + if (flags & SOCK_CLOEXEC) + fprintf(fp, "|SOCK_CLOEXEC"); + if (flags & SOCK_NONBLOCK) + fprintf(fp, "|SOCK_NONBLOCK"); + fclose(fp); break; + } case Shutdown: tmp = strdup(xlookup(shutdown_arg, args[sc->offset])); break; @@ -1447,6 +1451,9 @@ print_arg(struct syscall_args *sc, unsigned long *args, long retval, tmp = strdup(xlookup_bits(access_modes, args[sc->offset])); break; + case Sysarch: + tmp = strdup(xlookup(sysarch_ops, args[sc->offset])); + break; default: errx(1, "Invalid argument type %d\n", sc->type & ARG_MASK); } diff --git a/usr.bin/ypcat/ypcat.c b/usr.bin/ypcat/ypcat.c index aad07cc..b729e36 100644 --- a/usr.bin/ypcat/ypcat.c +++ b/usr.bin/ypcat/ypcat.c @@ -96,7 +96,7 @@ main(int argc, char *argv[]) while ((c = getopt(argc, argv, "xd:kt")) != -1) switch (c) { case 'x': - for (i=0; i<sizeof ypaliases/sizeof ypaliases[0]; i++) + for (i = 0; i < nitems(ypaliases); i++) printf("Use \"%s\" for \"%s\"\n", ypaliases[i].alias, ypaliases[i].name); exit(0); @@ -120,8 +120,8 @@ main(int argc, char *argv[]) yp_get_default_domain(&domain); inmap = argv[optind]; - if (!notrans) { - for (i=0; i<sizeof ypaliases/sizeof ypaliases[0]; i++) + if (notrans == 0) { + for (i = 0; i < nitems(ypaliases); i++) if (strcmp(inmap, ypaliases[i].alias) == 0) inmap = ypaliases[i].name; } diff --git a/usr.bin/ypwhich/ypwhich.c b/usr.bin/ypwhich/ypwhich.c index 14fc1b3..4e2c3a0 100644 --- a/usr.bin/ypwhich/ypwhich.c +++ b/usr.bin/ypwhich/ypwhich.c @@ -151,7 +151,7 @@ main(int argc, char *argv[]) while ((c = getopt(argc, argv, "xd:mt")) != -1) switch (c) { case 'x': - for (i = 0; i<sizeof ypaliases/sizeof ypaliases[0]; i++) + for (i = 0; i < nitems(ypaliases); i++) printf("\"%s\" is an alias for \"%s\"\n", ypaliases[i].alias, ypaliases[i].name); @@ -169,7 +169,7 @@ main(int argc, char *argv[]) usage(); } - if (!domnam) + if (domnam == NULL) yp_get_default_domain(&domnam); if (mode == 0) { @@ -206,9 +206,11 @@ main(int argc, char *argv[]) if (argv[optind]) { map = argv[optind]; - for (i = 0; (!notrans) && i<sizeof ypaliases/sizeof ypaliases[0]; i++) - if (strcmp(map, ypaliases[i].alias) == 0) - map = ypaliases[i].name; + if (notrans == 0) { + for (i = 0; i < nitems(ypaliases); i++) + if (strcmp(map, ypaliases[i].alias) == 0) + map = ypaliases[i].name; + } r = yp_master(domnam, map, &master); switch (r) { case 0: diff --git a/usr.sbin/bhyve/pci_ahci.c b/usr.sbin/bhyve/pci_ahci.c index 35a0859..13ab7c1 100644 --- a/usr.sbin/bhyve/pci_ahci.c +++ b/usr.sbin/bhyve/pci_ahci.c @@ -1687,11 +1687,17 @@ ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) ahci_write_fis_d2h(p, slot, cfis, (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); break; + case ATA_CHECK_POWER_MODE: + cfis[12] = 0xff; /* always on */ + ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); + break; case ATA_STANDBY_CMD: case ATA_STANDBY_IMMEDIATE: case ATA_IDLE_CMD: case ATA_IDLE_IMMEDIATE: case ATA_SLEEP: + case ATA_READ_VERIFY: + case ATA_READ_VERIFY48: ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); break; case ATA_ATAPI_IDENTIFY: diff --git a/usr.sbin/ctladm/ctladm.8 b/usr.sbin/ctladm/ctladm.8 index 114b5fe..2612056 100644 --- a/usr.sbin/ctladm/ctladm.8 +++ b/usr.sbin/ctladm/ctladm.8 @@ -83,12 +83,6 @@ .Op Fl c Ar cdbsize .Op Fl N .Nm -.Ic bbrread -.Aq target:lun -.Op general options -.Aq Fl -l Ar lba -.Aq Fl -d Ar datalen -.Nm .Ic readcap .Aq target:lun .Op general options @@ -129,10 +123,6 @@ .Ic startup .Op general options .Nm -.Ic hardstop -.Nm -.Ic hardstart -.Nm .Ic lunlist .Nm .Ic delay @@ -364,34 +354,6 @@ to the kernel when doing a write, just execute the command without copying data. This is to be used for performance testing. .El -.It Ic bbrread -Issue a SCSI READ command to the logical device to potentially force a bad -block on a disk in the RAID set to be reconstructed from the other disks in -the array. This command should only be used on an array that is in the -normal state. If used on a critical array, it could cause the array to go -offline if the bad block to be remapped is on one of the disks that is -still active in the array. -.Pp -The data for this particular command will be discarded, and not returned to -the user. -.Pp -In order to determine which LUN to read from, the user should first -determine which LUN the disk with a bad block belongs to. Then he should -map the bad disk block back to the logical block address for the array in -order to determine which LBA to pass in to the -.Ic bbrread -command. -.Pp -This command is primarily intended for testing. In practice, bad block -remapping will generally be triggered by the in-kernel Disk Aerobics and -Disk Scrubbing code. -.Bl -tag -width 10n -.It Fl l Ar lba -Specify the starting Logical Block Address. -.It Fl d Ar datalen -Specify the amount of data in bytes to read from the LUN. This must be a -multiple of the LUN blocksize. -.El .It Ic readcap Send the .Tn SCSI @@ -545,22 +507,6 @@ START STOP UNIT command with the start bit set and the on/offline bit set to all direct access LUNs. This will mark all direct access LUNs "online" again. It will not cause any LUNs to start up. A separate start command without the on/offline bit set is necessary for that. -.It Ic hardstop -Use the kernel facility for stopping all direct access LUNs and setting the -offline bit. Unlike the -.Ic shutdown -command above, this command allows shutting down LUNs with I/O active. It -will also issue a LUN reset to any reserved LUNs to break the reservation -so that the LUN can be stopped. -.Ic shutdown -command instead. -.It Ic hardstart -This command is functionally identical to the -.Ic startup -command described above. The primary difference is that the LUNs are -enumerated and commands sent by the in-kernel Front End Target Driver -instead of by -.Nm . .It Ic lunlist List all LUNs registered with CTL. Because this command uses the ioctl port, it will only work when the FETDs diff --git a/usr.sbin/ctladm/ctladm.c b/usr.sbin/ctladm/ctladm.c index 6baf0902..10d819f 100644 --- a/usr.sbin/ctladm/ctladm.c +++ b/usr.sbin/ctladm/ctladm.c @@ -66,7 +66,6 @@ __FBSDID("$FreeBSD$"); #include <cam/scsi/scsi_message.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_io.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_ioctl.h> #include <cam/ctl/ctl_backend_block.h> @@ -106,14 +105,11 @@ typedef enum { CTLADM_CMD_SHUTDOWN, CTLADM_CMD_STARTUP, CTLADM_CMD_LUNLIST, - CTLADM_CMD_HARDSTOP, - CTLADM_CMD_HARDSTART, CTLADM_CMD_DELAY, CTLADM_CMD_REALSYNC, CTLADM_CMD_SETSYNC, CTLADM_CMD_GETSYNC, CTLADM_CMD_ERR_INJECT, - CTLADM_CMD_BBRREAD, CTLADM_CMD_PRES_IN, CTLADM_CMD_PRES_OUT, CTLADM_CMD_INQ_VPD_DEVID, @@ -172,7 +168,6 @@ static const char startstop_opts[] = "io"; static struct ctladm_opts option_table[] = { {"adddev", CTLADM_CMD_ADDDEV, CTLADM_ARG_NONE, NULL}, - {"bbrread", CTLADM_CMD_BBRREAD, CTLADM_ARG_NEED_TL, "d:l:"}, {"create", CTLADM_CMD_CREATE, CTLADM_ARG_NONE, "b:B:d:l:o:s:S:t:"}, {"delay", CTLADM_CMD_DELAY, CTLADM_ARG_NEED_TL, "T:l:t:"}, {"devid", CTLADM_CMD_INQ_VPD_DEVID, CTLADM_ARG_NEED_TL, NULL}, @@ -180,8 +175,6 @@ static struct ctladm_opts option_table[] = { {"dumpooa", CTLADM_CMD_DUMPOOA, CTLADM_ARG_NONE, NULL}, {"dumpstructs", CTLADM_CMD_DUMPSTRUCTS, CTLADM_ARG_NONE, NULL}, {"getsync", CTLADM_CMD_GETSYNC, CTLADM_ARG_NEED_TL, NULL}, - {"hardstart", CTLADM_CMD_HARDSTART, CTLADM_ARG_NONE, NULL}, - {"hardstop", CTLADM_CMD_HARDSTOP, CTLADM_ARG_NONE, NULL}, {"help", CTLADM_CMD_HELP, CTLADM_ARG_NONE, NULL}, {"inject", CTLADM_CMD_ERR_INJECT, CTLADM_ARG_NEED_TL, "cd:i:p:r:s:"}, {"inquiry", CTLADM_CMD_INQUIRY, CTLADM_ARG_NEED_TL, NULL}, @@ -228,11 +221,6 @@ static int cctl_do_io(int fd, int retries, union ctl_io *io, const char *func); static int cctl_delay(int fd, int target, int lun, int argc, char **argv, char *combinedopt); static int cctl_lunlist(int fd); -static void cctl_cfi_mt_statusstr(cfi_mt_status status, char *str, int str_len); -static void cctl_cfi_bbr_statusstr(cfi_bbrread_status, char *str, int str_len); -static int cctl_hardstopstart(int fd, ctladm_cmdfunction command); -static int cctl_bbrread(int fd, int target, int lun, int iid, int argc, - char **argv, char *combinedopt); static int cctl_startup_shutdown(int fd, int target, int lun, int iid, ctladm_cmdfunction command); static int cctl_sync_cache(int fd, int target, int lun, int iid, int retries, @@ -1341,180 +1329,6 @@ bailout: return (retval); } -static void -cctl_cfi_mt_statusstr(cfi_mt_status status, char *str, int str_len) -{ - switch (status) { - case CFI_MT_PORT_OFFLINE: - snprintf(str, str_len, "Port Offline"); - break; - case CFI_MT_ERROR: - snprintf(str, str_len, "Error"); - break; - case CFI_MT_SUCCESS: - snprintf(str, str_len, "Success"); - break; - case CFI_MT_NONE: - snprintf(str, str_len, "None??"); - break; - default: - snprintf(str, str_len, "Unknown status: %d", status); - break; - } -} - -static void -cctl_cfi_bbr_statusstr(cfi_bbrread_status status, char *str, int str_len) -{ - switch (status) { - case CFI_BBR_SUCCESS: - snprintf(str, str_len, "Success"); - break; - case CFI_BBR_LUN_UNCONFIG: - snprintf(str, str_len, "LUN not configured"); - break; - case CFI_BBR_NO_LUN: - snprintf(str, str_len, "LUN does not exist"); - break; - case CFI_BBR_NO_MEM: - snprintf(str, str_len, "Memory allocation error"); - break; - case CFI_BBR_BAD_LEN: - snprintf(str, str_len, "Length is not a multiple of blocksize"); - break; - case CFI_BBR_RESERV_CONFLICT: - snprintf(str, str_len, "Reservation conflict"); - break; - case CFI_BBR_LUN_STOPPED: - snprintf(str, str_len, "LUN is powered off"); - break; - case CFI_BBR_LUN_OFFLINE_CTL: - snprintf(str, str_len, "LUN is offline"); - break; - case CFI_BBR_LUN_OFFLINE_RC: - snprintf(str, str_len, "RAIDCore array is offline (double " - "failure?)"); - break; - case CFI_BBR_SCSI_ERROR: - snprintf(str, str_len, "SCSI Error"); - break; - case CFI_BBR_ERROR: - snprintf(str, str_len, "Error"); - break; - default: - snprintf(str, str_len, "Unknown status: %d", status); - break; - } -} - -static int -cctl_hardstopstart(int fd, ctladm_cmdfunction command) -{ - struct ctl_hard_startstop_info hs_info; - char error_str[256]; - int do_start; - int retval; - - retval = 0; - - if (command == CTLADM_CMD_HARDSTART) - do_start = 1; - else - do_start = 0; - - if (ioctl(fd, (do_start == 1) ? CTL_HARD_START : CTL_HARD_STOP, - &hs_info) == -1) { - warn("%s: CTL_HARD_%s ioctl failed", __func__, - (do_start == 1) ? "START" : "STOP"); - retval = 1; - goto bailout; - } - - fprintf(stdout, "Hard %s Status: ", (command == CTLADM_CMD_HARDSTOP) ? - "Stop" : "Start"); - cctl_cfi_mt_statusstr(hs_info.status, error_str, sizeof(error_str)); - fprintf(stdout, "%s\n", error_str); - fprintf(stdout, "Total LUNs: %d\n", hs_info.total_luns); - fprintf(stdout, "LUNs complete: %d\n", hs_info.luns_complete); - fprintf(stdout, "LUNs failed: %d\n", hs_info.luns_failed); - -bailout: - return (retval); -} - -static int -cctl_bbrread(int fd, int target __unused, int lun, int iid __unused, - int argc, char **argv, char *combinedopt) -{ - struct ctl_bbrread_info bbr_info; - char error_str[256]; - int datalen = -1; - uint64_t lba = 0; - int lba_set = 0; - int retval; - int c; - - retval = 0; - - while ((c = getopt(argc, argv, combinedopt)) != -1) { - switch (c) { - case 'd': - datalen = strtoul(optarg, NULL, 0); - break; - case 'l': - lba = strtoull(optarg, NULL, 0); - lba_set = 1; - break; - default: - break; - } - } - - if (lba_set == 0) { - warnx("%s: you must specify an LBA with -l", __func__); - retval = 1; - goto bailout; - } - - if (datalen == -1) { - warnx("%s: you must specify a length with -d", __func__); - retval = 1; - goto bailout; - } - - bbr_info.lun_num = lun; - bbr_info.lba = lba; - /* - * XXX KDM get the blocksize first?? - */ - if ((datalen % 512) != 0) { - warnx("%s: data length %d is not a multiple of 512 bytes", - __func__, datalen); - retval = 1; - goto bailout; - } - bbr_info.len = datalen; - - if (ioctl(fd, CTL_BBRREAD, &bbr_info) == -1) { - warn("%s: CTL_BBRREAD ioctl failed", __func__); - retval = 1; - goto bailout; - } - cctl_cfi_mt_statusstr(bbr_info.status, error_str, sizeof(error_str)); - fprintf(stdout, "BBR Read Overall Status: %s\n", error_str); - cctl_cfi_bbr_statusstr(bbr_info.bbr_status, error_str, - sizeof(error_str)); - fprintf(stdout, "BBR Read Status: %s\n", error_str); - /* - * XXX KDM should we bother printing out SCSI status if we get - * CFI_BBR_SCSI_ERROR back? - * - * Return non-zero if this fails? - */ -bailout: - return (retval); -} - static int cctl_startup_shutdown(int fd, int target, int lun, int iid, ctladm_cmdfunction command) @@ -4499,11 +4313,8 @@ usage(int error) " ctladm devlist [-b backend] [-v] [-x]\n" " ctladm shutdown\n" " ctladm startup\n" -" ctladm hardstop\n" -" ctladm hardstart\n" " ctladm lunlist\n" " ctladm lunmap -p targ_port [-l pLUN] [-L cLUN]\n" -" ctladm bbrread [dev_id] <-l lba> <-d datalen>\n" " ctladm delay [dev_id] <-l datamove|done> [-T oneshot|cont]\n" " [-t secs]\n" " ctladm realsync <on|off|query>\n" @@ -4610,10 +4421,7 @@ usage(int error) "lunmap options:\n" "-p targ_port : specify target port number\n" "-L pLUN : specify port-visible LUN\n" -"-L cLUN : specify CTL LUN\n" -"bbrread options:\n" -"-l lba : starting LBA\n" -"-d datalen : length, in bytes, to read\n", +"-L cLUN : specify CTL LUN\n", CTL_DEFAULT_DEV); } @@ -4864,14 +4672,6 @@ main(int argc, char **argv) retval = cctl_startup_shutdown(fd, target, lun, initid, command); break; - case CTLADM_CMD_HARDSTOP: - case CTLADM_CMD_HARDSTART: - retval = cctl_hardstopstart(fd, command); - break; - case CTLADM_CMD_BBRREAD: - retval = cctl_bbrread(fd, target, lun, initid, argc, argv, - combinedopt); - break; case CTLADM_CMD_LUNLIST: retval = cctl_lunlist(fd); break; diff --git a/usr.sbin/ctld/kernel.c b/usr.sbin/ctld/kernel.c index 6cccdab..c523905 100644 --- a/usr.sbin/ctld/kernel.c +++ b/usr.sbin/ctld/kernel.c @@ -60,7 +60,6 @@ __FBSDID("$FreeBSD$"); #include <cam/scsi/scsi_message.h> #include <cam/ctl/ctl.h> #include <cam/ctl/ctl_io.h> -#include <cam/ctl/ctl_frontend_internal.h> #include <cam/ctl/ctl_backend.h> #include <cam/ctl/ctl_ioctl.h> #include <cam/ctl/ctl_backend_block.h> diff --git a/usr.sbin/pw/pw_user.c b/usr.sbin/pw/pw_user.c index d9bce87..5ccbd53 100644 --- a/usr.sbin/pw/pw_user.c +++ b/usr.sbin/pw/pw_user.c @@ -1645,6 +1645,8 @@ pw_user_mod(int argc, char **argv, char *arg1) if (lc == NULL || login_setcryptfmt(lc, "sha512", NULL) == NULL) warn("setting crypt(3) format"); login_close(lc); + cnf->default_password = boolean_val(passwd, + cnf->default_password); pwd->pw_passwd = pw_password(cnf, pwd->pw_name, dryrun); edited = true; } diff --git a/usr.sbin/pw/tests/pw_useradd.sh b/usr.sbin/pw/tests/pw_useradd.sh index 2ac31c9..f126bf0 100755 --- a/usr.sbin/pw/tests/pw_useradd.sh +++ b/usr.sbin/pw/tests/pw_useradd.sh @@ -314,6 +314,19 @@ user_add_already_exists_body() { ${PW} useradd foo } +atf_test_case user_add_w_yes +user_add_w_yes_body() { + populate_etc_skel + atf_check -s exit:0 ${PW} useradd foo -w yes + atf_check -s exit:0 \ + -o match:'^foo:\$.*' \ + grep "^foo" ${HOME}/master.passwd + atf_check -s exit:0 ${PW} usermod foo -w yes + atf_check -s exit:0 \ + -o match:'^foo:\$.*' \ + grep "^foo" ${HOME}/master.passwd +} + atf_init_test_cases() { atf_add_test_case user_add atf_add_test_case user_add_noupdate @@ -341,4 +354,5 @@ atf_init_test_cases() { atf_add_test_case user_add_uid_too_large atf_add_test_case user_add_bad_shell atf_add_test_case user_add_already_exists + atf_add_test_case user_add_w_yes } diff --git a/usr.sbin/wlandebug/wlandebug.8 b/usr.sbin/wlandebug/wlandebug.8 index 8c8122c..0640eff 100644 --- a/usr.sbin/wlandebug/wlandebug.8 +++ b/usr.sbin/wlandebug/wlandebug.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd July 17, 2009 +.Dd August 17, 2015 .Dt WLANDEBUG 8 .Os .Sh NAME @@ -45,7 +45,7 @@ Running .Nm without any options will display the current messages enabled for the specified network interface -(by default, ``ath0'). +(by default, ``wlan0'). The default debugging level for new interfaces can be set by specifying the .Fl d @@ -148,7 +148,7 @@ trace transmit rate control operation. .Sh EXAMPLES The following might be used to debug basic station mode operation: .Pp -.Dl "wlandebug -i ral0 scan+auth+assoc" +.Dl "wlandebug -i wlan1 scan+auth+assoc" .Pp it enables debug messages while scanning, authenticating to an access point, and associating to an access point. |
