diff options
231 files changed, 10406 insertions, 8386 deletions
diff --git a/Makefile.inc1 b/Makefile.inc1 index ca84c60..f733032 100644 --- a/Makefile.inc1 +++ b/Makefile.inc1 @@ -82,7 +82,7 @@ MK_CROSS_COMPILER= no # Check if there is a local compiler that can satisfy as an external compiler. .if ${MK_SYSTEM_COMPILER} == "yes" && ${MK_CROSS_COMPILER} == "yes" && \ (${MK_CLANG_BOOTSTRAP} == "yes" || ${MK_GCC_BOOTSTRAP} == "yes") && \ - !make(showconfig) + !make(showconfig) && !make(native-xtools) && !make(xdev*) # Which compiler is expected to be used? .if ${MK_CLANG_BOOTSTRAP} == "yes" _expected_compiler_type= clang diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc index d3a16389..b56eb86 100644 --- a/ObsoleteFiles.inc +++ b/ObsoleteFiles.inc @@ -38,6 +38,105 @@ # xargs -n1 | sort | uniq -d; # done +# 20160703: POSIXify locales with variants +OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hant_TW.UTF-8 +OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hant_TW.Big5 +OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hant_HK.UTF-8 +OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hans_CN.eucCN +OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hans_CN.UTF-8 +OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hans_CN.GBK +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hans_CN.GB2312 +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_COLLATE +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_CTYPE +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_MESSAGES +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_MONETARY +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_NUMERIC +OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_TIME +OLD_DIRS+=usr/share/locale/zh_Hans_CN.GB18030 +OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_TIME +OLD_DIRS+=usr/share/locale/sr_Latn_RS.UTF-8 +OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_TIME +OLD_DIRS+=usr/share/locale/sr_Latn_RS.ISO8859-2 +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_TIME +OLD_DIRS+=usr/share/locale/sr_Cyrl_RS.UTF-8 +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_TIME +OLD_DIRS+=usr/share/locale/sr_Cyrl_RS.ISO8859-5 +OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_TIME +OLD_DIRS+=usr/share/locale/mn_Cyrl_MN.UTF-8 +OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_TIME +OLD_DIRS+=usr/share/locale/kk_Cyrl_KZ.UTF-8 # 20160608: removed pam_verbose_error OLD_LIBS+=usr/lib/libpam.so.5 OLD_LIBS+=usr/lib/pam_chroot.so.5 @@ -398,13 +497,6 @@ OLD_FILES+=usr/share/locale/lt_LT.ISO8859-4/LC_MONETARY OLD_FILES+=usr/share/locale/lt_LT.ISO8859-4/LC_CTYPE OLD_FILES+=usr/share/locale/lt_LT.ISO8859-4/LC_NUMERIC OLD_DIRS+=usr/share/locale/lt_LT.ISO8859-4 -OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_TIME -OLD_DIRS+=usr/share/locale/mn_MN.UTF-8 OLD_FILES+=usr/share/locale/no_NO.ISO8859-1/LC_COLLATE OLD_FILES+=usr/share/locale/no_NO.ISO8859-1/LC_CTYPE OLD_FILES+=usr/share/locale/no_NO.ISO8859-1/LC_MESSAGES @@ -7922,7 +8014,9 @@ OLD_FILES+=usr/share/man/man5/usbd.conf.5.gz .if ${TARGET_ARCH} != "i386" && ${TARGET_ARCH} != "amd64" OLD_FILES+=usr/share/man/man8/boot_i386.8.gz .endif -.if ${TARGET_ARCH} != "powerpc" && ${TARGET_ARCH} != "powerpc64" && ${TARGET_ARCH} != "sparc64" +.if ${TARGET_ARCH} != "aarch64" && ${TARGET_CPUARCH} != "arm" && \ + ${TARGET_ARCH} != "powerpc" && ${TARGET_ARCH} != "powerpc64" && \ + ${TARGET_ARCH} != "sparc64" OLD_FILES+=usr/share/man/man8/ofwdump.8.gz .endif OLD_FILES+=usr/share/man/man8/mount_reiserfs.8.gz @@ -16,21 +16,6 @@ from older versions of FreeBSD, try WITHOUT_CLANG and WITH_GCC to bootstrap to the tip of head, and then rebuild without this option. The bootstrap process from older version of current across the gcc/clang cutover is a bit fragile. -NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: - FreeBSD 11.x has many debugging features turned on, in both the kernel - and userland. These features attempt to detect incorrect use of - system primitives, and encourage loud failure through extra sanity - checking and fail stop semantics. They also substantially impact - system performance. If you want to do performance measurement, - benchmarking, and optimization, you'll want to turn them off. This - includes various WITNESS- related kernel options, INVARIANTS, malloc - debugging flags in userland, and various verbose features in the - kernel. Many developers choose to disable these features on build - machines to maximize performance. (To completely disable malloc - debugging, define MALLOC_PRODUCTION in /etc/make.conf, or to merely - disable the most expensive debugging functionality run - "ln -s 'abort:false,junk:false' /etc/malloc.conf".) - 20160622: The libc stub for the pipe(2) system call has been replaced with a wrapper which calls the pipe2(2) system call and the pipe(2) is now diff --git a/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h b/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h index c58a8f3..e2ddfd8 100644 --- a/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h +++ b/contrib/jemalloc/include/jemalloc/jemalloc_FreeBSD.h @@ -5,6 +5,9 @@ #undef JEMALLOC_OVERRIDE_VALLOC #ifndef MALLOC_PRODUCTION +#define MALLOC_PRODUCTION +#endif +#ifndef MALLOC_PRODUCTION #define JEMALLOC_DEBUG #endif diff --git a/contrib/libxo/configure.ac b/contrib/libxo/configure.ac index 0ff0a64..b47dedb 100644 --- a/contrib/libxo/configure.ac +++ b/contrib/libxo/configure.ac @@ -12,7 +12,7 @@ # AC_PREREQ(2.2) -AC_INIT([libxo], [0.6.2], [phil@juniper.net]) +AC_INIT([libxo], [0.6.3], [phil@juniper.net]) AM_INIT_AUTOMAKE([-Wall -Werror foreign -Wno-portability]) # Support silent build rules. Requires at least automake-1.11. diff --git a/contrib/libxo/tests/core/test_02.c b/contrib/libxo/tests/core/test_02.c index 9a02680..cf98d34 100644 --- a/contrib/libxo/tests/core/test_02.c +++ b/contrib/libxo/tests/core/test_02.c @@ -70,7 +70,7 @@ main (int argc, char **argv) xo_emit(" {:lines/%7ju} {:words/%7ju} " "{:characters/%7ju} {d:filename/%s}\n", - 20, 30, 40, "file"); + (uintmax_t) 20, (uintmax_t) 30, (uintmax_t) 40, "file"); int i; for (i = 0; i < 5; i++) diff --git a/etc/defaults/rc.conf b/etc/defaults/rc.conf index 32e75f6..33a1ce4 100644 --- a/etc/defaults/rc.conf +++ b/etc/defaults/rc.conf @@ -609,7 +609,7 @@ lpd_flags="" # Flags to lpd (if enabled). nscd_enable="NO" # Run the nsswitch caching daemon. chkprintcap_enable="NO" # Run chkprintcap(8) before running lpd. chkprintcap_flags="-d" # Create missing directories by default. -dumpdev="AUTO" # Device to crashdump to (device name, AUTO, or NO). +dumpdev="NO" # Device to crashdump to (device name, AUTO, or NO). dumpdir="/var/crash" # Directory where crash dumps are to be stored savecore_enable="YES" # Extract core from dump devices if any savecore_flags="-m 10" # Used if dumpdev is enabled above, and present. diff --git a/etc/mtree/BSD.usr.dist b/etc/mtree/BSD.usr.dist index 973c7c3..9fef5de 100644 --- a/etc/mtree/BSD.usr.dist +++ b/etc/mtree/BSD.usr.dist @@ -769,7 +769,7 @@ .. ja_JP.eucJP .. - kk_Cyrl_KZ.UTF-8 + kk_KZ.UTF-8 .. ko_KR.CP949 .. @@ -785,7 +785,7 @@ .. lv_LV.UTF-8 .. - mn_Cyrl_MN.UTF-8 + mn_MN.UTF-8 .. nb_NO.ISO8859-1 .. @@ -851,13 +851,13 @@ .. sl_SI.UTF-8 .. - sr_Cyrl_RS.ISO8859-5 + sr_RS.ISO8859-5 .. - sr_Cyrl_RS.UTF-8 + sr_RS.UTF-8 .. - sr_Latn_RS.ISO8859-2 + sr_RS.ISO8859-2 .. - sr_Latn_RS.UTF-8 + sr_RS.UTF-8@latin .. sv_FI.ISO8859-1 .. @@ -893,22 +893,6 @@ .. zh_CN.UTF-8 .. - zh_Hans_CN.GB18030 - .. - zh_Hans_CN.GB2312 - .. - zh_Hans_CN.GBK - .. - zh_Hans_CN.UTF-8 - .. - zh_Hans_CN.eucCN - .. - zh_Hant_HK.UTF-8 - .. - zh_Hant_TW.Big5 - .. - zh_Hant_TW.UTF-8 - .. zh_HK.UTF-8 .. zh_TW.Big5 diff --git a/include/stdlib.h b/include/stdlib.h index 8a645c0..e0c20f7 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -172,8 +172,7 @@ char *realpath(const char * __restrict, char * __restrict); int rand_r(unsigned *); /* (TSF) */ #endif #if __POSIX_VISIBLE >= 200112 -int posix_memalign(void **, size_t, size_t) __nonnull(1) __alloc_align(2) - __alloc_size(3); /* (ADV) */ +int posix_memalign(void **, size_t, size_t) __nonnull(1); /* (ADV) */ int setenv(const char *, const char *, int); int unsetenv(const char *); #endif diff --git a/lib/libc/locale/collate.c b/lib/libc/locale/collate.c index 0236630..53b6c77 100644 --- a/lib/libc/locale/collate.c +++ b/lib/libc/locale/collate.c @@ -310,7 +310,7 @@ _collate_lookup(struct xlocale_collate *table, const wchar_t *t, int *len, if ((sptr = *state) != NULL) { *pri = *sptr; sptr++; - if ((sptr == *state) || (sptr == NULL)) + if ((sptr == *state) || (*sptr == 0)) *state = NULL; else *state = sptr; diff --git a/lib/libc/sys/fcntl.2 b/lib/libc/sys/fcntl.2 index 8e0ca73..cb91fba 100644 --- a/lib/libc/sys/fcntl.2 +++ b/lib/libc/sys/fcntl.2 @@ -28,7 +28,7 @@ .\" @(#)fcntl.2 8.2 (Berkeley) 1/12/94 .\" $FreeBSD$ .\" -.Dd February 8, 2013 +.Dd July 7, 2016 .Dt FCNTL 2 .Os .Sh NAME @@ -363,6 +363,13 @@ request fails or blocks respectively when another process has existing locks on bytes in the specified region and the type of any of those locks conflicts with the type specified in the request. .Pp +The queuing for +.Dv F_SETLKW +requests on local files is fair; +that is, while the thread is blocked, +subsequent requests conflicting with its requests will not be granted, +even if these requests do not conflict with existing locks. +.Pp This interface follows the completely stupid semantics of System V and .St -p1003.1-88 that require that all locks associated with a file for a given process are @@ -646,6 +653,20 @@ The .Dv F_DUP2FD constant is non portable. It is provided for compatibility with AIX and Solaris. +.Pp +Per +.St -susv4 , +a call with +.Dv F_SETLKW +should fail with +.Bq Er EINTR +after any caught signal +and should continue waiting during thread suspension such as a stop signal. +However, in this implementation a call with +.Dv F_SETLKW +is restarted after catching a signal with a +.Dv SA_RESTART +handler or a thread suspension such as a stop signal. .Sh HISTORY The .Fn fcntl diff --git a/libexec/rtld-elf/Makefile b/libexec/rtld-elf/Makefile index 6ae9130..de98da2 100644 --- a/libexec/rtld-elf/Makefile +++ b/libexec/rtld-elf/Makefile @@ -69,8 +69,6 @@ SYMBOL_MAPS= ${.CURDIR}/Symbol.map VERSION_MAP= Version.map LDFLAGS+= -Wl,--version-script=${VERSION_MAP} -${PROG}: ${VERSION_MAP} - .if exists(${.CURDIR}/${RTLD_ARCH}/Symbol.map) SYMBOL_MAPS+= ${.CURDIR}/${RTLD_ARCH}/Symbol.map .endif @@ -92,4 +90,5 @@ SUBDIR+= tests .endif .include <bsd.prog.mk> +${PROG_FULL}: ${VERSION_MAP} .include <bsd.symver.mk> diff --git a/release/arm64/make-memstick.sh b/release/arm64/make-memstick.sh index af73276..d47fad0 100755 --- a/release/arm64/make-memstick.sh +++ b/release/arm64/make-memstick.sh @@ -38,6 +38,6 @@ fi rm ${1}/etc/fstab rm ${1}/etc/rc.conf.local -mkimg -s mbr -p efi:=${1}/boot/boot1.efifat -p freebsd:=${2}.part -o ${2} +mkimg -s gpt -p efi:=${1}/boot/boot1.efifat -p freebsd:=${2}.part -o ${2} rm ${2}.part diff --git a/release/doc/en_US.ISO8859-1/relnotes/article.xml b/release/doc/en_US.ISO8859-1/relnotes/article.xml index b2cea9f..9cfed5a 100644 --- a/release/doc/en_US.ISO8859-1/relnotes/article.xml +++ b/release/doc/en_US.ISO8859-1/relnotes/article.xml @@ -182,12 +182,6 @@ <sect2 xml:id="userland-programs"> <title>Userland Application Changes</title> - <para revision="258838" contrib="sponsor" sponsor="&ff;, - &google;" sponsorurl="">The &man.casperd.8; daemon has been - added, which provides access to functionality that is not - available in the <quote>capability mode</quote> - sandbox.</para> - <para revision="260594">When unable to load a kernel module with &man.kldload.8;, a message informing to view output of &man.dmesg.8; is now printed, opposed to the previous output @@ -580,8 +574,8 @@ <para revision="288090">&man.jemalloc.3; has been updated to version 4.0.2.</para> - <para revision="298192">The &man.file.1; utility has been - updated to version 5.26.</para> + <para revision="302221">The &man.file.1; utility has been + updated to version 5.28.</para> <para revision="288303">The &man.nc.1; utility has been updated to the OpenBSD 5.8 version.</para> @@ -1413,6 +1407,9 @@ updated to support <literal>DSM TRIM</literal> commands for virtual <acronym>AHCI</acronym> disks.</para> + <para revision="302332">Native graphics support has been added to + the &man.bhyve.8; hypervisor.</para> + <para revision="281439" arch="arm">Support for the <application>QEMU</application> <literal>virt</literal> system has been added.</para> @@ -1516,6 +1513,9 @@ <para revision="299688" arch="arm">Support for the Allwinner H3 SoC has been added.</para> + <para revision="299786" arch="arm">Support for X-Powers AXP813 and + AXP818 power management integrated circuits have been added.</para> + <para revision="300777" arch="arm">Support for GPIO, Sensors and interrupts on AXP209 power management integrated circuits have been added.</para> @@ -1567,6 +1567,10 @@ &man.diskinfo.8; and the names of <filename>/dev/diskid/DISK-*</filename> device nodes, among other things.</para> + <para revision="300207" contrib="sponsor" sponsor="&spectralogic;"> + Support for managing Shingled Magnetic Recording (SMR) drives + has been added.</para> + </sect2> <sect2 xml:id="storage-net"> diff --git a/release/doc/share/xml/release.ent b/release/doc/share/xml/release.ent index f72b4d0..a21dfb6 100644 --- a/release/doc/share/xml/release.ent +++ b/release/doc/share/xml/release.ent @@ -6,23 +6,23 @@ <!-- Version of the OS we're describing. This needs to be updated with each new release. --> -<!ENTITY release.current "11.0-CURRENT"> +<!ENTITY release.current "11.0-STABLE"> <!-- The previous version used for comparison in the "What's New" section. For -CURRENT, we might point back to the last branchpoint. --> -<!ENTITY release.prev "10.0-RELEASE"> +<!ENTITY release.prev "10.3-RELEASE"> <!-- The previous stable release, useful for pointing user's at the release they SHOULD be running if they don't want the bleeding edge. --> -<!ENTITY release.prev.stable "9.3-RELEASE"> +<!ENTITY release.prev.stable "10.2-RELEASE"> <!-- The next version to be released, usually used for snapshots. --> -<!ENTITY release.next "11.0-RELEASE"> +<!ENTITY release.next "12.0-RELEASE"> <!-- The name of this branch. --> -<!ENTITY release.branch "11-CURRENT"> +<!ENTITY release.branch "12-CURRENT"> <!-- The URL for obtaining this version of FreeBSD. --> <!ENTITY release.url "https://www.FreeBSD.org/snapshots/"> @@ -31,16 +31,16 @@ <!ENTITY security.url "https://www.FreeBSD.org/security/advisories"> <!-- The recommended mailing list to track. --> -<!ENTITY release.maillist "current"> +<!ENTITY release.maillist "stable"> <!-- The type of release (usually this will be either "snapshot" or "release" --> <!-- WARNING: Do not forget to also change the release type in doc.relnotes.mk when updating this --> <!ENTITY release.type "snapshot"> -<!ENTITY % release.type.current "INCLUDE"> +<!ENTITY % release.type.current "IGNORE"> <!ENTITY % release.type.snapshot "IGNORE"> -<!ENTITY % release.type.release "IGNORE"> +<!ENTITY % release.type.release "INCLUDE"> <![%release.type.current;[ <!ENTITY release '&release.current;'> diff --git a/sbin/ipfw/tables.c b/sbin/ipfw/tables.c index 2264e32..d14c9e9 100644 --- a/sbin/ipfw/tables.c +++ b/sbin/ipfw/tables.c @@ -914,9 +914,10 @@ table_modify_record(ipfw_obj_header *oh, int ac, char *av[], int add, xi.vmask = vmask; strlcpy(xi.tablename, oh->ntlv.name, sizeof(xi.tablename)); - fprintf(stderr, "DEPRECATED: inserting data into " - "non-existent table %s. (auto-created)\n", - xi.tablename); + if (quiet == 0) + warnx("DEPRECATED: inserting data into " + "non-existent table %s. (auto-created)", + xi.tablename); table_do_create(oh, &xi); } @@ -937,8 +938,6 @@ table_modify_record(ipfw_obj_header *oh, int ac, char *av[], int add, error = table_do_modify_record(cmd, oh, tent_buf, count, atomic); - quiet = 0; - /* * Compatibility stuff: do not yell on duplicate keys or * failed deletions. diff --git a/sbin/ping6/ping6.c b/sbin/ping6/ping6.c index 732e634..51a154d 100644 --- a/sbin/ping6/ping6.c +++ b/sbin/ping6/ping6.c @@ -515,7 +515,6 @@ main(int argc, char *argv[]) memcpy(&src, res->ai_addr, res->ai_addrlen); srclen = res->ai_addrlen; freeaddrinfo(res); - res = NULL; options |= F_SRCADDR; break; case 's': /* size of packet to send */ @@ -631,7 +630,7 @@ main(int argc, char *argv[]) if (error) errx(1, "%s", gai_strerror(error)); if (res->ai_canonname) - hostname = res->ai_canonname; + hostname = strdup(res->ai_canonname); else hostname = target; @@ -643,6 +642,7 @@ main(int argc, char *argv[]) if ((s = socket(res->ai_family, res->ai_socktype, res->ai_protocol)) < 0) err(1, "socket"); + freeaddrinfo(res); /* set the source address if specified. */ if ((options & F_SRCADDR) != 0) { @@ -1208,9 +1208,6 @@ main(int argc, char *argv[]) sigaction(SIGALRM, &si_sa, 0); summary(); - if (res != NULL) - freeaddrinfo(res); - if(packet != NULL) free(packet); diff --git a/sbin/umount/umount.8 b/sbin/umount/umount.8 index 2ddbf5a..0f672b8 100644 --- a/sbin/umount/umount.8 +++ b/sbin/umount/umount.8 @@ -28,7 +28,7 @@ .\" @(#)umount.8 8.2 (Berkeley) 5/8/95 .\" $FreeBSD$ .\" -.Dd June 17, 2015 +.Dd July 7, 2016 .Dt UMOUNT 8 .Os .Sh NAME @@ -36,12 +36,12 @@ .Nd unmount file systems .Sh SYNOPSIS .Nm -.Op Fl fv +.Op Fl fnv .Ar special ... | node ... | fsid ... .Nm .Fl a | A .Op Fl F Ar fstab -.Op Fl fv +.Op Fl fnv .Op Fl h Ar host .Op Fl t Ar type .Sh DESCRIPTION @@ -94,6 +94,15 @@ option and, unless otherwise specified with the option, will only unmount .Tn NFS file systems. +.It Fl n +Unless the +.Fl f +is used, the +.Nm +will not unmount an active file system. +It will, however, perform a flush. +This flag disables this behaviour, preventing the flush +if there are any files open. .It Fl t Ar type Is used to indicate the actions should only be taken on file systems of the specified type. diff --git a/sbin/umount/umount.c b/sbin/umount/umount.c index 6cd8ea7..20b7804 100644 --- a/sbin/umount/umount.c +++ b/sbin/umount/umount.c @@ -91,7 +91,7 @@ main(int argc, char *argv[]) struct addrinfo hints; all = errs = 0; - while ((ch = getopt(argc, argv, "AaF:fh:t:v")) != -1) + while ((ch = getopt(argc, argv, "AaF:fh:nt:v")) != -1) switch (ch) { case 'A': all = 2; @@ -103,12 +103,15 @@ main(int argc, char *argv[]) setfstab(optarg); break; case 'f': - fflag = MNT_FORCE; + fflag |= MNT_FORCE; break; case 'h': /* -h implies -A. */ all = 2; nfshost = optarg; break; + case 'n': + fflag |= MNT_NONBUSY; + break; case 't': if (typelist != NULL) err(1, "only one -t option may be specified"); @@ -124,8 +127,11 @@ main(int argc, char *argv[]) argc -= optind; argv += optind; + if ((fflag & MNT_FORCE) != 0 && (fflag & MNT_NONBUSY) != 0) + err(1, "-f and -n are mutually exclusive"); + /* Start disks transferring immediately. */ - if ((fflag & MNT_FORCE) == 0) + if ((fflag & (MNT_FORCE | MNT_NONBUSY)) == 0) sync(); if ((argc == 0 && !all) || (argc != 0 && all)) @@ -609,7 +615,7 @@ usage(void) { (void)fprintf(stderr, "%s\n%s\n", - "usage: umount [-fv] special ... | node ... | fsid ...", - " umount -a | -A [-F fstab] [-fv] [-h host] [-t type]"); + "usage: umount [-fnv] special ... | node ... | fsid ...", + " umount -a | -A [-F fstab] [-fnv] [-h host] [-t type]"); exit(1); } diff --git a/share/Makefile b/share/Makefile index 56cebef..25b2ba3 100644 --- a/share/Makefile +++ b/share/Makefile @@ -13,7 +13,6 @@ SUBDIR= ${_colldef} \ ${_examples} \ ${_i18n} \ keys \ - ${_locale-links} \ ${_man} \ ${_me} \ misc \ @@ -61,7 +60,6 @@ _i18n= i18n .if ${MK_LOCALES} != "no" _colldef= colldef _ctypedef= ctypedef -_locale-links= locale-links _monetdef= monetdef _msgdef= msgdef _numericdef= numericdef diff --git a/share/colldef/Makefile b/share/colldef/Makefile index 01578af..5cd981a 100644 --- a/share/colldef/Makefile +++ b/share/colldef/Makefile @@ -9,7 +9,7 @@ MAPLOC= ${.CURDIR}/../../tools/tools/locale/etc/final-maps .src.LC_COLLATE: localedef -D -U -i ${.IMPSRC} \ - -f ${MAPLOC}/map.${.TARGET:T:R:E} ${.OBJDIR}/${.IMPSRC:T:R} + -f ${MAPLOC}/map.${.TARGET:T:R:E:C/@.*//} ${.OBJDIR}/${.IMPSRC:T:R} LOCALES+= af_ZA.UTF-8 LOCALES+= am_ET.UTF-8 @@ -30,7 +30,7 @@ LOCALES+= hu_HU.UTF-8 LOCALES+= hy_AM.UTF-8 LOCALES+= is_IS.UTF-8 LOCALES+= ja_JP.UTF-8 -LOCALES+= kk_Cyrl_KZ.UTF-8 +LOCALES+= kk_KZ.UTF-8 LOCALES+= ko_KR.UTF-8 LOCALES+= lt_LT.UTF-8 LOCALES+= lv_LV.UTF-8 @@ -44,15 +44,15 @@ LOCALES+= sl_SI.UTF-8 LOCALES+= sv_SE.UTF-8 LOCALES+= tr_TR.UTF-8 LOCALES+= uk_UA.UTF-8 -LOCALES+= zh_Hans_CN.UTF-8 -LOCALES+= zh_Hant_TW.UTF-8 +LOCALES+= zh_CN.UTF-8 +LOCALES+= zh_TW.UTF-8 LOCALES_MAPPED+= af_ZA.UTF-8 af_ZA.ISO8859-15 LOCALES_MAPPED+= af_ZA.UTF-8 af_ZA.ISO8859-1 LOCALES_MAPPED+= be_BY.UTF-8 be_BY.ISO8859-5 LOCALES_MAPPED+= be_BY.UTF-8 be_BY.CP1251 LOCALES_MAPPED+= be_BY.UTF-8 be_BY.CP1131 -LOCALES_MAPPED+= ru_RU.UTF-8 sr_Cyrl_RS.ISO8859-5 +LOCALES_MAPPED+= ru_RU.UTF-8 sr_RS.ISO8859-5 LOCALES_MAPPED+= ru_RU.UTF-8 ru_RU.KOI8-R LOCALES_MAPPED+= ru_RU.UTF-8 ru_RU.ISO8859-5 LOCALES_MAPPED+= ru_RU.UTF-8 ru_RU.CP866 @@ -66,7 +66,8 @@ LOCALES_MAPPED+= ca_AD.UTF-8 ca_ES.ISO8859-15 LOCALES_MAPPED+= ca_AD.UTF-8 ca_ES.ISO8859-1 LOCALES_MAPPED+= ca_AD.UTF-8 ca_AD.ISO8859-15 LOCALES_MAPPED+= ca_AD.UTF-8 ca_AD.ISO8859-1 -LOCALES_MAPPED+= en_US.UTF-8 sr_Latn_RS.ISO8859-2 +LOCALES_MAPPED+= en_US.UTF-8 sr_RS.UTF-8@latin +LOCALES_MAPPED+= en_US.UTF-8 sr_RS.ISO8859-2 LOCALES_MAPPED+= en_US.UTF-8 pt_PT.ISO8859-15 LOCALES_MAPPED+= en_US.UTF-8 pt_PT.ISO8859-1 LOCALES_MAPPED+= en_US.UTF-8 pt_BR.ISO8859-1 @@ -147,9 +148,9 @@ LOCALES_MAPPED+= tr_TR.UTF-8 tr_TR.ISO8859-9 LOCALES_MAPPED+= uk_UA.UTF-8 uk_UA.KOI8-U LOCALES_MAPPED+= uk_UA.UTF-8 uk_UA.ISO8859-5 LOCALES_MAPPED+= uk_UA.UTF-8 uk_UA.CP1251 -LOCALES_MAPPED+= zh_Hans_CN.UTF-8 zh_Hans_CN.GBK -LOCALES_MAPPED+= zh_Hans_CN.UTF-8 zh_Hans_CN.GB18030 -LOCALES_MAPPED+= zh_Hant_TW.UTF-8 zh_Hant_TW.Big5 +LOCALES_MAPPED+= zh_CN.UTF-8 zh_CN.GBK +LOCALES_MAPPED+= zh_CN.UTF-8 zh_CN.GB18030 +LOCALES_MAPPED+= zh_TW.UTF-8 zh_TW.Big5 LOCALES+= cs_CZ.ISO8859-2 LOCALES+= da_DK.ISO8859-1 @@ -159,8 +160,8 @@ LOCALES+= hu_HU.ISO8859-2 LOCALES+= nb_NO.ISO8859-1 LOCALES+= nb_NO.ISO8859-15 LOCALES+= sk_SK.ISO8859-2 -LOCALES+= zh_Hans_CN.GB2312 -LOCALES+= zh_Hans_CN.eucCN +LOCALES+= zh_CN.GB2312 +LOCALES+= zh_CN.eucCN SAME+= ar_SA.UTF-8 ar_QA.UTF-8 @@ -168,13 +169,12 @@ SAME+= ar_SA.UTF-8 ar_MA.UTF-8 SAME+= ar_SA.UTF-8 ar_JO.UTF-8 SAME+= ar_SA.UTF-8 ar_EG.UTF-8 SAME+= ar_SA.UTF-8 ar_AE.UTF-8 -SAME+= ru_RU.UTF-8 sr_Cyrl_RS.UTF-8 -SAME+= ru_RU.UTF-8 mn_Cyrl_MN.UTF-8 +SAME+= ru_RU.UTF-8 sr_RS.UTF-8 +SAME+= ru_RU.UTF-8 mn_MN.UTF-8 SAME+= ru_RU.UTF-8 bg_BG.UTF-8 SAME+= ca_AD.UTF-8 ca_IT.UTF-8 SAME+= ca_AD.UTF-8 ca_FR.UTF-8 SAME+= ca_AD.UTF-8 ca_ES.UTF-8 -SAME+= en_US.UTF-8 sr_Latn_RS.UTF-8 SAME+= en_US.UTF-8 pt_PT.UTF-8 SAME+= en_US.UTF-8 pt_BR.UTF-8 SAME+= en_US.UTF-8 nn_NO.UTF-8 @@ -204,7 +204,7 @@ SAME+= es_MX.UTF-8 es_CR.UTF-8 SAME+= es_MX.UTF-8 es_AR.UTF-8 SAME+= se_NO.UTF-8 se_FI.UTF-8 SAME+= sv_SE.UTF-8 sv_FI.UTF-8 -SAME+= zh_Hant_TW.UTF-8 zh_Hant_HK.UTF-8 +SAME+= zh_TW.UTF-8 zh_HK.UTF-8 SAME+= ko_KR.eucKR ko_KR.CP949 # legacy (same charset) FILES= ${LOCALES:S/$/.LC_COLLATE/} @@ -224,7 +224,7 @@ FILES+= $t.LC_COLLATE FILESDIR_$t.LC_COLLATE= ${LOCALEDIR}/$t $t.LC_COLLATE: ${.CURDIR}/$f.src localedef -D -U -i ${.ALLSRC} \ - -f ${MAPLOC}/map.${.TARGET:T:R:E} \ + -f ${MAPLOC}/map.${.TARGET:T:R:E:C/@.*//} \ ${.OBJDIR}/${.TARGET:T:R} .endfor diff --git a/share/colldef/kk_Cyrl_KZ.UTF-8.src b/share/colldef/kk_KZ.UTF-8.src index abc0aeb..abc0aeb 100644 --- a/share/colldef/kk_Cyrl_KZ.UTF-8.src +++ b/share/colldef/kk_KZ.UTF-8.src diff --git a/share/colldef/zh_Hans_CN.GB2312.src b/share/colldef/zh_CN.GB2312.src index 81bcfc5..81bcfc5 100644 --- a/share/colldef/zh_Hans_CN.GB2312.src +++ b/share/colldef/zh_CN.GB2312.src diff --git a/share/colldef/zh_Hans_CN.UTF-8.src b/share/colldef/zh_CN.UTF-8.src index d734ba9..d734ba9 100644 --- a/share/colldef/zh_Hans_CN.UTF-8.src +++ b/share/colldef/zh_CN.UTF-8.src diff --git a/share/colldef/zh_Hans_CN.eucCN.src b/share/colldef/zh_CN.eucCN.src index 81bcfc5..81bcfc5 100644 --- a/share/colldef/zh_Hans_CN.eucCN.src +++ b/share/colldef/zh_CN.eucCN.src diff --git a/share/colldef/zh_Hant_TW.UTF-8.src b/share/colldef/zh_TW.UTF-8.src index 84aa7ac..84aa7ac 100644 --- a/share/colldef/zh_Hant_TW.UTF-8.src +++ b/share/colldef/zh_TW.UTF-8.src diff --git a/share/ctypedef/Makefile b/share/ctypedef/Makefile index d7f2cd1..dcc7708 100644 --- a/share/ctypedef/Makefile +++ b/share/ctypedef/Makefile @@ -30,29 +30,29 @@ LOCALES+= ru_RU.CP1251 LOCALES+= ru_RU.CP866 LOCALES+= ru_RU.ISO8859-5 LOCALES+= ru_RU.KOI8-R -LOCALES+= sr_Latn_RS.ISO8859-2 +LOCALES+= sr_RS.ISO8859-2 LOCALES+= tr_TR.ISO8859-9 LOCALES+= uk_UA.CP1251 LOCALES+= uk_UA.ISO8859-5 LOCALES+= uk_UA.KOI8-U -LOCALES+= zh_Hans_CN.GB18030 -LOCALES+= zh_Hans_CN.GB2312 -LOCALES+= zh_Hans_CN.GBK -LOCALES+= zh_Hans_CN.eucCN -LOCALES+= zh_Hant_TW.Big5 +LOCALES+= zh_CN.GB18030 +LOCALES+= zh_CN.GB2312 +LOCALES+= zh_CN.GBK +LOCALES+= zh_CN.eucCN +LOCALES+= zh_TW.Big5 SAME+= en_US.UTF-8 ru_RU.UTF-8 -SAME+= en_US.UTF-8 zh_Hant_TW.UTF-8 -SAME+= en_US.UTF-8 zh_Hant_HK.UTF-8 -SAME+= en_US.UTF-8 zh_Hans_CN.UTF-8 +SAME+= en_US.UTF-8 zh_TW.UTF-8 +SAME+= en_US.UTF-8 zh_HK.UTF-8 +SAME+= en_US.UTF-8 zh_CN.UTF-8 SAME+= en_US.UTF-8 uk_UA.UTF-8 SAME+= en_US.UTF-8 tr_TR.UTF-8 SAME+= en_US.UTF-8 sv_SE.UTF-8 SAME+= en_US.UTF-8 sv_FI.UTF-8 -SAME+= en_US.UTF-8 sr_Latn_RS.UTF-8 -SAME+= en_US.UTF-8 sr_Cyrl_RS.UTF-8 +SAME+= en_US.UTF-8 sr_RS.UTF-8@latin +SAME+= en_US.UTF-8 sr_RS.UTF-8 SAME+= en_US.UTF-8 sl_SI.UTF-8 SAME+= en_US.UTF-8 sk_SK.UTF-8 SAME+= en_US.UTF-8 se_NO.UTF-8 @@ -65,11 +65,11 @@ SAME+= en_US.UTF-8 nn_NO.UTF-8 SAME+= en_US.UTF-8 nl_NL.UTF-8 SAME+= en_US.UTF-8 nl_BE.UTF-8 SAME+= en_US.UTF-8 nb_NO.UTF-8 -SAME+= en_US.UTF-8 mn_Cyrl_MN.UTF-8 +SAME+= en_US.UTF-8 mn_MN.UTF-8 SAME+= en_US.UTF-8 lv_LV.UTF-8 SAME+= en_US.UTF-8 lt_LT.UTF-8 SAME+= en_US.UTF-8 ko_KR.UTF-8 -SAME+= en_US.UTF-8 kk_Cyrl_KZ.UTF-8 +SAME+= en_US.UTF-8 kk_KZ.UTF-8 SAME+= en_US.UTF-8 ja_JP.UTF-8 SAME+= en_US.UTF-8 it_IT.UTF-8 SAME+= en_US.UTF-8 it_CH.UTF-8 @@ -184,7 +184,7 @@ SAME+= en_US.ISO8859-15 da_DK.ISO8859-15 SAME+= en_US.ISO8859-15 af_ZA.ISO8859-15 SAME+= ru_RU.CP1251 bg_BG.CP1251 SAME+= ru_RU.CP1251 be_BY.CP1251 -SAME+= ru_RU.ISO8859-5 sr_Cyrl_RS.ISO8859-5 +SAME+= ru_RU.ISO8859-5 sr_RS.ISO8859-5 SAME+= ru_RU.ISO8859-5 be_BY.ISO8859-5 SAME+= ca_IT.ISO8859-1 ca_FR.ISO8859-1 SAME+= ca_IT.ISO8859-1 ca_ES.ISO8859-1 @@ -192,13 +192,13 @@ SAME+= ca_IT.ISO8859-1 ca_AD.ISO8859-1 SAME+= ca_IT.ISO8859-15 ca_FR.ISO8859-15 SAME+= ca_IT.ISO8859-15 ca_ES.ISO8859-15 SAME+= ca_IT.ISO8859-15 ca_AD.ISO8859-15 -SAME+= sr_Latn_RS.ISO8859-2 sl_SI.ISO8859-2 -SAME+= sr_Latn_RS.ISO8859-2 sk_SK.ISO8859-2 -SAME+= sr_Latn_RS.ISO8859-2 ro_RO.ISO8859-2 -SAME+= sr_Latn_RS.ISO8859-2 pl_PL.ISO8859-2 -SAME+= sr_Latn_RS.ISO8859-2 hu_HU.ISO8859-2 -SAME+= sr_Latn_RS.ISO8859-2 hr_HR.ISO8859-2 -SAME+= sr_Latn_RS.ISO8859-2 cs_CZ.ISO8859-2 +SAME+= sr_RS.ISO8859-2 sl_SI.ISO8859-2 +SAME+= sr_RS.ISO8859-2 sk_SK.ISO8859-2 +SAME+= sr_RS.ISO8859-2 ro_RO.ISO8859-2 +SAME+= sr_RS.ISO8859-2 pl_PL.ISO8859-2 +SAME+= sr_RS.ISO8859-2 hu_HU.ISO8859-2 +SAME+= sr_RS.ISO8859-2 hr_HR.ISO8859-2 +SAME+= sr_RS.ISO8859-2 cs_CZ.ISO8859-2 SAME+= en_US.US-ASCII en_ZA.US-ASCII SAME+= en_US.US-ASCII en_NZ.US-ASCII SAME+= en_US.US-ASCII en_GB.US-ASCII @@ -226,15 +226,15 @@ SYMPAIRS+= be_BY.CP1131.src ru_RU.ISO8859-5.src SYMPAIRS+= be_BY.CP1131.src ru_RU.KOI8-R.src SYMPAIRS+= uk_UA.CP1251.src uk_UA.ISO8859-5.src SYMPAIRS+= uk_UA.CP1251.src uk_UA.KOI8-U.src -SYMPAIRS+= zh_Hans_CN.eucCN.src zh_Hans_CN.GB18030.src -SYMPAIRS+= zh_Hans_CN.eucCN.src zh_Hans_CN.GB2312.src -SYMPAIRS+= zh_Hans_CN.eucCN.src zh_Hans_CN.GBK.src +SYMPAIRS+= zh_CN.GB18030.src zh_CN.GB2312.src +SYMPAIRS+= zh_CN.GB18030.src zh_CN.GBK.src +SYMPAIRS+= zh_CN.GB18030.src zh_CN.eucCN.src SYMPAIRS+= en_US.ISO8859-1.src en_US.ISO8859-15.src SYMPAIRS+= en_US.ISO8859-1.src en_US.US-ASCII.src SYMPAIRS+= en_US.ISO8859-1.src lv_LV.ISO8859-13.src -SYMPAIRS+= en_US.ISO8859-1.src sr_Latn_RS.ISO8859-2.src +SYMPAIRS+= en_US.ISO8859-1.src sr_RS.ISO8859-2.src SYMPAIRS+= en_US.ISO8859-1.src tr_TR.ISO8859-9.src -SYMPAIRS+= ja_JP.eucJP.src ja_JP.SJIS.src +SYMPAIRS+= ja_JP.SJIS.src ja_JP.eucJP.src .for s t in ${SYMPAIRS} ${t:S/src$/LC_CTYPE/}: $s diff --git a/share/ctypedef/ja_JP.eucJP.src b/share/ctypedef/ja_JP.SJIS.src index 73b93d8..73b93d8 100644 --- a/share/ctypedef/ja_JP.eucJP.src +++ b/share/ctypedef/ja_JP.SJIS.src diff --git a/share/ctypedef/zh_Hans_CN.eucCN.src b/share/ctypedef/zh_CN.GB18030.src index e70b37b..e70b37b 100644 --- a/share/ctypedef/zh_Hans_CN.eucCN.src +++ b/share/ctypedef/zh_CN.GB18030.src diff --git a/share/ctypedef/zh_Hant_TW.Big5.src b/share/ctypedef/zh_TW.Big5.src index 99a0420..99a0420 100644 --- a/share/ctypedef/zh_Hant_TW.Big5.src +++ b/share/ctypedef/zh_TW.Big5.src diff --git a/share/locale-links/Makefile b/share/locale-links/Makefile deleted file mode 100644 index 6487a14..0000000 --- a/share/locale-links/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# $FreeBSD$ - -LOCALEDIR= ${SHAREDIR}/locale -LC_FILES= LC_COLLATE LC_CTYPE LC_MESSAGES LC_MONETARY LC_NUMERIC \ - LC_TIME - -ALIASES= zh_Hans_CN.GB18030 zh_CN.GB18030 \ - zh_Hans_CN.GB2312 zh_CN.GB2312 \ - zh_Hans_CN.GBK zh_CN.GBK \ - zh_Hans_CN.eucCN zh_CN.eucCN \ - zh_Hans_CN.UTF-8 zh_CN.UTF-8 \ - zh_Hant_HK.UTF-8 zh_HK.UTF-8 \ - zh_Hant_TW.Big5 zh_TW.Big5 \ - zh_Hant_TW.UTF-8 zh_TW.UTF-8 - -.for from to in ${ALIASES} -.for f in ${LC_FILES} -SYMLINKS+= ../${from}/${f} ${LOCALEDIR}/${to}/${f} -.endfor -.endfor - -.include <bsd.prog.mk> diff --git a/share/locale-links/Makefile.depend b/share/locale-links/Makefile.depend deleted file mode 100644 index f80275d..0000000 --- a/share/locale-links/Makefile.depend +++ /dev/null @@ -1,11 +0,0 @@ -# $FreeBSD$ -# Autogenerated - do NOT edit! - -DIRDEPS = \ - - -.include <dirdeps.mk> - -.if ${DEP_RELDIR} == ${_DEP_RELDIR} -# local dependencies - needed for -jN in clean tree -.endif diff --git a/share/man/man4/capsicum.4 b/share/man/man4/capsicum.4 index aa1568e..74cf281 100644 --- a/share/man/man4/capsicum.4 +++ b/share/man/man4/capsicum.4 @@ -26,7 +26,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 25, 2016 +.Dd July 5, 2016 .Dt CAPSICUM 4 .Os .Sh NAME @@ -104,7 +104,7 @@ associated with file descriptors; described in greater detail in .Xr shm_open 2 , .Xr write 2 , .Xr cap_rights_get 3 , -.Xr casper 3 , +.Xr libcasper 3 , .Xr procdesc 4 .Sh HISTORY .Nm diff --git a/share/man/man9/timeout.9 b/share/man/man9/timeout.9 index df8538e..73925b2 100644 --- a/share/man/man9/timeout.9 +++ b/share/man/man9/timeout.9 @@ -29,7 +29,7 @@ .\" .\" $FreeBSD$ .\" -.Dd September 14, 2015 +.Dd July 4, 2016 .Dt TIMEOUT 9 .Os .Sh NAME @@ -247,6 +247,10 @@ has already been serviced, then negative one is returned. If the callout is currently being serviced and cannot be stopped, then zero will be returned. +If the callout is currently being serviced and cannot be stopped, and at the +same time a next invocation of the same callout is also scheduled, then +.Fn callout_stop +unschedules the next run and returns zero. If the callout has an associated lock, then that lock must be held when this function is called. .Pp @@ -814,7 +818,7 @@ and .Fn callout_drain functions return a value of one if the callout was still pending when it was called, a zero if the callout could not be stopped and a negative one is it -was either not running or haas already completed. +was either not running or has already completed. The .Fn timeout function returns a diff --git a/share/misc/committers-src.dot b/share/misc/committers-src.dot index 89ce465..a1d5574 100644 --- a/share/misc/committers-src.dot +++ b/share/misc/committers-src.dot @@ -120,6 +120,7 @@ arybchik [label="Andrew Rybchenko\narybchik@FreeBSD.org\n2014/10/12"] asomers [label="Alan Somers\nasomers@FreeBSD.org\n2013/04/24"] avg [label="Andriy Gapon\navg@FreeBSD.org\n2009/02/18"] avos [label="Andriy Voskoboinyk\navos@FreeBSD.org\n2015/09/24"] +badger [label="Eric Badger\nbadger@FreeBSD.org\n2016/07/01"] bapt [label="Baptiste Daroussin\nbapt@FreeBSD.org\n2011/12/23"] bdrewery [label="Bryan Drewery\nbdrewery@FreeBSD.org\n2013/12/14"] benl [label="Ben Laurie\nbenl@FreeBSD.org\n2011/05/18"] @@ -588,6 +589,7 @@ ken -> asomers ken -> slm kib -> ae +kib -> badger kib -> dchagin kib -> gjb kib -> jah @@ -767,6 +769,8 @@ ume -> jinmei ume -> suz ume -> tshiozak +vangyzen -> badger + wes -> scf wkoszek -> jceel diff --git a/share/monetdef/Makefile b/share/monetdef/Makefile index c31f5bf..c06792c 100644 --- a/share/monetdef/Makefile +++ b/share/monetdef/Makefile @@ -63,12 +63,12 @@ LOCALES+= it_CH.UTF-8 LOCALES+= ja_JP.SJIS LOCALES+= ja_JP.UTF-8 LOCALES+= ja_JP.eucJP -LOCALES+= kk_Cyrl_KZ.UTF-8 +LOCALES+= kk_KZ.UTF-8 LOCALES+= ko_KR.UTF-8 LOCALES+= ko_KR.eucKR LOCALES+= lv_LV.ISO8859-13 LOCALES+= lv_LV.UTF-8 -LOCALES+= mn_Cyrl_MN.UTF-8 +LOCALES+= mn_MN.UTF-8 LOCALES+= nb_NO.ISO8859-15 LOCALES+= nb_NO.UTF-8 LOCALES+= nl_BE.ISO8859-15 @@ -89,7 +89,7 @@ LOCALES+= se_NO.UTF-8 LOCALES+= sk_SK.UTF-8 LOCALES+= sl_SI.ISO8859-2 LOCALES+= sl_SI.UTF-8 -LOCALES+= sr_Latn_RS.UTF-8 +LOCALES+= sr_RS.UTF-8@latin LOCALES+= sv_FI.ISO8859-1 LOCALES+= sv_FI.ISO8859-15 LOCALES+= sv_FI.UTF-8 @@ -101,13 +101,13 @@ LOCALES+= uk_UA.CP1251 LOCALES+= uk_UA.ISO8859-5 LOCALES+= uk_UA.KOI8-U LOCALES+= uk_UA.UTF-8 -LOCALES+= zh_Hans_CN.GB2312 -LOCALES+= zh_Hans_CN.GBK -LOCALES+= zh_Hans_CN.UTF-8 -LOCALES+= zh_Hans_CN.eucCN -LOCALES+= zh_Hant_HK.UTF-8 -LOCALES+= zh_Hant_TW.Big5 -LOCALES+= zh_Hant_TW.UTF-8 +LOCALES+= zh_CN.GB2312 +LOCALES+= zh_CN.GBK +LOCALES+= zh_CN.UTF-8 +LOCALES+= zh_CN.eucCN +LOCALES+= zh_HK.UTF-8 +LOCALES+= zh_TW.Big5 +LOCALES+= zh_TW.UTF-8 @@ -160,8 +160,8 @@ SAME+= en_CA.UTF-8 en_CA.US-ASCII SAME+= en_CA.UTF-8 en_CA.ISO8859-15 SAME+= en_CA.UTF-8 en_CA.ISO8859-1 SAME+= en_GB.ISO8859-15 en_GB.ISO8859-1 -SAME+= zh_Hant_HK.UTF-8 en_HK.UTF-8 -SAME+= zh_Hant_HK.UTF-8 en_HK.ISO8859-1 +SAME+= zh_HK.UTF-8 en_HK.UTF-8 +SAME+= zh_HK.UTF-8 en_HK.ISO8859-1 SAME+= en_NZ.UTF-8 en_NZ.US-ASCII SAME+= en_NZ.UTF-8 en_NZ.ISO8859-15 SAME+= en_NZ.UTF-8 en_NZ.ISO8859-1 @@ -197,11 +197,11 @@ SAME+= nn_NO.ISO8859-15 nn_NO.ISO8859-1 SAME+= se_NO.UTF-8 nn_NO.UTF-8 SAME+= pt_BR.UTF-8 pt_BR.ISO8859-1 SAME+= ro_RO.UTF-8 ro_RO.ISO8859-2 -SAME+= sr_Latn_RS.UTF-8 sr_Latn_RS.ISO8859-2 -SAME+= sr_Latn_RS.UTF-8 sr_Cyrl_RS.UTF-8 -SAME+= sr_Latn_RS.UTF-8 sr_Cyrl_RS.ISO8859-5 +SAME+= sr_RS.UTF-8@latin sr_RS.ISO8859-2 +SAME+= sr_RS.UTF-8@latin sr_RS.UTF-8 +SAME+= sr_RS.UTF-8@latin sr_RS.ISO8859-5 SAME+= sv_SE.ISO8859-15 sv_SE.ISO8859-1 -SAME+= zh_Hans_CN.GBK zh_Hans_CN.GB18030 +SAME+= zh_CN.GBK zh_CN.GB18030 SAME+= ko_KR.eucKR ko_KR.CP949 # legacy (same charset) FILES= ${LOCALES:S/$/.out/} diff --git a/share/monetdef/kk_Cyrl_KZ.UTF-8.src b/share/monetdef/kk_KZ.UTF-8.src index a5dc90c..a5dc90c 100644 --- a/share/monetdef/kk_Cyrl_KZ.UTF-8.src +++ b/share/monetdef/kk_KZ.UTF-8.src diff --git a/share/monetdef/mn_Cyrl_MN.UTF-8.src b/share/monetdef/mn_MN.UTF-8.src index 3706866..3706866 100644 --- a/share/monetdef/mn_Cyrl_MN.UTF-8.src +++ b/share/monetdef/mn_MN.UTF-8.src diff --git a/share/monetdef/sr_Latn_RS.UTF-8.src b/share/monetdef/sr_RS.UTF-8@latin.src index c4dbd27..c4dbd27 100644 --- a/share/monetdef/sr_Latn_RS.UTF-8.src +++ b/share/monetdef/sr_RS.UTF-8@latin.src diff --git a/share/monetdef/zh_Hans_CN.GB2312.src b/share/monetdef/zh_CN.GB2312.src index 98bbbf1..98bbbf1 100644 --- a/share/monetdef/zh_Hans_CN.GB2312.src +++ b/share/monetdef/zh_CN.GB2312.src diff --git a/share/monetdef/zh_Hans_CN.GBK.src b/share/monetdef/zh_CN.GBK.src index 03faef2..03faef2 100644 --- a/share/monetdef/zh_Hans_CN.GBK.src +++ b/share/monetdef/zh_CN.GBK.src diff --git a/share/monetdef/zh_Hans_CN.UTF-8.src b/share/monetdef/zh_CN.UTF-8.src index e1c1ce8..e1c1ce8 100644 --- a/share/monetdef/zh_Hans_CN.UTF-8.src +++ b/share/monetdef/zh_CN.UTF-8.src diff --git a/share/monetdef/zh_Hans_CN.eucCN.src b/share/monetdef/zh_CN.eucCN.src index 1919a03..1919a03 100644 --- a/share/monetdef/zh_Hans_CN.eucCN.src +++ b/share/monetdef/zh_CN.eucCN.src diff --git a/share/monetdef/zh_Hant_HK.UTF-8.src b/share/monetdef/zh_HK.UTF-8.src index faf104e..faf104e 100644 --- a/share/monetdef/zh_Hant_HK.UTF-8.src +++ b/share/monetdef/zh_HK.UTF-8.src diff --git a/share/monetdef/zh_Hant_TW.Big5.src b/share/monetdef/zh_TW.Big5.src index 9c37150..9c37150 100644 --- a/share/monetdef/zh_Hant_TW.Big5.src +++ b/share/monetdef/zh_TW.Big5.src diff --git a/share/monetdef/zh_Hant_TW.UTF-8.src b/share/monetdef/zh_TW.UTF-8.src index 80109b9..80109b9 100644 --- a/share/monetdef/zh_Hant_TW.UTF-8.src +++ b/share/monetdef/zh_TW.UTF-8.src diff --git a/share/msgdef/Makefile b/share/msgdef/Makefile index ab8a7ad..4c0e6d9 100644 --- a/share/msgdef/Makefile +++ b/share/msgdef/Makefile @@ -41,13 +41,13 @@ LOCALES+= it_IT.UTF-8 LOCALES+= ja_JP.SJIS LOCALES+= ja_JP.UTF-8 LOCALES+= ja_JP.eucJP -LOCALES+= kk_Cyrl_KZ.UTF-8 +LOCALES+= kk_KZ.UTF-8 LOCALES+= ko_KR.UTF-8 LOCALES+= ko_KR.eucKR LOCALES+= lt_LT.UTF-8 LOCALES+= lv_LV.ISO8859-13 LOCALES+= lv_LV.UTF-8 -LOCALES+= mn_Cyrl_MN.UTF-8 +LOCALES+= mn_MN.UTF-8 LOCALES+= nb_NO.UTF-8 LOCALES+= nl_NL.UTF-8 LOCALES+= nn_NO.UTF-8 @@ -63,9 +63,9 @@ LOCALES+= ru_RU.UTF-8 LOCALES+= se_NO.UTF-8 LOCALES+= sk_SK.ISO8859-2 LOCALES+= sk_SK.UTF-8 -LOCALES+= sr_Cyrl_RS.ISO8859-5 -LOCALES+= sr_Cyrl_RS.UTF-8 -LOCALES+= sr_Latn_RS.UTF-8 +LOCALES+= sr_RS.ISO8859-5 +LOCALES+= sr_RS.UTF-8 +LOCALES+= sr_RS.UTF-8@latin LOCALES+= sv_SE.UTF-8 LOCALES+= tr_TR.ISO8859-9 LOCALES+= tr_TR.UTF-8 @@ -73,12 +73,12 @@ LOCALES+= uk_UA.CP1251 LOCALES+= uk_UA.ISO8859-5 LOCALES+= uk_UA.KOI8-U LOCALES+= uk_UA.UTF-8 -LOCALES+= zh_Hans_CN.GB2312 -LOCALES+= zh_Hans_CN.GBK -LOCALES+= zh_Hans_CN.UTF-8 -LOCALES+= zh_Hant_HK.UTF-8 -LOCALES+= zh_Hant_TW.Big5 -LOCALES+= zh_Hant_TW.UTF-8 +LOCALES+= zh_CN.GB2312 +LOCALES+= zh_CN.GBK +LOCALES+= zh_CN.UTF-8 +LOCALES+= zh_HK.UTF-8 +LOCALES+= zh_TW.Big5 +LOCALES+= zh_TW.UTF-8 @@ -95,7 +95,7 @@ SAME+= ar_SA.UTF-8 ar_MA.UTF-8 SAME+= ar_SA.UTF-8 ar_JO.UTF-8 SAME+= ar_SA.UTF-8 ar_EG.UTF-8 SAME+= ar_SA.UTF-8 ar_AE.UTF-8 -SAME+= sr_Cyrl_RS.UTF-8 bg_BG.UTF-8 +SAME+= sr_RS.UTF-8 bg_BG.UTF-8 SAME+= es_MX.ISO8859-1 es_ES.ISO8859-15 SAME+= es_MX.ISO8859-1 es_ES.ISO8859-1 SAME+= es_MX.ISO8859-1 es_AR.ISO8859-1 @@ -178,11 +178,11 @@ SAME+= fr_FR.UTF-8 fr_CA.ISO8859-1 SAME+= fr_FR.UTF-8 fr_BE.UTF-8 SAME+= fr_FR.UTF-8 fr_BE.ISO8859-15 SAME+= fr_FR.UTF-8 fr_BE.ISO8859-1 -SAME+= sr_Latn_RS.UTF-8 sr_Latn_RS.ISO8859-2 -SAME+= sr_Latn_RS.UTF-8 sl_SI.UTF-8 -SAME+= sr_Latn_RS.UTF-8 sl_SI.ISO8859-2 -SAME+= sr_Latn_RS.UTF-8 hr_HR.UTF-8 -SAME+= sr_Latn_RS.UTF-8 hr_HR.ISO8859-2 +SAME+= sr_RS.UTF-8@latin sr_RS.ISO8859-2 +SAME+= sr_RS.UTF-8@latin sl_SI.UTF-8 +SAME+= sr_RS.UTF-8@latin sl_SI.ISO8859-2 +SAME+= sr_RS.UTF-8@latin hr_HR.UTF-8 +SAME+= sr_RS.UTF-8@latin hr_HR.ISO8859-2 SAME+= hu_HU.UTF-8 hu_HU.ISO8859-2 SAME+= is_IS.ISO8859-15 is_IS.ISO8859-1 SAME+= it_IT.ISO8859-15 it_IT.ISO8859-1 @@ -200,8 +200,8 @@ SAME+= pt_PT.ISO8859-15 pt_BR.ISO8859-1 SAME+= pt_PT.UTF-8 pt_BR.UTF-8 SAME+= ro_RO.UTF-8 ro_RO.ISO8859-2 SAME+= se_NO.UTF-8 se_FI.UTF-8 -SAME+= zh_Hans_CN.GBK zh_Hans_CN.GB18030 -SAME+= zh_Hans_CN.GBK zh_Hans_CN.eucCN +SAME+= zh_CN.GBK zh_CN.GB18030 +SAME+= zh_CN.GBK zh_CN.eucCN SAME+= ko_KR.eucKR ko_KR.CP949 # legacy (same charset) FILES= ${LOCALES:S/$/.out/} diff --git a/share/msgdef/kk_Cyrl_KZ.UTF-8.src b/share/msgdef/kk_KZ.UTF-8.src index 80f5bfa..80f5bfa 100644 --- a/share/msgdef/kk_Cyrl_KZ.UTF-8.src +++ b/share/msgdef/kk_KZ.UTF-8.src diff --git a/share/msgdef/mn_Cyrl_MN.UTF-8.src b/share/msgdef/mn_MN.UTF-8.src index 4051025..4051025 100644 --- a/share/msgdef/mn_Cyrl_MN.UTF-8.src +++ b/share/msgdef/mn_MN.UTF-8.src diff --git a/share/msgdef/sr_Cyrl_RS.ISO8859-5.src b/share/msgdef/sr_RS.ISO8859-5.src index 21d5a5e..21d5a5e 100644 --- a/share/msgdef/sr_Cyrl_RS.ISO8859-5.src +++ b/share/msgdef/sr_RS.ISO8859-5.src diff --git a/share/msgdef/sr_Cyrl_RS.UTF-8.src b/share/msgdef/sr_RS.UTF-8.src index 1e4662c..1e4662c 100644 --- a/share/msgdef/sr_Cyrl_RS.UTF-8.src +++ b/share/msgdef/sr_RS.UTF-8.src diff --git a/share/msgdef/sr_Latn_RS.UTF-8.src b/share/msgdef/sr_RS.UTF-8@latin.src index cc22eaa..cc22eaa 100644 --- a/share/msgdef/sr_Latn_RS.UTF-8.src +++ b/share/msgdef/sr_RS.UTF-8@latin.src diff --git a/share/msgdef/zh_Hans_CN.GB2312.src b/share/msgdef/zh_CN.GB2312.src index 0dcd3e2..0dcd3e2 100644 --- a/share/msgdef/zh_Hans_CN.GB2312.src +++ b/share/msgdef/zh_CN.GB2312.src diff --git a/share/msgdef/zh_Hans_CN.GBK.src b/share/msgdef/zh_CN.GBK.src index c81391c..c81391c 100644 --- a/share/msgdef/zh_Hans_CN.GBK.src +++ b/share/msgdef/zh_CN.GBK.src diff --git a/share/msgdef/zh_Hans_CN.UTF-8.src b/share/msgdef/zh_CN.UTF-8.src index 14f5b1a..14f5b1a 100644 --- a/share/msgdef/zh_Hans_CN.UTF-8.src +++ b/share/msgdef/zh_CN.UTF-8.src diff --git a/share/msgdef/zh_Hant_HK.UTF-8.src b/share/msgdef/zh_HK.UTF-8.src index 53c58af..53c58af 100644 --- a/share/msgdef/zh_Hant_HK.UTF-8.src +++ b/share/msgdef/zh_HK.UTF-8.src diff --git a/share/msgdef/zh_Hant_TW.Big5.src b/share/msgdef/zh_TW.Big5.src index 964f9ed..964f9ed 100644 --- a/share/msgdef/zh_Hant_TW.Big5.src +++ b/share/msgdef/zh_TW.Big5.src diff --git a/share/msgdef/zh_Hant_TW.UTF-8.src b/share/msgdef/zh_TW.UTF-8.src index 40deaaf..40deaaf 100644 --- a/share/msgdef/zh_Hant_TW.UTF-8.src +++ b/share/msgdef/zh_TW.UTF-8.src diff --git a/share/numericdef/Makefile b/share/numericdef/Makefile index 1205c12..3ff8484 100644 --- a/share/numericdef/Makefile +++ b/share/numericdef/Makefile @@ -22,9 +22,9 @@ LOCALES+= tr_TR.UTF-8 LOCALES+= uk_UA.ISO8859-5 LOCALES+= uk_UA.KOI8-U LOCALES+= uk_UA.UTF-8 -LOCALES+= zh_Hans_CN.GB2312 -LOCALES+= zh_Hans_CN.eucCN -LOCALES+= zh_Hant_TW.Big5 +LOCALES+= zh_CN.GB2312 +LOCALES+= zh_CN.eucCN +LOCALES+= zh_TW.Big5 @@ -74,7 +74,7 @@ SAME+= uk_UA.UTF-8 nn_NO.UTF-8 SAME+= uk_UA.UTF-8 nb_NO.UTF-8 SAME+= uk_UA.UTF-8 lv_LV.UTF-8 SAME+= uk_UA.UTF-8 lt_LT.UTF-8 -SAME+= uk_UA.UTF-8 kk_Cyrl_KZ.UTF-8 +SAME+= uk_UA.UTF-8 kk_KZ.UTF-8 SAME+= uk_UA.UTF-8 hu_HU.UTF-8 SAME+= uk_UA.UTF-8 fr_FR.UTF-8 SAME+= uk_UA.UTF-8 fr_CA.UTF-8 @@ -85,12 +85,12 @@ SAME+= uk_UA.UTF-8 cs_CZ.UTF-8 SAME+= uk_UA.UTF-8 bg_BG.UTF-8 SAME+= uk_UA.UTF-8 be_BY.UTF-8 SAME+= uk_UA.UTF-8 af_ZA.UTF-8 -SAME+= en_US.UTF-8 zh_Hant_TW.UTF-8 -SAME+= en_US.UTF-8 zh_Hant_HK.UTF-8 -SAME+= en_US.UTF-8 zh_Hans_CN.UTF-8 -SAME+= en_US.UTF-8 zh_Hans_CN.GBK -SAME+= en_US.UTF-8 zh_Hans_CN.GB18030 -SAME+= en_US.UTF-8 mn_Cyrl_MN.UTF-8 +SAME+= en_US.UTF-8 zh_TW.UTF-8 +SAME+= en_US.UTF-8 zh_HK.UTF-8 +SAME+= en_US.UTF-8 zh_CN.UTF-8 +SAME+= en_US.UTF-8 zh_CN.GBK +SAME+= en_US.UTF-8 zh_CN.GB18030 +SAME+= en_US.UTF-8 mn_MN.UTF-8 SAME+= en_US.UTF-8 ko_KR.UTF-8 SAME+= en_US.UTF-8 ko_KR.eucKR SAME+= en_US.UTF-8 ja_JP.UTF-8 @@ -132,10 +132,10 @@ SAME+= ar_SA.UTF-8 ar_JO.UTF-8 SAME+= ar_SA.UTF-8 ar_EG.UTF-8 SAME+= ar_SA.UTF-8 ar_AE.UTF-8 SAME+= tr_TR.UTF-8 tr_TR.ISO8859-9 -SAME+= tr_TR.UTF-8 sr_Latn_RS.UTF-8 -SAME+= tr_TR.UTF-8 sr_Latn_RS.ISO8859-2 -SAME+= tr_TR.UTF-8 sr_Cyrl_RS.UTF-8 -SAME+= tr_TR.UTF-8 sr_Cyrl_RS.ISO8859-5 +SAME+= tr_TR.UTF-8 sr_RS.UTF-8@latin +SAME+= tr_TR.UTF-8 sr_RS.ISO8859-2 +SAME+= tr_TR.UTF-8 sr_RS.UTF-8 +SAME+= tr_TR.UTF-8 sr_RS.ISO8859-5 SAME+= tr_TR.UTF-8 sl_SI.UTF-8 SAME+= tr_TR.UTF-8 sl_SI.ISO8859-2 SAME+= tr_TR.UTF-8 ro_RO.UTF-8 diff --git a/share/numericdef/zh_Hans_CN.GB2312.src b/share/numericdef/zh_CN.GB2312.src index 21fa435..21fa435 100644 --- a/share/numericdef/zh_Hans_CN.GB2312.src +++ b/share/numericdef/zh_CN.GB2312.src diff --git a/share/numericdef/zh_Hans_CN.eucCN.src b/share/numericdef/zh_CN.eucCN.src index 64d21ed..64d21ed 100644 --- a/share/numericdef/zh_Hans_CN.eucCN.src +++ b/share/numericdef/zh_CN.eucCN.src diff --git a/share/numericdef/zh_Hant_TW.Big5.src b/share/numericdef/zh_TW.Big5.src index d88fa8f..d88fa8f 100644 --- a/share/numericdef/zh_Hant_TW.Big5.src +++ b/share/numericdef/zh_TW.Big5.src diff --git a/share/timedef/Makefile b/share/timedef/Makefile index 6866291..a1a211f 100644 --- a/share/timedef/Makefile +++ b/share/timedef/Makefile @@ -76,14 +76,14 @@ LOCALES+= it_IT.UTF-8 LOCALES+= ja_JP.SJIS LOCALES+= ja_JP.UTF-8 LOCALES+= ja_JP.eucJP -LOCALES+= kk_Cyrl_KZ.UTF-8 +LOCALES+= kk_KZ.UTF-8 LOCALES+= ko_KR.UTF-8 LOCALES+= ko_KR.eucKR LOCALES+= lt_LT.ISO8859-13 LOCALES+= lt_LT.UTF-8 LOCALES+= lv_LV.ISO8859-13 LOCALES+= lv_LV.UTF-8 -LOCALES+= mn_Cyrl_MN.UTF-8 +LOCALES+= mn_MN.UTF-8 LOCALES+= nb_NO.ISO8859-15 LOCALES+= nb_NO.UTF-8 LOCALES+= nl_BE.UTF-8 @@ -109,10 +109,10 @@ LOCALES+= sk_SK.ISO8859-2 LOCALES+= sk_SK.UTF-8 LOCALES+= sl_SI.ISO8859-2 LOCALES+= sl_SI.UTF-8 -LOCALES+= sr_Cyrl_RS.ISO8859-5 -LOCALES+= sr_Cyrl_RS.UTF-8 -LOCALES+= sr_Latn_RS.ISO8859-2 -LOCALES+= sr_Latn_RS.UTF-8 +LOCALES+= sr_RS.ISO8859-5 +LOCALES+= sr_RS.UTF-8 +LOCALES+= sr_RS.ISO8859-2 +LOCALES+= sr_RS.UTF-8@latin LOCALES+= sv_FI.ISO8859-15 LOCALES+= sv_FI.UTF-8 LOCALES+= sv_SE.ISO8859-15 @@ -123,13 +123,13 @@ LOCALES+= uk_UA.CP1251 LOCALES+= uk_UA.ISO8859-5 LOCALES+= uk_UA.KOI8-U LOCALES+= uk_UA.UTF-8 -LOCALES+= zh_Hans_CN.GB2312 -LOCALES+= zh_Hans_CN.GBK -LOCALES+= zh_Hans_CN.UTF-8 -LOCALES+= zh_Hans_CN.eucCN -LOCALES+= zh_Hant_HK.UTF-8 -LOCALES+= zh_Hant_TW.Big5 -LOCALES+= zh_Hant_TW.UTF-8 +LOCALES+= zh_CN.GB2312 +LOCALES+= zh_CN.GBK +LOCALES+= zh_CN.UTF-8 +LOCALES+= zh_CN.eucCN +LOCALES+= zh_HK.UTF-8 +LOCALES+= zh_TW.Big5 +LOCALES+= zh_TW.UTF-8 @@ -201,7 +201,7 @@ SAME+= nn_NO.ISO8859-15 nn_NO.ISO8859-1 SAME+= pt_PT.ISO8859-15 pt_PT.ISO8859-1 SAME+= sv_FI.ISO8859-15 sv_FI.ISO8859-1 SAME+= sv_SE.ISO8859-15 sv_SE.ISO8859-1 -SAME+= zh_Hans_CN.GBK zh_Hans_CN.GB18030 +SAME+= zh_CN.GBK zh_CN.GB18030 SAME+= ko_KR.eucKR ko_KR.CP949 # legacy (same charset) FILES= ${LOCALES:S/$/.out/} diff --git a/share/timedef/kk_Cyrl_KZ.UTF-8.src b/share/timedef/kk_KZ.UTF-8.src index 822b115..822b115 100644 --- a/share/timedef/kk_Cyrl_KZ.UTF-8.src +++ b/share/timedef/kk_KZ.UTF-8.src diff --git a/share/timedef/mn_Cyrl_MN.UTF-8.src b/share/timedef/mn_MN.UTF-8.src index fd4fa05..fd4fa05 100644 --- a/share/timedef/mn_Cyrl_MN.UTF-8.src +++ b/share/timedef/mn_MN.UTF-8.src diff --git a/share/timedef/sr_Latn_RS.ISO8859-2.src b/share/timedef/sr_RS.ISO8859-2.src index c9254fc..c9254fc 100644 --- a/share/timedef/sr_Latn_RS.ISO8859-2.src +++ b/share/timedef/sr_RS.ISO8859-2.src diff --git a/share/timedef/sr_Cyrl_RS.ISO8859-5.src b/share/timedef/sr_RS.ISO8859-5.src index 99e50b6..99e50b6 100644 --- a/share/timedef/sr_Cyrl_RS.ISO8859-5.src +++ b/share/timedef/sr_RS.ISO8859-5.src diff --git a/share/timedef/sr_Cyrl_RS.UTF-8.src b/share/timedef/sr_RS.UTF-8.src index 096d929..096d929 100644 --- a/share/timedef/sr_Cyrl_RS.UTF-8.src +++ b/share/timedef/sr_RS.UTF-8.src diff --git a/share/timedef/sr_Latn_RS.UTF-8.src b/share/timedef/sr_RS.UTF-8@latin.src index 2f22f70..2f22f70 100644 --- a/share/timedef/sr_Latn_RS.UTF-8.src +++ b/share/timedef/sr_RS.UTF-8@latin.src diff --git a/share/timedef/zh_Hans_CN.GB2312.src b/share/timedef/zh_CN.GB2312.src index efa11cd..efa11cd 100644 --- a/share/timedef/zh_Hans_CN.GB2312.src +++ b/share/timedef/zh_CN.GB2312.src diff --git a/share/timedef/zh_Hans_CN.GBK.src b/share/timedef/zh_CN.GBK.src index 9f5dd0f..9f5dd0f 100644 --- a/share/timedef/zh_Hans_CN.GBK.src +++ b/share/timedef/zh_CN.GBK.src diff --git a/share/timedef/zh_Hans_CN.UTF-8.src b/share/timedef/zh_CN.UTF-8.src index 9c994d4..9c994d4 100644 --- a/share/timedef/zh_Hans_CN.UTF-8.src +++ b/share/timedef/zh_CN.UTF-8.src diff --git a/share/timedef/zh_Hans_CN.eucCN.src b/share/timedef/zh_CN.eucCN.src index 5589bf9..5589bf9 100644 --- a/share/timedef/zh_Hans_CN.eucCN.src +++ b/share/timedef/zh_CN.eucCN.src diff --git a/share/timedef/zh_Hant_HK.UTF-8.src b/share/timedef/zh_HK.UTF-8.src index afd3217..afd3217 100644 --- a/share/timedef/zh_Hant_HK.UTF-8.src +++ b/share/timedef/zh_HK.UTF-8.src diff --git a/share/timedef/zh_Hant_TW.Big5.src b/share/timedef/zh_TW.Big5.src index 012b870..012b870 100644 --- a/share/timedef/zh_Hant_TW.Big5.src +++ b/share/timedef/zh_TW.Big5.src diff --git a/share/timedef/zh_Hant_TW.UTF-8.src b/share/timedef/zh_TW.UTF-8.src index 9b84865..9b84865 100644 --- a/share/timedef/zh_Hant_TW.UTF-8.src +++ b/share/timedef/zh_TW.UTF-8.src diff --git a/sys/amd64/conf/GENERIC b/sys/amd64/conf/GENERIC index 2859de5..6f68eb3 100644 --- a/sys/amd64/conf/GENERIC +++ b/sys/amd64/conf/GENERIC @@ -81,15 +81,6 @@ options RCTL # Resource limits # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. -# For full debugger support use (turn off in stable branch): -options DDB # Support DDB. -options GDB # Support remote GDB. -options DEADLKRES # Enable the deadlock resolver -options INVARIANTS # Enable calls of extra sanity checking -options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS -options WITNESS # Enable checks to detect deadlocks and cycles -options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed -options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones # Make an SMP-capable kernel by default options SMP # Symmetric MultiProcessor Kernel diff --git a/sys/amd64/include/counter.h b/sys/amd64/include/counter.h index b571e70..a79eab4 100644 --- a/sys/amd64/include/counter.h +++ b/sys/amd64/include/counter.h @@ -51,7 +51,7 @@ counter_u64_fetch_inline(uint64_t *p) int i; r = 0; - for (i = 0; i < mp_ncpus; i++) + CPU_FOREACH(i) r += counter_u64_read_one((uint64_t *)p, i); return (r); diff --git a/sys/arm/ti/cpsw/if_cpsw.c b/sys/arm/ti/cpsw/if_cpsw.c index 9358183..70204c0 100644 --- a/sys/arm/ti/cpsw/if_cpsw.c +++ b/sys/arm/ti/cpsw/if_cpsw.c @@ -1874,6 +1874,7 @@ cpswp_tx_enqueue(struct cpswp_softc *sc) return; } else if (last_old_slot == NULL) { /* Start a fresh queue. */ + sc->swsc->last_hdp = cpsw_cpdma_bd_paddr(sc->swsc, first_new_slot); cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); } else { /* Add buffers to end of current queue. */ @@ -1882,6 +1883,7 @@ cpswp_tx_enqueue(struct cpswp_softc *sc) /* If underrun, restart queue. */ if (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) & CPDMA_BD_EOQ) { + sc->swsc->last_hdp = cpsw_cpdma_bd_paddr(sc->swsc, first_new_slot); cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); } @@ -1897,6 +1899,7 @@ static int cpsw_tx_dequeue(struct cpsw_softc *sc) { struct cpsw_slot *slot, *last_removed_slot = NULL; + struct cpsw_cpdma_bd bd; uint32_t flags, removed = 0; slot = STAILQ_FIRST(&sc->tx.active); @@ -1931,13 +1934,26 @@ cpsw_tx_dequeue(struct cpsw_softc *sc) } /* TearDown complete is only marked on the SOP for the packet. */ - if (flags & CPDMA_BD_TDOWNCMPLT) { + if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) == + (CPDMA_BD_EOP | CPDMA_BD_TDOWNCMPLT)) { CPSW_DEBUGF(sc, ("TX teardown in progress")); cpsw_write_cp(sc, &sc->tx, 0xfffffffc); // TODO: Increment a count of dropped TX packets sc->tx.running = 0; break; } + + if ((flags & CPDMA_BD_EOP) == 0) + flags = cpsw_cpdma_read_bd_flags(sc, last_removed_slot); + if ((flags & (CPDMA_BD_EOP | CPDMA_BD_EOQ)) == + (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { + cpsw_cpdma_read_bd(sc, last_removed_slot, &bd); + if (bd.next != 0 && bd.next != sc->last_hdp) { + /* Restart the queue. */ + sc->last_hdp = bd.next; + cpsw_write_4(sc, sc->tx.hdp_offset, bd.next); + } + } } if (removed != 0) { diff --git a/sys/arm/ti/cpsw/if_cpswvar.h b/sys/arm/ti/cpsw/if_cpswvar.h index adf2a37..953766b 100644 --- a/sys/arm/ti/cpsw/if_cpswvar.h +++ b/sys/arm/ti/cpsw/if_cpswvar.h @@ -83,6 +83,7 @@ struct cpsw_softc { /* RX and TX buffer tracking */ struct cpsw_queue rx, tx; + uint32_t last_hdp; /* We expect 1 memory resource and 4 interrupts from the device tree. */ int mem_rid; diff --git a/sys/arm64/arm64/gic.c b/sys/arm64/arm64/gic.c deleted file mode 100644 index 68b7cab..0000000 --- a/sys/arm64/arm64/gic.c +++ /dev/null @@ -1,496 +0,0 @@ -/*- - * Copyright (c) 2011 The FreeBSD Foundation - * Copyright (c) 2014 Andrew Turner - * All rights reserved. - * - * Developed by Damjan Marion <damjan.marion@gmail.com> - * - * Based on OMAP4 GIC code by Ben Gray - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/ktr.h> -#include <sys/module.h> -#include <sys/rman.h> -#include <sys/pcpu.h> -#include <sys/proc.h> -#include <sys/cpuset.h> -#include <sys/lock.h> -#include <sys/mutex.h> - -#include <machine/bus.h> -#include <machine/intr.h> -#include <machine/smp.h> - -#include <vm/vm.h> -#include <vm/pmap.h> - -#include <arm64/arm64/gic.h> - -#include "pic_if.h" - -/* We are using GICv2 register naming */ - -/* Distributor Registers */ -#define GICD_CTLR 0x000 /* v1 ICDDCR */ -#define GICD_TYPER 0x004 /* v1 ICDICTR */ -#define GICD_IIDR 0x008 /* v1 ICDIIDR */ -#define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */ -#define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */ -#define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */ -#define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */ -#define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */ -#define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */ -#define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */ -#define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */ -#define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */ -#define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */ -#define GICD_SGI_TARGET_SHIFT 16 - -/* CPU Registers */ -#define GICC_CTLR 0x0000 /* v1 ICCICR */ -#define GICC_PMR 0x0004 /* v1 ICCPMR */ -#define GICC_BPR 0x0008 /* v1 ICCBPR */ -#define GICC_IAR 0x000C /* v1 ICCIAR */ -#define GICC_EOIR 0x0010 /* v1 ICCEOIR */ -#define GICC_RPR 0x0014 /* v1 ICCRPR */ -#define GICC_HPPIR 0x0018 /* v1 ICCHPIR */ -#define GICC_ABPR 0x001C /* v1 ICCABPR */ -#define GICC_IIDR 0x00FC /* v1 ICCIIDR*/ - -#define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */ -#define GIC_LAST_IPI 15 -#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ -#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ -#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ - -/* TYPER Registers */ -#define GICD_TYPER_SECURITYEXT 0x400 -#define GIC_SUPPORT_SECEXT(_sc) \ - ((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT) - -/* First bit is a polarity bit (0 - low, 1 - high) */ -#define GICD_ICFGR_POL_LOW (0 << 0) -#define GICD_ICFGR_POL_HIGH (1 << 0) -#define GICD_ICFGR_POL_MASK 0x1 -/* Second bit is a trigger bit (0 - level, 1 - edge) */ -#define GICD_ICFGR_TRIG_LVL (0 << 1) -#define GICD_ICFGR_TRIG_EDGE (1 << 1) -#define GICD_ICFGR_TRIG_MASK 0x2 - -static struct resource_spec arm_gic_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */ - { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */ - { -1, 0 } -}; - -static u_int arm_gic_map[MAXCPU]; - -static struct arm_gic_softc *arm_gic_sc = NULL; - -#define gic_c_read_4(_sc, _reg) \ - bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg)) -#define gic_c_write_4(_sc, _reg, _val) \ - bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val)) -#define gic_d_read_4(_sc, _reg) \ - bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg)) -#define gic_d_write_4(_sc, _reg, _val) \ - bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val)) - -static pic_dispatch_t gic_dispatch; -static pic_eoi_t gic_eoi; -static pic_mask_t gic_mask_irq; -static pic_unmask_t gic_unmask_irq; - -static uint8_t -gic_cpu_mask(struct arm_gic_softc *sc) -{ - uint32_t mask; - int i; - - /* Read the current cpuid mask by reading ITARGETSR{0..7} */ - for (i = 0; i < 8; i++) { - mask = gic_d_read_4(sc, GICD_ITARGETSR(i)); - if (mask != 0) - break; - } - /* No mask found, assume we are on CPU interface 0 */ - if (mask == 0) - return (1); - - /* Collect the mask in the lower byte */ - mask |= mask >> 16; - mask |= mask >> 8; - - return (mask); -} - -#ifdef SMP -static void -gic_init_secondary(device_t dev) -{ - struct arm_gic_softc *sc = device_get_softc(dev); - int i; - - /* Set the mask so we can find this CPU to send it IPIs */ - arm_gic_map[PCPU_GET(cpuid)] = gic_cpu_mask(sc); - - for (i = 0; i < sc->nirqs; i += 4) - gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); - - /* Set all the interrupts to be in Group 0 (secure) */ - for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) { - gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); - } - - /* Enable CPU interface */ - gic_c_write_4(sc, GICC_CTLR, 1); - - /* Set priority mask register. */ - gic_c_write_4(sc, GICC_PMR, 0xff); - - /* Enable interrupt distribution */ - gic_d_write_4(sc, GICD_CTLR, 0x01); - - /* - * Activate the timer interrupts: virtual, secure, and non-secure. - */ - gic_d_write_4(sc, GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F))); - gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F))); - gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F))); -} -#endif - -int -arm_gic_attach(device_t dev) -{ - struct arm_gic_softc *sc; - int i; - uint32_t icciidr, mask; - - if (arm_gic_sc) - return (ENXIO); - - sc = device_get_softc(dev); - - if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) { - device_printf(dev, "could not allocate resources\n"); - return (ENXIO); - } - - sc->gic_dev = dev; - arm_gic_sc = sc; - - /* Initialize mutex */ - mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN); - - /* Distributor Interface */ - sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]); - sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]); - - /* CPU Interface */ - sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]); - sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]); - - /* Disable interrupt forwarding to the CPU interface */ - gic_d_write_4(sc, GICD_CTLR, 0x00); - - /* Get the number of interrupts */ - sc->typer = gic_d_read_4(sc, GICD_TYPER); - sc->nirqs = 32 * ((sc->typer & 0x1f) + 1); - - arm_register_root_pic(dev, sc->nirqs); - - icciidr = gic_c_read_4(sc, GICC_IIDR); - device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n", - icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf, - (icciidr & 0xfff), sc->nirqs); - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < sc->nirqs; i += 16) { - gic_d_write_4(sc, GICD_ICFGR(i >> 4), 0x00000000); - } - - /* Disable all interrupts. */ - for (i = 32; i < sc->nirqs; i += 32) { - gic_d_write_4(sc, GICD_ICENABLER(i >> 5), 0xFFFFFFFF); - } - - /* Find the current cpu mask */ - mask = gic_cpu_mask(sc); - /* Set the mask so we can find this CPU to send it IPIs */ - arm_gic_map[PCPU_GET(cpuid)] = mask; - /* Set all four targets to this cpu */ - mask |= mask << 8; - mask |= mask << 16; - - for (i = 0; i < sc->nirqs; i += 4) { - gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); - if (i > 32) { - gic_d_write_4(sc, GICD_ITARGETSR(i >> 2), mask); - } - } - - /* Set all the interrupts to be in Group 0 (secure) */ - for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) { - gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); - } - - /* Enable CPU interface */ - gic_c_write_4(sc, GICC_CTLR, 1); - - /* Set priority mask register. */ - gic_c_write_4(sc, GICC_PMR, 0xff); - - /* Enable interrupt distribution */ - gic_d_write_4(sc, GICD_CTLR, 0x01); - - return (0); -} - -static void gic_dispatch(device_t dev, struct trapframe *frame) -{ - struct arm_gic_softc *sc = device_get_softc(dev); - uint32_t active_irq; - int first = 1; - - while (1) { - active_irq = gic_c_read_4(sc, GICC_IAR); - - /* - * Immediatly EOIR the SGIs, because doing so requires the other - * bits (ie CPU number), not just the IRQ number, and we do not - * have this information later. - */ - - if ((active_irq & 0x3ff) <= GIC_LAST_IPI) - gic_c_write_4(sc, GICC_EOIR, active_irq); - active_irq &= 0x3FF; - - if (active_irq == 0x3FF) { - if (first) - printf("Spurious interrupt detected\n"); - return; - } - - arm_dispatch_intr(active_irq, frame); - first = 0; - } -} - -static void -gic_eoi(device_t dev, u_int irq) -{ - struct arm_gic_softc *sc = device_get_softc(dev); - - gic_c_write_4(sc, GICC_EOIR, irq); -} - -void -gic_mask_irq(device_t dev, u_int irq) -{ - struct arm_gic_softc *sc = device_get_softc(dev); - - gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F))); - gic_c_write_4(sc, GICC_EOIR, irq); -} - -void -gic_unmask_irq(device_t dev, u_int irq) -{ - struct arm_gic_softc *sc = device_get_softc(dev); - - gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F))); -} - -#ifdef SMP -static void -gic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi) -{ - struct arm_gic_softc *sc = device_get_softc(dev); - uint32_t val = 0, i; - - for (i = 0; i < MAXCPU; i++) - if (CPU_ISSET(i, &cpus)) - val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT; - - gic_d_write_4(sc, GICD_SGIR(0), val | ipi); -} -#endif - -static device_method_t arm_gic_methods[] = { - /* Device interface */ - DEVMETHOD(device_attach, arm_gic_attach), - - /* pic_if */ - DEVMETHOD(pic_dispatch, gic_dispatch), - DEVMETHOD(pic_eoi, gic_eoi), - DEVMETHOD(pic_mask, gic_mask_irq), - DEVMETHOD(pic_unmask, gic_unmask_irq), - -#ifdef SMP - DEVMETHOD(pic_init_secondary, gic_init_secondary), - DEVMETHOD(pic_ipi_send, gic_ipi_send), -#endif - - { 0, 0 } -}; - -DEFINE_CLASS_0(gic, arm_gic_driver, arm_gic_methods, - sizeof(struct arm_gic_softc)); - -#define GICV2M_MSI_TYPER 0x008 -#define MSI_TYPER_SPI_BASE(x) (((x) >> 16) & 0x3ff) -#define MSI_TYPER_SPI_COUNT(x) (((x) >> 0) & 0x3ff) -#define GICv2M_MSI_SETSPI_NS 0x040 -#define GICV2M_MSI_IIDR 0xFCC - -static int -gicv2m_attach(device_t dev) -{ - struct gicv2m_softc *sc; - uint32_t typer; - int rid; - - sc = device_get_softc(dev); - - rid = 0; - sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (sc->sc_mem == NULL) { - device_printf(dev, "Unable to allocate resources\n"); - return (ENXIO); - } - - typer = bus_read_4(sc->sc_mem, GICV2M_MSI_TYPER); - sc->sc_spi_start = MSI_TYPER_SPI_BASE(typer); - sc->sc_spi_count = MSI_TYPER_SPI_COUNT(typer); - - device_printf(dev, "using spi %u to %u\n", sc->sc_spi_start, - sc->sc_spi_start + sc->sc_spi_count - 1); - - mtx_init(&sc->sc_mutex, "GICv2m lock", "", MTX_DEF); - - arm_register_msi_pic(dev); - - return (0); -} - -static int -gicv2m_alloc_msix(device_t dev, device_t pci_dev, int *pirq) -{ - struct arm_gic_softc *psc; - struct gicv2m_softc *sc; - uint32_t reg; - int irq; - - psc = device_get_softc(device_get_parent(dev)); - sc = device_get_softc(dev); - - mtx_lock(&sc->sc_mutex); - /* Find an unused interrupt */ - KASSERT(sc->sc_spi_offset < sc->sc_spi_count, ("No free SPIs")); - - irq = sc->sc_spi_start + sc->sc_spi_offset; - sc->sc_spi_offset++; - - /* Interrupts need to be edge triggered, set this */ - reg = gic_d_read_4(psc, GICD_ICFGR(irq >> 4)); - reg |= (GICD_ICFGR_TRIG_EDGE | GICD_ICFGR_POL_HIGH) << - ((irq & 0xf) * 2); - gic_d_write_4(psc, GICD_ICFGR(irq >> 4), reg); - - *pirq = irq; - mtx_unlock(&sc->sc_mutex); - - return (0); -} - -static int -gicv2m_alloc_msi(device_t dev, device_t pci_dev, int count, int *irqs) -{ - struct arm_gic_softc *psc; - struct gicv2m_softc *sc; - uint32_t reg; - int i, irq; - - psc = device_get_softc(device_get_parent(dev)); - sc = device_get_softc(dev); - - mtx_lock(&sc->sc_mutex); - KASSERT(sc->sc_spi_offset + count <= sc->sc_spi_count, - ("No free SPIs for %d MSI interrupts", count)); - - /* Find an unused interrupt */ - for (i = 0; i < count; i++) { - irq = sc->sc_spi_start + sc->sc_spi_offset; - sc->sc_spi_offset++; - - /* Interrupts need to be edge triggered, set this */ - reg = gic_d_read_4(psc, GICD_ICFGR(irq >> 4)); - reg |= (GICD_ICFGR_TRIG_EDGE | GICD_ICFGR_POL_HIGH) << - ((irq & 0xf) * 2); - gic_d_write_4(psc, GICD_ICFGR(irq >> 4), reg); - - irqs[i] = irq; - } - mtx_unlock(&sc->sc_mutex); - - return (0); -} - -static int -gicv2m_map_msi(device_t dev, device_t pci_dev, int irq, uint64_t *addr, - uint32_t *data) -{ - struct gicv2m_softc *sc = device_get_softc(dev); - - *addr = vtophys(rman_get_virtual(sc->sc_mem)) + 0x40; - *data = irq; - - return (0); -} - -static device_method_t arm_gicv2m_methods[] = { - /* Device interface */ - DEVMETHOD(device_attach, gicv2m_attach), - - /* MSI/MSI-X */ - DEVMETHOD(pic_alloc_msix, gicv2m_alloc_msix), - DEVMETHOD(pic_alloc_msi, gicv2m_alloc_msi), - DEVMETHOD(pic_map_msi, gicv2m_map_msi), - - { 0, 0 } -}; - -DEFINE_CLASS_0(gicv2m, arm_gicv2m_driver, arm_gicv2m_methods, - sizeof(struct gicv2m_softc)); diff --git a/sys/arm64/arm64/gic_acpi.c b/sys/arm64/arm64/gic_acpi.c deleted file mode 100644 index ad26c0c..0000000 --- a/sys/arm64/arm64/gic_acpi.c +++ /dev/null @@ -1,161 +0,0 @@ -/*- - * Copyright (c) 2015 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Andrew Turner under - * sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/types.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> - -#include <machine/bus.h> - -#include <arm64/arm64/gic.h> - -#include <contrib/dev/acpica/include/acpi.h> - -#include <dev/acpica/acpivar.h> - -struct arm_gic_acpi_softc { - struct arm_gic_softc gic_sc; - struct resource_list res; -}; - -struct madt_table_data { - device_t parent; - ACPI_MADT_GENERIC_DISTRIBUTOR *dist; - ACPI_MADT_GENERIC_INTERRUPT *intr; -}; - -static void -madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg) -{ - struct madt_table_data *madt_data; - - madt_data = (struct madt_table_data *)arg; - - switch(entry->Type) { - case ACPI_MADT_TYPE_GENERIC_INTERRUPT: - if (madt_data->intr != NULL) { - if (bootverbose) - device_printf(madt_data->parent, - "gic: Already have an interrupt table"); - break; - } - - madt_data->intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry; - break; - - case ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR: - if (madt_data->dist != NULL) { - if (bootverbose) - device_printf(madt_data->parent, - "gic: Already have a distributor table"); - break; - } - - madt_data->dist = (ACPI_MADT_GENERIC_DISTRIBUTOR *)entry; - break; - - default: - break; - } -} - -static void -arm_gic_acpi_identify(driver_t *driver, device_t parent) -{ - struct madt_table_data madt_data; - ACPI_TABLE_MADT *madt; - vm_paddr_t physaddr; - device_t dev; - - physaddr = acpi_find_table(ACPI_SIG_MADT); - if (physaddr == 0) - return; - - madt = acpi_map_table(physaddr, ACPI_SIG_MADT); - if (madt == NULL) { - device_printf(parent, "gic: Unable to map the MADT\n"); - return; - } - - madt_data.parent = parent; - madt_data.dist = NULL; - madt_data.intr = NULL; - - acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length, - madt_handler, &madt_data); - if (madt_data.intr == NULL || madt_data.dist == NULL) { - device_printf(parent, - "No gic interrupt or distributor table\n"); - goto out; - } - - dev = BUS_ADD_CHILD(parent, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE, - "gic", -1); - if (dev == NULL) { - device_printf(parent, "add gic child failed\n"); - goto out; - } - - /* Add the MADT data */ - BUS_SET_RESOURCE(parent, dev, SYS_RES_MEMORY, 0, - madt_data.dist->BaseAddress, PAGE_SIZE); - BUS_SET_RESOURCE(parent, dev, SYS_RES_MEMORY, 1, - madt_data.intr->BaseAddress, PAGE_SIZE); - -out: - acpi_unmap_table(madt); -} - -static int -arm_gic_acpi_probe(device_t dev) -{ - - device_set_desc(dev, "ARM Generic Interrupt Controller"); - return (BUS_PROBE_NOWILDCARD); -} - -static device_method_t arm_gic_acpi_methods[] = { - /* Device interface */ - DEVMETHOD(device_identify, arm_gic_acpi_identify), - DEVMETHOD(device_probe, arm_gic_acpi_probe), - - DEVMETHOD_END -}; - -DEFINE_CLASS_1(gic, arm_gic_acpi_driver, arm_gic_acpi_methods, - sizeof(struct arm_gic_acpi_softc), arm_gic_driver); - -static devclass_t arm_gic_acpi_devclass; - -EARLY_DRIVER_MODULE(gic, acpi, arm_gic_acpi_driver, - arm_gic_acpi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/arm64/arm64/gic_fdt.c b/sys/arm64/arm64/gic_fdt.c deleted file mode 100644 index f92cd83..0000000 --- a/sys/arm64/arm64/gic_fdt.c +++ /dev/null @@ -1,332 +0,0 @@ -/*- - * Copyright (c) 2015 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Andrew Turner under - * sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/rman.h> - -#include <machine/bus.h> - -#include <dev/ofw/openfirm.h> -#include <dev/ofw/ofw_bus.h> -#include <dev/ofw/ofw_bus_subr.h> - -#include <arm64/arm64/gic.h> - -static struct ofw_compat_data compat_data[] = { - {"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */ - {"arm,gic-400", true}, - {"arm,cortex-a15-gic", true}, - {"arm,cortex-a9-gic", true}, - {"arm,cortex-a7-gic", true}, - {"arm,arm11mp-gic", true}, - {"brcm,brahma-b15-gic", true}, - {"qcom,msm-qgic2", true}, - {NULL, false} -}; - -struct gic_range { - uint64_t bus; - uint64_t host; - uint64_t size; -}; - -struct arm_gic_fdt_softc { - struct arm_gic_softc sc_gic; - pcell_t sc_host_cells; - pcell_t sc_addr_cells; - pcell_t sc_size_cells; - struct gic_range *sc_ranges; - int sc_nranges; -}; - -struct gic_devinfo { - struct ofw_bus_devinfo obdinfo; - struct resource_list rl; -}; - -static int -gic_fill_ranges(phandle_t node, struct arm_gic_fdt_softc *sc) -{ - cell_t *base_ranges; - ssize_t nbase_ranges; - int i, j, k; - - nbase_ranges = OF_getproplen(node, "ranges"); - if (nbase_ranges < 0) - return (-1); - sc->sc_nranges = nbase_ranges / sizeof(cell_t) / - (sc->sc_addr_cells + sc->sc_host_cells + sc->sc_size_cells); - if (sc->sc_nranges == 0) - return (0); - - sc->sc_ranges = malloc(sc->sc_nranges * sizeof(sc->sc_ranges[0]), - M_DEVBUF, M_WAITOK); - base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); - OF_getencprop(node, "ranges", base_ranges, nbase_ranges); - - for (i = 0, j = 0; i < sc->sc_nranges; i++) { - sc->sc_ranges[i].bus = 0; - for (k = 0; k < sc->sc_addr_cells; k++) { - sc->sc_ranges[i].bus <<= 32; - sc->sc_ranges[i].bus |= base_ranges[j++]; - } - sc->sc_ranges[i].host = 0; - for (k = 0; k < sc->sc_host_cells; k++) { - sc->sc_ranges[i].host <<= 32; - sc->sc_ranges[i].host |= base_ranges[j++]; - } - sc->sc_ranges[i].size = 0; - for (k = 0; k < sc->sc_size_cells; k++) { - sc->sc_ranges[i].size <<= 32; - sc->sc_ranges[i].size |= base_ranges[j++]; - } - } - - free(base_ranges, M_DEVBUF); - return (sc->sc_nranges); -} - -static int -arm_gic_fdt_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) - return (ENXIO); - - device_set_desc(dev, "ARM Generic Interrupt Controller"); - return (BUS_PROBE_DEFAULT); -} - -static int -arm_gic_fdt_attach(device_t dev) -{ - struct arm_gic_fdt_softc *sc = device_get_softc(dev); - phandle_t root, child; - struct gic_devinfo *dinfo; - device_t cdev; - int err; - - err = arm_gic_attach(dev); - if (err != 0) - return (err); - - root = ofw_bus_get_node(dev); - - sc->sc_host_cells = 1; - OF_getencprop(OF_parent(root), "#address-cells", &sc->sc_host_cells, - sizeof(sc->sc_host_cells)); - sc->sc_addr_cells = 2; - OF_getencprop(root, "#address-cells", &sc->sc_addr_cells, - sizeof(sc->sc_addr_cells)); - sc->sc_size_cells = 2; - OF_getencprop(root, "#size-cells", &sc->sc_size_cells, - sizeof(sc->sc_size_cells)); - - /* If we have no children don't probe for them */ - child = OF_child(root); - if (child == 0) - return (0); - - if (gic_fill_ranges(root, sc) < 0) { - device_printf(dev, "could not get ranges\n"); - return (ENXIO); - } - - for (; child != 0; child = OF_peer(child)) { - dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_WAITOK | M_ZERO); - - if (ofw_bus_gen_setup_devinfo(&dinfo->obdinfo, child) != 0) { - free(dinfo, M_DEVBUF); - continue; - } - - resource_list_init(&dinfo->rl); - ofw_bus_reg_to_rl(dev, child, sc->sc_addr_cells, - sc->sc_size_cells, &dinfo->rl); - - cdev = device_add_child(dev, NULL, -1); - if (cdev == NULL) { - device_printf(dev, "<%s>: device_add_child failed\n", - dinfo->obdinfo.obd_name); - resource_list_free(&dinfo->rl); - ofw_bus_gen_destroy_devinfo(&dinfo->obdinfo); - free(dinfo, M_DEVBUF); - continue; - } - device_set_ivars(cdev, dinfo); - } - - bus_generic_probe(dev); - return (bus_generic_attach(dev)); -} - -static struct resource * -arm_gic_fdt_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct arm_gic_fdt_softc *sc = device_get_softc(bus); - struct gic_devinfo *di; - struct resource_list_entry *rle; - int j; - - KASSERT(type == SYS_RES_MEMORY, ("Invalid resoure type %x", type)); - - /* - * Request for the default allocation with a given rid: use resource - * list stored in the local device info. - */ - if (RMAN_IS_DEFAULT_RANGE(start, end)) { - if ((di = device_get_ivars(child)) == NULL) - return (NULL); - - if (type == SYS_RES_IOPORT) - type = SYS_RES_MEMORY; - - rle = resource_list_find(&di->rl, type, *rid); - if (rle == NULL) { - if (bootverbose) - device_printf(bus, "no default resources for " - "rid = %d, type = %d\n", *rid, type); - return (NULL); - } - start = rle->start; - end = rle->end; - count = rle->count; - } - - /* Remap through ranges property */ - for (j = 0; j < sc->sc_nranges; j++) { - if (start >= sc->sc_ranges[j].bus && end < - sc->sc_ranges[j].bus + sc->sc_ranges[j].size) { - start -= sc->sc_ranges[j].bus; - start += sc->sc_ranges[j].host; - end -= sc->sc_ranges[j].bus; - end += sc->sc_ranges[j].host; - break; - } - } - if (j == sc->sc_nranges && sc->sc_nranges != 0) { - if (bootverbose) - device_printf(bus, "Could not map resource " - "%#lx-%#lx\n", start, end); - - return (NULL); - } - - return (bus_generic_alloc_resource(bus, child, type, rid, start, end, - count, flags)); -} - -static const struct ofw_bus_devinfo * -arm_gic_fdt_ofw_get_devinfo(device_t bus __unused, device_t child) -{ - struct gic_devinfo *di; - - di = device_get_ivars(child); - - return (&di->obdinfo); -} - - -static device_method_t arm_gic_fdt_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, arm_gic_fdt_probe), - DEVMETHOD(device_attach, arm_gic_fdt_attach), - - /* Bus interface */ - DEVMETHOD(bus_add_child, bus_generic_add_child), - DEVMETHOD(bus_alloc_resource, arm_gic_fdt_alloc_resource), - DEVMETHOD(bus_release_resource, bus_generic_release_resource), - DEVMETHOD(bus_activate_resource,bus_generic_activate_resource), - - /* ofw_bus interface */ - DEVMETHOD(ofw_bus_get_devinfo, arm_gic_fdt_ofw_get_devinfo), - DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), - DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), - DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), - DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), - DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), - - DEVMETHOD_END -}; - -DEFINE_CLASS_1(gic, arm_gic_fdt_driver, arm_gic_fdt_methods, - sizeof(struct arm_gic_fdt_softc), arm_gic_driver); - -static devclass_t arm_gic_fdt_devclass; - -EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_fdt_driver, - arm_gic_fdt_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); -EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_fdt_driver, arm_gic_fdt_devclass, - 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); - -static struct ofw_compat_data gicv2m_compat_data[] = { - {"arm,gic-v2m-frame", true}, - {NULL, false} -}; - -static int -arm_gicv2m_fdt_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_search_compatible(dev, gicv2m_compat_data)->ocd_data) - return (ENXIO); - - device_set_desc(dev, "ARM Generic Interrupt Controller MSI/MSIX"); - return (BUS_PROBE_DEFAULT); -} - -static device_method_t arm_gicv2m_fdt_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, arm_gicv2m_fdt_probe), - - /* End */ - DEVMETHOD_END -}; - -DEFINE_CLASS_1(gicv2m, arm_gicv2m_fdt_driver, arm_gicv2m_fdt_methods, - sizeof(struct gicv2m_softc), arm_gicv2m_driver); - -static devclass_t arm_gicv2m_fdt_devclass; - -EARLY_DRIVER_MODULE(gicv2m, gic, arm_gicv2m_fdt_driver, - arm_gicv2m_fdt_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/arm64/arm64/gic_v3_its.c b/sys/arm64/arm64/gic_v3_its.c deleted file mode 100644 index c16cf0a..0000000 --- a/sys/arm64/arm64/gic_v3_its.c +++ /dev/null @@ -1,1805 +0,0 @@ -/*- - * Copyright (c) 2015 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Semihalf under - * the sponsorship of the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bitset.h> -#include <sys/bitstring.h> -#include <sys/bus.h> -#include <sys/endian.h> -#include <sys/kernel.h> -#include <sys/malloc.h> -#include <sys/rman.h> -#include <sys/pciio.h> -#include <sys/pcpu.h> -#include <sys/lock.h> -#include <sys/mutex.h> -#include <sys/smp.h> - -#include <dev/pci/pcireg.h> -#include <dev/pci/pcivar.h> - -#include <vm/vm.h> -#include <vm/pmap.h> - -#include <machine/bus.h> -#include <machine/cpu.h> -#include <machine/cpufunc.h> -#include <machine/intr.h> - -#include "gic_v3_reg.h" -#include "gic_v3_var.h" - -#define GIC_V3_ITS_QUIRK_THUNDERX_PEM_BUS_OFFSET 88 - -#include "pic_if.h" -#include "pcib_if.h" - -/* Device and PIC methods */ -static int gic_v3_its_attach(device_t); - -static device_method_t gic_v3_its_methods[] = { - /* Device interface */ - DEVMETHOD(device_attach, gic_v3_its_attach), - /* - * PIC interface - */ - /* MSI-X */ - DEVMETHOD(pic_alloc_msix, gic_v3_its_alloc_msix), - DEVMETHOD(pic_release_msix, gic_v3_its_release_msix), - /* MSI */ - DEVMETHOD(pic_alloc_msi, gic_v3_its_alloc_msi), - DEVMETHOD(pic_release_msi, gic_v3_its_release_msi), - DEVMETHOD(pic_map_msi, gic_v3_its_map_msi), - - /* End */ - DEVMETHOD_END -}; - -DEFINE_CLASS_0(its, gic_v3_its_driver, gic_v3_its_methods, - sizeof(struct gic_v3_its_softc)); - -MALLOC_DEFINE(M_GIC_V3_ITS, "GICv3 ITS", GIC_V3_ITS_DEVSTR); - -static int its_alloc_tables(struct gic_v3_its_softc *); -static void its_free_tables(struct gic_v3_its_softc *); -static void its_init_commandq(struct gic_v3_its_softc *); -static void its_init_cpu_collection(struct gic_v3_its_softc *); -static uint32_t its_get_devid(device_t); -static struct its_dev * its_device_find_locked(struct gic_v3_its_softc *, - device_t, uint32_t); - -static int its_cmd_send(struct gic_v3_its_softc *, struct its_cmd_desc *); - -static void its_cmd_movi(struct gic_v3_its_softc *, struct its_dev *, - struct its_col *, uint32_t); -static void its_cmd_mapc(struct gic_v3_its_softc *, struct its_col *, uint8_t); -static void its_cmd_mapvi(struct gic_v3_its_softc *, struct its_dev *, uint32_t, - uint32_t); -static void its_cmd_mapi(struct gic_v3_its_softc *, struct its_dev *, uint32_t); -static void its_cmd_inv(struct gic_v3_its_softc *, struct its_dev *, uint32_t); -static void its_cmd_invall(struct gic_v3_its_softc *, struct its_col *); - -static uint32_t its_get_devbits(device_t); - -static void lpi_init_conftable(struct gic_v3_its_softc *); -static void lpi_bitmap_init(struct gic_v3_its_softc *); -static int lpi_config_cpu(struct gic_v3_its_softc *); -static void lpi_alloc_cpu_pendtables(struct gic_v3_its_softc *); - -const char *its_ptab_cache[] = { - [GITS_BASER_CACHE_NCNB] = "(NC,NB)", - [GITS_BASER_CACHE_NC] = "(NC)", - [GITS_BASER_CACHE_RAWT] = "(RA,WT)", - [GITS_BASER_CACHE_RAWB] = "(RA,WB)", - [GITS_BASER_CACHE_WAWT] = "(WA,WT)", - [GITS_BASER_CACHE_WAWB] = "(WA,WB)", - [GITS_BASER_CACHE_RAWAWT] = "(RAWA,WT)", - [GITS_BASER_CACHE_RAWAWB] = "(RAWA,WB)", -}; - -const char *its_ptab_share[] = { - [GITS_BASER_SHARE_NS] = "none", - [GITS_BASER_SHARE_IS] = "inner", - [GITS_BASER_SHARE_OS] = "outer", - [GITS_BASER_SHARE_RES] = "none", -}; - -const char *its_ptab_type[] = { - [GITS_BASER_TYPE_UNIMPL] = "Unimplemented", - [GITS_BASER_TYPE_DEV] = "Devices", - [GITS_BASER_TYPE_VP] = "Virtual Processors", - [GITS_BASER_TYPE_PP] = "Physical Processors", - [GITS_BASER_TYPE_IC] = "Interrupt Collections", - [GITS_BASER_TYPE_RES5] = "Reserved (5)", - [GITS_BASER_TYPE_RES6] = "Reserved (6)", - [GITS_BASER_TYPE_RES7] = "Reserved (7)", -}; - -/* - * Vendor specific quirks. - * One needs to add appropriate entry to its_quirks[] - * table if the imlementation varies from the generic ARM ITS. - */ - -/* Cavium ThunderX PCI devid acquire function */ -static uint32_t its_get_devbits_thunder(device_t); - -static const struct its_quirks its_quirks[] = { - { - /* - * Hardware: Cavium ThunderX - * Chip revision: Pass 1.0, Pass 1.1 - */ - .cpuid = CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0), - .cpuid_mask = CPU_IMPL_MASK | CPU_PART_MASK, - .devbits_func = its_get_devbits_thunder, - }, -}; - -static struct gic_v3_its_softc *its_sc; - -#define gic_its_read(sc, len, reg) \ - bus_read_##len(&sc->its_res[0], reg) - -#define gic_its_write(sc, len, reg, val) \ - bus_write_##len(&sc->its_res[0], reg, val) - -static int -gic_v3_its_attach(device_t dev) -{ - struct gic_v3_its_softc *sc; - uint64_t gits_tmp; - uint32_t gits_pidr2; - int rid; - int ret; - - sc = device_get_softc(dev); - - /* - * XXX ARM64TODO: Avoid configuration of more than one ITS - * device. To be removed when multi-PIC support is added - * to FreeBSD (or at least multi-ITS is implemented). Limit - * supported ITS sockets to '0' only. - */ - if (device_get_unit(dev) != 0) { - device_printf(dev, - "Only single instance of ITS is supported, exiting...\n"); - return (ENXIO); - } - sc->its_socket = 0; - - /* - * Initialize sleep & spin mutex for ITS - */ - /* Protects ITS device list and assigned LPIs bitmaps. */ - mtx_init(&sc->its_dev_lock, "ITS dev lock", NULL, MTX_SPIN); - /* Protects access to ITS command circular buffer. */ - mtx_init(&sc->its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN); - - rid = 0; - sc->its_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, - RF_ACTIVE); - if (sc->its_res == NULL) { - device_printf(dev, "Could not allocate memory\n"); - return (ENXIO); - } - - sc->dev = dev; - - gits_pidr2 = gic_its_read(sc, 4, GITS_PIDR2); - switch (gits_pidr2 & GITS_PIDR2_ARCH_MASK) { - case GITS_PIDR2_ARCH_GICv3: /* fall through */ - case GITS_PIDR2_ARCH_GICv4: - if (bootverbose) { - device_printf(dev, "ITS found. Architecture rev. %u\n", - (u_int)(gits_pidr2 & GITS_PIDR2_ARCH_MASK) >> 4); - } - break; - default: - device_printf(dev, "No ITS found in the system\n"); - gic_v3_its_detach(dev); - return (ENODEV); - } - - /* 1. Initialize commands queue */ - its_init_commandq(sc); - - /* 2. Provide memory for any private ITS tables */ - ret = its_alloc_tables(sc); - if (ret != 0) { - gic_v3_its_detach(dev); - return (ret); - } - - /* 3. Allocate collections. One per-CPU */ - for (int cpu = 0; cpu < mp_ncpus; cpu++) - if (CPU_ISSET(cpu, &all_cpus) != 0) - sc->its_cols[cpu] = malloc(sizeof(*sc->its_cols[0]), - M_GIC_V3_ITS, (M_WAITOK | M_ZERO)); - else - sc->its_cols[cpu] = NULL; - - /* 4. Enable ITS in GITS_CTLR */ - gits_tmp = gic_its_read(sc, 4, GITS_CTLR); - gic_its_write(sc, 4, GITS_CTLR, gits_tmp | GITS_CTLR_EN); - - /* 5. Initialize LPIs configuration table */ - lpi_init_conftable(sc); - - /* 6. LPIs bitmap init */ - lpi_bitmap_init(sc); - - /* 7. Allocate pending tables for all CPUs */ - lpi_alloc_cpu_pendtables(sc); - - /* 8. CPU init */ - (void)its_init_cpu(sc); - - /* 9. Init ITS devices list */ - TAILQ_INIT(&sc->its_dev_list); - - arm_register_msi_pic(dev); - - /* - * XXX ARM64TODO: We need to have ITS software context - * when being called by the interrupt code (mask/unmask). - * This may be used only when one ITS is present in - * the system and eventually should be removed. - */ - KASSERT(its_sc == NULL, - ("Trying to assign its_sc that is already set")); - its_sc = sc; - - return (0); -} - -/* Will not detach but use it for convenience */ -int -gic_v3_its_detach(device_t dev) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - struct gic_v3_its_softc *sc; - u_int cpuid; - int rid = 0; - - sc = device_get_softc(dev); - cpuid = PCPU_GET(cpuid); - - /* Release what's possible */ - - /* Command queue */ - if ((void *)sc->its_cmdq_base != NULL) { - contigfree((void *)sc->its_cmdq_base, - ITS_CMDQ_SIZE, M_GIC_V3_ITS); - } - /* ITTs */ - its_free_tables(sc); - /* Collections */ - for (cpuid = 0; cpuid < mp_ncpus; cpuid++) - free(sc->its_cols[cpuid], M_GIC_V3_ITS); - /* LPI config table */ - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - if ((void *)gic_sc->gic_redists.lpis.conf_base != NULL) { - contigfree((void *)gic_sc->gic_redists.lpis.conf_base, - LPI_CONFTAB_SIZE, M_GIC_V3_ITS); - } - for (cpuid = 0; cpuid < mp_ncpus; cpuid++) - if ((void *)gic_sc->gic_redists.lpis.pend_base[cpuid] != NULL) { - contigfree( - (void *)gic_sc->gic_redists.lpis.pend_base[cpuid], - roundup2(LPI_PENDTAB_SIZE, PAGE_SIZE_64K), - M_GIC_V3_ITS); - } - - /* Resource... */ - bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->its_res); - - /* XXX ARM64TODO: Reset global pointer to ITS software context */ - its_sc = NULL; - - return (0); -} - -static int -its_alloc_tables(struct gic_v3_its_softc *sc) -{ - uint64_t gits_baser, gits_tmp; - uint64_t type, esize, cache, share, psz; - size_t page_size, npages, nitspages, nidents, tn; - size_t its_tbl_size; - vm_offset_t ptab_vaddr; - vm_paddr_t ptab_paddr; - boolean_t first = TRUE; - - page_size = PAGE_SIZE_64K; - - for (tn = 0; tn < GITS_BASER_NUM; tn++) { - gits_baser = gic_its_read(sc, 8, GITS_BASER(tn)); - type = GITS_BASER_TYPE(gits_baser); - /* Get the Table Entry size */ - esize = GITS_BASER_ESIZE(gits_baser); - - switch (type) { - case GITS_BASER_TYPE_UNIMPL: /* fall through */ - case GITS_BASER_TYPE_RES5: - case GITS_BASER_TYPE_RES6: - case GITS_BASER_TYPE_RES7: - continue; - case GITS_BASER_TYPE_DEV: - nidents = (1 << its_get_devbits(sc->dev)); - its_tbl_size = esize * nidents; - its_tbl_size = roundup2(its_tbl_size, page_size); - npages = howmany(its_tbl_size, PAGE_SIZE); - break; - default: - npages = howmany(page_size, PAGE_SIZE); - break; - } - - /* Allocate required space */ - ptab_vaddr = (vm_offset_t)contigmalloc(npages * PAGE_SIZE, - M_GIC_V3_ITS, (M_WAITOK | M_ZERO), 0, ~0UL, PAGE_SIZE, 0); - - sc->its_ptabs[tn].ptab_vaddr = ptab_vaddr; - sc->its_ptabs[tn].ptab_pgsz = PAGE_SIZE; - sc->its_ptabs[tn].ptab_npages = npages; - - ptab_paddr = vtophys(ptab_vaddr); - KASSERT((ptab_paddr & GITS_BASER_PA_MASK) == ptab_paddr, - ("%s: Unaligned PA for Interrupt Translation Table", - device_get_name(sc->dev))); - - /* Set defaults: WAWB, IS */ - cache = GITS_BASER_CACHE_WAWB; - share = GITS_BASER_SHARE_IS; - - for (;;) { - nitspages = howmany(its_tbl_size, page_size); - - switch (page_size) { - case PAGE_SIZE: /* 4KB */ - psz = GITS_BASER_PSZ_4K; - break; - case PAGE_SIZE_16K: /* 16KB */ - psz = GITS_BASER_PSZ_4K; - break; - case PAGE_SIZE_64K: /* 64KB */ - psz = GITS_BASER_PSZ_64K; - break; - default: - device_printf(sc->dev, - "Unsupported page size: %zuKB\n", - (page_size / 1024)); - its_free_tables(sc); - return (ENXIO); - } - - /* Clear fields under modification first */ - gits_baser &= ~(GITS_BASER_VALID | - GITS_BASER_CACHE_MASK | GITS_BASER_TYPE_MASK | - GITS_BASER_ESIZE_MASK | GITS_BASER_PA_MASK | - GITS_BASER_SHARE_MASK | GITS_BASER_PSZ_MASK | - GITS_BASER_SIZE_MASK); - /* Construct register value */ - gits_baser |= - (type << GITS_BASER_TYPE_SHIFT) | - ((esize - 1) << GITS_BASER_ESIZE_SHIFT) | - (cache << GITS_BASER_CACHE_SHIFT) | - (share << GITS_BASER_SHARE_SHIFT) | - (psz << GITS_BASER_PSZ_SHIFT) | - ptab_paddr | (nitspages - 1) | - GITS_BASER_VALID; - - gic_its_write(sc, 8, GITS_BASER(tn), gits_baser); - /* - * Verify. - * Depending on implementation we may encounter - * shareability and page size mismatch. - */ - gits_tmp = gic_its_read(sc, 8, GITS_BASER(tn)); - if (((gits_tmp ^ gits_baser) & GITS_BASER_SHARE_MASK) != 0) { - share = gits_tmp & GITS_BASER_SHARE_MASK; - share >>= GITS_BASER_SHARE_SHIFT; - continue; - } - - if (((gits_tmp ^ gits_baser) & GITS_BASER_PSZ_MASK) != 0) { - switch (page_size) { - case PAGE_SIZE_16K: - /* Drop to 4KB page */ - page_size = PAGE_SIZE; - continue; - case PAGE_SIZE_64K: - /* Drop to 16KB page */ - page_size = PAGE_SIZE_16K; - continue; - } - } - /* - * All possible adjustments should - * be applied by now so just break the loop. - */ - break; - } - /* - * Do not compare Cacheability field since - * it is implementation defined. - */ - gits_tmp &= ~GITS_BASER_CACHE_MASK; - gits_baser &= ~GITS_BASER_CACHE_MASK; - - if (gits_tmp != gits_baser) { - device_printf(sc->dev, - "Could not allocate ITS tables\n"); - its_free_tables(sc); - return (ENXIO); - } - - if (bootverbose) { - if (first) { - device_printf(sc->dev, - "Allocated ITS private tables:\n"); - first = FALSE; - } - device_printf(sc->dev, - "\tPTAB%zu for %s: PA 0x%lx," - " %lu entries," - " cache policy %s, %s shareable," - " page size %zuKB\n", - tn, its_ptab_type[type], ptab_paddr, - (page_size * nitspages) / esize, - its_ptab_cache[cache], its_ptab_share[share], - page_size / 1024); - } - } - - return (0); -} - -static void -its_free_tables(struct gic_v3_its_softc *sc) -{ - vm_offset_t ptab_vaddr; - size_t size; - size_t tn; - - for (tn = 0; tn < GITS_BASER_NUM; tn++) { - ptab_vaddr = sc->its_ptabs[tn].ptab_vaddr; - if (ptab_vaddr == 0) - continue; - size = sc->its_ptabs[tn].ptab_pgsz; - size *= sc->its_ptabs[tn].ptab_npages; - - if ((void *)ptab_vaddr != NULL) - contigfree((void *)ptab_vaddr, size, M_GIC_V3_ITS); - - /* Clear the table description */ - memset(&sc->its_ptabs[tn], 0, sizeof(sc->its_ptabs[tn])); - } -} - -static void -its_init_commandq(struct gic_v3_its_softc *sc) -{ - uint64_t gits_cbaser, gits_tmp; - uint64_t cache, share; - vm_paddr_t cmdq_paddr; - device_t dev; - - dev = sc->dev; - /* Allocate memory for command queue */ - sc->its_cmdq_base = contigmalloc(ITS_CMDQ_SIZE, M_GIC_V3_ITS, - (M_WAITOK | M_ZERO), 0, ~0UL, ITS_CMDQ_SIZE, 0); - /* Set command queue write pointer (command queue empty) */ - sc->its_cmdq_write = sc->its_cmdq_base; - - /* Save command queue pointer and attributes */ - cmdq_paddr = vtophys(sc->its_cmdq_base); - - /* Set defaults: Normal Inner WAWB, IS */ - cache = GITS_CBASER_CACHE_NIWAWB; - share = GITS_CBASER_SHARE_IS; - - gits_cbaser = (cmdq_paddr | - (cache << GITS_CBASER_CACHE_SHIFT) | - (share << GITS_CBASER_SHARE_SHIFT) | - /* Number of 4KB pages - 1 */ - ((ITS_CMDQ_SIZE / PAGE_SIZE) - 1) | - /* Valid bit */ - GITS_CBASER_VALID); - - gic_its_write(sc, 8, GITS_CBASER, gits_cbaser); - gits_tmp = gic_its_read(sc, 8, GITS_CBASER); - - if (((gits_tmp ^ gits_cbaser) & GITS_CBASER_SHARE_MASK) != 0) { - if (bootverbose) { - device_printf(dev, - "Will use cache flushing for commands queue\n"); - } - /* Command queue needs cache flushing */ - sc->its_flags |= ITS_FLAGS_CMDQ_FLUSH; - } - - gic_its_write(sc, 8, GITS_CWRITER, 0x0); -} - -int -its_init_cpu(struct gic_v3_its_softc *sc) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - - /* - * NULL in place of the softc pointer means that - * this function was called during GICv3 secondary initialization. - */ - if (sc == NULL) { - if (its_sc != NULL && device_is_attached(its_sc->dev)) { - /* - * XXX ARM64TODO: This is part of the workaround that - * saves ITS software context for further use in - * mask/unmask and here. This should be removed as soon - * as the upper layer is capable of passing the ITS - * context to this function. - */ - sc = its_sc; - } else - return (ENXIO); - - /* Skip if running secondary init on a wrong socket */ - if (sc->its_socket != CPU_CURRENT_SOCKET) - return (ENXIO); - } - - /* - * Check for LPIs support on this Re-Distributor. - */ - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - if ((gic_r_read(gic_sc, 4, GICR_TYPER) & GICR_TYPER_PLPIS) == 0) { - if (bootverbose) { - device_printf(sc->dev, - "LPIs not supported on CPU%u\n", PCPU_GET(cpuid)); - } - return (ENXIO); - } - - /* Configure LPIs for this CPU */ - lpi_config_cpu(sc); - - /* Initialize collections */ - its_init_cpu_collection(sc); - - return (0); -} - -static void -its_init_cpu_collection(struct gic_v3_its_softc *sc) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - uint64_t typer; - uint64_t target; - vm_offset_t redist_base; - u_int cpuid; - - cpuid = PCPU_GET(cpuid); - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - - typer = gic_its_read(sc, 8, GITS_TYPER); - if ((typer & GITS_TYPER_PTA) != 0) { - redist_base = - rman_get_bushandle(gic_sc->gic_redists.pcpu[cpuid]); - /* - * Target Address correspond to the base physical - * address of Re-Distributors. - */ - target = vtophys(redist_base); - } else { - /* Target Address correspond to unique processor numbers */ - typer = gic_r_read(gic_sc, 8, GICR_TYPER); - target = GICR_TYPER_CPUNUM(typer); - } - - sc->its_cols[cpuid]->col_target = target; - sc->its_cols[cpuid]->col_id = cpuid; - - its_cmd_mapc(sc, sc->its_cols[cpuid], 1); - its_cmd_invall(sc, sc->its_cols[cpuid]); - -} - -static void -lpi_init_conftable(struct gic_v3_its_softc *sc) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - vm_offset_t conf_base; - uint8_t prio_default; - - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - /* - * LPI Configuration Table settings. - * Notice that Configuration Table is shared among all - * Re-Distributors, so this is going to be created just once. - */ - conf_base = (vm_offset_t)contigmalloc(LPI_CONFTAB_SIZE, - M_GIC_V3_ITS, (M_WAITOK | M_ZERO), 0, ~0UL, PAGE_SIZE_64K, 0); - - if (bootverbose) { - device_printf(sc->dev, - "LPI Configuration Table at PA: 0x%lx\n", - vtophys(conf_base)); - } - - /* - * Let the default priority be aligned with all other - * interrupts assuming that each interrupt is assigned - * MAX priority at startup. MAX priority on the other - * hand cannot be higher than 0xFC for LPIs. - */ - prio_default = GIC_PRIORITY_MAX; - - /* Write each settings byte to LPI configuration table */ - memset((void *)conf_base, - (prio_default & LPI_CONF_PRIO_MASK) | LPI_CONF_GROUP1, - LPI_CONFTAB_SIZE); - - cpu_dcache_wb_range((vm_offset_t)conf_base, roundup2(LPI_CONFTAB_SIZE, - PAGE_SIZE_64K)); - - gic_sc->gic_redists.lpis.conf_base = conf_base; -} - -static void -lpi_alloc_cpu_pendtables(struct gic_v3_its_softc *sc) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - vm_offset_t pend_base; - u_int cpuid; - - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - - /* - * LPI Pending Table settings. - * This has to be done for each Re-Distributor, hence for each CPU. - */ - for (cpuid = 0; cpuid < mp_ncpus; cpuid++) { - - /* Limit allocation to active CPUs only */ - if (CPU_ISSET(cpuid, &all_cpus) == 0) - continue; - - pend_base = (vm_offset_t)contigmalloc( - roundup2(LPI_PENDTAB_SIZE, PAGE_SIZE_64K), M_GIC_V3_ITS, - (M_WAITOK | M_ZERO), 0, ~0UL, PAGE_SIZE_64K, 0); - - /* Clean D-cache so that ITS can see zeroed pages */ - cpu_dcache_wb_range((vm_offset_t)pend_base, - roundup2(LPI_PENDTAB_SIZE, PAGE_SIZE_64K)); - - if (bootverbose) { - device_printf(sc->dev, - "LPI Pending Table for CPU%u at PA: 0x%lx\n", - cpuid, vtophys(pend_base)); - } - - gic_sc->gic_redists.lpis.pend_base[cpuid] = pend_base; - } - - /* Ensure visibility of pend_base addresses on other CPUs */ - wmb(); -} - -static int -lpi_config_cpu(struct gic_v3_its_softc *sc) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - vm_offset_t conf_base, pend_base; - uint64_t gicr_xbaser, gicr_temp; - uint64_t cache, share, idbits; - uint32_t gicr_ctlr; - u_int cpuid; - - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - cpuid = PCPU_GET(cpuid); - - /* Ensure data observability on a current CPU */ - rmb(); - - conf_base = gic_sc->gic_redists.lpis.conf_base; - pend_base = gic_sc->gic_redists.lpis.pend_base[cpuid]; - - /* Disable LPIs */ - gicr_ctlr = gic_r_read(gic_sc, 4, GICR_CTLR); - gicr_ctlr &= ~GICR_CTLR_LPI_ENABLE; - gic_r_write(gic_sc, 4, GICR_CTLR, gicr_ctlr); - /* Perform full system barrier */ - dsb(sy); - - /* - * Set GICR_PROPBASER - */ - - /* - * Find out how many bits do we need for LPI identifiers. - * Remark 1.: Even though we have (LPI_CONFTAB_SIZE / 8) LPIs - * the notified LPI ID still starts from 8192 - * (GIC_FIRST_LPI). - * Remark 2.: This could be done on compilation time but there - * seems to be no sufficient macro. - */ - idbits = flsl(LPI_CONFTAB_SIZE + GIC_FIRST_LPI) - 1; - - /* Set defaults: Normal Inner WAWB, IS */ - cache = GICR_PROPBASER_CACHE_NIWAWB; - share = GICR_PROPBASER_SHARE_IS; - - gicr_xbaser = vtophys(conf_base) | - ((idbits - 1) & GICR_PROPBASER_IDBITS_MASK) | - (cache << GICR_PROPBASER_CACHE_SHIFT) | - (share << GICR_PROPBASER_SHARE_SHIFT); - - gic_r_write(gic_sc, 8, GICR_PROPBASER, gicr_xbaser); - gicr_temp = gic_r_read(gic_sc, 8, GICR_PROPBASER); - - if (((gicr_xbaser ^ gicr_temp) & GICR_PROPBASER_SHARE_MASK) != 0) { - if (bootverbose) { - device_printf(sc->dev, - "Will use cache flushing for LPI " - "Configuration Table\n"); - } - gic_sc->gic_redists.lpis.flags |= LPI_FLAGS_CONF_FLUSH; - } - - /* - * Set GICR_PENDBASER - */ - - /* Set defaults: Normal Inner WAWB, IS */ - cache = GICR_PENDBASER_CACHE_NIWAWB; - share = GICR_PENDBASER_SHARE_IS; - - gicr_xbaser = vtophys(pend_base) | - (cache << GICR_PENDBASER_CACHE_SHIFT) | - (share << GICR_PENDBASER_SHARE_SHIFT); - - gic_r_write(gic_sc, 8, GICR_PENDBASER, gicr_xbaser); - - /* Enable LPIs */ - gicr_ctlr = gic_r_read(gic_sc, 4, GICR_CTLR); - gicr_ctlr |= GICR_CTLR_LPI_ENABLE; - gic_r_write(gic_sc, 4, GICR_CTLR, gicr_ctlr); - - dsb(sy); - - return (0); -} - -static void -lpi_bitmap_init(struct gic_v3_its_softc *sc) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - uint32_t lpi_id_num; - size_t lpi_chunks_num; - size_t bits_in_chunk; - - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - - lpi_id_num = (1 << gic_sc->gic_idbits) - 1; - /* Substract IDs dedicated for SGIs, PPIs and SPIs */ - lpi_id_num -= GIC_FIRST_LPI; - - sc->its_lpi_maxid = lpi_id_num; - - bits_in_chunk = sizeof(*sc->its_lpi_bitmap) * NBBY; - - /* - * Round up to the number of bits in chunk. - * We will need to take care to avoid using invalid LPI IDs later. - */ - lpi_id_num = roundup2(lpi_id_num, bits_in_chunk); - lpi_chunks_num = lpi_id_num / bits_in_chunk; - - sc->its_lpi_bitmap = - contigmalloc((lpi_chunks_num * sizeof(*sc->its_lpi_bitmap)), - M_GIC_V3_ITS, (M_WAITOK | M_ZERO), 0, ~0UL, - sizeof(*sc->its_lpi_bitmap), 0); -} - -static int -lpi_alloc_chunk(struct gic_v3_its_softc *sc, struct lpi_chunk *lpic, - u_int nvecs) -{ - u_int *col_ids; - int fclr; /* First cleared bit */ - bitstr_t *bitmap; - size_t nb, i; - - col_ids = malloc(sizeof(*col_ids) * nvecs, M_GIC_V3_ITS, - (M_NOWAIT | M_ZERO)); - if (col_ids == NULL) - return (ENOMEM); - - mtx_lock_spin(&sc->its_dev_lock); - bitmap = sc->its_lpi_bitmap; - - fclr = 0; -retry: - /* Check other bits - sloooow */ - for (i = 0, nb = fclr; i < nvecs; i++, nb++) { - if (nb > sc->its_lpi_maxid) { - mtx_unlock_spin(&sc->its_dev_lock); - free(col_ids, M_GIC_V3_ITS); - return (EINVAL); - } - - if (isset(bitmap, nb)) { - /* To little free bits in this area. Move on. */ - fclr = nb + 1; - goto retry; - } - } - /* This area is free. Take it. */ - bit_nset(bitmap, fclr, fclr + nvecs - 1); - lpic->lpi_base = fclr + GIC_FIRST_LPI; - lpic->lpi_num = nvecs; - lpic->lpi_busy = 0; - lpic->lpi_free = lpic->lpi_num; - lpic->lpi_col_ids = col_ids; - for (i = 0; i < lpic->lpi_num; i++) { - /* - * Initially all interrupts go to CPU0 but can be moved - * to another CPU by bus_bind_intr() or interrupts shuffling. - */ - lpic->lpi_col_ids[i] = 0; - } - mtx_unlock_spin(&sc->its_dev_lock); - - return (0); -} - -static void -lpi_free_chunk(struct gic_v3_its_softc *sc, struct lpi_chunk *lpic) -{ - int start, end; - - mtx_lock_spin(&sc->its_dev_lock); - KASSERT((lpic->lpi_busy == 0), - ("Trying to free LPI chunk that is still in use.\n")); - /* First bit of this chunk in a global bitmap */ - start = lpic->lpi_base - GIC_FIRST_LPI; - /* and last bit of this chunk... */ - end = start + lpic->lpi_num - 1; - - /* Finally free this chunk */ - bit_nclear(sc->its_lpi_bitmap, start, end); - mtx_unlock_spin(&sc->its_dev_lock); - - free(lpic->lpi_col_ids, M_GIC_V3_ITS); - lpic->lpi_col_ids = NULL; -} - -static void -lpi_configure(struct gic_v3_its_softc *sc, struct its_dev *its_dev, - uint32_t lpinum, boolean_t unmask) -{ - device_t parent; - struct gic_v3_softc *gic_sc; - uint8_t *conf_byte; - - parent = device_get_parent(sc->dev); - gic_sc = device_get_softc(parent); - - conf_byte = (uint8_t *)gic_sc->gic_redists.lpis.conf_base; - conf_byte += (lpinum - GIC_FIRST_LPI); - - if (unmask) - *conf_byte |= LPI_CONF_ENABLE; - else - *conf_byte &= ~LPI_CONF_ENABLE; - - if ((gic_sc->gic_redists.lpis.flags & LPI_FLAGS_CONF_FLUSH) != 0) { - /* Clean D-cache under configuration byte */ - cpu_dcache_wb_range((vm_offset_t)conf_byte, sizeof(*conf_byte)); - } else { - /* DSB inner shareable, store */ - dsb(ishst); - } - - its_cmd_inv(sc, its_dev, lpinum); -} - -static void -lpi_map_to_device(struct gic_v3_its_softc *sc, struct its_dev *its_dev, - uint32_t id, uint32_t pid) -{ - - if ((pid < its_dev->lpis.lpi_base) || - (pid >= (its_dev->lpis.lpi_base + its_dev->lpis.lpi_num))) - panic("Trying to map ivalid LPI %u for the device\n", pid); - - its_cmd_mapvi(sc, its_dev, id, pid); -} - -static void -lpi_xmask_irq(device_t parent, uint32_t irq, boolean_t unmask) -{ - struct its_dev *its_dev; - - TAILQ_FOREACH(its_dev, &its_sc->its_dev_list, entry) { - if (irq >= its_dev->lpis.lpi_base && - irq < (its_dev->lpis.lpi_base + its_dev->lpis.lpi_num)) { - lpi_configure(its_sc, its_dev, irq, unmask); - return; - } - } - - panic("Trying to %s not existing LPI: %u\n", - (unmask == TRUE) ? "unmask" : "mask", irq); -} - -int -lpi_migrate(device_t parent, uint32_t irq, u_int cpuid) -{ - struct gic_v3_its_softc *sc; - struct its_dev *its_dev; - struct its_col *col; - - sc = its_sc; - mtx_lock_spin(&sc->its_dev_lock); - its_dev = its_device_find_locked(sc, NULL, irq); - mtx_unlock_spin(&sc->its_dev_lock); - if (its_dev == NULL) { - /* Cannot migrate not configured LPI */ - return (ENXIO); - } - - /* Find local device's interrupt identifier */ - irq = irq - its_dev->lpis.lpi_base; - /* Move interrupt to another collection */ - col = sc->its_cols[cpuid]; - its_cmd_movi(sc, its_dev, col, irq); - its_dev->lpis.lpi_col_ids[irq] = cpuid; - - return (0); -} - -void -lpi_unmask_irq(device_t parent, uint32_t irq) -{ - - lpi_xmask_irq(parent, irq, 1); -} - -void -lpi_mask_irq(device_t parent, uint32_t irq) -{ - - lpi_xmask_irq(parent, irq, 0); -} - -/* - * Commands handling. - */ - -static __inline void -cmd_format_command(struct its_cmd *cmd, uint8_t cmd_type) -{ - /* Command field: DW0 [7:0] */ - cmd->cmd_dword[0] &= ~CMD_COMMAND_MASK; - cmd->cmd_dword[0] |= cmd_type; -} - -static __inline void -cmd_format_devid(struct its_cmd *cmd, uint32_t devid) -{ - /* Device ID field: DW0 [63:32] */ - cmd->cmd_dword[0] &= ~CMD_DEVID_MASK; - cmd->cmd_dword[0] |= ((uint64_t)devid << CMD_DEVID_SHIFT); -} - -static __inline void -cmd_format_size(struct its_cmd *cmd, uint16_t size) -{ - /* Size field: DW1 [4:0] */ - cmd->cmd_dword[1] &= ~CMD_SIZE_MASK; - cmd->cmd_dword[1] |= (size & CMD_SIZE_MASK); -} - -static __inline void -cmd_format_id(struct its_cmd *cmd, uint32_t id) -{ - /* ID field: DW1 [31:0] */ - cmd->cmd_dword[1] &= ~CMD_ID_MASK; - cmd->cmd_dword[1] |= id; -} - -static __inline void -cmd_format_pid(struct its_cmd *cmd, uint32_t pid) -{ - /* Physical ID field: DW1 [63:32] */ - cmd->cmd_dword[1] &= ~CMD_PID_MASK; - cmd->cmd_dword[1] |= ((uint64_t)pid << CMD_PID_SHIFT); -} - -static __inline void -cmd_format_col(struct its_cmd *cmd, uint16_t col_id) -{ - /* Collection field: DW2 [16:0] */ - cmd->cmd_dword[2] &= ~CMD_COL_MASK; - cmd->cmd_dword[2] |= col_id; -} - -static __inline void -cmd_format_target(struct its_cmd *cmd, uint64_t target) -{ - /* Target Address field: DW2 [47:16] */ - cmd->cmd_dword[2] &= ~CMD_TARGET_MASK; - cmd->cmd_dword[2] |= (target & CMD_TARGET_MASK); -} - -static __inline void -cmd_format_itt(struct its_cmd *cmd, uint64_t itt) -{ - /* ITT Address field: DW2 [47:8] */ - cmd->cmd_dword[2] &= ~CMD_ITT_MASK; - cmd->cmd_dword[2] |= (itt & CMD_ITT_MASK); -} - -static __inline void -cmd_format_valid(struct its_cmd *cmd, uint8_t valid) -{ - /* Valid field: DW2 [63] */ - cmd->cmd_dword[2] &= ~CMD_VALID_MASK; - cmd->cmd_dword[2] |= ((uint64_t)valid << CMD_VALID_SHIFT); -} - -static __inline void -cmd_fix_endian(struct its_cmd *cmd) -{ - size_t i; - - for (i = 0; i < nitems(cmd->cmd_dword); i++) - cmd->cmd_dword[i] = htole64(cmd->cmd_dword[i]); -} - -static void -its_cmd_movi(struct gic_v3_its_softc *sc, struct its_dev *its_dev, - struct its_col *col, uint32_t id) -{ - struct its_cmd_desc desc; - - desc.cmd_type = ITS_CMD_MOVI; - desc.cmd_desc_movi.its_dev = its_dev; - desc.cmd_desc_movi.col = col; - desc.cmd_desc_movi.id = id; - - its_cmd_send(sc, &desc); -} - -static void -its_cmd_mapc(struct gic_v3_its_softc *sc, struct its_col *col, uint8_t valid) -{ - struct its_cmd_desc desc; - - desc.cmd_type = ITS_CMD_MAPC; - desc.cmd_desc_mapc.col = col; - /* - * Valid bit set - map the collection. - * Valid bit cleared - unmap the collection. - */ - desc.cmd_desc_mapc.valid = valid; - - its_cmd_send(sc, &desc); -} - -static void -its_cmd_mapvi(struct gic_v3_its_softc *sc, struct its_dev *its_dev, - uint32_t id, uint32_t pid) -{ - struct its_cmd_desc desc; - struct its_col *col; - u_int col_id; - - col_id = its_dev->lpis.lpi_col_ids[id]; - col = sc->its_cols[col_id]; - - desc.cmd_type = ITS_CMD_MAPVI; - desc.cmd_desc_mapvi.its_dev = its_dev; - desc.cmd_desc_mapvi.col = col; - desc.cmd_desc_mapvi.id = id; - desc.cmd_desc_mapvi.pid = pid; - - its_cmd_send(sc, &desc); -} - -static void __unused -its_cmd_mapi(struct gic_v3_its_softc *sc, struct its_dev *its_dev, uint32_t pid) -{ - struct its_cmd_desc desc; - struct its_col *col; - u_int col_id; - uint32_t id; - - KASSERT(pid >= its_dev->lpis.lpi_base, - ("%s: invalid pid: %d for the ITS device", __func__, pid)); - id = pid - its_dev->lpis.lpi_base; - col_id = its_dev->lpis.lpi_col_ids[id]; - col = sc->its_cols[col_id]; - - desc.cmd_type = ITS_CMD_MAPI; - desc.cmd_desc_mapi.its_dev = its_dev; - desc.cmd_desc_mapi.col = col; - desc.cmd_desc_mapi.pid = pid; - - its_cmd_send(sc, &desc); -} - -static void -its_cmd_mapd(struct gic_v3_its_softc *sc, struct its_dev *its_dev, - uint8_t valid) -{ - struct its_cmd_desc desc; - - desc.cmd_type = ITS_CMD_MAPD; - desc.cmd_desc_mapd.its_dev = its_dev; - desc.cmd_desc_mapd.valid = valid; - - its_cmd_send(sc, &desc); -} - -static void -its_cmd_inv(struct gic_v3_its_softc *sc, struct its_dev *its_dev, uint32_t pid) -{ - struct its_cmd_desc desc; - struct its_col *col; - u_int col_id; - uint32_t id; - - KASSERT(pid >= its_dev->lpis.lpi_base, - ("%s: invalid pid: %d for the ITS device", __func__, pid)); - id = pid - its_dev->lpis.lpi_base; - col_id = its_dev->lpis.lpi_col_ids[id]; - col = sc->its_cols[col_id]; - - desc.cmd_type = ITS_CMD_INV; - desc.cmd_desc_inv.pid = pid - its_dev->lpis.lpi_base; - desc.cmd_desc_inv.its_dev = its_dev; - desc.cmd_desc_inv.col = col; - - its_cmd_send(sc, &desc); -} - -static void -its_cmd_invall(struct gic_v3_its_softc *sc, struct its_col *col) -{ - struct its_cmd_desc desc; - - desc.cmd_type = ITS_CMD_INVALL; - desc.cmd_desc_invall.col = col; - - its_cmd_send(sc, &desc); -} - -/* - * Helper routines for commands processing. - */ -static __inline boolean_t -its_cmd_queue_full(struct gic_v3_its_softc *sc) -{ - size_t read_idx, write_idx; - - write_idx = (size_t)(sc->its_cmdq_write - sc->its_cmdq_base); - read_idx = gic_its_read(sc, 4, GITS_CREADR) / sizeof(struct its_cmd); - - /* - * The queue is full when the write offset points - * at the command before the current read offset. - */ - if (((write_idx + 1) % ITS_CMDQ_NENTRIES) == read_idx) - return (TRUE); - - return (FALSE); -} - -static __inline void -its_cmd_sync(struct gic_v3_its_softc *sc, struct its_cmd *cmd) -{ - - if ((sc->its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0) { - /* Clean D-cache under command. */ - cpu_dcache_wb_range((vm_offset_t)cmd, sizeof(*cmd)); - } else { - /* DSB inner shareable, store */ - dsb(ishst); - } - -} - -static struct its_cmd * -its_cmd_alloc_locked(struct gic_v3_its_softc *sc) -{ - struct its_cmd *cmd; - size_t us_left; - - /* - * XXX ARM64TODO: This is obviously a significant delay. - * The reason for that is that currently the time frames for - * the command to complete (and therefore free the descriptor) - * are not known. - */ - us_left = 1000000; - - mtx_assert(&sc->its_cmd_lock, MA_OWNED); - while (its_cmd_queue_full(sc)) { - if (us_left-- == 0) { - /* Timeout while waiting for free command */ - device_printf(sc->dev, - "Timeout while waiting for free command\n"); - return (NULL); - } - DELAY(1); - } - - cmd = sc->its_cmdq_write; - sc->its_cmdq_write++; - - if (sc->its_cmdq_write == (sc->its_cmdq_base + ITS_CMDQ_NENTRIES)) { - /* Wrap the queue */ - sc->its_cmdq_write = sc->its_cmdq_base; - } - - return (cmd); -} - -static uint64_t -its_cmd_prepare(struct its_cmd *cmd, struct its_cmd_desc *desc) -{ - uint64_t target; - uint8_t cmd_type; - u_int size; - boolean_t error; - - error = FALSE; - cmd_type = desc->cmd_type; - target = ITS_TARGET_NONE; - - switch (cmd_type) { - case ITS_CMD_MOVI: /* Move interrupt ID to another collection */ - target = desc->cmd_desc_movi.col->col_target; - cmd_format_command(cmd, ITS_CMD_MOVI); - cmd_format_id(cmd, desc->cmd_desc_movi.id); - cmd_format_col(cmd, desc->cmd_desc_movi.col->col_id); - cmd_format_devid(cmd, desc->cmd_desc_movi.its_dev->devid); - break; - case ITS_CMD_SYNC: /* Wait for previous commands completion */ - target = desc->cmd_desc_sync.col->col_target; - cmd_format_command(cmd, ITS_CMD_SYNC); - cmd_format_target(cmd, target); - break; - case ITS_CMD_MAPD: /* Assign ITT to device */ - cmd_format_command(cmd, ITS_CMD_MAPD); - cmd_format_itt(cmd, vtophys(desc->cmd_desc_mapd.its_dev->itt)); - /* - * Size describes number of bits to encode interrupt IDs - * supported by the device minus one. - * When V (valid) bit is zero, this field should be written - * as zero. - */ - if (desc->cmd_desc_mapd.valid != 0) { - size = fls(desc->cmd_desc_mapd.its_dev->lpis.lpi_num); - size = MAX(1, size) - 1; - } else - size = 0; - - cmd_format_size(cmd, size); - cmd_format_devid(cmd, desc->cmd_desc_mapd.its_dev->devid); - cmd_format_valid(cmd, desc->cmd_desc_mapd.valid); - break; - case ITS_CMD_MAPC: /* Map collection to Re-Distributor */ - target = desc->cmd_desc_mapc.col->col_target; - cmd_format_command(cmd, ITS_CMD_MAPC); - cmd_format_col(cmd, desc->cmd_desc_mapc.col->col_id); - cmd_format_valid(cmd, desc->cmd_desc_mapc.valid); - cmd_format_target(cmd, target); - break; - case ITS_CMD_MAPVI: - target = desc->cmd_desc_mapvi.col->col_target; - cmd_format_command(cmd, ITS_CMD_MAPVI); - cmd_format_devid(cmd, desc->cmd_desc_mapvi.its_dev->devid); - cmd_format_id(cmd, desc->cmd_desc_mapvi.id); - cmd_format_pid(cmd, desc->cmd_desc_mapvi.pid); - cmd_format_col(cmd, desc->cmd_desc_mapvi.col->col_id); - break; - case ITS_CMD_MAPI: - target = desc->cmd_desc_mapi.col->col_target; - cmd_format_command(cmd, ITS_CMD_MAPI); - cmd_format_devid(cmd, desc->cmd_desc_mapi.its_dev->devid); - cmd_format_id(cmd, desc->cmd_desc_mapi.pid); - cmd_format_col(cmd, desc->cmd_desc_mapi.col->col_id); - break; - case ITS_CMD_INV: - target = desc->cmd_desc_inv.col->col_target; - cmd_format_command(cmd, ITS_CMD_INV); - cmd_format_devid(cmd, desc->cmd_desc_inv.its_dev->devid); - cmd_format_id(cmd, desc->cmd_desc_inv.pid); - break; - case ITS_CMD_INVALL: - cmd_format_command(cmd, ITS_CMD_INVALL); - cmd_format_col(cmd, desc->cmd_desc_invall.col->col_id); - break; - default: - error = TRUE; - break; - } - - if (!error) - cmd_fix_endian(cmd); - - return (target); -} - -static __inline uint64_t -its_cmd_cwriter_offset(struct gic_v3_its_softc *sc, struct its_cmd *cmd) -{ - uint64_t off; - - off = (cmd - sc->its_cmdq_base) * sizeof(*cmd); - - return (off); -} - -static void -its_cmd_wait_completion(struct gic_v3_its_softc *sc, struct its_cmd *cmd_first, - struct its_cmd *cmd_last) -{ - uint64_t first, last, read; - size_t us_left; - - /* - * XXX ARM64TODO: This is obviously a significant delay. - * The reason for that is that currently the time frames for - * the command to complete are not known. - */ - us_left = 1000000; - - first = its_cmd_cwriter_offset(sc, cmd_first); - last = its_cmd_cwriter_offset(sc, cmd_last); - - for (;;) { - read = gic_its_read(sc, 8, GITS_CREADR); - if (read < first || read >= last) - break; - - if (us_left-- == 0) { - /* This means timeout */ - device_printf(sc->dev, - "Timeout while waiting for CMD completion.\n"); - return; - } - DELAY(1); - } -} - -static int -its_cmd_send(struct gic_v3_its_softc *sc, struct its_cmd_desc *desc) -{ - struct its_cmd *cmd, *cmd_sync, *cmd_write; - struct its_col col_sync; - struct its_cmd_desc desc_sync; - uint64_t target, cwriter; - - mtx_lock_spin(&sc->its_cmd_lock); - cmd = its_cmd_alloc_locked(sc); - if (cmd == NULL) { - device_printf(sc->dev, "could not allocate ITS command\n"); - mtx_unlock_spin(&sc->its_cmd_lock); - return (EBUSY); - } - - target = its_cmd_prepare(cmd, desc); - its_cmd_sync(sc, cmd); - - if (target != ITS_TARGET_NONE) { - cmd_sync = its_cmd_alloc_locked(sc); - if (cmd_sync == NULL) - goto end; - desc_sync.cmd_type = ITS_CMD_SYNC; - col_sync.col_target = target; - desc_sync.cmd_desc_sync.col = &col_sync; - its_cmd_prepare(cmd_sync, &desc_sync); - its_cmd_sync(sc, cmd_sync); - } -end: - /* Update GITS_CWRITER */ - cwriter = its_cmd_cwriter_offset(sc, sc->its_cmdq_write); - gic_its_write(sc, 8, GITS_CWRITER, cwriter); - cmd_write = sc->its_cmdq_write; - mtx_unlock_spin(&sc->its_cmd_lock); - - its_cmd_wait_completion(sc, cmd, cmd_write); - - return (0); -} - -/* Find ITS device descriptor by pci_dev or irq number */ -static struct its_dev * -its_device_find_locked(struct gic_v3_its_softc *sc, device_t pci_dev, - uint32_t irq) -{ - struct its_dev *its_dev; - struct lpi_chunk *lpis; - - mtx_assert(&sc->its_dev_lock, MA_OWNED); - KASSERT((pci_dev == NULL || irq == 0), - ("%s: Can't search by both pci_dev and irq number", __func__)); - /* Find existing device if any */ - TAILQ_FOREACH(its_dev, &sc->its_dev_list, entry) { - if (pci_dev != NULL) { - if (its_dev->pci_dev == pci_dev) - return (its_dev); - } else if (irq != 0) { - lpis = &its_dev->lpis; - if ((irq >= lpis->lpi_base) && - (irq < (lpis->lpi_base + lpis->lpi_num))) - return (its_dev); - } - } - - return (NULL); -} - -static struct its_dev * -its_device_alloc(struct gic_v3_its_softc *sc, device_t pci_dev, - u_int nvecs) -{ - struct its_dev *newdev; - vm_offset_t itt_addr; - uint64_t typer; - uint32_t devid; - size_t esize; - int err; - - mtx_lock_spin(&sc->its_dev_lock); - /* Find existing device if any */ - newdev = its_device_find_locked(sc, pci_dev, 0); - mtx_unlock_spin(&sc->its_dev_lock); - if (newdev != NULL) - return (newdev); - - devid = its_get_devid(pci_dev); - - /* There was no previously created device. Create one now */ - newdev = malloc(sizeof(*newdev), M_GIC_V3_ITS, (M_NOWAIT | M_ZERO)); - if (newdev == NULL) - return (NULL); - - newdev->pci_dev = pci_dev; - newdev->devid = devid; - - err = lpi_alloc_chunk(sc, &newdev->lpis, nvecs); - if (err != 0) { - free(newdev, M_GIC_V3_ITS); - return (NULL); - } - - /* Get ITT entry size */ - typer = gic_its_read(sc, 8, GITS_TYPER); - esize = GITS_TYPER_ITTES(typer); - /* - * Allocate ITT for this device. - * PA has to be 256 B aligned. At least two entries for device. - */ - newdev->itt_size = roundup2(roundup2(nvecs, 2) * esize, 0x100); - itt_addr = (vm_offset_t)contigmalloc( - newdev->itt_size, M_GIC_V3_ITS, (M_NOWAIT | M_ZERO), - 0, ~0UL, 0x100, 0); - if (itt_addr == 0) { - lpi_free_chunk(sc, &newdev->lpis); - free(newdev, M_GIC_V3_ITS); - return (NULL); - } - - mtx_lock_spin(&sc->its_dev_lock); - newdev->itt = itt_addr; - TAILQ_INSERT_TAIL(&sc->its_dev_list, newdev, entry); - mtx_unlock_spin(&sc->its_dev_lock); - - /* Map device to its ITT */ - its_cmd_mapd(sc, newdev, 1); - - return (newdev); -} - -static void -its_device_free(struct gic_v3_its_softc *sc, device_t pci_dev, - u_int nvecs) -{ - struct its_dev *odev; - - mtx_lock_spin(&sc->its_dev_lock); - /* Find existing device if any */ - odev = its_device_find_locked(sc, pci_dev, 0); - if (odev == NULL) { - mtx_unlock_spin(&sc->its_dev_lock); - return; - } - - KASSERT((nvecs <= odev->lpis.lpi_num) && (nvecs <= odev->lpis.lpi_busy), - ("Invalid number of LPI vectors to free %d (total %d) (busy %d)", - nvecs, odev->lpis.lpi_num, odev->lpis.lpi_busy)); - /* Just decrement number of busy LPIs in chunk */ - odev->lpis.lpi_busy -= nvecs; - if (odev->lpis.lpi_busy != 0) { - mtx_unlock_spin(&sc->its_dev_lock); - return; - } - - /* - * At that point we know that there are no busy LPIs for this device. - * Entire ITS device can now be removed. - */ - mtx_unlock_spin(&sc->its_dev_lock); - /* Unmap device in ITS */ - its_cmd_mapd(sc, odev, 0); - /* Free ITT */ - KASSERT(odev->itt != 0, ("Invalid ITT in valid ITS device")); - contigfree((void *)odev->itt, odev->itt_size, M_GIC_V3_ITS); - /* Free chunk */ - lpi_free_chunk(sc, &odev->lpis); - /* Free device */ - mtx_lock_spin(&sc->its_dev_lock); - TAILQ_REMOVE(&sc->its_dev_list, odev, entry); - mtx_unlock_spin(&sc->its_dev_lock); - free((void *)odev, M_GIC_V3_ITS); - -} - -static __inline void -its_device_asign_lpi_locked(struct gic_v3_its_softc *sc, - struct its_dev *its_dev, u_int *irq) -{ - - mtx_assert(&sc->its_dev_lock, MA_OWNED); - if (its_dev->lpis.lpi_free == 0) { - panic("Requesting more LPIs than allocated for this device. " - "LPI num: %u, free %u", its_dev->lpis.lpi_num, - its_dev->lpis.lpi_free); - } - *irq = its_dev->lpis.lpi_base + (its_dev->lpis.lpi_num - - its_dev->lpis.lpi_free); - its_dev->lpis.lpi_free--; - its_dev->lpis.lpi_busy++; -} - -/* - * ITS quirks. - * Add vendor specific PCI devid function here. - */ -static uint32_t -its_get_devbits_thunder(device_t dev) -{ - uint32_t devid_bits; - - /* - * GITS_TYPER[17:13] of ThunderX reports that device IDs - * are to be 21 bits in length. - * The entry size of the ITS table can be read from GITS_BASERn[52:48] - * and on ThunderX is supposed to be 8 bytes in length (for device - * table). Finally the page size that is to be used by ITS to access - * this table will be set to 64KB. - * - * This gives 0x200000 entries of size 0x8 bytes covered by 256 pages - * each of which 64KB in size. The number of pages (minus 1) should - * then be written to GITS_BASERn[7:0]. In that case this value would - * be 0xFF but on ThunderX the maximum value that HW accepts is 0xFD. - * - * Set arbitrary number of device ID bits to 20 in order to limit - * the number of entries in ITS device table to 0x100000 and hence - * the table size to 8MB. - */ - devid_bits = 20; - if (bootverbose) { - device_printf(dev, - "Limiting number of Device ID bits implemented to %d\n", - devid_bits); - } - - return (devid_bits); -} - -static __inline uint32_t -its_get_devbits_default(device_t dev) -{ - uint64_t gits_typer; - struct gic_v3_its_softc *sc; - - sc = device_get_softc(dev); - - gits_typer = gic_its_read(sc, 8, GITS_TYPER); - - return (GITS_TYPER_DEVB(gits_typer)); -} - -static uint32_t -its_get_devbits(device_t dev) -{ - const struct its_quirks *quirk; - size_t i; - - for (i = 0; i < nitems(its_quirks); i++) { - quirk = &its_quirks[i]; - if (CPU_MATCH_RAW(quirk->cpuid_mask, quirk->cpuid)) { - if (quirk->devbits_func != NULL) - return ((*quirk->devbits_func)(dev)); - } - } - - return (its_get_devbits_default(dev)); -} - -static uint32_t -its_get_devid(device_t pci_dev) -{ - uintptr_t id; - - if (pci_get_id(pci_dev, PCI_ID_MSI, &id) != 0) - panic("its_get_devid: Unable to get the MSI DeviceID"); - - return (id); -} - -/* - * Message signalled interrupts handling. - */ - -/* - * XXX ARM64TODO: Watch out for "irq" type. - * - * In theory GIC can handle up to (2^32 - 1) interrupt IDs whereas - * we pass "irq" pointer of type integer. This is obviously wrong but - * is determined by the way as PCI layer wants it to be done. - */ -int -gic_v3_its_alloc_msix(device_t dev, device_t pci_dev, int *irq) -{ - struct gic_v3_its_softc *sc; - struct its_dev *its_dev; - u_int nvecs; - - sc = device_get_softc(dev); - - nvecs = PCI_MSIX_NUM(pci_dev); - - /* - * Allocate device as seen by ITS if not already available. - * Notice that MSI-X interrupts are allocated on one-by-one basis. - */ - its_dev = its_device_alloc(sc, pci_dev, nvecs); - if (its_dev == NULL) - return (ENOMEM); - - mtx_lock_spin(&sc->its_dev_lock); - its_device_asign_lpi_locked(sc, its_dev, irq); - mtx_unlock_spin(&sc->its_dev_lock); - - return (0); -} - -int -gic_v3_its_release_msix(device_t dev, device_t pci_dev, int irq __unused) -{ - - struct gic_v3_its_softc *sc; - - sc = device_get_softc(dev); - its_device_free(sc, pci_dev, 1); - - return (0); -} - -int -gic_v3_its_alloc_msi(device_t dev, device_t pci_dev, int count, int *irqs) -{ - struct gic_v3_its_softc *sc; - struct its_dev *its_dev; - - sc = device_get_softc(dev); - - /* Allocate device as seen by ITS if not already available. */ - its_dev = its_device_alloc(sc, pci_dev, count); - if (its_dev == NULL) - return (ENOMEM); - - mtx_lock_spin(&sc->its_dev_lock); - for (; count > 0; count--) { - its_device_asign_lpi_locked(sc, its_dev, irqs); - irqs++; - } - mtx_unlock_spin(&sc->its_dev_lock); - - return (0); -} - -int -gic_v3_its_release_msi(device_t dev, device_t pci_dev, int count, - int *irqs __unused) -{ - struct gic_v3_its_softc *sc; - - sc = device_get_softc(dev); - its_device_free(sc, pci_dev, count); - - return (0); -} - -int -gic_v3_its_map_msi(device_t dev, device_t pci_dev, int irq, uint64_t *addr, - uint32_t *data) -{ - struct gic_v3_its_softc *sc; - bus_space_handle_t its_bsh; - struct its_dev *its_dev; - uint64_t its_pa; - uint32_t id; - - sc = device_get_softc(dev); - /* Verify that this device is allocated and owns this LPI */ - mtx_lock_spin(&sc->its_dev_lock); - its_dev = its_device_find_locked(sc, pci_dev, 0); - mtx_unlock_spin(&sc->its_dev_lock); - if (its_dev == NULL) - return (EINVAL); - - id = irq - its_dev->lpis.lpi_base; - lpi_map_to_device(sc, its_dev, id, irq); - - its_bsh = rman_get_bushandle(&sc->its_res[0]); - its_pa = vtophys(its_bsh); - - *addr = (its_pa + GITS_TRANSLATER); - *data = id; - - return (0); -} diff --git a/sys/arm64/arm64/intr_machdep.c b/sys/arm64/arm64/intr_machdep.c deleted file mode 100644 index d99303e..0000000 --- a/sys/arm64/arm64/intr_machdep.c +++ /dev/null @@ -1,584 +0,0 @@ -/*- - * Copyright (c) 1991 The Regents of the University of California. - * Copyright (c) 2002 Benno Rice. - * Copyright (c) 2014 The FreeBSD Foundation - * All rights reserved. - * - * This software was developed by Semihalf under - * the sponsorship of the FreeBSD Foundation. - * - * This code is derived from software contributed by - * William Jolitz (Berkeley) and Benno Rice. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * form: src/sys/powerpc/powerpc/intr_machdep.c, r271712 2014/09/17 - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/proc.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/ktr.h> -#include <sys/lock.h> -#include <sys/malloc.h> -#include <sys/mutex.h> -#include <sys/cpuset.h> -#include <sys/interrupt.h> -#include <sys/queue.h> -#include <sys/smp.h> - -#include <machine/cpufunc.h> -#include <machine/intr.h> - -#ifdef SMP -#include <machine/smp.h> -#endif - -#include "pic_if.h" - -#define MAX_STRAY_LOG 5 -#define INTRNAME_LEN (MAXCOMLEN + 1) - -#define NIRQS 1024 /* Maximum number of interrupts in the system */ - -static MALLOC_DEFINE(M_INTR, "intr", "Interrupt Services"); - -/* - * Linked list of interrupts that have been set-up. - * Each element holds the interrupt description - * and has to be allocated and freed dynamically. - */ -static SLIST_HEAD(, arm64_intr_entry) irq_slist_head = - SLIST_HEAD_INITIALIZER(irq_slist_head); - -struct arm64_intr_entry { - SLIST_ENTRY(arm64_intr_entry) entries; - struct intr_event *i_event; - - enum intr_trigger i_trig; - enum intr_polarity i_pol; - - u_int i_hw_irq; /* Physical interrupt number */ - u_int i_cntidx; /* Index in intrcnt table */ - u_int i_handlers; /* Allocated handlers */ - u_int i_cpu; /* Assigned CPU */ - u_long *i_cntp; /* Interrupt hit counter */ -}; - -/* Counts and names for statistics - see sys/sys/interrupt.h */ -/* Tables are indexed by i_cntidx */ -u_long intrcnt[NIRQS]; -char intrnames[NIRQS * INTRNAME_LEN]; -size_t sintrcnt = sizeof(intrcnt); -size_t sintrnames = sizeof(intrnames); - -static u_int intrcntidx; /* Current index into intrcnt table */ -static u_int arm64_nintrs; /* Max interrupts number of the root PIC */ -static u_int arm64_nstray; /* Number of received stray interrupts */ -static device_t root_pic; /* PIC device for all incoming interrupts */ -static device_t msi_pic; /* Device which handles MSI/MSI-X interrupts */ -static struct mtx intr_list_lock; - -static void -intr_init(void *dummy __unused) -{ - - mtx_init(&intr_list_lock, "intr sources lock", NULL, MTX_SPIN); -} -SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL); - -/* - * Helper routines. - */ - -/* Set interrupt name for statistics */ -static void -intrcnt_setname(const char *name, u_int idx) -{ - - snprintf(&intrnames[idx * INTRNAME_LEN], INTRNAME_LEN, "%-*s", - INTRNAME_LEN - 1, name); -} - -/* - * Find the interrupt descriptor in the list - * based on the hardware IRQ number. - */ -static __inline struct arm64_intr_entry * -intr_lookup_locked(u_int hw_irq) -{ - struct arm64_intr_entry *intr; - - mtx_assert(&intr_list_lock, MA_OWNED); - SLIST_FOREACH(intr, &irq_slist_head, entries) { - if (intr->i_hw_irq == hw_irq) - return (intr); - } - return (NULL); -} -/* - * Get intr structure for the given interrupt number. - * Allocate one if this is the first time. - */ -static struct arm64_intr_entry * -intr_allocate(u_int hw_irq) -{ - struct arm64_intr_entry *intr; - - /* Check if already allocated */ - mtx_lock_spin(&intr_list_lock); - intr = intr_lookup_locked(hw_irq); - mtx_unlock_spin(&intr_list_lock); - if (intr != NULL) - return (intr); - - /* Do not alloc another intr when max number of IRQs has been reached */ - if (intrcntidx >= NIRQS) - return (NULL); - - intr = malloc(sizeof(*intr), M_INTR, M_NOWAIT); - if (intr == NULL) - return (NULL); - - /* The default CPU is 0 but can be changed later by bind or shuffle */ - intr->i_cpu = 0; - intr->i_event = NULL; - intr->i_handlers = 0; - intr->i_trig = INTR_TRIGGER_CONFORM; - intr->i_pol = INTR_POLARITY_CONFORM; - intr->i_cntidx = atomic_fetchadd_int(&intrcntidx, 1); - intr->i_cntp = &intrcnt[intr->i_cntidx]; - intr->i_hw_irq = hw_irq; - mtx_lock_spin(&intr_list_lock); - SLIST_INSERT_HEAD(&irq_slist_head, intr, entries); - mtx_unlock_spin(&intr_list_lock); - - return intr; -} - -static int -intr_assign_cpu(void *arg, int cpu) -{ -#ifdef SMP - struct arm64_intr_entry *intr; - int error; - - if (root_pic == NULL) - panic("Cannot assing interrupt to CPU. No PIC configured"); - /* - * Set the interrupt to CPU affinity. - * Do not configure this in hardware during early boot. - * We will pick up the assignment once the APs are started. - */ - if (cpu != NOCPU) { - intr = arg; - if (!cold && smp_started) { - /* - * Bind the interrupt immediately - * if SMP is up and running. - */ - error = PIC_BIND(root_pic, intr->i_hw_irq, cpu); - if (error == 0) - intr->i_cpu = cpu; - } else { - /* Postpone binding until SMP is operational */ - intr->i_cpu = cpu; - error = 0; - } - } else - error = 0; - - return (error); -#else - return (EOPNOTSUPP); -#endif -} - -static void -intr_pre_ithread(void *arg) -{ - struct arm64_intr_entry *intr = arg; - - PIC_PRE_ITHREAD(root_pic, intr->i_hw_irq); -} - -static void -intr_post_ithread(void *arg) -{ - struct arm64_intr_entry *intr = arg; - - PIC_POST_ITHREAD(root_pic, intr->i_hw_irq); -} - -static void -intr_post_filter(void *arg) -{ - struct arm64_intr_entry *intr = arg; - - PIC_POST_FILTER(root_pic, intr->i_hw_irq); -} - -/* - * Register PIC driver. - * This is intended to be called by the very first PIC driver - * at the end of the successful attach. - * Note that during boot this can be called after first references - * to bus_setup_intr() so it is required to not use root_pic if it - * is not 100% safe. - */ -void -arm_register_root_pic(device_t dev, u_int nirq) -{ - - KASSERT(root_pic == NULL, ("Unable to set the pic twice")); - KASSERT(nirq <= NIRQS, ("PIC is trying to handle too many IRQs")); - - arm64_nintrs = NIRQS; /* Number of IRQs limited only by array size */ - root_pic = dev; -} - -/* Register device which allocates MSI interrupts */ -void -arm_register_msi_pic(device_t dev) -{ - - KASSERT(msi_pic == NULL, ("Unable to set msi_pic twice")); - msi_pic = dev; -} - -int -arm_alloc_msi(device_t pci, device_t child, int count, int maxcount, int *irqs) -{ - - return (PIC_ALLOC_MSI(msi_pic, child, count, irqs)); -} - -int -arm_release_msi(device_t pci, device_t child, int count, int *irqs) -{ - - return (PIC_RELEASE_MSI(msi_pic, child, count, irqs)); -} - -int -arm_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, uint32_t *data) -{ - - return (PIC_MAP_MSI(msi_pic, child, irq, addr, data)); -} - -int -arm_alloc_msix(device_t pci, device_t child, int *irq) -{ - - return (PIC_ALLOC_MSIX(msi_pic, child, irq)); -} - -int -arm_release_msix(device_t pci, device_t child, int irq) -{ - - return (PIC_RELEASE_MSIX(msi_pic, child, irq)); -} - - -/* - * Finalize interrupts bring-up (should be called from configure_final()). - * Enables all interrupts registered by bus_setup_intr() during boot - * as well as unlocks interrups reception on primary CPU. - */ -int -arm_enable_intr(void) -{ - struct arm64_intr_entry *intr; - - if (root_pic == NULL) - panic("Cannot enable interrupts. No PIC configured"); - - /* - * Iterate through all possible interrupts and perform - * configuration if the interrupt is registered. - */ - SLIST_FOREACH(intr, &irq_slist_head, entries) { - /* - * XXX: In case we allowed to set up interrupt whose number - * exceeds maximum number of interrupts for the root PIC - * disable it and print proper error message. - * - * This can happen only when calling bus_setup_intr() - * before the interrupt controller is attached. - */ - if (intr->i_cntidx >= arm64_nintrs) { - /* Better fail when IVARIANTS enabled */ - KASSERT(0, ("%s: Interrupt %u cannot be handled by the " - "registered PIC. Max interrupt number: %u", __func__, - intr->i_cntidx, arm64_nintrs - 1)); - /* Print message and disable otherwise */ - printf("ERROR: Cannot enable irq %u. Disabling.\n", - intr->i_cntidx); - PIC_MASK(root_pic, intr->i_hw_irq); - } - - if (intr->i_trig != INTR_TRIGGER_CONFORM || - intr->i_pol != INTR_POLARITY_CONFORM) { - PIC_CONFIG(root_pic, intr->i_hw_irq, - intr->i_trig, intr->i_pol); - } - - if (intr->i_handlers > 0) - PIC_UNMASK(root_pic, intr->i_hw_irq); - - } - /* Enable interrupt reception on this CPU */ - intr_enable(); - - return (0); -} - -int -arm_setup_intr(const char *name, driver_filter_t *filt, driver_intr_t handler, - void *arg, u_int hw_irq, enum intr_type flags, void **cookiep) -{ - struct arm64_intr_entry *intr; - int error; - - intr = intr_allocate(hw_irq); - if (intr == NULL) - return (ENOMEM); - - /* - * Watch out for interrupts' numbers. - * If this is a system boot then don't allow to overfill interrupts - * table (the interrupts will be deconfigured in arm_enable_intr()). - */ - if (intr->i_cntidx >= NIRQS) - return (EINVAL); - - if (intr->i_event == NULL) { - error = intr_event_create(&intr->i_event, (void *)intr, 0, - hw_irq, intr_pre_ithread, intr_post_ithread, - intr_post_filter, intr_assign_cpu, "irq%u", hw_irq); - if (error) - return (error); - } - - error = intr_event_add_handler(intr->i_event, name, filt, handler, arg, - intr_priority(flags), flags, cookiep); - - if (!error) { - intrcnt_setname(intr->i_event->ie_fullname, intr->i_cntidx); - intr->i_handlers++; - - if (!cold && intr->i_handlers == 1) { - if (intr->i_trig != INTR_TRIGGER_CONFORM || - intr->i_pol != INTR_POLARITY_CONFORM) { - PIC_CONFIG(root_pic, intr->i_hw_irq, intr->i_trig, - intr->i_pol); - } - - PIC_UNMASK(root_pic, intr->i_hw_irq); - } - } - - return (error); -} - -int -intr_irq_remove_handler(device_t dev, u_int irq, void *cookie) -{ - struct arm64_intr_entry *intr; - int error; - - intr = intr_handler_source(cookie); - error = intr_event_remove_handler(cookie); - if (!error) { - intr->i_handlers--; - if (intr->i_handlers == 0) - PIC_MASK(root_pic, intr->i_hw_irq); - intrcnt_setname(intr->i_event->ie_fullname, intr->i_cntidx); - } - - return (error); -} - -int -intr_irq_config(u_int hw_irq, enum intr_trigger trig, enum intr_polarity pol) -{ - struct arm64_intr_entry *intr; - - mtx_lock_spin(&intr_list_lock); - intr = intr_lookup_locked(hw_irq); - mtx_unlock_spin(&intr_list_lock); - if (intr == NULL) - return (EINVAL); - - intr->i_trig = trig; - intr->i_pol = pol; - - if (!cold && root_pic != NULL) - PIC_CONFIG(root_pic, intr->i_hw_irq, trig, pol); - - return (0); -} - -void -arm_dispatch_intr(u_int hw_irq, struct trapframe *tf) -{ - struct arm64_intr_entry *intr; - - mtx_lock_spin(&intr_list_lock); - intr = intr_lookup_locked(hw_irq); - mtx_unlock_spin(&intr_list_lock); - if (intr == NULL) - goto stray; - - (*intr->i_cntp)++; - - if (!intr_event_handle(intr->i_event, tf)) - return; - -stray: - if (arm64_nstray < MAX_STRAY_LOG) { - arm64_nstray++; - printf("Stray IRQ %u\n", hw_irq); - if (arm64_nstray >= MAX_STRAY_LOG) { - printf("Got %d stray IRQs. Not logging anymore.\n", - MAX_STRAY_LOG); - } - } - - if (intr != NULL) - PIC_MASK(root_pic, intr->i_hw_irq); -} - -void -intr_irq_handler(struct trapframe *tf) -{ - - critical_enter(); - PIC_DISPATCH(root_pic, tf); - critical_exit(); -#ifdef HWPMC_HOOKS - if (pmc_hook && (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN)) - pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf); -#endif -} - -#ifdef SMP -static void -arm_intr_smp_init(void *dummy __unused) -{ - struct arm64_intr_entry *intr; - int error; - - if (root_pic == NULL) - panic("Cannot assing interrupts to CPUs. No PIC configured"); - - mtx_lock_spin(&intr_list_lock); - SLIST_FOREACH(intr, &irq_slist_head, entries) { - mtx_unlock_spin(&intr_list_lock); - error = PIC_BIND(root_pic, intr->i_hw_irq, intr->i_cpu); - if (error != 0) - intr->i_cpu = 0; - mtx_lock_spin(&intr_list_lock); - } - mtx_unlock_spin(&intr_list_lock); -} -SYSINIT(arm_intr_smp_init, SI_SUB_SMP, SI_ORDER_ANY, arm_intr_smp_init, NULL); - -/* Attempt to bind the specified IRQ to the specified CPU. */ -int -intr_irq_bind(u_int hw_irq, int cpu) -{ - struct arm64_intr_entry *intr; - - mtx_lock_spin(&intr_list_lock); - intr = intr_lookup_locked(hw_irq); - mtx_unlock_spin(&intr_list_lock); - if (intr == NULL) - return (EINVAL); - - return (intr_event_bind(intr->i_event, cpu)); -} - -void -arm_setup_ipihandler(driver_filter_t *filt, u_int ipi) -{ - - arm_setup_intr("ipi", filt, NULL, (void *)((uintptr_t)ipi | 1<<16), ipi, - INTR_TYPE_MISC | INTR_EXCL, NULL); - arm_unmask_ipi(ipi); -} - -void -arm_unmask_ipi(u_int ipi) -{ - - PIC_UNMASK(root_pic, ipi); -} - -void -arm_init_secondary(void) -{ - - PIC_INIT_SECONDARY(root_pic); -} - -/* Sending IPI */ -void -ipi_all_but_self(u_int ipi) -{ - cpuset_t other_cpus; - - other_cpus = all_cpus; - CPU_CLR(PCPU_GET(cpuid), &other_cpus); - - CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); - PIC_IPI_SEND(root_pic, other_cpus, ipi); -} - -void -ipi_cpu(int cpu, u_int ipi) -{ - cpuset_t cpus; - - CPU_ZERO(&cpus); - CPU_SET(cpu, &cpus); - - CTR2(KTR_SMP, "ipi_cpu: cpu: %d, ipi: %x", cpu, ipi); - PIC_IPI_SEND(root_pic, cpus, ipi); -} - -void -ipi_selected(cpuset_t cpus, u_int ipi) -{ - - CTR1(KTR_SMP, "ipi_selected: ipi: %x", ipi); - PIC_IPI_SEND(root_pic, cpus, ipi); -} - -#endif diff --git a/sys/arm64/arm64/pic_if.m b/sys/arm64/arm64/pic_if.m deleted file mode 100644 index 33d1bcd..0000000 --- a/sys/arm64/arm64/pic_if.m +++ /dev/null @@ -1,176 +0,0 @@ -#- -# Copyright (c) 1998 Doug Rabson -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# -# from: src/sys/kern/bus_if.m,v 1.21 2002/04/21 11:16:10 markm Exp -# $FreeBSD$ -# - -#include <sys/bus.h> -#include <sys/cpuset.h> -#include <machine/frame.h> - -INTERFACE pic; - -CODE { - static int pic_bind_default(device_t dev, u_int irq, u_int cpu) - { - - return (EOPNOTSUPP); - } - - static void pic_translate_code_default(device_t dev, u_int irq, - int code, enum intr_trigger *trig, enum intr_polarity *pol) - { - *trig = INTR_TRIGGER_CONFORM; - *pol = INTR_POLARITY_CONFORM; - } - - static void pic_pre_ithread(device_t dev, u_int irq) - { - PIC_MASK(dev, irq); - PIC_EOI(dev, irq); - } - - static void pic_post_ithread(device_t dev, u_int irq) - { - PIC_UNMASK(dev, irq); - } - - static void pic_post_filter(device_t dev, u_int irq) - { - PIC_EOI(dev, irq); - } -}; - -METHOD int bind { - device_t dev; - u_int irq; - u_int cpu; -} DEFAULT pic_bind_default; - -METHOD void translate_code { - device_t dev; - u_int irq; - int code; - enum intr_trigger *trig; - enum intr_polarity *pol; -} DEFAULT pic_translate_code_default; - -METHOD void config { - device_t dev; - u_int irq; - enum intr_trigger trig; - enum intr_polarity pol; -}; - -METHOD void dispatch { - device_t dev; - struct trapframe *tf; -}; - -METHOD void enable { - device_t dev; - u_int irq; - u_int vector; -}; - -METHOD void pre_ithread { - device_t dev; - u_int irq; -} DEFAULT pic_pre_ithread; - -METHOD void post_ithread { - device_t dev; - u_int irq; -} DEFAULT pic_post_ithread; - -METHOD void post_filter { - device_t dev; - u_int irq; -} DEFAULT pic_post_filter; - -METHOD void eoi { - device_t dev; - u_int irq; -}; - -METHOD void ipi { - device_t dev; - u_int cpu; -}; - -METHOD void mask { - device_t dev; - u_int irq; -}; - -METHOD void unmask { - device_t dev; - u_int irq; -}; - -METHOD void init_secondary { - device_t dev; -}; - -METHOD void ipi_send { - device_t dev; - cpuset_t cpus; - u_int ipi; -}; - -METHOD int alloc_msi { - device_t dev; - device_t pci_dev; - int count; - int *irqs; -}; - -METHOD int alloc_msix { - device_t dev; - device_t pci_dev; - int *irq; -}; - -METHOD int map_msi { - device_t dev; - device_t pci_dev; - int irq; - uint64_t *addr; - uint32_t *data; -}; - -METHOD int release_msi { - device_t dev; - device_t pci_dev; - int count; - int *irqs; -}; - -METHOD int release_msix { - device_t dev; - device_t pci_dev; - int irq; -}; diff --git a/sys/boot/efi/boot1/boot1.c b/sys/boot/efi/boot1/boot1.c index 7383387..92eb345 100644 --- a/sys/boot/efi/boot1/boot1.c +++ b/sys/boot/efi/boot1/boot1.c @@ -629,7 +629,7 @@ efi_main(EFI_HANDLE Ximage, EFI_SYSTEM_TABLE *Xsystab) case EFI_BUFFER_TOO_SMALL: (void)bs->FreePool(handles); if ((status = bs->AllocatePool(EfiLoaderData, hsize, - (void **)&handles) != EFI_SUCCESS)) { + (void **)&handles)) != EFI_SUCCESS) { panic("Failed to allocate %zu handles (%lu)", hsize / sizeof(*handles), EFI_ERROR_CODE(status)); } diff --git a/sys/cam/cam_iosched.c b/sys/cam/cam_iosched.c index d098ae5..b24f4ca 100644 --- a/sys/cam/cam_iosched.c +++ b/sys/cam/cam_iosched.c @@ -59,15 +59,19 @@ static MALLOC_DEFINE(M_CAMSCHED, "CAM I/O Scheduler", * Default I/O scheduler for FreeBSD. This implementation is just a thin-vineer * over the bioq_* interface, with notions of separate calls for normal I/O and * for trims. + * + * When CAM_IOSCHED_DYNAMIC is defined, the scheduler is enhanced to dynamically + * steer the rate of one type of traffic to help other types of traffic (eg + * limit writes when read latency deteriorates on SSDs). */ #ifdef CAM_IOSCHED_DYNAMIC -static int do_netflix_iosched = 1; -TUNABLE_INT("kern.cam.do_netflix_iosched", &do_netflix_iosched); -SYSCTL_INT(_kern_cam, OID_AUTO, do_netflix_iosched, CTLFLAG_RD, - &do_netflix_iosched, 1, - "Enable Netflix I/O scheduler optimizations."); +static int do_dynamic_iosched = 1; +TUNABLE_INT("kern.cam.do_dynamic_iosched", &do_dynamic_iosched); +SYSCTL_INT(_kern_cam, OID_AUTO, do_dynamic_iosched, CTLFLAG_RD, + &do_dynamic_iosched, 1, + "Enable Dynamic I/O scheduler optimizations."); static int alpha_bits = 9; TUNABLE_INT("kern.cam.iosched_alpha_bits", &alpha_bits); @@ -640,7 +644,7 @@ static inline int cam_iosched_has_io(struct cam_iosched_softc *isc) { #ifdef CAM_IOSCHED_DYNAMIC - if (do_netflix_iosched) { + if (do_dynamic_iosched) { struct bio *rbp = bioq_first(&isc->bio_queue); struct bio *wbp = bioq_first(&isc->write_queue); int can_write = wbp != NULL && @@ -954,7 +958,7 @@ cam_iosched_init(struct cam_iosched_softc **iscp, struct cam_periph *periph) bioq_init(&(*iscp)->bio_queue); bioq_init(&(*iscp)->trim_queue); #ifdef CAM_IOSCHED_DYNAMIC - if (do_netflix_iosched) { + if (do_dynamic_iosched) { bioq_init(&(*iscp)->write_queue); (*iscp)->read_bias = 100; (*iscp)->current_read_bias = 100; @@ -1019,7 +1023,7 @@ void cam_iosched_sysctl_init(struct cam_iosched_softc *isc, "Sort IO queue to try and optimise disk access patterns"); #ifdef CAM_IOSCHED_DYNAMIC - if (!do_netflix_iosched) + if (!do_dynamic_iosched) return; isc->sysctl_tree = SYSCTL_ADD_NODE(&isc->sysctl_ctx, @@ -1061,7 +1065,7 @@ cam_iosched_flush(struct cam_iosched_softc *isc, struct devstat *stp, int err) bioq_flush(&isc->bio_queue, stp, err); bioq_flush(&isc->trim_queue, stp, err); #ifdef CAM_IOSCHED_DYNAMIC - if (do_netflix_iosched) + if (do_dynamic_iosched) bioq_flush(&isc->write_queue, stp, err); #endif } @@ -1206,7 +1210,7 @@ cam_iosched_next_bio(struct cam_iosched_softc *isc) * See if we have any pending writes, and room in the queue for them, * and if so, those are next. */ - if (do_netflix_iosched) { + if (do_dynamic_iosched) { if ((bp = cam_iosched_get_write(isc)) != NULL) return bp; } @@ -1223,7 +1227,7 @@ cam_iosched_next_bio(struct cam_iosched_softc *isc) * For the netflix scheduler, bio_queue is only for reads, so enforce * the limits here. Enforce only for reads. */ - if (do_netflix_iosched) { + if (do_dynamic_iosched) { if (bp->bio_cmd == BIO_READ && cam_iosched_limiter_iop(&isc->read_stats, bp) != 0) return NULL; @@ -1231,7 +1235,7 @@ cam_iosched_next_bio(struct cam_iosched_softc *isc) #endif bioq_remove(&isc->bio_queue, bp); #ifdef CAM_IOSCHED_DYNAMIC - if (do_netflix_iosched) { + if (do_dynamic_iosched) { if (bp->bio_cmd == BIO_READ) { isc->read_stats.queued--; isc->read_stats.total++; @@ -1268,7 +1272,7 @@ cam_iosched_queue_work(struct cam_iosched_softc *isc, struct bio *bp) #endif } #ifdef CAM_IOSCHED_DYNAMIC - else if (do_netflix_iosched && + else if (do_dynamic_iosched && (bp->bio_cmd == BIO_WRITE || bp->bio_cmd == BIO_FLUSH)) { if (cam_iosched_sort_queue(isc)) bioq_disksort(&isc->write_queue, bp); @@ -1332,7 +1336,7 @@ cam_iosched_bio_complete(struct cam_iosched_softc *isc, struct bio *bp, { int retval = 0; #ifdef CAM_IOSCHED_DYNAMIC - if (!do_netflix_iosched) + if (!do_dynamic_iosched) return retval; if (iosched_debug > 10) diff --git a/sys/cddl/compat/opensolaris/sys/proc.h b/sys/cddl/compat/opensolaris/sys/proc.h index 1fe2e9a..5c9e8de 100644 --- a/sys/cddl/compat/opensolaris/sys/proc.h +++ b/sys/cddl/compat/opensolaris/sys/proc.h @@ -45,8 +45,8 @@ #define CPU curcpu #define minclsyspri PRIBIO #define maxclsyspri PVM -#define max_ncpus mp_ncpus -#define boot_max_ncpus mp_ncpus +#define max_ncpus (mp_maxid + 1) +#define boot_max_ncpus (mp_maxid + 1) #define TS_RUN 0 diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c index 19a1666..31a8c65 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c @@ -919,6 +919,12 @@ sysctl_vfs_zfs_arc_max(SYSCTL_HANDLER_ARGS) if (err != 0 || req->newptr == NULL) return (err); + if (zfs_arc_max == 0) { + /* Loader tunable so blindly set */ + zfs_arc_max = val; + return (0); + } + if (val < arc_abs_min || val > kmem_size()) return (EINVAL); if (val < arc_c_min) @@ -956,6 +962,12 @@ sysctl_vfs_zfs_arc_min(SYSCTL_HANDLER_ARGS) if (err != 0 || req->newptr == NULL) return (err); + if (zfs_arc_min == 0) { + /* Loader tunable so blindly set */ + zfs_arc_min = val; + return (0); + } + if (val < arc_abs_min || val > arc_c_max) return (EINVAL); diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index 3f0d627..6a78f08 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -25,15 +25,10 @@ arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard -arm64/arm64/gic.c optional !intrng arm64/arm64/gicv3_its.c optional intrng -arm64/arm64/gic_acpi.c optional !intrng acpi -arm64/arm64/gic_fdt.c optional !intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt -arm64/arm64/gic_v3_its.c optional !intrng arm64/arm64/identcpu.c standard -arm64/arm64/intr_machdep.c optional !intrng arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard @@ -42,7 +37,6 @@ arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt -arm64/arm64/pic_if.m optional !intrng arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard diff --git a/sys/conf/kern.mk b/sys/conf/kern.mk index f561f8a..0eb50e6 100644 --- a/sys/conf/kern.mk +++ b/sys/conf/kern.mk @@ -62,7 +62,7 @@ CWARNEXTRA?= -Wno-uninitialized FORMAT_EXTENSIONS= -Wno-format .elif ${COMPILER_TYPE} == "clang" && ${COMPILER_VERSION} >= 30600 FORMAT_EXTENSIONS= -D__printf__=__freebsd_kprintf__ -.else +.elif ${COMPILER_TYPE} == "gcc" && ${COMPILER_VERSION} == 40201 FORMAT_EXTENSIONS= -fformat-extensions .endif diff --git a/sys/conf/newvers.sh b/sys/conf/newvers.sh index 7e6b1d2..9be2fcd 100644 --- a/sys/conf/newvers.sh +++ b/sys/conf/newvers.sh @@ -32,7 +32,7 @@ TYPE="FreeBSD" REVISION="11.0" -BRANCH="ALPHA6" +BRANCH="BETA1" if [ -n "${BRANCH_OVERRIDE}" ]; then BRANCH=${BRANCH_OVERRIDE} fi diff --git a/sys/contrib/ipfilter/netinet/mlfk_ipl.c b/sys/contrib/ipfilter/netinet/mlfk_ipl.c index d8c40cd..3713911 100644 --- a/sys/contrib/ipfilter/netinet/mlfk_ipl.c +++ b/sys/contrib/ipfilter/netinet/mlfk_ipl.c @@ -291,13 +291,14 @@ vnet_ipf_uninit(void) return; if (V_ipfmain.ipf_running >= 0) { + if (ipfdetach(&V_ipfmain) != 0) return; + V_ipfmain.ipf_running = -2; + ipf_destroy_all(&V_ipfmain); } - - V_ipfmain.ipf_running = -2; } VNET_SYSUNINIT(vnet_ipf_uninit, SI_SUB_PROTO_FIREWALL, SI_ORDER_THIRD, vnet_ipf_uninit, NULL); diff --git a/sys/contrib/ncsw/inc/error_ext.h b/sys/contrib/ncsw/inc/error_ext.h index 778ba30..29a7930 100644 --- a/sys/contrib/ncsw/inc/error_ext.h +++ b/sys/contrib/ncsw/inc/error_ext.h @@ -353,6 +353,7 @@ int ERROR_DYNAMIC_LEVEL = ERROR_GLOBAL_LEVEL; #define PRINT_FORMAT "[CPU%02d, %s:%d %s]" #define PRINT_FMT_PARAMS CORE_GetId(), __FILE__, __LINE__, __FUNCTION__ +#define ERR_STRING(err) #err #if (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0)) /* No debug/error/event messages at all */ @@ -398,7 +399,7 @@ extern const char *eventStrings[]; if (REPORT_LEVEL_##_level <= DEBUG_DYNAMIC_LEVEL) { \ XX_Print("> %s (%s) " PRINT_FORMAT ": ", \ dbgLevelStrings[REPORT_LEVEL_##_level - 1], \ - moduleStrings[__ERR_MODULE__ >> 16], \ + ERR_STRING(__ERR_MODULE__), \ PRINT_FMT_PARAMS); \ XX_Print _vmsg; \ XX_Print("\r\n"); \ @@ -412,7 +413,7 @@ extern const char *eventStrings[]; if (REPORT_LEVEL_##_level <= ERROR_DYNAMIC_LEVEL) { \ XX_Print("! %s %s Error " PRINT_FORMAT ": %s; ", \ dbgLevelStrings[REPORT_LEVEL_##_level - 1], \ - moduleStrings[__ERR_MODULE__ >> 16], \ + ERR_STRING(__ERR_MODULE__), \ PRINT_FMT_PARAMS, \ errTypeStrings[(GET_ERROR_TYPE(_err) - E_OK - 1)]); \ XX_Print _vmsg; \ @@ -435,7 +436,7 @@ extern const char *eventStrings[]; if (_ev##_LEVEL <= EVENT_DYNAMIC_LEVEL) { \ XX_Print("~ %s %s Event " PRINT_FORMAT ": %s (flags: 0x%04x); ", \ dbgLevelStrings[_ev##_LEVEL - 1], \ - moduleStrings[__ERR_MODULE__ >> 16], \ + ERR_STRING(__ERR_MODULE__), \ PRINT_FMT_PARAMS, \ eventStrings[((_ev) - EV_NO_EVENT - 1)], \ (uint16_t)(_flg)); \ diff --git a/sys/contrib/ncsw/inc/integrations/P2041/dpaa_integration_ext.h b/sys/contrib/ncsw/inc/integrations/P2041/dpaa_integration_ext.h deleted file mode 100644 index f94fa70..0000000 --- a/sys/contrib/ncsw/inc/integrations/P2041/dpaa_integration_ext.h +++ /dev/null @@ -1,349 +0,0 @@ -/****************************************************************************** - - © 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. - All rights reserved. - - This is proprietary source code of Freescale Semiconductor Inc., - and its use is subject to the NetComm Device Drivers EULA. - The copyright notice above does not evidence any actual or intended - publication of such source code. - - ALTERNATIVELY, redistribution and use in source and binary forms, with - or without modification, are permitted provided that the following - conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Freescale Semiconductor nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - **************************************************************************/ -/** - - @File dpaa_integration_ext.h - - @Description P2041 FM external definitions and structures. -*//***************************************************************************/ -#ifndef __DPAA_INTEGRATION_EXT_H -#define __DPAA_INTEGRATION_EXT_H - -#include "std_ext.h" - - -/**************************************************************************//** - @Description DPAA SW Portals Enumeration. -*//***************************************************************************/ -typedef enum -{ - e_DPAA_SWPORTAL0 = 0, - e_DPAA_SWPORTAL1, - e_DPAA_SWPORTAL2, - e_DPAA_SWPORTAL3, - e_DPAA_SWPORTAL4, - e_DPAA_SWPORTAL5, - e_DPAA_SWPORTAL6, - e_DPAA_SWPORTAL7, - e_DPAA_SWPORTAL8, - e_DPAA_SWPORTAL9, - e_DPAA_SWPORTAL_DUMMY_LAST -} e_DpaaSwPortal; - -/**************************************************************************//** - @Description DPAA Direct Connect Portals Enumeration. -*//***************************************************************************/ -typedef enum -{ - e_DPAA_DCPORTAL0 = 0, - e_DPAA_DCPORTAL1, - e_DPAA_DCPORTAL2, - e_DPAA_DCPORTAL3, - e_DPAA_DCPORTAL4, - e_DPAA_DCPORTAL_DUMMY_LAST -} e_DpaaDcPortal; - -#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST -#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST - -/***************************************************************************** - QMan INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */ -#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */ -#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */ -#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE) - /**< FQIDs range - 24 bits */ - -/**************************************************************************//** - @Description Work Queue Channel assignments in QMan. -*//***************************************************************************/ -typedef enum -{ - e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */ - e_QM_FQ_CHANNEL_SWPORTAL1, - e_QM_FQ_CHANNEL_SWPORTAL2, - e_QM_FQ_CHANNEL_SWPORTAL3, - e_QM_FQ_CHANNEL_SWPORTAL4, - e_QM_FQ_CHANNEL_SWPORTAL5, - e_QM_FQ_CHANNEL_SWPORTAL6, - e_QM_FQ_CHANNEL_SWPORTAL7, - e_QM_FQ_CHANNEL_SWPORTAL8, - e_QM_FQ_CHANNEL_SWPORTAL9, - - e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */ - e_QM_FQ_CHANNEL_POOL2, - e_QM_FQ_CHANNEL_POOL3, - e_QM_FQ_CHANNEL_POOL4, - e_QM_FQ_CHANNEL_POOL5, - e_QM_FQ_CHANNEL_POOL6, - e_QM_FQ_CHANNEL_POOL7, - e_QM_FQ_CHANNEL_POOL8, - e_QM_FQ_CHANNEL_POOL9, - e_QM_FQ_CHANNEL_POOL10, - e_QM_FQ_CHANNEL_POOL11, - e_QM_FQ_CHANNEL_POOL12, - e_QM_FQ_CHANNEL_POOL13, - e_QM_FQ_CHANNEL_POOL14, - e_QM_FQ_CHANNEL_POOL15, - - e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0: - connected to FMan 0; assigned in incrementing order to - each sub-portal (SP) in the portal */ - e_QM_FQ_CHANNEL_FMAN0_SP1, - e_QM_FQ_CHANNEL_FMAN0_SP2, - e_QM_FQ_CHANNEL_FMAN0_SP3, - e_QM_FQ_CHANNEL_FMAN0_SP4, - e_QM_FQ_CHANNEL_FMAN0_SP5, - e_QM_FQ_CHANNEL_FMAN0_SP6, - e_QM_FQ_CHANNEL_FMAN0_SP7, - e_QM_FQ_CHANNEL_FMAN0_SP8, - e_QM_FQ_CHANNEL_FMAN0_SP9, - e_QM_FQ_CHANNEL_FMAN0_SP10, - e_QM_FQ_CHANNEL_FMAN0_SP11, - - e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */ - e_QM_FQ_CHANNEL_RMAN_SP3, - - e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2: - connected to SEC 4.x */ - - e_QM_FQ_CHANNEL_PME = 0xA0 /**< Dedicated channel serviced by Direct Connect Portal 3: - connected to PME */ -} e_QmFQChannel; - -/***************************************************************************** - BMan INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */ - -/***************************************************************************** - SEC INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define SEC_NUM_OF_DECOS 2 -#define SEC_ALL_DECOS_MASK 0x00000003 - -/***************************************************************************** - FM INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define INTG_MAX_NUM_OF_FM 1 - -/* Ports defines */ -#define FM_MAX_NUM_OF_1G_MACS 5 -#define FM_MAX_NUM_OF_10G_MACS 1 -#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) -#define FM_MAX_NUM_OF_OH_PORTS 7 - -#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS -#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS -#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) - -#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS -#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS -#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) - -#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */ -#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */ -#define FM_MAX_NUM_OF_SUB_PORTALS 12 -#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0 - -/* RAMs defines */ -#define FM_MURAM_SIZE (160 * KILOBYTE) -#define FM_IRAM_SIZE ( 64 * KILOBYTE) - -/* PCD defines */ -#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */ -#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */ -#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */ - -/* RTC defines */ -#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */ -#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */ -#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */ - -/* QMI defines */ -#define QMI_MAX_NUM_OF_TNUMS 64 -#define MAX_QMI_DEQ_SUBPORTAL 12 -#define QMI_DEF_TNUMS_THRESH 48 - -/* FPM defines */ -#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 - -/* DMA defines */ -#define DMA_THRESH_MAX_COMMQ 31 -#define DMA_THRESH_MAX_BUF 127 - -/* BMI defines */ -#define BMI_MAX_NUM_OF_TASKS 128 -#define BMI_MAX_NUM_OF_DMAS 32 -#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -#define PORT_MAX_WEIGHT 16 /**< Port weight in BMI arbitration register */ - - -/**************************************************************************//** - @Description Enum for inter-module interrupts registration -*//***************************************************************************/ -typedef enum e_FmEventModules -{ - e_FM_MOD_PRS, /**< Parser event */ - e_FM_MOD_KG, /**< Keygen event */ - e_FM_MOD_PLCR, /**< Policer event */ - e_FM_MOD_10G_MAC, /**< 10G MAC error event */ - e_FM_MOD_1G_MAC, /**< 1G MAC error event */ - e_FM_MOD_TMR, /**< Timer event */ - e_FM_MOD_1G_MAC_TMR, /**< 1G MAC timer event */ - e_FM_MOD_FMAN_CTRL, /**< FMAN Controller timer event */ - e_FM_MOD_DUMMY_LAST -} e_FmEventModules; - -/**************************************************************************//** - @Description Enum for interrupts types -*//***************************************************************************/ -typedef enum e_FmIntrType -{ - e_FM_INTR_TYPE_ERR, - e_FM_INTR_TYPE_NORMAL -} e_FmIntrType; - -/**************************************************************************//** - @Description Enum for inter-module interrupts registration -*//***************************************************************************/ -typedef enum e_FmInterModuleEvent -{ - e_FM_EV_PRS, /**< Parser event */ - e_FM_EV_ERR_PRS, /**< Parser error event */ - e_FM_EV_KG, /**< Keygen event */ - e_FM_EV_ERR_KG, /**< Keygen error event */ - e_FM_EV_PLCR, /**< Policer event */ - e_FM_EV_ERR_PLCR, /**< Policer error event */ - e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */ - e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */ - e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */ - e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */ - e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */ - e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */ - e_FM_EV_TMR, /**< Timer event */ - e_FM_EV_1G_MAC0_TMR, /**< 1G MAC 0 timer event */ - e_FM_EV_1G_MAC1_TMR, /**< 1G MAC 1 timer event */ - e_FM_EV_1G_MAC2_TMR, /**< 1G MAC 2 timer event */ - e_FM_EV_1G_MAC3_TMR, /**< 1G MAC 3 timer event */ - e_FM_EV_1G_MAC4_TMR, /**< 1G MAC 4 timer event */ - e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */ - e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */ - e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */ - e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */ - e_FM_EV_DUMMY_LAST -} e_FmInterModuleEvent; - -#define GET_FM_MODULE_EVENT(mod, id, intrType, event) \ - switch(mod){ \ - case e_FM_MOD_PRS: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \ - break; \ - case e_FM_MOD_KG: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \ - break; \ - case e_FM_MOD_PLCR: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \ - break; \ - case e_FM_MOD_10G_MAC: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_10G_MAC0 : e_FM_EV_DUMMY_LAST; \ - break; \ - case e_FM_MOD_1G_MAC: \ - switch(id){ \ - case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC0 : e_FM_EV_DUMMY_LAST; break; \ - case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC1 : e_FM_EV_DUMMY_LAST; break; \ - case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC2 : e_FM_EV_DUMMY_LAST; break; \ - case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC3 : e_FM_EV_DUMMY_LAST; break; \ - case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC4 : e_FM_EV_DUMMY_LAST; break; \ - } \ - break; \ - case e_FM_MOD_TMR: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \ - break; \ - case e_FM_MOD_1G_MAC_TMR: \ - switch(id){ \ - case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC0_TMR; break; \ - case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC1_TMR; break; \ - case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC2_TMR; break; \ - case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC3_TMR; break; \ - case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC4_TMR; break; \ - } \ - break; \ - case e_FM_MOD_FMAN_CTRL: \ - if (intrType == e_FM_INTR_TYPE_ERR) event = e_FM_EV_DUMMY_LAST; \ - else switch(id){ \ - case(0): event = e_FM_EV_FMAN_CTRL_0; break; \ - case(1): event = e_FM_EV_FMAN_CTRL_1; break; \ - case(2): event = e_FM_EV_FMAN_CTRL_2; break; \ - case(3): event = e_FM_EV_FMAN_CTRL_3; break; \ - } \ - break; \ - default: event = e_FM_EV_DUMMY_LAST; \ - break;} - -#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE - -/* P2041 unique features */ -#define FM_QMI_DEQ_OPTIONS_SUPPORT -#define FM_NO_DISPATCH_RAM_ECC -#define FM_FIFO_ALLOCATION_OLD_ALG -#define FM_NO_WATCHDOG -#define FM_NO_TNUM_AGING -#define FM_NO_TGEC_LOOPBACK -#define FM_KG_NO_BYPASS_FQID_GEN -#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN -#define FM_NO_BACKUP_POOLS -#define FM_NO_OP_OBSERVED_POOLS -#define FM_NO_ADVANCED_RATE_LIMITER -#define FM_NO_OP_OBSERVED_CGS - -/* FM erratas */ -#define FM_BAD_VLAN_DETECT_ERRATA_10GMAC_A010 - -#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 -#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */ - -#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 - -#define FM_LEN_CHECK_ERRATA_FMAN_SW002 -#define FM_PRS_MEM_ERRATA_FMAN_SW003 - -#endif /* __DPAA_INTEGRATION_EXT_H */ diff --git a/sys/contrib/ncsw/inc/integrations/P2041/part_integration_ext.h b/sys/contrib/ncsw/inc/integrations/P2041/part_integration_ext.h deleted file mode 100644 index 5a00dfb..0000000 --- a/sys/contrib/ncsw/inc/integrations/P2041/part_integration_ext.h +++ /dev/null @@ -1,758 +0,0 @@ -/****************************************************************************** - - © 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. - All rights reserved. - - This is proprietary source code of Freescale Semiconductor Inc., - and its use is subject to the NetComm Device Drivers EULA. - The copyright notice above does not evidence any actual or intended - publication of such source code. - - ALTERNATIVELY, redistribution and use in source and binary forms, with - or without modification, are permitted provided that the following - conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Freescale Semiconductor nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - **************************************************************************/ -/** - - @File part_integration_ext.h - - @Description P2041 external definitions and structures. -*//***************************************************************************/ -#ifndef __PART_INTEGRATION_EXT_H -#define __PART_INTEGRATION_EXT_H - -#include "std_ext.h" -#include "ddr_std_ext.h" -#include "enet_ext.h" -#include "dpaa_integration_ext.h" - - -/**************************************************************************//** - @Group P2041_chip_id P2041 Application Programming Interface - - @Description P2041 Chip functions,definitions and enums. - - @{ -*//***************************************************************************/ - -#define CORE_E500MC - -#define INTG_MAX_NUM_OF_CORES 4 - - -/**************************************************************************//** - @Description Module types. -*//***************************************************************************/ -typedef enum e_ModuleId -{ - e_MODULE_ID_DUART_1 = 0, - e_MODULE_ID_DUART_2, - e_MODULE_ID_DUART_3, - e_MODULE_ID_DUART_4, - e_MODULE_ID_LAW, - e_MODULE_ID_LBC, - e_MODULE_ID_PAMU, - e_MODULE_ID_QM, /**< Queue manager module */ - e_MODULE_ID_BM, /**< Buffer manager module */ - e_MODULE_ID_QM_CE_PORTAL_0, - e_MODULE_ID_QM_CI_PORTAL_0, - e_MODULE_ID_QM_CE_PORTAL_1, - e_MODULE_ID_QM_CI_PORTAL_1, - e_MODULE_ID_QM_CE_PORTAL_2, - e_MODULE_ID_QM_CI_PORTAL_2, - e_MODULE_ID_QM_CE_PORTAL_3, - e_MODULE_ID_QM_CI_PORTAL_3, - e_MODULE_ID_QM_CE_PORTAL_4, - e_MODULE_ID_QM_CI_PORTAL_4, - e_MODULE_ID_QM_CE_PORTAL_5, - e_MODULE_ID_QM_CI_PORTAL_5, - e_MODULE_ID_QM_CE_PORTAL_6, - e_MODULE_ID_QM_CI_PORTAL_6, - e_MODULE_ID_QM_CE_PORTAL_7, - e_MODULE_ID_QM_CI_PORTAL_7, - e_MODULE_ID_QM_CE_PORTAL_8, - e_MODULE_ID_QM_CI_PORTAL_8, - e_MODULE_ID_QM_CE_PORTAL_9, - e_MODULE_ID_QM_CI_PORTAL_9, - e_MODULE_ID_BM_CE_PORTAL_0, - e_MODULE_ID_BM_CI_PORTAL_0, - e_MODULE_ID_BM_CE_PORTAL_1, - e_MODULE_ID_BM_CI_PORTAL_1, - e_MODULE_ID_BM_CE_PORTAL_2, - e_MODULE_ID_BM_CI_PORTAL_2, - e_MODULE_ID_BM_CE_PORTAL_3, - e_MODULE_ID_BM_CI_PORTAL_3, - e_MODULE_ID_BM_CE_PORTAL_4, - e_MODULE_ID_BM_CI_PORTAL_4, - e_MODULE_ID_BM_CE_PORTAL_5, - e_MODULE_ID_BM_CI_PORTAL_5, - e_MODULE_ID_BM_CE_PORTAL_6, - e_MODULE_ID_BM_CI_PORTAL_6, - e_MODULE_ID_BM_CE_PORTAL_7, - e_MODULE_ID_BM_CI_PORTAL_7, - e_MODULE_ID_BM_CE_PORTAL_8, - e_MODULE_ID_BM_CI_PORTAL_8, - e_MODULE_ID_BM_CE_PORTAL_9, - e_MODULE_ID_BM_CI_PORTAL_9, - e_MODULE_ID_FM, /**< Frame manager module */ - e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */ - e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */ - e_MODULE_ID_FM_BMI, /**< FM BMI block */ - e_MODULE_ID_FM_QMI, /**< FM QMI block */ - e_MODULE_ID_FM_PARSER, /**< FM parser block */ - e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */ - e_MODULE_ID_FM_PLCR, /**< FM Policer */ - e_MODULE_ID_FM_KG, /**< FM Keygen */ - e_MODULE_ID_FM_DMA, /**< FM DMA */ - e_MODULE_ID_FM_FPM, /**< FM FPM */ - e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */ - e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/ - e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/ - e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/ - e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/ - e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/ - e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */ - e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ - e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */ - e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */ - e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */ - e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */ - e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */ - e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */ - - e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ - e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ - e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ - e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ - e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ - e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ - e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ - e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ - e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ - e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ - e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ - e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ - - e_MODULE_ID_PIC, /**< PIC */ - e_MODULE_ID_GPIO, /**< GPIO */ - e_MODULE_ID_SERDES, /**< SERDES */ - e_MODULE_ID_CPC, /**< CoreNet-Platform-Cache */ - e_MODULE_ID_DUMMY_LAST -} e_ModuleId; - -#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST - -/* Offsets relative to CCSR base */ -#define P2041_OFFSET_LAW 0x00000c00 -#define P2041_OFFSET_DDR 0x00008000 -#define P2041_OFFSET_CPC 0x00010000 -#define P2041_OFFSET_CCM 0x00018000 -#define P2041_OFFSET_PAMU 0x00020000 -#define P2041_OFFSET_PIC 0x00040000 -#define P2041_OFFSET_GUTIL 0x000e0000 -#define P2041_OFFSET_RCPM 0x000e2000 -#define P2041_OFFSET_SERDES 0x000ea000 -#define P2041_OFFSET_DMA1 0x00100100 -#define P2041_OFFSET_DMA2 0x00101100 -#define P2041_OFFSET_ESPI 0x00110000 -#define P2041_OFFSET_ESDHC 0x00114000 -#define P2041_OFFSET_I2C1 0x00118000 -#define P2041_OFFSET_I2C2 0x00118100 -#define P2041_OFFSET_I2C3 0x00119000 -#define P2041_OFFSET_I2C4 0x00119100 -#define P2041_OFFSET_DUART1 0x0011c500 -#define P2041_OFFSET_DUART2 0x0011c600 -#define P2041_OFFSET_DUART3 0x0011d500 -#define P2041_OFFSET_DUART4 0x0011d600 -#define P2041_OFFSET_LBC 0x00124000 -#define P2041_OFFSET_GPIO 0x00130000 -#define P2041_OFFSET_PCIE1 0x00200000 -#define P2041_OFFSET_PCIE2 0x00201000 -#define P2041_OFFSET_PCIE3 0x00202000 -#define P2041_OFFSET_USB1 0x00210000 -#define P2041_OFFSET_USB2 0x00211000 -#define P2041_OFFSET_USB_PHY 0x00214000 -#define P2041_OFFSET_SATA1 0x00220000 -#define P2041_OFFSET_SATA2 0x00221000 -#define P2041_OFFSET_SEC_GEN 0x00300000 -#define P2041_OFFSET_SEC_JQ0 0x00301000 -#define P2041_OFFSET_SEC_JQ1 0x00302000 -#define P2041_OFFSET_SEC_JQ2 0x00303000 -#define P2041_OFFSET_SEC_JQ3 0x00304000 -#define P2041_OFFSET_SEC_RESERVED 0x00305000 -#define P2041_OFFSET_SEC_RTIC 0x00306000 -#define P2041_OFFSET_SEC_QI 0x00307000 -#define P2041_OFFSET_SEC_DECO0_CCB0 0x00308000 -#define P2041_OFFSET_SEC_DECO1_CCB1 0x00309000 -#define P2041_OFFSET_PME 0x00316000 -#define P2041_OFFSET_QM 0x00318000 -#define P2041_OFFSET_BM 0x0031a000 -#define P2041_OFFSET_FM 0x00400000 - -#define P2041_OFFSET_FM_MURAM P2041_OFFSET_FM -#define P2041_OFFSET_FM_BMI (P2041_OFFSET_FM + 0x00080000) -#define P2041_OFFSET_FM_QMI (P2041_OFFSET_FM + 0x00080400) -#define P2041_OFFSET_FM_PARSER (P2041_OFFSET_FM + 0x00080800) -#define P2041_OFFSET_FM_PORT_HO1 (P2041_OFFSET_FM + 0x00081000) /* host command/offline parser */ -#define P2041_OFFSET_FM_PORT_HO2 (P2041_OFFSET_FM + 0x00082000) -#define P2041_OFFSET_FM_PORT_HO3 (P2041_OFFSET_FM + 0x00083000) -#define P2041_OFFSET_FM_PORT_HO4 (P2041_OFFSET_FM + 0x00084000) -#define P2041_OFFSET_FM_PORT_HO5 (P2041_OFFSET_FM + 0x00085000) -#define P2041_OFFSET_FM_PORT_HO6 (P2041_OFFSET_FM + 0x00086000) -#define P2041_OFFSET_FM_PORT_HO7 (P2041_OFFSET_FM + 0x00087000) -#define P2041_OFFSET_FM_PORT_1GRX1 (P2041_OFFSET_FM + 0x00088000) -#define P2041_OFFSET_FM_PORT_1GRX2 (P2041_OFFSET_FM + 0x00089000) -#define P2041_OFFSET_FM_PORT_1GRX3 (P2041_OFFSET_FM + 0x0008a000) -#define P2041_OFFSET_FM_PORT_1GRX4 (P2041_OFFSET_FM + 0x0008b000) -#define P2041_OFFSET_FM_PORT_1GRX5 (P2041_OFFSET_FM + 0x0008c000) -#define P2041_OFFSET_FM_PORT_10GRX (P2041_OFFSET_FM + 0x00090000) -#define P2041_OFFSET_FM_PORT_1GTX1 (P2041_OFFSET_FM + 0x000a8000) -#define P2041_OFFSET_FM_PORT_1GTX2 (P2041_OFFSET_FM + 0x000a9000) -#define P2041_OFFSET_FM_PORT_1GTX3 (P2041_OFFSET_FM + 0x000aa000) -#define P2041_OFFSET_FM_PORT_1GTX4 (P2041_OFFSET_FM + 0x000ab000) -#define P2041_OFFSET_FM_PORT_1GTX5 (P2041_OFFSET_FM + 0x000ac000) -#define P2041_OFFSET_FM_PORT_10GTX (P2041_OFFSET_FM + 0x000b0000) -#define P2041_OFFSET_FM_PLCR (P2041_OFFSET_FM + 0x000c0000) -#define P2041_OFFSET_FM_KG (P2041_OFFSET_FM + 0x000c1000) -#define P2041_OFFSET_FM_DMA (P2041_OFFSET_FM + 0x000c2000) -#define P2041_OFFSET_FM_FPM (P2041_OFFSET_FM + 0x000c3000) -#define P2041_OFFSET_FM_IRAM (P2041_OFFSET_FM + 0x000c4000) -#define P2041_OFFSET_FM_PARSER_IRAM (P2041_OFFSET_FM + 0x000c7000) -#define P2041_OFFSET_FM_1GMAC1 (P2041_OFFSET_FM + 0x000e0000) -#define P2041_OFFSET_FM_1GMDIO (P2041_OFFSET_FM + 0x000e1000 + 0x120) -#define P2041_OFFSET_FM_1GMAC2 (P2041_OFFSET_FM + 0x000e2000) -#define P2041_OFFSET_FM_1GMAC3 (P2041_OFFSET_FM + 0x000e4000) -#define P2041_OFFSET_FM_1GMAC4 (P2041_OFFSET_FM + 0x000e6000) -#define P2041_OFFSET_FM_1GMAC5 (P2041_OFFSET_FM + 0x000e8000) -#define P2041_OFFSET_FM_10GMAC (P2041_OFFSET_FM + 0x000f0000) -#define P2041_OFFSET_FM_10GMDIO (P2041_OFFSET_FM + 0x000f1000 + 0x030) -#define P2041_OFFSET_FM_RTC (P2041_OFFSET_FM + 0x000fe000) - -/* Offsets relative to QM or BM portals base */ -#define P2041_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */ -#define P2041_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */ - -#define P2041_CE_PORTAL_SIZE 0x4000 -#define P2041_CI_PORTAL_SIZE 0x1000 - -#define P2041_OFFSET_PORTALS_CE(portal) \ - (P2041_OFFSET_PORTALS_CE_AREA + P2041_CE_PORTAL_SIZE * (portal)) -#define P2041_OFFSET_PORTALS_CI(portal) \ - (P2041_OFFSET_PORTALS_CI_AREA + P2041_CI_PORTAL_SIZE * (portal)) - - -/**************************************************************************//** - @Description Transaction source ID (for memory conrollers error reporting). -*//***************************************************************************/ -typedef enum e_TransSrc -{ - e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */ - e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */ - e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */ - e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */ - e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */ - e_TRANS_SRC_BMAN = 0x18, /**< BMan */ - e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */ - e_TRANS_SRC_PME = 0x20, /**< PME */ - e_TRANS_SRC_SEC = 0x21, /**< Security engine */ - e_TRANS_SRC_QMAN = 0x3C, /**< QMan */ - e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */ - e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */ - e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */ - e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */ - e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */ - e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */ - e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */ - e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */ - e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */ - e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */ - e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */ - e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */ - e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */ - e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */ - e_TRANS_SRC_CORE_2_INST = 0x84, /**< Processor 2 (instruction) */ - e_TRANS_SRC_CORE_2_DATA = 0x85, /**< Processor 2 (data) */ - e_TRANS_SRC_CORE_3_INST = 0x86, /**< Processor 3 (instruction) */ - e_TRANS_SRC_CORE_3_DATA = 0x87, /**< Processor 3 (data) */ - e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */ - e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */ - e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */ - e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */ - e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */ - e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */ - e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */ - e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */ - e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */ - e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */ - e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */ - e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */ - e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */ -} e_TransSrc; - -/**************************************************************************//** - @Description Local Access Window Target interface ID -*//***************************************************************************/ -typedef enum e_P2041LawTargetId -{ - e_P2041_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */ - e_P2041_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */ - e_P2041_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */ - e_P2041_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */ - e_P2041_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */ - e_P2041_LAW_TARGET_DDR_CPC = 0x10, /**< DDR controller or CPC SRAM */ - e_P2041_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */ - e_P2041_LAW_TARGET_DCSR = 0x1D, /**< DCSR */ - e_P2041_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */ - e_P2041_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */ - e_P2041_LAW_TARGET_NONE = 0xFF /**< None */ -} e_P2041LawTargetId; - -/*************************************************************** - P2041 general routines -****************************************************************/ -/**************************************************************************//** - @Group P2041_init_grp P2041 Initialization Unit - - @Description P2041 initialization unit API functions, definitions and enums - - @{ -*//***************************************************************************/ - -/**************************************************************************//** - @Description Part ID and revision number -*//***************************************************************************/ -typedef enum e_P2041DeviceName -{ - e_P2041_REV_INVALID = 0x00000000, /**< Invalid revision */ - e_P2040_REV_1_0 = (int)0x82180010, /**< P2040 with security, revision 1.0 */ - e_P2040_REV_1_0_NO_SEC = (int)0x82100010, /**< P2040 without security, revision 1.0 */ - e_P2041_REV_1_0 = (int)0x82180110, /**< P2041 with security, revision 1.0 */ - e_P2041_REV_1_0_NO_SEC = (int)0x82100110 /**< P2041 without security, revision 1.0 */ -} e_P2041DeviceName; - -/**************************************************************************//** - @Description Device Disable Register -*//***************************************************************************/ -typedef enum e_P2041DeviceDisable -{ - e_P2041_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */ - e_P2041_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */ - e_P2041_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */ - e_P2041_DEV_DISABLE_RMAN = 4, /**< RapidIO message manager disable */ - e_P2041_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */ - e_P2041_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */ - e_P2041_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */ - e_P2041_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */ - e_P2041_DEV_DISABLE_DDR, /**< DDR controller disable */ - e_P2041_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */ - e_P2041_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */ - e_P2041_DEV_DISABLE_LBC, /**< eLBC controller disable */ - e_P2041_DEV_DISABLE_USB_1, /**< USB controller 1 disable */ - e_P2041_DEV_DISABLE_USB_2, /**< USB controller 2 disable */ - e_P2041_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */ - e_P2041_DEV_DISABLE_GPIO, /**< GPIO controller disable */ - e_P2041_DEV_DISABLE_ESPI, /**< eSPI controller disable */ - e_P2041_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */ - e_P2041_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */ - e_P2041_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */ - e_P2041_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */ - e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST = 32, - /**< Dummy entry signing end of DEVDISR1 register controllers */ - e_P2041_DEV_DISABLE_PME = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST, - /**< Pattern match engine disable */ - e_P2041_DEV_DISABLE_SEC, /**< Security disable */ - e_P2041_DEV_DISABLE_QM_BM = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST + 4, - /**< Queue manager/buffer manager disable */ - e_P2041_DEV_DISABLE_FM = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST + 6, - /**< Frame manager disable */ - e_P2041_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */ - e_P2041_DEV_DISABLE_DTSEC_1, - /**< dTSEC controller 1 disable */ - e_P2041_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */ - e_P2041_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */ - e_P2041_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */ - e_P2041_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */ -} e_P2041DeviceDisable; - - -/**************************************************************************//* - @Description structure representing P2041 devices configuration -*//***************************************************************************/ -typedef struct t_P2041Devices -{ - struct - { - struct - { - bool enabled; - uint8_t serdesBank; - uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank, - one bit for lane, lane A is the first and so on, e.g., - set 0xF000 for ABCD lanes */ - e_EnetInterface ethIf; - uint8_t ratio; - bool divByTwo; - bool isTwoHalfSgmii; - } dtsecs[FM_MAX_NUM_OF_1G_MACS]; - struct - { - bool enabled; - uint8_t serdesBank; - uint16_t serdesLane; - } tgec; - } fm; -} t_P2041Devices; - -/**************************************************************************//** - @Function P2041_GetRevInfo - - @Description Obtain revision information. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return Part ID and revision. -*//***************************************************************************/ -e_P2041DeviceName P2041_GetRevInfo(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P2041_GetE500Factor - - @Description Obtain core's multiplication factors. - - @Param[in] gutilBase - Gutil memory map virtual base address. - @Param[in] coreIndex - Core index. - @Param[out] p_E500MulFactor - E500 to CCB multification factor. - @Param[out] p_E500DivFactor - E500 to CCB division factor. - -*//***************************************************************************/ -void P2041_GetE500Factor(uintptr_t gutilBase, - uint8_t coreIndex, - uint32_t *p_E500MulFactor, - uint32_t *p_E500DivFactor); - -/**************************************************************************//** - @Function P2041_GetCcbFactor - - @Description Obtain system multiplication factor. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return System multiplication factor. -*//***************************************************************************/ -uint32_t P2041_GetCcbFactor(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P2041_GetDdrFactor - - @Description Obtain DDR clock multiplication factor. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return DDR clock multiplication factor. -*//***************************************************************************/ -uint32_t P2041_GetDdrFactor(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P2041_GetDdrType - - @Description Obtain DDR memory type. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return DDR type. -*//***************************************************************************/ -e_DdrType P2041_GetDdrType(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P2041_GetFmFactor - - @Description returns FM multiplication factors. (This value is returned using - two parameters to avoid using float parameter). - - @Param[in] gutilBase - Gutil memory map virtual base address. - @Param[out] p_FmMulFactor - FM to CCB multification factor. - @Param[out] p_FmDivFactor - FM to CCB division factor. - -*//***************************************************************************/ -void P2041_GetFmFactor(uintptr_t gutilBase, - uint32_t *p_FmMulFactor, - uint32_t *p_FmDivFactor); - - -void P2041_CoreTimeBaseEnable(uintptr_t rcpmBase); -void P2041_CoreTimeBaseDisable(uintptr_t rcpmBase); - -typedef enum e_SerdesProtocol -{ - SRDS_PROTOCOL_NONE = 0, - SRDS_PROTOCOL_PCIE1, - SRDS_PROTOCOL_PCIE2, - SRDS_PROTOCOL_PCIE3, - SRDS_PROTOCOL_SRIO1, - SRDS_PROTOCOL_SRIO2, - SRDS_PROTOCOL_SGMII_FM, - SRDS_PROTOCOL_XAUI_FM, - SRDS_PROTOCOL_SATA1, - SRDS_PROTOCOL_SATA2, - SRDS_PROTOCOL_AURORA -} e_SerdesProtocol; - -t_Error P2041_DeviceDisable(uintptr_t gutilBase, e_P2041DeviceDisable device, bool disable); -void P2041_GetDevicesConfiguration(uintptr_t gutilBase, t_P2041Devices *p_Devices); -t_Error P2041_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable); -void P2041_SetDmaLiodn(uintptr_t gutilBase, uint8_t dmaId, uint16_t liodn); -uint32_t P2041_SerdesRcwGetProtocol(uintptr_t gutilBase); -bool P2041_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device); -bool P2041_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane); - -/** @} */ /* end of P2041_init_grp group */ -/** @} */ /* end of P2041_grp group */ - - -/***************************************************************************** - INTEGRATION-SPECIFIC MODULE CODES -******************************************************************************/ -#define MODULE_UNKNOWN 0x00000000 -#define MODULE_MEM 0x00010000 -#define MODULE_MM 0x00020000 -#define MODULE_CORE 0x00030000 -#define MODULE_P2041 0x00040000 -#define MODULE_P2041_PLATFORM 0x00050000 -#define MODULE_PM 0x00060000 -#define MODULE_MMU 0x00070000 -#define MODULE_PIC 0x00080000 -#define MODULE_CPC 0x00090000 -#define MODULE_DUART 0x000a0000 -#define MODULE_SERDES 0x000b0000 -#define MODULE_PIO 0x000c0000 -#define MODULE_QM 0x000d0000 -#define MODULE_BM 0x000e0000 -#define MODULE_SEC 0x000f0000 -#define MODULE_LAW 0x00100000 -#define MODULE_LBC 0x00110000 -#define MODULE_PAMU 0x00120000 -#define MODULE_FM 0x00130000 -#define MODULE_FM_MURAM 0x00140000 -#define MODULE_FM_PCD 0x00150000 -#define MODULE_FM_RTC 0x00160000 -#define MODULE_FM_MAC 0x00170000 -#define MODULE_FM_PORT 0x00180000 -#define MODULE_DPA_PORT 0x00190000 -#define MODULE_MII 0x001a0000 -#define MODULE_I2C 0x001b0000 -#define MODULE_DMA 0x001c0000 -#define MODULE_DDR 0x001d0000 -#define MODULE_ESPI 0x001e0000 - -/***************************************************************************** - PAMU INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define PAMU_NUM_OF_PARTITIONS 4 - - -/***************************************************************************** - LAW INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define LAW_NUM_OF_WINDOWS 32 -#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */ -#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */ - - -/***************************************************************************** - LBC INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -/**************************************************************************//** - @Group lbc_exception_grp LBC Exception Unit - - @Description LBC Exception unit API functions, definitions and enums - - @{ -*//***************************************************************************/ - -/**************************************************************************//** - @Anchor lbc_exbm - - @Collection LBC Errors Bit Mask - - These errors are reported through the exceptions callback.. - The values can be or'ed in any combination in the errors mask - parameter of the errors report structure. - - These errors can also be passed as a bit-mask to - LBC_EnableErrorChecking() or LBC_DisableErrorChecking(), - for enabling or disabling error checking. - @{ -*//***************************************************************************/ -#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */ -#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */ -#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */ -#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */ - -#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \ - LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT) - /**< All possible errors */ -/* @} */ -/** @} */ /* end of lbc_exception_grp group */ - -#define LBC_INCORRECT_ERROR_REPORT_ERRATA - -#define LBC_NUM_OF_BANKS 4 -#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */ -#define LBC_PARITY_SUPPORT -#define LBC_ADDRESS_HOLD_TIME_CTRL -#define LBC_HIGH_CLK_DIVIDERS -#define LBC_FCM_AVAILABLE - -/***************************************************************************** - GPIO INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module; - Each port contains up to 32 I/O pins. */ - -#define GPIO_VALID_PIN_MASKS \ - { /* Port A */ 0xFFFFFFFF } - -#define GPIO_VALID_INTR_MASKS \ - { /* Port A */ 0xFFFFFFFF } - - -/***************************************************************************** - SERDES INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define SRDS_MAX_LANES 10 /* Lanes C - H on bank 1, lanes A - D on bank 2 */ -#define SRDS_MAX_BANK 2 - -/* Serdes lanes general information provided in the following form: - 1) Lane index in Serdes Control Registers Map - 2) Lane enable/disable bit number in RCW - 3) Lane bank index */ -#define SRDS_LANES \ -{ \ - { 2, 154, 0 }, \ - { 3, 155, 0 }, \ - { 4, 156, 0 }, \ - { 5, 157, 0 }, \ - { 6, 158, 0 }, \ - { 7, 159, 0 }, \ - { 16, 162, 1 }, \ - { 17, 163, 1 }, \ - { 18, 164, 1 }, \ - { 19, 165, 1 } \ -} - -#define SRDS_PROTOCOL_OPTIONS \ -/* Protocol Lane assignment */ \ -{ \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x05 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x08 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x09 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x0A */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x0F */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x14 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x17 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x19 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x1A */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ -/* 0x1C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_SGMII_FM, 0, 0} \ -} - - -/***************************************************************************** - DDR INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define DDR_NUM_OF_VALID_CS 4 - -/***************************************************************************** - DMA INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define DMA_NUM_OF_CONTROLLERS 2 - -/***************************************************************************** - CPC INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ - -#define CPC_MAX_SIZE_SRAM_ERRATA_CPC4 -#define CPC_HARDWARE_FLUSH_ERRATA_CPC10 - - -#endif /* __PART_INTEGRATION_EXT_H */ diff --git a/sys/contrib/ncsw/inc/integrations/P3041/dpaa_integration_ext.h b/sys/contrib/ncsw/inc/integrations/P3041/dpaa_integration_ext.h deleted file mode 100644 index caa4344..0000000 --- a/sys/contrib/ncsw/inc/integrations/P3041/dpaa_integration_ext.h +++ /dev/null @@ -1,371 +0,0 @@ -/****************************************************************************** - - © 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. - All rights reserved. - - This is proprietary source code of Freescale Semiconductor Inc., - and its use is subject to the NetComm Device Drivers EULA. - The copyright notice above does not evidence any actual or intended - publication of such source code. - - ALTERNATIVELY, redistribution and use in source and binary forms, with - or without modification, are permitted provided that the following - conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Freescale Semiconductor nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - **************************************************************************/ -/** - - @File dpaa_integration_ext.h - - @Description P3041 FM external definitions and structures. -*//***************************************************************************/ -#ifndef __DPAA_INTEGRATION_EXT_H -#define __DPAA_INTEGRATION_EXT_H - -#include "std_ext.h" - - -/**************************************************************************//** - @Description DPAA SW Portals Enumeration. -*//***************************************************************************/ -typedef enum -{ - e_DPAA_SWPORTAL0 = 0, - e_DPAA_SWPORTAL1, - e_DPAA_SWPORTAL2, - e_DPAA_SWPORTAL3, - e_DPAA_SWPORTAL4, - e_DPAA_SWPORTAL5, - e_DPAA_SWPORTAL6, - e_DPAA_SWPORTAL7, - e_DPAA_SWPORTAL8, - e_DPAA_SWPORTAL9, - e_DPAA_SWPORTAL_DUMMY_LAST -} e_DpaaSwPortal; - -/**************************************************************************//** - @Description DPAA Direct Connect Portals Enumeration. -*//***************************************************************************/ -typedef enum -{ - e_DPAA_DCPORTAL0 = 0, - e_DPAA_DCPORTAL1, - e_DPAA_DCPORTAL2, - e_DPAA_DCPORTAL3, - e_DPAA_DCPORTAL4, - e_DPAA_DCPORTAL_DUMMY_LAST -} e_DpaaDcPortal; - -#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST -#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST - -/***************************************************************************** - QMan INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */ -#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */ -#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */ -#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE) - /**< FQIDs range - 24 bits */ - -/**************************************************************************//** - @Description Work Queue Channel assignments in QMan. -*//***************************************************************************/ -typedef enum -{ - e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */ - e_QM_FQ_CHANNEL_SWPORTAL1, - e_QM_FQ_CHANNEL_SWPORTAL2, - e_QM_FQ_CHANNEL_SWPORTAL3, - e_QM_FQ_CHANNEL_SWPORTAL4, - e_QM_FQ_CHANNEL_SWPORTAL5, - e_QM_FQ_CHANNEL_SWPORTAL6, - e_QM_FQ_CHANNEL_SWPORTAL7, - e_QM_FQ_CHANNEL_SWPORTAL8, - e_QM_FQ_CHANNEL_SWPORTAL9, - - e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */ - e_QM_FQ_CHANNEL_POOL2, - e_QM_FQ_CHANNEL_POOL3, - e_QM_FQ_CHANNEL_POOL4, - e_QM_FQ_CHANNEL_POOL5, - e_QM_FQ_CHANNEL_POOL6, - e_QM_FQ_CHANNEL_POOL7, - e_QM_FQ_CHANNEL_POOL8, - e_QM_FQ_CHANNEL_POOL9, - e_QM_FQ_CHANNEL_POOL10, - e_QM_FQ_CHANNEL_POOL11, - e_QM_FQ_CHANNEL_POOL12, - e_QM_FQ_CHANNEL_POOL13, - e_QM_FQ_CHANNEL_POOL14, - e_QM_FQ_CHANNEL_POOL15, - - e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0: - connected to FMan 0; assigned in incrementing order to - each sub-portal (SP) in the portal */ - e_QM_FQ_CHANNEL_FMAN0_SP1, - e_QM_FQ_CHANNEL_FMAN0_SP2, - e_QM_FQ_CHANNEL_FMAN0_SP3, - e_QM_FQ_CHANNEL_FMAN0_SP4, - e_QM_FQ_CHANNEL_FMAN0_SP5, - e_QM_FQ_CHANNEL_FMAN0_SP6, - e_QM_FQ_CHANNEL_FMAN0_SP7, - e_QM_FQ_CHANNEL_FMAN0_SP8, - e_QM_FQ_CHANNEL_FMAN0_SP9, - e_QM_FQ_CHANNEL_FMAN0_SP10, - e_QM_FQ_CHANNEL_FMAN0_SP11, - - e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */ - e_QM_FQ_CHANNEL_RMAN_SP3, - - e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2: - connected to SEC 4.x */ - - e_QM_FQ_CHANNEL_PME = 0xA0 /**< Dedicated channel serviced by Direct Connect Portal 3: - connected to PME */ -} e_QmFQChannel; - -/***************************************************************************** - BMan INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */ - -/***************************************************************************** - FM INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define INTG_MAX_NUM_OF_FM 1 - -/* Ports defines */ -#define FM_MAX_NUM_OF_1G_MACS 5 -#define FM_MAX_NUM_OF_10G_MACS 1 -#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) -#define FM_MAX_NUM_OF_OH_PORTS 7 - -#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS -#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS -#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) - -#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS -#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS -#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) - -#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */ -#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */ -#define FM_MAX_NUM_OF_SUB_PORTALS 12 -#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0 - -/* RAMs defines */ -#define FM_MURAM_SIZE (160 * KILOBYTE) -#define FM_IRAM_SIZE ( 64 * KILOBYTE) - -/* PCD defines */ -#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */ -#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */ -#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */ - -/* RTC defines */ -#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */ -#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */ -#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */ - -/* QMI defines */ -#define QMI_MAX_NUM_OF_TNUMS 64 -#define MAX_QMI_DEQ_SUBPORTAL 12 -#define QMI_DEF_TNUMS_THRESH 48 - -/* FPM defines */ -#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 - -/* DMA defines */ -#define DMA_THRESH_MAX_COMMQ 31 -#define DMA_THRESH_MAX_BUF 127 - -/* BMI defines */ -#define BMI_MAX_NUM_OF_TASKS 128 -#define BMI_MAX_NUM_OF_DMAS 32 -#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -#define PORT_MAX_WEIGHT 16 - - -/**************************************************************************//** - @Description Enum for inter-module interrupts registration -*//***************************************************************************/ -typedef enum e_FmEventModules -{ - e_FM_MOD_PRS, /**< Parser event */ - e_FM_MOD_KG, /**< Keygen event */ - e_FM_MOD_PLCR, /**< Policer event */ - e_FM_MOD_10G_MAC, /**< 10G MAC error event */ - e_FM_MOD_1G_MAC, /**< 1G MAC error event */ - e_FM_MOD_TMR, /**< Timer event */ - e_FM_MOD_1G_MAC_TMR, /**< 1G MAC timer event */ - e_FM_MOD_FMAN_CTRL, /**< FMAN Controller timer event */ - e_FM_MOD_DUMMY_LAST -} e_FmEventModules; - -/**************************************************************************//** - @Description Enum for interrupts types -*//***************************************************************************/ -typedef enum e_FmIntrType -{ - e_FM_INTR_TYPE_ERR, - e_FM_INTR_TYPE_NORMAL -} e_FmIntrType; - -/**************************************************************************//** - @Description Enum for inter-module interrupts registration -*//***************************************************************************/ -typedef enum e_FmInterModuleEvent -{ - e_FM_EV_PRS, /**< Parser event */ - e_FM_EV_ERR_PRS, /**< Parser error event */ - e_FM_EV_KG, /**< Keygen event */ - e_FM_EV_ERR_KG, /**< Keygen error event */ - e_FM_EV_PLCR, /**< Policer event */ - e_FM_EV_ERR_PLCR, /**< Policer error event */ - e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */ - e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */ - e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */ - e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */ - e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */ - e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */ - e_FM_EV_TMR, /**< Timer event */ - e_FM_EV_1G_MAC0_TMR, /**< 1G MAC 0 timer event */ - e_FM_EV_1G_MAC1_TMR, /**< 1G MAC 1 timer event */ - e_FM_EV_1G_MAC2_TMR, /**< 1G MAC 2 timer event */ - e_FM_EV_1G_MAC3_TMR, /**< 1G MAC 3 timer event */ - e_FM_EV_1G_MAC4_TMR, /**< 1G MAC 4 timer event */ - e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */ - e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */ - e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */ - e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */ - e_FM_EV_DUMMY_LAST -} e_FmInterModuleEvent; - -#define GET_FM_MODULE_EVENT(mod, id, intrType, event) \ - switch(mod){ \ - case e_FM_MOD_PRS: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \ - break; \ - case e_FM_MOD_KG: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \ - break; \ - case e_FM_MOD_PLCR: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \ - break; \ - case e_FM_MOD_10G_MAC: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_10G_MAC0 : e_FM_EV_DUMMY_LAST; \ - break; \ - case e_FM_MOD_1G_MAC: \ - switch(id){ \ - case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC0 : e_FM_EV_DUMMY_LAST; break; \ - case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC1 : e_FM_EV_DUMMY_LAST; break; \ - case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC2 : e_FM_EV_DUMMY_LAST; break; \ - case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC3 : e_FM_EV_DUMMY_LAST; break; \ - case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC4 : e_FM_EV_DUMMY_LAST; break; \ - } \ - break; \ - case e_FM_MOD_TMR: \ - if (id) event = e_FM_EV_DUMMY_LAST; \ - else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \ - break; \ - case e_FM_MOD_1G_MAC_TMR: \ - switch(id){ \ - case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC0_TMR; break; \ - case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC1_TMR; break; \ - case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC2_TMR; break; \ - case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC3_TMR; break; \ - case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC4_TMR; break; \ - } \ - break; \ - case e_FM_MOD_FMAN_CTRL: \ - if (intrType == e_FM_INTR_TYPE_ERR) event = e_FM_EV_DUMMY_LAST; \ - else switch(id){ \ - case(0): event = e_FM_EV_FMAN_CTRL_0; break; \ - case(1): event = e_FM_EV_FMAN_CTRL_1; break; \ - case(2): event = e_FM_EV_FMAN_CTRL_2; break; \ - case(3): event = e_FM_EV_FMAN_CTRL_3; break; \ - } \ - break; \ - default: event = e_FM_EV_DUMMY_LAST; \ - break;} - -#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE - -/* P3041 unique features */ -#define FM_QMI_DEQ_OPTIONS_SUPPORT -#define FM_NO_DISPATCH_RAM_ECC -#define FM_FIFO_ALLOCATION_OLD_ALG -#define FM_NO_WATCHDOG -#define FM_NO_TNUM_AGING -#define FM_NO_TGEC_LOOPBACK -#define FM_KG_NO_BYPASS_FQID_GEN -#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN -#define FM_NO_BACKUP_POOLS -#define FM_NO_OP_OBSERVED_POOLS -#define FM_NO_ADVANCED_RATE_LIMITER -#define FM_NO_OP_OBSERVED_CGS - -/* FM erratas */ -#define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -#define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */ -#define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 -#define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008 - -#define FM_NO_RX_PREAM_ERRATA_DTSECx1 -#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1 -#define FM_GRS_ERRATA_DTSEC_A002 -#define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 -#define FM_GTS_ERRATA_DTSEC_A004 -#define FM_PAUSE_BLOCK_ERRATA_DTSEC_A006 /* do nothing */ -#define FM_RESERVED_ACCESS_TO_DISABLED_DEV_ERRATA_DTSEC_A0011 /* do nothing */ -#define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 FM_GTS_ERRATA_DTSEC_A004 -#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */ -#define FM_10_100_SGMII_NO_TS_ERRATA_DTSEC3 -#define FM_TX_LOCKUP_ERRATA_DTSEC6 - -#define FM_IM_TX_SYNC_SKIP_TNUM_ERRATA_FMAN_A001 /* Implemented by ucode */ -#define FM_HC_DEF_FQID_ONLY_ERRATA_FMAN_A003 /* Implemented by ucode */ -#define FM_IM_TX_SHARED_TNUM_ERRATA_FMAN4 /* Implemented by ucode */ -#define FM_IM_GS_DEADLOCK_ERRATA_FMAN5 /* Implemented by ucode */ -#define FM_IM_DEQ_PIPELINE_DEPTH_ERRATA_FMAN10 /* Implemented by ucode */ -#define FM_CC_GEN6_MISSMATCH_ERRATA_FMAN12 /* Implemented by ucode */ -#define FM_CC_CHANGE_SHARED_TNUM_ERRATA_FMAN13 /* Implemented by ucode */ -#define FM_IM_LARGE_MRBLR_ERRATA_FMAN15 /* Implemented by ucode */ -#define FM_BMI_TO_RISC_ENQ_ERRATA_FMANc /* No implementation, Out of LLD scope */ -#define FM_INVALID_SWPRS_DATA_ERRATA_FMANd -/* #define FM_PRS_MPLS_SSA_ERRATA_FMANj */ /* No implementation, No patch yet */ -/* #define FM_PRS_INITIAL_PLANID_ERRATA_FMANk */ /* No implementation, No patch yet */ - -#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 - -#define FM_NO_COPY_CTXA_CTXB_ERRATA_FMAN_SW001 -#define FM_PRS_MEM_ERRATA_FMAN_SW003 -#define FM_LEN_CHECK_ERRATA_FMAN_SW002 -#define FM_10G_REM_N_LCL_FLT_EX_ERRATA_10GMAC001 - - -#endif /* __DPAA_INTEGRATION_EXT_H */ diff --git a/sys/contrib/ncsw/inc/integrations/P3041/part_integration_ext.h b/sys/contrib/ncsw/inc/integrations/P3041/part_integration_ext.h deleted file mode 100644 index 0eb5746..0000000 --- a/sys/contrib/ncsw/inc/integrations/P3041/part_integration_ext.h +++ /dev/null @@ -1,995 +0,0 @@ -/****************************************************************************** - - © 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. - All rights reserved. - - This is proprietary source code of Freescale Semiconductor Inc., - and its use is subject to the NetComm Device Drivers EULA. - The copyright notice above does not evidence any actual or intended - publication of such source code. - - ALTERNATIVELY, redistribution and use in source and binary forms, with - or without modification, are permitted provided that the following - conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Freescale Semiconductor nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - **************************************************************************/ -/** - - @File part_integration_ext.h - - @Description P3041 external definitions and structures. -*//***************************************************************************/ -#ifndef __PART_INTEGRATION_EXT_H -#define __PART_INTEGRATION_EXT_H - -#include "std_ext.h" -#include "ddr_std_ext.h" -#include "enet_ext.h" -#include "dpaa_integration_ext.h" - - -/**************************************************************************//** - @Group P3041_chip_id P3041 Application Programming Interface - - @Description P3041 Chip functions,definitions and enums. - - @{ -*//***************************************************************************/ - -#define CORE_E500MC - -#define INTG_MAX_NUM_OF_CORES 4 - - -/**************************************************************************//** - @Description Module types. -*//***************************************************************************/ -typedef enum e_ModuleId -{ - e_MODULE_ID_DUART_1 = 0, - e_MODULE_ID_DUART_2, - e_MODULE_ID_DUART_3, - e_MODULE_ID_DUART_4, - e_MODULE_ID_LAW, - e_MODULE_ID_LBC, - e_MODULE_ID_PAMU, - e_MODULE_ID_QM, /**< Queue manager module */ - e_MODULE_ID_BM, /**< Buffer manager module */ - e_MODULE_ID_QM_CE_PORTAL_0, - e_MODULE_ID_QM_CI_PORTAL_0, - e_MODULE_ID_QM_CE_PORTAL_1, - e_MODULE_ID_QM_CI_PORTAL_1, - e_MODULE_ID_QM_CE_PORTAL_2, - e_MODULE_ID_QM_CI_PORTAL_2, - e_MODULE_ID_QM_CE_PORTAL_3, - e_MODULE_ID_QM_CI_PORTAL_3, - e_MODULE_ID_QM_CE_PORTAL_4, - e_MODULE_ID_QM_CI_PORTAL_4, - e_MODULE_ID_QM_CE_PORTAL_5, - e_MODULE_ID_QM_CI_PORTAL_5, - e_MODULE_ID_QM_CE_PORTAL_6, - e_MODULE_ID_QM_CI_PORTAL_6, - e_MODULE_ID_QM_CE_PORTAL_7, - e_MODULE_ID_QM_CI_PORTAL_7, - e_MODULE_ID_QM_CE_PORTAL_8, - e_MODULE_ID_QM_CI_PORTAL_8, - e_MODULE_ID_QM_CE_PORTAL_9, - e_MODULE_ID_QM_CI_PORTAL_9, - e_MODULE_ID_BM_CE_PORTAL_0, - e_MODULE_ID_BM_CI_PORTAL_0, - e_MODULE_ID_BM_CE_PORTAL_1, - e_MODULE_ID_BM_CI_PORTAL_1, - e_MODULE_ID_BM_CE_PORTAL_2, - e_MODULE_ID_BM_CI_PORTAL_2, - e_MODULE_ID_BM_CE_PORTAL_3, - e_MODULE_ID_BM_CI_PORTAL_3, - e_MODULE_ID_BM_CE_PORTAL_4, - e_MODULE_ID_BM_CI_PORTAL_4, - e_MODULE_ID_BM_CE_PORTAL_5, - e_MODULE_ID_BM_CI_PORTAL_5, - e_MODULE_ID_BM_CE_PORTAL_6, - e_MODULE_ID_BM_CI_PORTAL_6, - e_MODULE_ID_BM_CE_PORTAL_7, - e_MODULE_ID_BM_CI_PORTAL_7, - e_MODULE_ID_BM_CE_PORTAL_8, - e_MODULE_ID_BM_CI_PORTAL_8, - e_MODULE_ID_BM_CE_PORTAL_9, - e_MODULE_ID_BM_CI_PORTAL_9, - e_MODULE_ID_FM, /**< Frame manager module */ - e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */ - e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */ - e_MODULE_ID_FM_BMI, /**< FM BMI block */ - e_MODULE_ID_FM_QMI, /**< FM QMI block */ - e_MODULE_ID_FM_PARSER, /**< FM parser block */ - e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */ - e_MODULE_ID_FM_PLCR, /**< FM Policer */ - e_MODULE_ID_FM_KG, /**< FM Keygen */ - e_MODULE_ID_FM_DMA, /**< FM DMA */ - e_MODULE_ID_FM_FPM, /**< FM FPM */ - e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */ - e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/ - e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/ - e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/ - e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/ - e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/ - e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */ - e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ - e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */ - e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */ - e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */ - e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */ - e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */ - e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */ - - e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ - e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ - e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ - e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ - e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ - e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ - e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ - e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ - e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ - e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ - e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ - e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ - - e_MODULE_ID_PIC, /**< PIC */ - e_MODULE_ID_GPIO, /**< GPIO */ - e_MODULE_ID_SERDES, /**< SERDES */ - e_MODULE_ID_CPC, /**< CoreNet-Platform-Cache */ - e_MODULE_ID_DUMMY_LAST -} e_ModuleId; - -#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST - -/* Offsets relative to CCSR base */ -#define P3041_OFFSET_LAW 0x00000c00 -#define P3041_OFFSET_DDR 0x00008000 -#define P3041_OFFSET_CPC 0x00010000 -#define P3041_OFFSET_CCM 0x00018000 -#define P3041_OFFSET_PAMU 0x00020000 -#define P3041_OFFSET_PIC 0x00040000 -#define P3041_OFFSET_GUTIL 0x000e0000 -#define P3041_OFFSET_RCPM 0x000e2000 -#define P3041_OFFSET_SERDES 0x000ea000 -#define P3041_OFFSET_DMA1 0x00100100 -#define P3041_OFFSET_DMA2 0x00101100 -#define P3041_OFFSET_ESPI 0x00110000 -#define P3041_OFFSET_ESDHC 0x00114000 -#define P3041_OFFSET_I2C1 0x00118000 -#define P3041_OFFSET_I2C2 0x00118100 -#define P3041_OFFSET_I2C3 0x00119000 -#define P3041_OFFSET_I2C4 0x00119100 -#define P3041_OFFSET_DUART1 0x0011c500 -#define P3041_OFFSET_DUART2 0x0011c600 -#define P3041_OFFSET_DUART3 0x0011d500 -#define P3041_OFFSET_DUART4 0x0011d600 -#define P3041_OFFSET_LBC 0x00124000 -#define P3041_OFFSET_GPIO 0x00130000 -#define P3041_OFFSET_PCIE1 0x00200000 -#define P3041_OFFSET_PCIE2 0x00201000 -#define P3041_OFFSET_PCIE3 0x00202000 -#define P3041_OFFSET_PCIE4 0x00203000 -#define P3041_OFFSET_USB1 0x00210000 -#define P3041_OFFSET_USB2 0x00211000 -#define P3041_OFFSET_USB_PHY 0x00214000 -#define P3041_OFFSET_SATA1 0x00220000 -#define P3041_OFFSET_SATA2 0x00221000 -#define P3041_OFFSET_SEC_GEN 0x00300000 -#define P3041_OFFSET_SEC_JQ0 0x00301000 -#define P3041_OFFSET_SEC_JQ1 0x00302000 -#define P3041_OFFSET_SEC_JQ2 0x00303000 -#define P3041_OFFSET_SEC_JQ3 0x00304000 -#define P3041_OFFSET_SEC_RESERVED 0x00305000 -#define P3041_OFFSET_SEC_RTIC 0x00306000 -#define P3041_OFFSET_SEC_QI 0x00307000 -#define P3041_OFFSET_SEC_DECO0_CCB0 0x00308000 -#define P3041_OFFSET_SEC_DECO1_CCB1 0x00309000 -#define P3041_OFFSET_PME 0x00316000 -#define P3041_OFFSET_QM 0x00318000 -#define P3041_OFFSET_BM 0x0031a000 -#define P3041_OFFSET_FM 0x00400000 - -#define P3041_OFFSET_FM_MURAM P3041_OFFSET_FM -#define P3041_OFFSET_FM_BMI (P3041_OFFSET_FM + 0x00080000) -#define P3041_OFFSET_FM_QMI (P3041_OFFSET_FM + 0x00080400) -#define P3041_OFFSET_FM_PARSER (P3041_OFFSET_FM + 0x00080800) -#define P3041_OFFSET_FM_PORT_HO1 (P3041_OFFSET_FM + 0x00081000) /* host command/offline parser */ -#define P3041_OFFSET_FM_PORT_HO2 (P3041_OFFSET_FM + 0x00082000) -#define P3041_OFFSET_FM_PORT_HO3 (P3041_OFFSET_FM + 0x00083000) -#define P3041_OFFSET_FM_PORT_HO4 (P3041_OFFSET_FM + 0x00084000) -#define P3041_OFFSET_FM_PORT_HO5 (P3041_OFFSET_FM + 0x00085000) -#define P3041_OFFSET_FM_PORT_HO6 (P3041_OFFSET_FM + 0x00086000) -#define P3041_OFFSET_FM_PORT_HO7 (P3041_OFFSET_FM + 0x00087000) -#define P3041_OFFSET_FM_PORT_1GRX1 (P3041_OFFSET_FM + 0x00088000) -#define P3041_OFFSET_FM_PORT_1GRX2 (P3041_OFFSET_FM + 0x00089000) -#define P3041_OFFSET_FM_PORT_1GRX3 (P3041_OFFSET_FM + 0x0008a000) -#define P3041_OFFSET_FM_PORT_1GRX4 (P3041_OFFSET_FM + 0x0008b000) -#define P3041_OFFSET_FM_PORT_1GRX5 (P3041_OFFSET_FM + 0x0008c000) -#define P3041_OFFSET_FM_PORT_10GRX (P3041_OFFSET_FM + 0x00090000) -#define P3041_OFFSET_FM_PORT_1GTX1 (P3041_OFFSET_FM + 0x000a8000) -#define P3041_OFFSET_FM_PORT_1GTX2 (P3041_OFFSET_FM + 0x000a9000) -#define P3041_OFFSET_FM_PORT_1GTX3 (P3041_OFFSET_FM + 0x000aa000) -#define P3041_OFFSET_FM_PORT_1GTX4 (P3041_OFFSET_FM + 0x000ab000) -#define P3041_OFFSET_FM_PORT_1GTX5 (P3041_OFFSET_FM + 0x000ac000) -#define P3041_OFFSET_FM_PORT_10GTX (P3041_OFFSET_FM + 0x000b0000) -#define P3041_OFFSET_FM_PLCR (P3041_OFFSET_FM + 0x000c0000) -#define P3041_OFFSET_FM_KG (P3041_OFFSET_FM + 0x000c1000) -#define P3041_OFFSET_FM_DMA (P3041_OFFSET_FM + 0x000c2000) -#define P3041_OFFSET_FM_FPM (P3041_OFFSET_FM + 0x000c3000) -#define P3041_OFFSET_FM_IRAM (P3041_OFFSET_FM + 0x000c4000) -#define P3041_OFFSET_FM_PARSER_IRAM (P3041_OFFSET_FM + 0x000c7000) -#define P3041_OFFSET_FM_1GMAC1 (P3041_OFFSET_FM + 0x000e0000) -#define P3041_OFFSET_FM_1GMDIO (P3041_OFFSET_FM + 0x000e1000 + 0x120) -#define P3041_OFFSET_FM_1GMAC2 (P3041_OFFSET_FM + 0x000e2000) -#define P3041_OFFSET_FM_1GMAC3 (P3041_OFFSET_FM + 0x000e4000) -#define P3041_OFFSET_FM_1GMAC4 (P3041_OFFSET_FM + 0x000e6000) -#define P3041_OFFSET_FM_1GMAC5 (P3041_OFFSET_FM + 0x000e8000) -#define P3041_OFFSET_FM_10GMAC (P3041_OFFSET_FM + 0x000f0000) -#define P3041_OFFSET_FM_10GMDIO (P3041_OFFSET_FM + 0x000f1000 + 0x030) -#define P3041_OFFSET_FM_RTC (P3041_OFFSET_FM + 0x000fe000) - -/* Offsets relative to QM or BM portals base */ -#define P3041_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */ -#define P3041_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */ - -#define P3041_CE_PORTAL_SIZE 0x4000 -#define P3041_CI_PORTAL_SIZE 0x1000 - -#define P3041_OFFSET_PORTALS_CE(portal) \ - (P3041_OFFSET_PORTALS_CE_AREA + P3041_CE_PORTAL_SIZE * (portal)) -#define P3041_OFFSET_PORTALS_CI(portal) \ - (P3041_OFFSET_PORTALS_CI_AREA + P3041_CI_PORTAL_SIZE * (portal)) - - -/**************************************************************************//** - @Description Transaction source ID (for memory controllers error reporting). -*//***************************************************************************/ -typedef enum e_TransSrc -{ - e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */ - e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */ - e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */ - e_TRANS_SRC_PCIE_4 = 0x3, /**< PCI Express 4 */ - e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */ - e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */ - e_TRANS_SRC_BMAN = 0x18, /**< BMan */ - e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */ - e_TRANS_SRC_PME = 0x20, /**< PME */ - e_TRANS_SRC_SEC = 0x21, /**< Security engine */ - e_TRANS_SRC_QMAN = 0x3C, /**< QMan */ - e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */ - e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */ - e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */ - e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */ - e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */ - e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */ - e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */ - e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */ - e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */ - e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */ - e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */ - e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */ - e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */ - e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */ - e_TRANS_SRC_CORE_2_INST = 0x84, /**< Processor 2 (instruction) */ - e_TRANS_SRC_CORE_2_DATA = 0x85, /**< Processor 2 (data) */ - e_TRANS_SRC_CORE_3_INST = 0x86, /**< Processor 3 (instruction) */ - e_TRANS_SRC_CORE_3_DATA = 0x87, /**< Processor 3 (data) */ - e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */ - e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */ - e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */ - e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */ - e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */ - e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */ - e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */ - e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */ - e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */ - e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */ - e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */ - e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */ - e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */ -} e_TransSrc; - -/**************************************************************************//** - @Description Local Access Window Target interface ID -*//***************************************************************************/ -typedef enum e_P3041LawTargetId -{ - e_P3041_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */ - e_P3041_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */ - e_P3041_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */ - e_P3041_LAW_TARGET_PCIE_4 = 0x3, /**< PCI Express 4 */ - e_P3041_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */ - e_P3041_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */ - e_P3041_LAW_TARGET_DDR_CPC = 0x10, /**< DDR controller or CPC SRAM */ - e_P3041_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */ - e_P3041_LAW_TARGET_DCSR = 0x1D, /**< DCSR */ - e_P3041_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */ - e_P3041_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */ - e_P3041_LAW_TARGET_NONE = 0xFF /**< None */ -} e_P3041LawTargetId; - -/*************************************************************** - P3041 general routines -****************************************************************/ -/**************************************************************************//** - @Group P3041_init_grp P3041 Initialization Unit - - @Description P3041 initialization unit API functions, definitions and enums - - @{ -*//***************************************************************************/ - -/**************************************************************************//** - @Description Part ID and revision number -*//***************************************************************************/ -typedef enum e_P3041DeviceName -{ - e_P3041_REV_INVALID = 0x00000000, /**< Invalid revision */ - e_P3041_REV_1_0 = (int)0x82190310, /**< P3041 with security, revision 1.0 */ - e_P3041_REV_1_0_NO_SEC = (int)0x82110310 /**< P3041 without security, revision 1.0 */ -} e_P3041DeviceName; - -/**************************************************************************//** - @Description Device Disable Register -*//***************************************************************************/ -typedef enum e_P3041DeviceDisable -{ - e_P3041_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */ - e_P3041_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */ - e_P3041_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */ - e_P3041_DEV_DISABLE_PCIE_4, /**< PCI Express controller 4 disable */ - e_P3041_DEV_DISABLE_RMAN, /**< RapidIO message manager disable */ - e_P3041_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */ - e_P3041_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */ - e_P3041_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */ - e_P3041_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */ - e_P3041_DEV_DISABLE_DDR, /**< DDR controller disable */ - e_P3041_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */ - e_P3041_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */ - e_P3041_DEV_DISABLE_LBC, /**< eLBC controller disable */ - e_P3041_DEV_DISABLE_USB_1, /**< USB controller 1 disable */ - e_P3041_DEV_DISABLE_USB_2, /**< USB controller 2 disable */ - e_P3041_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */ - e_P3041_DEV_DISABLE_GPIO, /**< GPIO controller disable */ - e_P3041_DEV_DISABLE_ESPI, /**< eSPI controller disable */ - e_P3041_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */ - e_P3041_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */ - e_P3041_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */ - e_P3041_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */ - e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST = 32, - /**< Dummy entry signing end of DEVDISR1 register controllers */ - e_P3041_DEV_DISABLE_PME = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST, - /**< Pattern match engine disable */ - e_P3041_DEV_DISABLE_SEC, /**< Security disable */ - e_P3041_DEV_DISABLE_QM_BM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 4, - /**< Queue manager/buffer manager disable */ - e_P3041_DEV_DISABLE_FM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 6, - /**< Frame manager disable */ - e_P3041_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */ - e_P3041_DEV_DISABLE_DTSEC_1, /**< dTSEC controller 1 disable */ - e_P3041_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */ - e_P3041_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */ - e_P3041_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */ - e_P3041_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */ -} e_P3041DeviceDisable; - - -/**************************************************************************//* - @Description structure representing P3041 devices configuration -*//***************************************************************************/ -typedef struct t_P3041Devices -{ - struct - { - struct - { - bool enabled; - uint8_t serdesBank; - uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank, - one bit for lane, lane A is the first and so on, e.g., - set 0xF000 for ABCD lanes */ - e_EnetInterface ethIf; - uint8_t ratio; - bool divByTwo; - bool isTwoHalfSgmii; - } dtsecs[FM_MAX_NUM_OF_1G_MACS]; - struct - { - bool enabled; - uint8_t serdesBank; - uint16_t serdesLane; - } tgec; - } fm; -} t_P3041Devices; - -/**************************************************************************//** - @Function P3041_GetRevInfo - - @Description Obtain revision information. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return Part ID and revision. -*//***************************************************************************/ -e_P3041DeviceName P3041_GetRevInfo(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P3041_GetE500Factor - - @Description Obtain core's multiplication factors. - - @Param[in] gutilBase - Gutil memory map virtual base address. - @Param[in] coreIndex - Core index. - @Param[out] p_E500MulFactor - E500 to CCB multification factor. - @Param[out] p_E500DivFactor - E500 to CCB division factor. - -*//***************************************************************************/ -void P3041_GetE500Factor(uintptr_t gutilBase, - uint8_t coreIndex, - uint32_t *p_E500MulFactor, - uint32_t *p_E500DivFactor); - -/**************************************************************************//** - @Function P3041_GetCcbFactor - - @Description Obtain system multiplication factor. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return System multiplication factor. -*//***************************************************************************/ -uint32_t P3041_GetCcbFactor(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P3041_GetDdrFactor - - @Description Obtain DDR clock multiplication factor. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return DDR clock multiplication factor. -*//***************************************************************************/ -uint32_t P3041_GetDdrFactor(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P3041_GetDdrType - - @Description Obtain DDR memory type. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return DDR type. -*//***************************************************************************/ -e_DdrType P3041_GetDdrType(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P3041_GetFmFactor - - @Description returns FM multiplication factors. (This value is returned using - two parameters to avoid using float parameter). - - @Param[in] gutilBase - Gutil memory map virtual base address. - @Param[out] p_FmMulFactor - FM to CCB multification factor. - @Param[out] p_FmDivFactor - FM to CCB division factor. - -*//***************************************************************************/ -void P3041_GetFmFactor(uintptr_t gutilBase, - uint32_t *p_FmMulFactor, - uint32_t *p_FmDivFactor); - - -void P3041_CoreTimeBaseEnable(uintptr_t rcpmBase); -void P3041_CoreTimeBaseDisable(uintptr_t rcpmBase); - -typedef enum e_SerdesProtocol -{ - SRDS_PROTOCOL_NONE = 0, - SRDS_PROTOCOL_PCIE1, - SRDS_PROTOCOL_PCIE2, - SRDS_PROTOCOL_PCIE3, - SRDS_PROTOCOL_PCIE4, - SRDS_PROTOCOL_SRIO1, - SRDS_PROTOCOL_SRIO2, - SRDS_PROTOCOL_SGMII_FM, - SRDS_PROTOCOL_XAUI_FM, - SRDS_PROTOCOL_SATA1, - SRDS_PROTOCOL_SATA2, - SRDS_PROTOCOL_AURORA -} e_SerdesProtocol; - -t_Error P3041_DeviceDisable(uintptr_t gutilBase, e_P3041DeviceDisable device, bool disable); -void P3041_GetDevicesConfiguration(uintptr_t gutilBase, t_P3041Devices *p_Devices); -t_Error P3041_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable); -uint32_t P3041_SerdesRcwGetProtocol(uintptr_t gutilBase); -bool P3041_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device); -bool P3041_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane); - -/** @} */ /* end of P3041_init_grp group */ -/** @} */ /* end of P3041_grp group */ - - -/***************************************************************************** - INTEGRATION-SPECIFIC MODULE CODES -******************************************************************************/ -#define MODULE_UNKNOWN 0x00000000 -#define MODULE_MEM 0x00010000 -#define MODULE_MM 0x00020000 -#define MODULE_CORE 0x00030000 -#define MODULE_P3041 0x00040000 -#define MODULE_P3041_PLATFORM 0x00050000 -#define MODULE_PM 0x00060000 -#define MODULE_MMU 0x00070000 -#define MODULE_PIC 0x00080000 -#define MODULE_CPC 0x00090000 -#define MODULE_DUART 0x000a0000 -#define MODULE_SERDES 0x000b0000 -#define MODULE_PIO 0x000c0000 -#define MODULE_QM 0x000d0000 -#define MODULE_BM 0x000e0000 -#define MODULE_SEC 0x000f0000 -#define MODULE_LAW 0x00100000 -#define MODULE_LBC 0x00110000 -#define MODULE_PAMU 0x00120000 -#define MODULE_FM 0x00130000 -#define MODULE_FM_MURAM 0x00140000 -#define MODULE_FM_PCD 0x00150000 -#define MODULE_FM_RTC 0x00160000 -#define MODULE_FM_MAC 0x00170000 -#define MODULE_FM_PORT 0x00180000 -#define MODULE_DPA 0x00190000 -#define MODULE_MII 0x001a0000 -#define MODULE_I2C 0x001b0000 -#define MODULE_DMA 0x001c0000 -#define MODULE_DDR 0x001d0000 -#define MODULE_ESPI 0x001e0000 - -/***************************************************************************** - PAMU INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define PAMU_NUM_OF_PARTITIONS 4 - - -/***************************************************************************** - LAW INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define LAW_NUM_OF_WINDOWS 32 -#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */ -#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */ - - -/***************************************************************************** - LBC INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -/**************************************************************************//** - @Group lbc_exception_grp LBC Exception Unit - - @Description LBC Exception unit API functions, definitions and enums - - @{ -*//***************************************************************************/ - -/**************************************************************************//** - @Anchor lbc_exbm - - @Collection LBC Errors Bit Mask - - These errors are reported through the exceptions callback.. - The values can be or'ed in any combination in the errors mask - parameter of the errors report structure. - - These errors can also be passed as a bit-mask to - LBC_EnableErrorChecking() or LBC_DisableErrorChecking(), - for enabling or disabling error checking. - @{ -*//***************************************************************************/ -#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */ -#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */ -#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */ -#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */ - -#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \ - LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT) - /**< All possible errors */ -/* @} */ -/** @} */ /* end of lbc_exception_grp group */ - -#define LBC_INCORRECT_ERROR_REPORT_ERRATA - -#define LBC_NUM_OF_BANKS 8 -#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */ -#define LBC_PARITY_SUPPORT -#define LBC_HIGH_CLK_DIVIDERS -#define LBC_FCM_AVAILABLE - -/***************************************************************************** - GPIO INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module; - Each port contains up to 32 I/O pins. */ - -#define GPIO_VALID_PIN_MASKS \ - { /* Port A */ 0xFFFFFFFF } - -#define GPIO_VALID_INTR_MASKS \ - { /* Port A */ 0xFFFFFFFF } - - -/***************************************************************************** - SERDES INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define SRDS_MAX_LANES 18 -#define SRDS_MAX_BANK 3 - -/* Serdes lanes general information provided in the following form: - 1) Lane index in Serdes Control Registers Map - 2) Lane enable/disable bit number in RCW - 3) Lane bank index */ -#define SRDS_LANES \ -{ \ - { 0, 152, 0 }, \ - { 1, 153, 0 }, \ - { 2, 154, 0 }, \ - { 3, 155, 0 }, \ - { 4, 156, 0 }, \ - { 5, 157, 0 }, \ - { 6, 158, 0 }, \ - { 7, 159, 0 }, \ - { 8, 160, 0 }, \ - { 9, 161, 0 }, \ - { 16, 162, 1 }, \ - { 17, 163, 1 }, \ - { 18, 164, 1 }, \ - { 19, 165, 1 }, \ - { 20, 166, 2 }, \ - { 21, 167, 2 }, \ - { 22, 168, 2 }, \ - { 23, 169, 2 } \ -} - -#define SRDS_PROTOCOL_ALL_OPTIONS -/* Serdes lanes assignment and multiplexing. - Each option is selected by SRDS_PRTCL bits of RCW. */ -#define SRDS_PROTOCOL_OPTIONS \ -/* Protocol Lane assignment */ \ -{ \ -/* 0x00 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x01 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x03 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x04 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x05 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x06 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x07 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x08 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x09 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x0A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x0B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x0C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x0D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x0E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x0F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x10 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x11 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x12 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x13 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x14 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x15 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1}, \ -/* 0x17 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x18 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x19 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x1A */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x1B */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x1C */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x1D */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x1E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x1F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x20 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x21 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x22 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x23 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x24 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x25 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x26 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x27 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x28 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x29 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x2A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x2B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x2C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x2D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x2E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x2F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x30 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x31 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x32 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x33 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x34 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x35 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x36 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x37 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2} \ -} - -/***************************************************************************** - DDR INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define DDR_NUM_OF_VALID_CS 4 - -/***************************************************************************** - DMA INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define DMA_NUM_OF_CONTROLLERS 2 - -/***************************************************************************** - CPC INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ - -#define CPC_MAX_SIZE_SRAM_ERRATA_CPC4 -#define CPC_HARDWARE_FLUSH_ERRATA_CPC10 - - -#endif /* __PART_INTEGRATION_EXT_H */ diff --git a/sys/contrib/ncsw/inc/integrations/P5020/part_integration_ext.h b/sys/contrib/ncsw/inc/integrations/P5020/part_integration_ext.h deleted file mode 100644 index 5c0f3bb..0000000 --- a/sys/contrib/ncsw/inc/integrations/P5020/part_integration_ext.h +++ /dev/null @@ -1,1004 +0,0 @@ -/****************************************************************************** - - © 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. - All rights reserved. - - This is proprietary source code of Freescale Semiconductor Inc., - and its use is subject to the NetComm Device Drivers EULA. - The copyright notice above does not evidence any actual or intended - publication of such source code. - - ALTERNATIVELY, redistribution and use in source and binary forms, with - or without modification, are permitted provided that the following - conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Freescale Semiconductor nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - **************************************************************************/ -/** - - @File part_integration_ext.h - - @Description P5020 external definitions and structures. -*//***************************************************************************/ -#ifndef __PART_INTEGRATION_EXT_H -#define __PART_INTEGRATION_EXT_H - -#include "std_ext.h" -#include "ddr_std_ext.h" -#include "enet_ext.h" -#include "dpaa_integration_ext.h" - - -/**************************************************************************//** - @Group P5020_chip_id P5020 Application Programming Interface - - @Description P5020 Chip functions,definitions and enums. - - @{ -*//***************************************************************************/ - -#define CORE_E500MC - -#define INTG_MAX_NUM_OF_CORES 2 - - -/**************************************************************************//** - @Description Module types. -*//***************************************************************************/ -typedef enum e_ModuleId -{ - e_MODULE_ID_DUART_1 = 0, - e_MODULE_ID_DUART_2, - e_MODULE_ID_DUART_3, - e_MODULE_ID_DUART_4, - e_MODULE_ID_LAW, - e_MODULE_ID_LBC, - e_MODULE_ID_PAMU, - e_MODULE_ID_QM, /**< Queue manager module */ - e_MODULE_ID_BM, /**< Buffer manager module */ - e_MODULE_ID_QM_CE_PORTAL_0, - e_MODULE_ID_QM_CI_PORTAL_0, - e_MODULE_ID_QM_CE_PORTAL_1, - e_MODULE_ID_QM_CI_PORTAL_1, - e_MODULE_ID_QM_CE_PORTAL_2, - e_MODULE_ID_QM_CI_PORTAL_2, - e_MODULE_ID_QM_CE_PORTAL_3, - e_MODULE_ID_QM_CI_PORTAL_3, - e_MODULE_ID_QM_CE_PORTAL_4, - e_MODULE_ID_QM_CI_PORTAL_4, - e_MODULE_ID_QM_CE_PORTAL_5, - e_MODULE_ID_QM_CI_PORTAL_5, - e_MODULE_ID_QM_CE_PORTAL_6, - e_MODULE_ID_QM_CI_PORTAL_6, - e_MODULE_ID_QM_CE_PORTAL_7, - e_MODULE_ID_QM_CI_PORTAL_7, - e_MODULE_ID_QM_CE_PORTAL_8, - e_MODULE_ID_QM_CI_PORTAL_8, - e_MODULE_ID_QM_CE_PORTAL_9, - e_MODULE_ID_QM_CI_PORTAL_9, - e_MODULE_ID_BM_CE_PORTAL_0, - e_MODULE_ID_BM_CI_PORTAL_0, - e_MODULE_ID_BM_CE_PORTAL_1, - e_MODULE_ID_BM_CI_PORTAL_1, - e_MODULE_ID_BM_CE_PORTAL_2, - e_MODULE_ID_BM_CI_PORTAL_2, - e_MODULE_ID_BM_CE_PORTAL_3, - e_MODULE_ID_BM_CI_PORTAL_3, - e_MODULE_ID_BM_CE_PORTAL_4, - e_MODULE_ID_BM_CI_PORTAL_4, - e_MODULE_ID_BM_CE_PORTAL_5, - e_MODULE_ID_BM_CI_PORTAL_5, - e_MODULE_ID_BM_CE_PORTAL_6, - e_MODULE_ID_BM_CI_PORTAL_6, - e_MODULE_ID_BM_CE_PORTAL_7, - e_MODULE_ID_BM_CI_PORTAL_7, - e_MODULE_ID_BM_CE_PORTAL_8, - e_MODULE_ID_BM_CI_PORTAL_8, - e_MODULE_ID_BM_CE_PORTAL_9, - e_MODULE_ID_BM_CI_PORTAL_9, - e_MODULE_ID_FM, /**< Frame manager module */ - e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */ - e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */ - e_MODULE_ID_FM_BMI, /**< FM BMI block */ - e_MODULE_ID_FM_QMI, /**< FM QMI block */ - e_MODULE_ID_FM_PARSER, /**< FM parser block */ - e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */ - e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */ - e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */ - e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */ - e_MODULE_ID_FM_PLCR, /**< FM Policer */ - e_MODULE_ID_FM_KG, /**< FM Keygen */ - e_MODULE_ID_FM_DMA, /**< FM DMA */ - e_MODULE_ID_FM_FPM, /**< FM FPM */ - e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */ - e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/ - e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/ - e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/ - e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/ - e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/ - e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */ - e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ - e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */ - e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */ - e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */ - e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */ - e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */ - e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */ - - e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ - e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ - e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ - e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ - e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ - e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ - e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ - e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ - e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ - e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ - e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ - e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ - - e_MODULE_ID_PIC, /**< PIC */ - e_MODULE_ID_GPIO, /**< GPIO */ - e_MODULE_ID_SERDES, /**< SERDES */ - e_MODULE_ID_CPC_1, /**< CoreNet-Platform-Cache 1 */ - e_MODULE_ID_CPC_2, /**< CoreNet-Platform-Cache 2 */ - e_MODULE_ID_DUMMY_LAST -} e_ModuleId; - -#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST - -/* Offsets relative to CCSR base */ -#define P5020_OFFSET_LAW 0x00000c00 -#define P5020_OFFSET_DDR1 0x00008000 -#define P5020_OFFSET_DDR2 0x00009000 -#define P5020_OFFSET_CPC1 0x00010000 -#define P5020_OFFSET_CPC2 0x00011000 -#define P5020_OFFSET_CCF 0x00018000 -#define P5020_OFFSET_PAMU 0x00020000 -#define P5020_OFFSET_PIC 0x00040000 -#define P5020_OFFSET_GUTIL 0x000e0000 -#define P5020_OFFSET_RCPM 0x000e2000 -#define P5020_OFFSET_SERDES 0x000ea000 -#define P5020_OFFSET_DMA1 0x00100100 -#define P5020_OFFSET_DMA2 0x00101100 -#define P5020_OFFSET_ESPI 0x00110000 -#define P5020_OFFSET_ESDHC 0x00114000 -#define P5020_OFFSET_I2C1 0x00118000 -#define P5020_OFFSET_I2C2 0x00118100 -#define P5020_OFFSET_I2C3 0x00119000 -#define P5020_OFFSET_I2C4 0x00119100 -#define P5020_OFFSET_DUART1 0x0011c500 -#define P5020_OFFSET_DUART2 0x0011c600 -#define P5020_OFFSET_DUART3 0x0011d500 -#define P5020_OFFSET_DUART4 0x0011d600 -#define P5020_OFFSET_LBC 0x00124000 -#define P5020_OFFSET_GPIO 0x00130000 -#define P5020_OFFSET_PCIE1 0x00200000 -#define P5020_OFFSET_PCIE2 0x00201000 -#define P5020_OFFSET_PCIE3 0x00202000 -#define P5020_OFFSET_PCIE4 0x00203000 -#define P5020_OFFSET_USB1 0x00210000 -#define P5020_OFFSET_USB2 0x00211000 -#define P5020_OFFSET_USB_PHY 0x00214000 -#define P5020_OFFSET_SATA1 0x00220000 -#define P5020_OFFSET_SATA2 0x00221000 -#define P5020_OFFSET_SEC_GEN 0x00300000 -#define P5020_OFFSET_SEC_JQ0 0x00301000 -#define P5020_OFFSET_SEC_JQ1 0x00302000 -#define P5020_OFFSET_SEC_JQ2 0x00303000 -#define P5020_OFFSET_SEC_JQ3 0x00304000 -#define P5020_OFFSET_SEC_RESERVED 0x00305000 -#define P5020_OFFSET_SEC_RTIC 0x00306000 -#define P5020_OFFSET_SEC_QI 0x00307000 -#define P5020_OFFSET_SEC_DECO0_CCB0 0x00308000 -#define P5020_OFFSET_SEC_DECO1_CCB1 0x00309000 -#define P5020_OFFSET_PME 0x00316000 -#define P5020_OFFSET_QM 0x00318000 -#define P5020_OFFSET_BM 0x0031a000 -#define P5020_OFFSET_RAID 0x00320000 -#define P5020_OFFSET_FM 0x00400000 - -#define P5020_OFFSET_FM_MURAM P5020_OFFSET_FM -#define P5020_OFFSET_FM_BMI (P5020_OFFSET_FM + 0x00080000) -#define P5020_OFFSET_FM_QMI (P5020_OFFSET_FM + 0x00080400) -#define P5020_OFFSET_FM_PARSER (P5020_OFFSET_FM + 0x00080800) -#define P5020_OFFSET_FM_PORT_HO1 (P5020_OFFSET_FM + 0x00081000) /* host command/offline parser */ -#define P5020_OFFSET_FM_PORT_HO2 (P5020_OFFSET_FM + 0x00082000) -#define P5020_OFFSET_FM_PORT_HO3 (P5020_OFFSET_FM + 0x00083000) -#define P5020_OFFSET_FM_PORT_HO4 (P5020_OFFSET_FM + 0x00084000) -#define P5020_OFFSET_FM_PORT_HO5 (P5020_OFFSET_FM + 0x00085000) -#define P5020_OFFSET_FM_PORT_HO6 (P5020_OFFSET_FM + 0x00086000) -#define P5020_OFFSET_FM_PORT_HO7 (P5020_OFFSET_FM + 0x00087000) -#define P5020_OFFSET_FM_PORT_1GRX1 (P5020_OFFSET_FM + 0x00088000) -#define P5020_OFFSET_FM_PORT_1GRX2 (P5020_OFFSET_FM + 0x00089000) -#define P5020_OFFSET_FM_PORT_1GRX3 (P5020_OFFSET_FM + 0x0008a000) -#define P5020_OFFSET_FM_PORT_1GRX4 (P5020_OFFSET_FM + 0x0008b000) -#define P5020_OFFSET_FM_PORT_1GRX5 (P5020_OFFSET_FM + 0x0008c000) -#define P5020_OFFSET_FM_PORT_10GRX (P5020_OFFSET_FM + 0x00090000) -#define P5020_OFFSET_FM_PORT_1GTX1 (P5020_OFFSET_FM + 0x000a8000) -#define P5020_OFFSET_FM_PORT_1GTX2 (P5020_OFFSET_FM + 0x000a9000) -#define P5020_OFFSET_FM_PORT_1GTX3 (P5020_OFFSET_FM + 0x000aa000) -#define P5020_OFFSET_FM_PORT_1GTX4 (P5020_OFFSET_FM + 0x000ab000) -#define P5020_OFFSET_FM_PORT_1GTX5 (P5020_OFFSET_FM + 0x000ac000) -#define P5020_OFFSET_FM_PORT_10GTX (P5020_OFFSET_FM + 0x000b0000) -#define P5020_OFFSET_FM_PLCR (P5020_OFFSET_FM + 0x000c0000) -#define P5020_OFFSET_FM_KG (P5020_OFFSET_FM + 0x000c1000) -#define P5020_OFFSET_FM_DMA (P5020_OFFSET_FM + 0x000c2000) -#define P5020_OFFSET_FM_FPM (P5020_OFFSET_FM + 0x000c3000) -#define P5020_OFFSET_FM_IRAM (P5020_OFFSET_FM + 0x000c4000) -#define P5020_OFFSET_FM_PARSER_IRAM (P5020_OFFSET_FM + 0x000c7000) -#define P5020_OFFSET_FM_1GMAC1 (P5020_OFFSET_FM + 0x000e0000) -#define P5020_OFFSET_FM_1GMDIO (P5020_OFFSET_FM + 0x000e1000 + 0x120) -#define P5020_OFFSET_FM_1GMAC2 (P5020_OFFSET_FM + 0x000e2000) -#define P5020_OFFSET_FM_1GMAC3 (P5020_OFFSET_FM + 0x000e4000) -#define P5020_OFFSET_FM_1GMAC4 (P5020_OFFSET_FM + 0x000e6000) -#define P5020_OFFSET_FM_1GMAC5 (P5020_OFFSET_FM + 0x000e8000) -#define P5020_OFFSET_FM_10GMAC (P5020_OFFSET_FM + 0x000f0000) -#define P5020_OFFSET_FM_10GMDIO (P5020_OFFSET_FM + 0x000f1000 + 0x030) -#define P5020_OFFSET_FM_RTC (P5020_OFFSET_FM + 0x000fe000) - -/* Offsets relative to QM or BM portals base */ -#define P5020_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */ -#define P5020_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */ - -#define P5020_CE_PORTAL_SIZE 0x4000 -#define P5020_CI_PORTAL_SIZE 0x1000 - -#define P5020_OFFSET_PORTALS_CE(portal) \ - (P5020_OFFSET_PORTALS_CE_AREA + P5020_CE_PORTAL_SIZE * (portal)) -#define P5020_OFFSET_PORTALS_CI(portal) \ - (P5020_OFFSET_PORTALS_CI_AREA + P5020_CI_PORTAL_SIZE * (portal)) - - -/**************************************************************************//** - @Description Transaction source ID (for memory controllers error reporting). -*//***************************************************************************/ -typedef enum e_TransSrc -{ - e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */ - e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */ - e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */ - e_TRANS_SRC_PCIE_4 = 0x3, /**< PCI Express 4 */ - e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */ - e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */ - e_TRANS_SRC_BMAN = 0x18, /**< BMan */ - e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */ - e_TRANS_SRC_PME = 0x20, /**< PME */ - e_TRANS_SRC_SEC = 0x21, /**< Security engine */ - e_TRANS_SRC_RAID = 0x28, /**< RAID engine */ - e_TRANS_SRC_QMAN = 0x3C, /**< QMan */ - e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */ - e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */ - e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */ - e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */ - e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */ - e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */ - e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */ - e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */ - e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */ - e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */ - e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */ - e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */ - e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */ - e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */ - e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */ - e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */ - e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */ - e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */ - e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */ - e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */ - e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */ - e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */ - e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */ - e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */ - e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */ - e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */ - e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */ -} e_TransSrc; - -/**************************************************************************//** - @Description Local Access Window Target interface ID -*//***************************************************************************/ -typedef enum e_P5020LawTargetId -{ - e_P5020_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */ - e_P5020_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */ - e_P5020_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */ - e_P5020_LAW_TARGET_PCIE_4 = 0x3, /**< PCI Express 4 */ - e_P5020_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */ - e_P5020_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */ - e_P5020_LAW_TARGET_LOCAL_SPACE = 0xF, /**< Inbound ATMUs */ - e_P5020_LAW_TARGET_DDR_CPC_1 = 0x10, /**< DDR controller 1 or CPC 1 SRAM */ - e_P5020_LAW_TARGET_DDR_CPC_2 = 0x11, /**< DDR controller 2 or CPC 2 SRAM */ - e_P5020_LAW_TARGET_DDR_CPC_INTLV = 0x14, /**< Interleaved DDR controllers or CPC SRAM */ - e_P5020_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */ - e_P5020_LAW_TARGET_DCSR = 0x1D, /**< DCSR */ - e_P5020_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */ - e_P5020_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */ - e_P5020_LAW_TARGET_NONE = 0xFF /**< None */ -} e_P5020LawTargetId; - -/*************************************************************** - P5020 general routines -****************************************************************/ -/**************************************************************************//** - @Group P5020_init_grp P5020 Initialization Unit - - @Description P5020 initialization unit API functions, definitions and enums - - @{ -*//***************************************************************************/ - -/**************************************************************************//** - @Description Part ID and revision number -*//***************************************************************************/ -typedef enum e_P5020DeviceName -{ - e_P5020_REV_INVALID = 0x00000000, /**< Invalid revision */ - e_P5020_REV_1_0 = (int)0x82280010, /**< P5020 with security, revision 1.0 */ - e_P5020_REV_1_0_NO_SEC = (int)0x82200010, /**< P5020 without security, revision 1.0 */ - e_P5010_REV_1_0 = (int)0x82290010, /**< P5010 with security, revision 1.0 */ - e_P5010_REV_1_0_NO_SEC = (int)0x82210010 /**< P5010 without security, revision 1.0 */ -} e_P5020DeviceName; - -/**************************************************************************//** - @Description Device Disable Register -*//***************************************************************************/ -typedef enum e_P5020DeviceDisable -{ - e_P5020_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */ - e_P5020_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */ - e_P5020_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */ - e_P5020_DEV_DISABLE_PCIE_4, /**< PCI Express controller 4 disable */ - e_P5020_DEV_DISABLE_RMAN, /**< RapidIO message manager disable */ - e_P5020_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */ - e_P5020_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */ - e_P5020_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */ - e_P5020_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */ - e_P5020_DEV_DISABLE_DDR_1, /**< DDR controller 1 disable */ - e_P5020_DEV_DISABLE_DDR_2, /**< DDR controller 2 disable */ - e_P5020_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */ - e_P5020_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */ - e_P5020_DEV_DISABLE_LBC, /**< eLBC controller disable */ - e_P5020_DEV_DISABLE_USB_1, /**< USB controller 1 disable */ - e_P5020_DEV_DISABLE_USB_2, /**< USB controller 2 disable */ - e_P5020_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */ - e_P5020_DEV_DISABLE_GPIO, /**< GPIO controller disable */ - e_P5020_DEV_DISABLE_ESPI, /**< eSPI controller disable */ - e_P5020_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */ - e_P5020_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */ - e_P5020_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */ - e_P5020_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */ - e_P5020_DEV_DISABLE_DISR1_DUMMY_LAST = 32, - /**< Dummy entry signing end of DEVDISR1 register controllers */ - e_P5020_DEV_DISABLE_PME = e_P5020_DEV_DISABLE_DISR1_DUMMY_LAST, - /**< Pattern match engine disable */ - e_P5020_DEV_DISABLE_SEC, /**< Security disable */ - e_P5020_DEV_DISABLE_RAID, /**< RAID engine disable */ - e_P5020_DEV_DISABLE_QM_BM = e_P5020_DEV_DISABLE_DISR1_DUMMY_LAST + 4, - /**< Queue manager/buffer manager disable */ - e_P5020_DEV_DISABLE_FM = e_P5020_DEV_DISABLE_DISR1_DUMMY_LAST + 6, - /**< Frame manager disable */ - e_P5020_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */ - e_P5020_DEV_DISABLE_DTSEC_1, /**< dTSEC controller 1 disable */ - e_P5020_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */ - e_P5020_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */ - e_P5020_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */ - e_P5020_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */ -} e_P5020DeviceDisable; - - -/**************************************************************************//* - @Description structure representing P5020 devices configuration -*//***************************************************************************/ -typedef struct t_P5020Devices -{ - struct - { - struct - { - bool enabled; - uint8_t serdesBank; - uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank, - one bit for lane, lane A is the first and so on, e.g., - set 0xF000 for ABCD lanes */ - e_EnetInterface ethIf; - uint8_t ratio; - bool divByTwo; - bool isTwoHalfSgmii; - } dtsecs[FM_MAX_NUM_OF_1G_MACS]; - struct - { - bool enabled; - uint8_t serdesBank; - uint16_t serdesLane; - } tgec; - } fm; -} t_P5020Devices; - -/**************************************************************************//** - @Function P5020_GetRevInfo - - @Description Obtain revision information. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return Part ID and revision. -*//***************************************************************************/ -e_P5020DeviceName P5020_GetRevInfo(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P5020_GetE500Factor - - @Description Obtain core's multiplication factors. - - @Param[in] gutilBase - Gutil memory map virtual base address. - @Param[in] coreIndex - Core index. - @Param[out] p_E500MulFactor - E500 to CCB multification factor. - @Param[out] p_E500DivFactor - E500 to CCB division factor. - -*//***************************************************************************/ -void P5020_GetE500Factor(uintptr_t gutilBase, - uint8_t coreIndex, - uint32_t *p_E500MulFactor, - uint32_t *p_E500DivFactor); - -/**************************************************************************//** - @Function P5020_GetCcbFactor - - @Description Obtain system multiplication factor. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return System multiplication factor. -*//***************************************************************************/ -uint32_t P5020_GetCcbFactor(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P5020_GetDdrFactor - - @Description Obtain DDR clock multiplication factor. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return DDR clock multiplication factor. -*//***************************************************************************/ -uint32_t P5020_GetDdrFactor(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P5020_GetDdrType - - @Description Obtain DDR memory type. - - @Param[in] gutilBase - Gutil memory map virtual base address. - - @Return DDR type. -*//***************************************************************************/ -e_DdrType P5020_GetDdrType(uintptr_t gutilBase); - -/**************************************************************************//** - @Function P5020_GetFmFactor - - @Description returns FM multiplication factors. (This value is returned using - two parameters to avoid using float parameter). - - @Param[in] gutilBase - Gutil memory map virtual base address. - @Param[out] p_FmMulFactor - FM to CCB multification factor. - @Param[out] p_FmDivFactor - FM to CCB division factor. - -*//***************************************************************************/ -void P5020_GetFmFactor(uintptr_t gutilBase, - uint32_t *p_FmMulFactor, - uint32_t *p_FmDivFactor); - - -void P5020_CoreTimeBaseEnable(uintptr_t rcpmBase); -void P5020_CoreTimeBaseDisable(uintptr_t rcpmBase); - -typedef enum e_SerdesProtocol -{ - SRDS_PROTOCOL_NONE = 0, - SRDS_PROTOCOL_PCIE1, - SRDS_PROTOCOL_PCIE2, - SRDS_PROTOCOL_PCIE3, - SRDS_PROTOCOL_PCIE4, - SRDS_PROTOCOL_SRIO1, - SRDS_PROTOCOL_SRIO2, - SRDS_PROTOCOL_SGMII_FM, - SRDS_PROTOCOL_XAUI_FM, - SRDS_PROTOCOL_SATA1, - SRDS_PROTOCOL_SATA2, - SRDS_PROTOCOL_AURORA -} e_SerdesProtocol; - -t_Error P5020_DeviceDisable(uintptr_t gutilBase, e_P5020DeviceDisable device, bool disable); -void P5020_GetDevicesConfiguration(uintptr_t gutilBase, t_P5020Devices *p_Devices); -t_Error P5020_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable); -uint32_t P5020_SerdesRcwGetProtocol(uintptr_t gutilBase); -bool P5020_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device); -bool P5020_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane); - -/** @} */ /* end of P5020_init_grp group */ -/** @} */ /* end of P5020_grp group */ - - -/***************************************************************************** - INTEGRATION-SPECIFIC MODULE CODES -******************************************************************************/ -#define MODULE_UNKNOWN 0x00000000 -#define MODULE_MEM 0x00010000 -#define MODULE_MM 0x00020000 -#define MODULE_CORE 0x00030000 -#define MODULE_P5020 0x00040000 -#define MODULE_P5020_PLATFORM 0x00050000 -#define MODULE_PM 0x00060000 -#define MODULE_MMU 0x00070000 -#define MODULE_PIC 0x00080000 -#define MODULE_CPC 0x00090000 -#define MODULE_DUART 0x000a0000 -#define MODULE_SERDES 0x000b0000 -#define MODULE_PIO 0x000c0000 -#define MODULE_QM 0x000d0000 -#define MODULE_BM 0x000e0000 -#define MODULE_SEC 0x000f0000 -#define MODULE_LAW 0x00100000 -#define MODULE_LBC 0x00110000 -#define MODULE_PAMU 0x00120000 -#define MODULE_FM 0x00130000 -#define MODULE_FM_MURAM 0x00140000 -#define MODULE_FM_PCD 0x00150000 -#define MODULE_FM_RTC 0x00160000 -#define MODULE_FM_MAC 0x00170000 -#define MODULE_FM_PORT 0x00180000 -#define MODULE_DPA 0x00190000 -#define MODULE_MII 0x001a0000 -#define MODULE_I2C 0x001b0000 -#define MODULE_DMA 0x001c0000 -#define MODULE_DDR 0x001d0000 -#define MODULE_ESPI 0x001e0000 - -/***************************************************************************** - PAMU INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define PAMU_NUM_OF_PARTITIONS 4 - - -/***************************************************************************** - LAW INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define LAW_NUM_OF_WINDOWS 32 -#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */ -#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */ - - -/***************************************************************************** - LBC INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -/**************************************************************************//** - @Group lbc_exception_grp LBC Exception Unit - - @Description LBC Exception unit API functions, definitions and enums - - @{ -*//***************************************************************************/ - -/**************************************************************************//** - @Anchor lbc_exbm - - @Collection LBC Errors Bit Mask - - These errors are reported through the exceptions callback.. - The values can be or'ed in any combination in the errors mask - parameter of the errors report structure. - - These errors can also be passed as a bit-mask to - LBC_EnableErrorChecking() or LBC_DisableErrorChecking(), - for enabling or disabling error checking. - @{ -*//***************************************************************************/ -#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */ -#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */ -#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */ -#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */ - -#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \ - LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT) - /**< All possible errors */ -/* @} */ -/** @} */ /* end of lbc_exception_grp group */ - -#define LBC_INCORRECT_ERROR_REPORT_ERRATA - -#define LBC_NUM_OF_BANKS 8 -#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */ -#define LBC_PARITY_SUPPORT -#define LBC_ADDRESS_HOLD_TIME_CTRL -#define LBC_HIGH_CLK_DIVIDERS -#define LBC_FCM_AVAILABLE - -/***************************************************************************** - GPIO INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module; - Each port contains up to 32 I/O pins. */ - -#define GPIO_VALID_PIN_MASKS \ - { /* Port A */ 0xFFFFFFFF } - -#define GPIO_VALID_INTR_MASKS \ - { /* Port A */ 0xFFFFFFFF } - - -/***************************************************************************** - SERDES INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define SRDS_MAX_LANES 18 -#define SRDS_MAX_BANK 3 - -/* Serdes lanes general information provided in the following form: - 1) Lane index in Serdes Control Registers Map - 2) Lane enable/disable bit number in RCW - 3) Lane bank index */ -#define SRDS_LANES \ -{ \ - { 0, 152, 0 }, \ - { 1, 153, 0 }, \ - { 2, 154, 0 }, \ - { 3, 155, 0 }, \ - { 4, 156, 0 }, \ - { 5, 157, 0 }, \ - { 6, 158, 0 }, \ - { 7, 159, 0 }, \ - { 8, 160, 0 }, \ - { 9, 161, 0 }, \ - { 16, 162, 1 }, \ - { 17, 163, 1 }, \ - { 18, 164, 1 }, \ - { 19, 165, 1 }, \ - { 20, 166, 2 }, \ - { 21, 167, 2 }, \ - { 22, 168, 2 }, \ - { 23, 169, 2 } \ -} - -#define SRDS_PROTOCOL_ALL_OPTIONS -/* Serdes lanes assignment and multiplexing. - Each option is selected by SRDS_PRTCL bits of RCW. */ -#define SRDS_PROTOCOL_OPTIONS \ -/* Protocol Lane assignment */ \ -{ \ -/* 0x00 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x01 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x03 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x04 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x05 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x06 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x07 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x08 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x09 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x0A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x0B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x0C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x0D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x0E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x0F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x10 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x11 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x12 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x13 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x14 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x15 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1}, \ -/* 0x17 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x18 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x19 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x1A */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x1B */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x1C */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x1D */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x1E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x1F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x20 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x21 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x22 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x23 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x24 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x25 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x26 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \ -/* 0x27 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x28 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x29 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x2A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x2B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x2C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x2D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x2E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x2F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x30 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x31 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \ -/* 0x32 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \ -/* 0x33 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x34 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x35 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x36 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \ -/* 0x37 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \ - SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \ - SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \ - SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \ - 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2} \ -} - -/***************************************************************************** - DDR INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define DDR_NUM_OF_VALID_CS 4 - -/***************************************************************************** - DMA INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ -#define DMA_NUM_OF_CONTROLLERS 2 - -/***************************************************************************** - CPC INTEGRATION-SPECIFIC DEFINITIONS -******************************************************************************/ - -#define CPC_MAX_SIZE_SRAM_ERRATA_CPC4 -#define CPC_HARDWARE_FLUSH_ERRATA_CPC10 - - -#endif /* __PART_INTEGRATION_EXT_H */ diff --git a/sys/contrib/ncsw/inc/integrations/P5020/dpaa_integration_ext.h b/sys/contrib/ncsw/inc/integrations/dpaa_integration_ext.h index 6283b1a..88443fa 100644 --- a/sys/contrib/ncsw/inc/integrations/P5020/dpaa_integration_ext.h +++ b/sys/contrib/ncsw/inc/integrations/dpaa_integration_ext.h @@ -331,21 +331,19 @@ typedef enum e_FmInterModuleEvent #define FM_NO_ADVANCED_RATE_LIMITER #define FM_NO_OP_OBSERVED_CGS -/* FM erratas */ +/* FM erratas (P5020, P3041) */ #define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 #define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */ #define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 #define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008 #define FM_NO_RX_PREAM_ERRATA_DTSECx1 -#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1 #define FM_GRS_ERRATA_DTSEC_A002 #define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 #define FM_GTS_ERRATA_DTSEC_A004 #define FM_PAUSE_BLOCK_ERRATA_DTSEC_A006 /* do nothing */ #define FM_RESERVED_ACCESS_TO_DISABLED_DEV_ERRATA_DTSEC_A0011 /* do nothing */ #define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 FM_GTS_ERRATA_DTSEC_A004 -#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */ #define FM_10_100_SGMII_NO_TS_ERRATA_DTSEC3 #define FM_TX_LOCKUP_ERRATA_DTSEC6 @@ -362,13 +360,19 @@ typedef enum e_FmInterModuleEvent //#define FM_PRS_MPLS_SSA_ERRATA_FMANj /* No implementation, No patch yet */ //#define FM_PRS_INITIAL_PLANID_ERRATA_FMANk /* No implementation, No patch yet */ -#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 - #define FM_NO_COPY_CTXA_CTXB_ERRATA_FMAN_SW001 -#define FM_PRS_MEM_ERRATA_FMAN_SW003 -#define FM_LEN_CHECK_ERRATA_FMAN_SW002 #define FM_10G_REM_N_LCL_FLT_EX_ERRATA_10GMAC001 +/* P2041 */ +#define FM_BAD_VLAN_DETECT_ERRATA_10GMAC_A010 + +/* Common to all */ +#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1 +#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 +#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */ +#define FM_PRS_MEM_ERRATA_FMAN_SW003 +#define FM_LEN_CHECK_ERRATA_FMAN_SW002 + #endif /* __DPAA_INTEGRATION_EXT_H */ diff --git a/sys/contrib/ncsw/inc/integrations/part_ext.h b/sys/contrib/ncsw/inc/integrations/part_ext.h index 015db86..8052c43 100644 --- a/sys/contrib/ncsw/inc/integrations/part_ext.h +++ b/sys/contrib/ncsw/inc/integrations/part_ext.h @@ -41,32 +41,24 @@ #define __PART_EXT_H #include "std_ext.h" -#include "part_integration_ext.h" +#include "enet_ext.h" +#include "dpaa_integration_ext.h" +#define CORE_E500MC -#if !(defined(MPC8306) || \ - defined(MPC8309) || \ - defined(MPC834x) || \ - defined(MPC836x) || \ - defined(MPC832x) || \ - defined(MPC837x) || \ - defined(MPC8568) || \ - defined(MPC8569) || \ - defined(P1020) || \ - defined(P1021) || \ - defined(P1022) || \ - defined(P1023) || \ - defined(P2020) || \ - defined(P2040) || \ - defined(P2041) || \ - defined(P3041) || \ - defined(P4080) || \ - defined(SC4080) || \ - defined(P5020) || \ - defined(MSC814x)) -#error "unable to proceed without chip-definition" -#endif /* !(defined(MPC834x) || ... */ - +/***************************************************************************** + INTEGRATION-SPECIFIC MODULE CODES +******************************************************************************/ +#define MODULE_MEM 0x00010000 +#define MODULE_MM 0x00020000 +#define MODULE_QM 0x000d0000 +#define MODULE_BM 0x000e0000 +#define MODULE_FM 0x00130000 +#define MODULE_FM_MURAM 0x00140000 +#define MODULE_FM_PCD 0x00150000 +#define MODULE_FM_RTC 0x00160000 +#define MODULE_FM_MAC 0x00170000 +#define MODULE_FM_PORT 0x00180000 /**************************************************************************//* @Description Part data structure - must be contained in any integration @@ -74,10 +66,6 @@ *//***************************************************************************/ typedef struct t_Part { - uintptr_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId); - /**< Returns the address of the module's memory map base. */ - e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uintptr_t baseAddress); - /**< Returns the module's ID according to its memory map base. */ } t_Part; diff --git a/sys/contrib/ncsw/integrations/P2041/module_strings.c b/sys/contrib/ncsw/integrations/P2041/module_strings.c deleted file mode 100644 index 674e10c..0000000 --- a/sys/contrib/ncsw/integrations/P2041/module_strings.c +++ /dev/null @@ -1,62 +0,0 @@ -/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Freescale Semiconductor nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Module names for debug messages */ -const char *moduleStrings[] = -{ - "???" /* MODULE_UNKNOWN */ - ,"MEM" /* MODULE_ */ - ,"MM" /* MODULE_MM */ - ,"CORE" /* MODULE_CORE */ - ,"P2041" /* MODULE_P2041 */ - ,"P2041-Platform" /* MODULE_P2041_PLTFRM */ - ,"PM" /* MODULE_PM */ - ,"MMU" /* MODULE_MMU */ - ,"PIC" /* MODULE_PIC */ - ,"L3 cache (CPC)" /* MODULE_CPC */ - ,"DUART" /* MODULE_DUART */ - ,"SerDes" /* MODULE_SERDES */ - ,"PIO" /* MODULE_PIO */ - ,"QM" /* MODULE_QM */ - ,"BM" /* MODULE_BM */ - ,"SEC" /* MODULE_SEC */ - ,"LAW" /* MODULE_LAW */ - ,"LBC" /* MODULE_LBC */ - ,"PAMU" /* MODULE_PAMU */ - ,"FM" /* MODULE_FM */ - ,"FM-MURAM" /* MODULE_FM_MURAM */ - ,"FM-PCD" /* MODULE_FM_PCD */ - ,"FM-RTC" /* MODULE_FM_RTC */ - ,"FM-MAC" /* MODULE_FM_MAC */ - ,"FM-Port" /* MODULE_FM_PORT */ - ,"DPA" /* MODULE_DPA */ -}; diff --git a/sys/contrib/ncsw/integrations/P3041/module_strings.c b/sys/contrib/ncsw/integrations/P3041/module_strings.c deleted file mode 100644 index 4fc7bc8..0000000 --- a/sys/contrib/ncsw/integrations/P3041/module_strings.c +++ /dev/null @@ -1,62 +0,0 @@ -/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Freescale Semiconductor nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Module names for debug messages */ -const char *moduleStrings[] = -{ - "???" /* MODULE_UNKNOWN */ - ,"MEM" /* MODULE_ */ - ,"MM" /* MODULE_MM */ - ,"CORE" /* MODULE_CORE */ - ,"P3041" /* MODULE_P3041 */ - ,"P3041-Platform" /* MODULE_P3041_PLTFRM */ - ,"PM" /* MODULE_PM */ - ,"MMU" /* MODULE_MMU */ - ,"PIC" /* MODULE_PIC */ - ,"L3 cache (CPC)" /* MODULE_CPC */ - ,"DUART" /* MODULE_DUART */ - ,"SerDes" /* MODULE_SERDES */ - ,"PIO" /* MODULE_PIO */ - ,"QM" /* MODULE_QM */ - ,"BM" /* MODULE_BM */ - ,"SEC" /* MODULE_SEC */ - ,"LAW" /* MODULE_LAW */ - ,"LBC" /* MODULE_LBC */ - ,"PAMU" /* MODULE_PAMU */ - ,"FM" /* MODULE_FM */ - ,"FM-MURAM" /* MODULE_FM_MURAM */ - ,"FM-PCD" /* MODULE_FM_PCD */ - ,"FM-RTC" /* MODULE_FM_RTC */ - ,"FM-MAC" /* MODULE_FM_MAC */ - ,"FM-Port" /* MODULE_FM_PORT */ - ,"DPA" /* MODULE_DPA */ -}; diff --git a/sys/contrib/ncsw/integrations/P5020/module_strings.c b/sys/contrib/ncsw/integrations/P5020/module_strings.c deleted file mode 100644 index 84509d0..0000000 --- a/sys/contrib/ncsw/integrations/P5020/module_strings.c +++ /dev/null @@ -1,62 +0,0 @@ -/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Freescale Semiconductor nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Module names for debug messages */ -const char *moduleStrings[] = -{ - "???" /* MODULE_UNKNOWN */ - ,"MEM" /* MODULE_ */ - ,"MM" /* MODULE_MM */ - ,"CORE" /* MODULE_CORE */ - ,"P5020" /* MODULE_P5020 */ - ,"P5020-Platform" /* MODULE_P5020_PLTFRM */ - ,"PM" /* MODULE_PM */ - ,"MMU" /* MODULE_MMU */ - ,"PIC" /* MODULE_PIC */ - ,"L3 cache (CPC)" /* MODULE_CPC */ - ,"DUART" /* MODULE_DUART */ - ,"SerDes" /* MODULE_SERDES */ - ,"PIO" /* MODULE_PIO */ - ,"QM" /* MODULE_QM */ - ,"BM" /* MODULE_BM */ - ,"SEC" /* MODULE_SEC */ - ,"LAW" /* MODULE_LAW */ - ,"LBC" /* MODULE_LBC */ - ,"PAMU" /* MODULE_PAMU */ - ,"FM" /* MODULE_FM */ - ,"FM-MURAM" /* MODULE_FM_MURAM */ - ,"FM-PCD" /* MODULE_FM_PCD */ - ,"FM-RTC" /* MODULE_FM_RTC */ - ,"FM-MAC" /* MODULE_FM_MAC */ - ,"FM-Port" /* MODULE_FM_PORT */ - ,"DPA" /* MODULE_DPA */ -}; diff --git a/sys/contrib/ncsw/integrations/P3041/fman_ctrl_code/p3041_r1.0.h b/sys/contrib/ncsw/integrations/fman_ctrl_code/p3041_r1.0.h index 21f9115..21f9115 100644 --- a/sys/contrib/ncsw/integrations/P3041/fman_ctrl_code/p3041_r1.0.h +++ b/sys/contrib/ncsw/integrations/fman_ctrl_code/p3041_r1.0.h diff --git a/sys/contrib/ncsw/integrations/fman_ucode.h b/sys/contrib/ncsw/integrations/fman_ucode.h index 7dfb151..526b7b9 100644 --- a/sys/contrib/ncsw/integrations/fman_ucode.h +++ b/sys/contrib/ncsw/integrations/fman_ucode.h @@ -38,7 +38,7 @@ /** * Header with actual uCode rel_101_8. */ -#include "P3041/fman_ctrl_code/p3041_r1.0.h" +#include "fman_ctrl_code/p3041_r1.0.h" /** * Generic macro. diff --git a/sys/dev/ahci/ahci.c b/sys/dev/ahci/ahci.c index f809937..ec42b3c 100644 --- a/sys/dev/ahci/ahci.c +++ b/sys/dev/ahci/ahci.c @@ -166,8 +166,8 @@ int ahci_attach(device_t dev) { struct ahci_controller *ctlr = device_get_softc(dev); - int error, i, u, speed, unit; - u_int32_t version; + int error, i, speed, unit; + uint32_t u, version; device_t child; ctlr->dev = dev; diff --git a/sys/dev/ahci/ahci.h b/sys/dev/ahci/ahci.h index e2a1caf..1dc75ca 100644 --- a/sys/dev/ahci/ahci.h +++ b/sys/dev/ahci/ahci.h @@ -474,7 +474,7 @@ struct ahci_enclosure { uint8_t status[AHCI_MAX_PORTS][4]; /* ArrayDev statuses */ int quirks; int channels; - int ichannels; + uint32_t ichannels; }; /* structure describing a AHCI controller */ @@ -509,7 +509,7 @@ struct ahci_controller { int quirks; int numirqs; int channels; - int ichannels; + uint32_t ichannels; int ccc; /* CCC timeout */ int cccv; /* CCC vector */ int direct; /* Direct command completion */ diff --git a/sys/dev/ath/if_ath_tx_ht.c b/sys/dev/ath/if_ath_tx_ht.c index 75e949a..5a55f60 100644 --- a/sys/dev/ath/if_ath_tx_ht.c +++ b/sys/dev/ath/if_ath_tx_ht.c @@ -222,6 +222,7 @@ void ath_tx_rate_fill_rcflags(struct ath_softc *sc, struct ath_buf *bf) { struct ieee80211_node *ni = bf->bf_node; + struct ieee80211vap *vap = ni->ni_vap; struct ieee80211com *ic = ni->ni_ic; const HAL_RATE_TABLE *rt = sc->sc_currates; struct ath_rc_series *rc = bf->bf_state.bfs_rc; @@ -280,12 +281,14 @@ ath_tx_rate_fill_rcflags(struct ath_softc *sc, struct ath_buf *bf) if (ni->ni_chw == 40 && ic->ic_htcaps & IEEE80211_HTCAP_SHORTGI40 && - ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) + ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40 && + vap->iv_flags_ht & IEEE80211_FHT_SHORTGI40) rc[i].flags |= ATH_RC_SGI_FLAG; if (ni->ni_chw == 20 && ic->ic_htcaps & IEEE80211_HTCAP_SHORTGI20 && - ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) + ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20 && + vap->iv_flags_ht & IEEE80211_FHT_SHORTGI20) rc[i].flags |= ATH_RC_SGI_FLAG; /* diff --git a/sys/dev/cpuctl/cpuctl.c b/sys/dev/cpuctl/cpuctl.c index 6519e1b..08a37c8 100644 --- a/sys/dev/cpuctl/cpuctl.c +++ b/sys/dev/cpuctl/cpuctl.c @@ -120,7 +120,7 @@ static void set_cpu(int cpu, struct thread *td) { - KASSERT(cpu >= 0 && cpu < mp_ncpus && cpu_enabled(cpu), + KASSERT(cpu >= 0 && cpu <= mp_maxid && cpu_enabled(cpu), ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); thread_lock(td); sched_bind(td, cpu); @@ -133,7 +133,7 @@ static void restore_cpu(int oldcpu, int is_bound, struct thread *td) { - KASSERT(oldcpu >= 0 && oldcpu < mp_ncpus && cpu_enabled(oldcpu), + KASSERT(oldcpu >= 0 && oldcpu <= mp_maxid && cpu_enabled(oldcpu), ("[cpuctl,%d]: bad cpu number %d", __LINE__, oldcpu)); thread_lock(td); if (is_bound == 0) @@ -150,7 +150,7 @@ cpuctl_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int ret; int cpu = dev2unit(dev); - if (cpu >= mp_ncpus || !cpu_enabled(cpu)) { + if (cpu > mp_maxid || !cpu_enabled(cpu)) { DPRINTF("[cpuctl,%d]: bad cpu number %d\n", __LINE__, cpu); return (ENXIO); } @@ -201,7 +201,7 @@ cpuctl_do_cpuid_count(int cpu, cpuctl_cpuid_count_args_t *data, int is_bound = 0; int oldcpu; - KASSERT(cpu >= 0 && cpu < mp_ncpus, + KASSERT(cpu >= 0 && cpu <= mp_maxid, ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); /* Explicitly clear cpuid data to avoid returning stale info. */ @@ -245,7 +245,7 @@ cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd, struct thread *td) int oldcpu; int ret; - KASSERT(cpu >= 0 && cpu < mp_ncpus, + KASSERT(cpu >= 0 && cpu <= mp_maxid, ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); /* @@ -296,7 +296,7 @@ cpuctl_do_update(int cpu, cpuctl_update_args_t *data, struct thread *td) char vendor[13]; int ret; - KASSERT(cpu >= 0 && cpu < mp_ncpus, + KASSERT(cpu >= 0 && cpu <= mp_maxid, ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); DPRINTF("[cpuctl,%d]: XXX %d", __LINE__, cpu); @@ -512,7 +512,7 @@ cpuctl_open(struct cdev *dev, int flags, int fmt __unused, struct thread *td) int cpu; cpu = dev2unit(dev); - if (cpu >= mp_ncpus || !cpu_enabled(cpu)) { + if (cpu > mp_maxid || !cpu_enabled(cpu)) { DPRINTF("[cpuctl,%d]: incorrect cpu number %d\n", __LINE__, cpu); return (ENXIO); @@ -531,15 +531,15 @@ cpuctl_modevent(module_t mod __unused, int type, void *data __unused) case MOD_LOAD: if (bootverbose) printf("cpuctl: access to MSR registers/cpuid info.\n"); - cpuctl_devs = malloc(sizeof(*cpuctl_devs) * mp_ncpus, M_CPUCTL, + cpuctl_devs = malloc(sizeof(*cpuctl_devs) * (mp_maxid + 1), M_CPUCTL, M_WAITOK | M_ZERO); - for (cpu = 0; cpu < mp_ncpus; cpu++) + CPU_FOREACH(cpu) if (cpu_enabled(cpu)) cpuctl_devs[cpu] = make_dev(&cpuctl_cdevsw, cpu, UID_ROOT, GID_KMEM, 0640, "cpuctl%d", cpu); break; case MOD_UNLOAD: - for (cpu = 0; cpu < mp_ncpus; cpu++) { + CPU_FOREACH(cpu) { if (cpuctl_devs[cpu] != NULL) destroy_dev(cpuctl_devs[cpu]); } diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h index 34cb38f..d311245 100644 --- a/sys/dev/cxgbe/adapter.h +++ b/sys/dev/cxgbe/adapter.h @@ -372,6 +372,13 @@ enum { NM_BUSY = 2, }; +struct sge_iq; +struct rss_header; +typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, + struct mbuf *); +typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); +typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); + /* * Ingress Queue: T4 is producer, driver is consumer. */ @@ -379,6 +386,8 @@ struct sge_iq { uint32_t flags; volatile int state; struct adapter *adapter; + cpl_handler_t set_tcb_rpl; + cpl_handler_t l2t_write_rpl; struct iq_desc *desc; /* KVA of descriptor ring */ int8_t intr_pktc_idx; /* packet count threshold index */ uint8_t gen; /* generation bit */ @@ -739,12 +748,6 @@ struct sge { struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; }; -struct rss_header; -typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, - struct mbuf *); -typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); -typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); - struct adapter { SLIST_ENTRY(adapter) link; device_t dev; @@ -783,6 +786,7 @@ struct adapter { struct sge sge; int lro_timeout; + int sc_do_rxcopy; struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ struct port_info *port[MAX_NPORTS]; @@ -842,15 +846,9 @@ struct adapter { struct memwin memwin[NUM_MEMWIN]; /* memory windows */ - an_handler_t an_handler __aligned(CACHE_LINE_SIZE); - fw_msg_handler_t fw_msg_handler[7]; /* NUM_FW6_TYPES */ - cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ - const char *last_op; const void *last_op_thr; int last_op_flags; - - int sc_do_rxcopy; }; #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) @@ -1080,9 +1078,6 @@ int t4_os_pci_restore_state(struct adapter *); void t4_os_portmod_changed(const struct adapter *, int); void t4_os_link_changed(struct adapter *, int, int, int); void t4_iterate(void (*)(struct adapter *, void *), void *); -int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); -int t4_register_an_handler(struct adapter *, an_handler_t); -int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); void doom_vi(struct adapter *, struct vi_info *); @@ -1107,7 +1102,6 @@ void t4_nm_intr(void *); void t4_sge_modload(void); void t4_sge_modunload(void); uint64_t t4_sge_extfree_refs(void); -void t4_init_sge_cpl_handlers(struct adapter *); void t4_tweak_chip_settings(struct adapter *); int t4_read_chip_settings(struct adapter *); int t4_create_dma_tag(struct adapter *); @@ -1129,6 +1123,9 @@ int parse_pkt(struct mbuf **); void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); int tnl_cong(struct port_info *, int); +int t4_register_an_handler(an_handler_t); +int t4_register_fw_msg_handler(int, fw_msg_handler_t); +int t4_register_cpl_handler(int, cpl_handler_t); /* t4_tracer.c */ struct t4_tracer; diff --git a/sys/dev/cxgbe/cxgbei/cxgbei.c b/sys/dev/cxgbe/cxgbei/cxgbei.c index 775e3a2..face22d 100644 --- a/sys/dev/cxgbe/cxgbei/cxgbei.c +++ b/sys/dev/cxgbe/cxgbei/cxgbei.c @@ -745,24 +745,6 @@ do_rx_iscsi_ddp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) return (0); } -static void -t4_register_cpl_handler_with_tom(struct adapter *sc) -{ - - t4_register_cpl_handler(sc, CPL_ISCSI_HDR, do_rx_iscsi_hdr); - t4_register_cpl_handler(sc, CPL_ISCSI_DATA, do_rx_iscsi_data); - t4_register_cpl_handler(sc, CPL_RX_ISCSI_DDP, do_rx_iscsi_ddp); -} - -static void -t4_unregister_cpl_handler_with_tom(struct adapter *sc) -{ - - t4_register_cpl_handler(sc, CPL_ISCSI_HDR, NULL); - t4_register_cpl_handler(sc, CPL_ISCSI_DATA, NULL); - t4_register_cpl_handler(sc, CPL_RX_ISCSI_DDP, NULL); -} - /* initiator */ void cxgbei_conn_task_reserve_itt(void *conn, void **prv, @@ -835,7 +817,6 @@ cxgbei_activate(struct adapter *sc) return (rc); } - t4_register_cpl_handler_with_tom(sc); sc->iscsi_ulp_softc = ci; return (0); @@ -849,7 +830,6 @@ cxgbei_deactivate(struct adapter *sc) if (sc->iscsi_ulp_softc != NULL) { cxgbei_ddp_cleanup(sc->iscsi_ulp_softc); - t4_unregister_cpl_handler_with_tom(sc); free(sc->iscsi_ulp_softc, M_CXGBE); sc->iscsi_ulp_softc = NULL; } @@ -1062,6 +1042,10 @@ cxgbei_mod_load(void) { int rc; + t4_register_cpl_handler(CPL_ISCSI_HDR, do_rx_iscsi_hdr); + t4_register_cpl_handler(CPL_ISCSI_DATA, do_rx_iscsi_data); + t4_register_cpl_handler(CPL_RX_ISCSI_DDP, do_rx_iscsi_ddp); + rc = start_worker_threads(); if (rc != 0) return (rc); @@ -1088,6 +1072,10 @@ cxgbei_mod_unload(void) stop_worker_threads(); + t4_register_cpl_handler(CPL_ISCSI_HDR, NULL); + t4_register_cpl_handler(CPL_ISCSI_DATA, NULL); + t4_register_cpl_handler(CPL_RX_ISCSI_DDP, NULL); + return (0); } #endif diff --git a/sys/dev/cxgbe/cxgbei/icl_cxgbei.c b/sys/dev/cxgbe/cxgbei/icl_cxgbei.c index d0e7f39..8f29452 100644 --- a/sys/dev/cxgbe/cxgbei/icl_cxgbei.c +++ b/sys/dev/cxgbe/cxgbei/icl_cxgbei.c @@ -71,6 +71,7 @@ __FBSDID("$FreeBSD$"); #include <icl_conn_if.h> #include "common/common.h" +#include "common/t4_tcb.h" #include "tom/t4_tom.h" #include "cxgbei.h" @@ -584,19 +585,19 @@ send_iscsi_flowc_wr(struct adapter *sc, struct toepcb *toep, int maxlen) static void set_ulp_mode_iscsi(struct adapter *sc, struct toepcb *toep, int hcrc, int dcrc) { - uint64_t val = 0; + uint64_t val = ULP_MODE_ISCSI; if (hcrc) - val |= ULP_CRC_HEADER; + val |= ULP_CRC_HEADER << 4; if (dcrc) - val |= ULP_CRC_DATA; - val <<= 4; - val |= ULP_MODE_ISCSI; + val |= ULP_CRC_DATA << 4; CTR4(KTR_CXGBE, "%s: tid %u, ULP_MODE_ISCSI, CRC hdr=%d data=%d", __func__, toep->tid, hcrc, dcrc); - t4_set_tcb_field(sc, toep, 1, 0, 0xfff, val); + t4_set_tcb_field(sc, toep->ctrlq, toep->tid, W_TCB_ULP_TYPE, + V_TCB_ULP_TYPE(M_TCB_ULP_TYPE) | V_TCB_ULP_RAW(M_TCB_ULP_RAW), val, + 0, 0, toep->ofld_rxq->iq.abs_id); } /* diff --git a/sys/dev/cxgbe/iw_cxgbe/cm.c b/sys/dev/cxgbe/iw_cxgbe/cm.c index 1f6cc37..bea5aa0 100644 --- a/sys/dev/cxgbe/iw_cxgbe/cm.c +++ b/sys/dev/cxgbe/iw_cxgbe/cm.c @@ -2463,28 +2463,14 @@ static int terminate(struct sge_iq *iq, const struct rss_header *rss, struct mbu return 0; } - void -c4iw_cm_init_cpl(struct adapter *sc) -{ - - t4_register_cpl_handler(sc, CPL_RDMA_TERMINATE, terminate); - t4_register_fw_msg_handler(sc, FW6_TYPE_WR_RPL, fw6_wr_rpl); - t4_register_fw_msg_handler(sc, FW6_TYPE_CQE, fw6_cqe_handler); - t4_register_an_handler(sc, c4iw_ev_handler); -} - - void -c4iw_cm_term_cpl(struct adapter *sc) -{ - - t4_register_cpl_handler(sc, CPL_RDMA_TERMINATE, NULL); - t4_register_fw_msg_handler(sc, FW6_TYPE_WR_RPL, NULL); - t4_register_fw_msg_handler(sc, FW6_TYPE_CQE, NULL); -} - int __init c4iw_cm_init(void) { + t4_register_cpl_handler(CPL_RDMA_TERMINATE, terminate); + t4_register_fw_msg_handler(FW6_TYPE_WR_RPL, fw6_wr_rpl); + t4_register_fw_msg_handler(FW6_TYPE_CQE, fw6_cqe_handler); + t4_register_an_handler(c4iw_ev_handler); + TAILQ_INIT(&req_list); spin_lock_init(&req_lock); INIT_LIST_HEAD(&timeout_list); @@ -2496,7 +2482,6 @@ int __init c4iw_cm_init(void) if (!c4iw_taskq) return -ENOMEM; - return 0; } @@ -2506,5 +2491,10 @@ void __exit c4iw_cm_term(void) WARN_ON(!list_empty(&timeout_list)); flush_workqueue(c4iw_taskq); destroy_workqueue(c4iw_taskq); + + t4_register_cpl_handler(CPL_RDMA_TERMINATE, NULL); + t4_register_fw_msg_handler(FW6_TYPE_WR_RPL, NULL); + t4_register_fw_msg_handler(FW6_TYPE_CQE, NULL); + t4_register_an_handler(NULL); } #endif diff --git a/sys/dev/cxgbe/iw_cxgbe/device.c b/sys/dev/cxgbe/iw_cxgbe/device.c index ea04190..310b99b 100644 --- a/sys/dev/cxgbe/iw_cxgbe/device.c +++ b/sys/dev/cxgbe/iw_cxgbe/device.c @@ -227,7 +227,6 @@ c4iw_activate(struct adapter *sc) } sc->iwarp_softc = iwsc; - c4iw_cm_init_cpl(sc); rc = -c4iw_register_device(iwsc); if (rc) { diff --git a/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h b/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h index 0aa2568..faeb5f4 100644 --- a/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h +++ b/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h @@ -936,9 +936,6 @@ extern int c4iw_max_read_depth; #define L1_CACHE_BYTES 32 #endif -void c4iw_cm_init_cpl(struct adapter *); -void c4iw_cm_term_cpl(struct adapter *); - void your_reg_device(struct c4iw_dev *dev); #define SGE_CTRLQ_NUM 0 diff --git a/sys/dev/cxgbe/t4_l2t.c b/sys/dev/cxgbe/t4_l2t.c index 7c4cede..b4b1ee4 100644 --- a/sys/dev/cxgbe/t4_l2t.c +++ b/sys/dev/cxgbe/t4_l2t.c @@ -111,27 +111,34 @@ found: * The write may be synchronous or asynchronous. */ int -t4_write_l2e(struct adapter *sc, struct l2t_entry *e, int sync) +t4_write_l2e(struct l2t_entry *e, int sync) { + struct sge_wrq *wrq; + struct adapter *sc; struct wrq_cookie cookie; struct cpl_l2t_write_req *req; - int idx = e->idx + sc->vres.l2t.start; + int idx; mtx_assert(&e->lock, MA_OWNED); + MPASS(e->wrq != NULL); - req = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*req), 16), &cookie); + wrq = e->wrq; + sc = wrq->adapter; + + req = start_wrq_wr(wrq, howmany(sizeof(*req), 16), &cookie); if (req == NULL) return (ENOMEM); + idx = e->idx + sc->vres.l2t.start; INIT_TP_WR(req, 0); OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, idx | - V_SYNC_WR(sync) | V_TID_QID(sc->sge.fwq.abs_id))); + V_SYNC_WR(sync) | V_TID_QID(e->iqid))); req->params = htons(V_L2T_W_PORT(e->lport) | V_L2T_W_NOREPLY(!sync)); req->l2t_idx = htons(idx); req->vlan = htons(e->vlan); memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac)); - commit_wrq_wr(&sc->sge.mgmtq, req, &cookie); + commit_wrq_wr(wrq, req, &cookie); if (sync && e->state != L2T_STATE_SWITCHING) e->state = L2T_STATE_SYNC_WRITE; @@ -173,9 +180,11 @@ t4_l2t_set_switching(struct adapter *sc, struct l2t_entry *e, uint16_t vlan, e->vlan = vlan; e->lport = port; + e->wrq = &sc->sge.mgmtq; + e->iqid = sc->sge.fwq.abs_id; memcpy(e->dmac, eth_addr, ETHER_ADDR_LEN); mtx_lock(&e->lock); - rc = t4_write_l2e(sc, e, 0); + rc = t4_write_l2e(e, 0); mtx_unlock(&e->lock); return (rc); } @@ -211,7 +220,6 @@ t4_init_l2t(struct adapter *sc, int flags) } sc->l2t = d; - t4_register_cpl_handler(sc, CPL_L2T_WRITE_RPL, do_l2t_write_rpl); return (0); } diff --git a/sys/dev/cxgbe/t4_l2t.h b/sys/dev/cxgbe/t4_l2t.h index c60eef1..2d861dc 100644 --- a/sys/dev/cxgbe/t4_l2t.h +++ b/sys/dev/cxgbe/t4_l2t.h @@ -61,6 +61,8 @@ struct l2t_entry { uint16_t state; /* entry state */ uint16_t idx; /* entry index */ uint32_t addr[4]; /* next hop IP or IPv6 address */ + uint32_t iqid; /* iqid for reply to write_l2e */ + struct sge_wrq *wrq; /* queue to use for write_l2e */ struct ifnet *ifp; /* outgoing interface */ uint16_t smt_idx; /* SMT index */ uint16_t vlan; /* VLAN TCI (id: 0-11, prio: 13-15) */ @@ -90,7 +92,7 @@ struct l2t_entry *t4_alloc_l2e(struct l2t_data *); struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *); int t4_l2t_set_switching(struct adapter *, struct l2t_entry *, uint16_t, uint8_t, uint8_t *); -int t4_write_l2e(struct adapter *, struct l2t_entry *, int); +int t4_write_l2e(struct l2t_entry *, int); int do_l2t_write_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); static inline void diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index eeb1180..247175d 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -458,10 +458,6 @@ static void vi_refresh_stats(struct adapter *, struct vi_info *); static void cxgbe_refresh_stats(struct adapter *, struct port_info *); static void cxgbe_tick(void *); static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); -static int cpl_not_handled(struct sge_iq *, const struct rss_header *, - struct mbuf *); -static int an_not_handled(struct sge_iq *, const struct rsp_ctrl *); -static int fw_msg_not_handled(struct adapter *, const __be64 *); static void t4_sysctls(struct adapter *); static void cxgbe_sysctls(struct port_info *); static int sysctl_int_array(SYSCTL_HANDLER_ARGS); @@ -525,6 +521,8 @@ static int del_filter(struct adapter *, struct t4_filter *); static void clear_filter(struct filter_entry *); static int set_filter_wr(struct adapter *, int); static int del_filter_wr(struct adapter *, int); +static int set_tcb_rpl(struct sge_iq *, const struct rss_header *, + struct mbuf *); static int get_sge_context(struct adapter *, struct t4_sge_context *); static int load_fw(struct adapter *, struct t4_data *); static int read_card_mem(struct adapter *, int, struct t4_mem_range *); @@ -589,11 +587,6 @@ struct { CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); #endif - -/* No easy way to include t4_msg.h before adapter.h so we check this way */ -CTASSERT(nitems(((struct adapter *)0)->cpl_handler) == NUM_CPL_CMDS); -CTASSERT(nitems(((struct adapter *)0)->fw_msg_handler) == NUM_FW6_TYPES); - CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); static int @@ -739,15 +732,6 @@ t4_attach(device_t dev) sc->mbox = sc->pf; memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); - sc->an_handler = an_not_handled; - for (i = 0; i < nitems(sc->cpl_handler); i++) - sc->cpl_handler[i] = cpl_not_handled; - for (i = 0; i < nitems(sc->fw_msg_handler); i++) - sc->fw_msg_handler[i] = fw_msg_not_handled; - t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, t4_filter_rpl); - t4_register_cpl_handler(sc, CPL_TRACE_PKT, t4_trace_pkt); - t4_register_cpl_handler(sc, CPL_T5_TRACE_PKT, t5_trace_pkt); - t4_init_sge_cpl_handlers(sc); /* Prepare the adapter for operation. */ buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); @@ -4500,98 +4484,6 @@ cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) VLAN_SETCOOKIE(vlan, ifp); } -static int -cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) -{ - -#ifdef INVARIANTS - panic("%s: opcode 0x%02x on iq %p with payload %p", - __func__, rss->opcode, iq, m); -#else - log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n", - __func__, rss->opcode, iq, m); - m_freem(m); -#endif - return (EDOOFUS); -} - -int -t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h) -{ - uintptr_t *loc, new; - - if (opcode >= nitems(sc->cpl_handler)) - return (EINVAL); - - new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled; - loc = (uintptr_t *) &sc->cpl_handler[opcode]; - atomic_store_rel_ptr(loc, new); - - return (0); -} - -static int -an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl) -{ - -#ifdef INVARIANTS - panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl); -#else - log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n", - __func__, iq, ctrl); -#endif - return (EDOOFUS); -} - -int -t4_register_an_handler(struct adapter *sc, an_handler_t h) -{ - uintptr_t *loc, new; - - new = h ? (uintptr_t)h : (uintptr_t)an_not_handled; - loc = (uintptr_t *) &sc->an_handler; - atomic_store_rel_ptr(loc, new); - - return (0); -} - -static int -fw_msg_not_handled(struct adapter *sc, const __be64 *rpl) -{ - const struct cpl_fw6_msg *cpl = - __containerof(rpl, struct cpl_fw6_msg, data[0]); - -#ifdef INVARIANTS - panic("%s: fw_msg type %d", __func__, cpl->type); -#else - log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type); -#endif - return (EDOOFUS); -} - -int -t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h) -{ - uintptr_t *loc, new; - - if (type >= nitems(sc->fw_msg_handler)) - return (EINVAL); - - /* - * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL - * handler dispatch table. Reject any attempt to install a handler for - * this subtype. - */ - if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) - return (EINVAL); - - new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled; - loc = (uintptr_t *) &sc->fw_msg_handler[type]; - atomic_store_rel_ptr(loc, new); - - return (0); -} - /* * Should match fw_caps_config_<foo> enums in t4fw_interface.h */ @@ -8262,36 +8154,51 @@ t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, rss->opcode)); + MPASS(iq == &sc->sge.fwq); + MPASS(is_ftid(sc, idx)); + + idx -= sc->tids.ftid_base; + f = &sc->tids.ftid_tab[idx]; + rc = G_COOKIE(rpl->cookie); + + mtx_lock(&sc->tids.ftid_lock); + if (rc == FW_FILTER_WR_FLT_ADDED) { + KASSERT(f->pending, ("%s: filter[%u] isn't pending.", + __func__, idx)); + f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; + f->pending = 0; /* asynchronous setup completed */ + f->valid = 1; + } else { + if (rc != FW_FILTER_WR_FLT_DELETED) { + /* Add or delete failed, display an error */ + log(LOG_ERR, + "filter %u setup failed with error %u\n", + idx, rc); + } - if (is_ftid(sc, idx)) { + clear_filter(f); + sc->tids.ftids_in_use--; + } + wakeup(&sc->tids.ftid_tab); + mtx_unlock(&sc->tids.ftid_lock); - idx -= sc->tids.ftid_base; - f = &sc->tids.ftid_tab[idx]; - rc = G_COOKIE(rpl->cookie); + return (0); +} - mtx_lock(&sc->tids.ftid_lock); - if (rc == FW_FILTER_WR_FLT_ADDED) { - KASSERT(f->pending, ("%s: filter[%u] isn't pending.", - __func__, idx)); - f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; - f->pending = 0; /* asynchronous setup completed */ - f->valid = 1; - } else { - if (rc != FW_FILTER_WR_FLT_DELETED) { - /* Add or delete failed, display an error */ - log(LOG_ERR, - "filter %u setup failed with error %u\n", - idx, rc); - } +static int +set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) +{ - clear_filter(f); - sc->tids.ftids_in_use--; - } - wakeup(&sc->tids.ftid_tab); - mtx_unlock(&sc->tids.ftid_lock); - } + MPASS(iq->set_tcb_rpl != NULL); + return (iq->set_tcb_rpl(iq, rss, m)); +} - return (0); +static int +l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) +{ + + MPASS(iq->l2t_write_rpl != NULL); + return (iq->l2t_write_rpl(iq, rss, m)); } static int @@ -9469,6 +9376,10 @@ mod_event(module_t mod, int cmd, void *arg) sx_xlock(&mlu); if (loaded++ == 0) { t4_sge_modload(); + t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl); + t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl); + t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); + t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); sx_init(&t4_list_lock, "T4/T5 adapters"); SLIST_INIT(&t4_list); #ifdef TCP_OFFLOAD diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c index 4cf3a53..6bf8d22 100644 --- a/sys/dev/cxgbe/t4_sge.c +++ b/sys/dev/cxgbe/t4_sge.c @@ -68,6 +68,7 @@ __FBSDID("$FreeBSD$"); #include "common/t4_regs.h" #include "common/t4_regs_values.h" #include "common/t4_msg.h" +#include "t4_l2t.h" #include "t4_mp_ring.h" #ifdef T4_PKT_TIMESTAMP @@ -253,12 +254,110 @@ static int sysctl_tc(SYSCTL_HANDLER_ARGS); static counter_u64_t extfree_refs; static counter_u64_t extfree_rels; +an_handler_t t4_an_handler; +fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; +cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; + + +static int +an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl) +{ + +#ifdef INVARIANTS + panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl); +#else + log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n", + __func__, iq, ctrl); +#endif + return (EDOOFUS); +} + +int +t4_register_an_handler(an_handler_t h) +{ + uintptr_t *loc, new; + + new = h ? (uintptr_t)h : (uintptr_t)an_not_handled; + loc = (uintptr_t *) &t4_an_handler; + atomic_store_rel_ptr(loc, new); + + return (0); +} + +static int +fw_msg_not_handled(struct adapter *sc, const __be64 *rpl) +{ + const struct cpl_fw6_msg *cpl = + __containerof(rpl, struct cpl_fw6_msg, data[0]); + +#ifdef INVARIANTS + panic("%s: fw_msg type %d", __func__, cpl->type); +#else + log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type); +#endif + return (EDOOFUS); +} + +int +t4_register_fw_msg_handler(int type, fw_msg_handler_t h) +{ + uintptr_t *loc, new; + + if (type >= nitems(t4_fw_msg_handler)) + return (EINVAL); + + /* + * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL + * handler dispatch table. Reject any attempt to install a handler for + * this subtype. + */ + if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) + return (EINVAL); + + new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled; + loc = (uintptr_t *) &t4_fw_msg_handler[type]; + atomic_store_rel_ptr(loc, new); + + return (0); +} + +static int +cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) +{ + +#ifdef INVARIANTS + panic("%s: opcode 0x%02x on iq %p with payload %p", + __func__, rss->opcode, iq, m); +#else + log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n", + __func__, rss->opcode, iq, m); + m_freem(m); +#endif + return (EDOOFUS); +} + +int +t4_register_cpl_handler(int opcode, cpl_handler_t h) +{ + uintptr_t *loc, new; + + if (opcode >= nitems(t4_cpl_handler)) + return (EINVAL); + + new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled; + loc = (uintptr_t *) &t4_cpl_handler[opcode]; + atomic_store_rel_ptr(loc, new); + + return (0); +} + /* * Called on MOD_LOAD. Validates and calculates the SGE tunables. */ void t4_sge_modload(void) { + int i; if (fl_pktshift < 0 || fl_pktshift > 7) { printf("Invalid hw.cxgbe.fl_pktshift value (%d)," @@ -291,6 +390,18 @@ t4_sge_modload(void) extfree_rels = counter_u64_alloc(M_WAITOK); counter_u64_zero(extfree_refs); counter_u64_zero(extfree_rels); + + t4_an_handler = an_not_handled; + for (i = 0; i < nitems(t4_fw_msg_handler); i++) + t4_fw_msg_handler[i] = fw_msg_not_handled; + for (i = 0; i < nitems(t4_cpl_handler); i++) + t4_cpl_handler[i] = cpl_not_handled; + + t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); + t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); + t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); + t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); + t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); } void @@ -312,17 +423,6 @@ t4_sge_extfree_refs(void) return (refs - rels); } -void -t4_init_sge_cpl_handlers(struct adapter *sc) -{ - - t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); - t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); - t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); - t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); - t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); -} - static inline void setup_pad_and_pack_boundaries(struct adapter *sc) { @@ -1316,7 +1416,7 @@ service_iq(struct sge_iq *iq, int budget) KASSERT(d->rss.opcode < NUM_CPL_CMDS, ("%s: bad opcode %02x.", __func__, d->rss.opcode)); - sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0); + t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); break; case X_RSPD_TYPE_INTR: @@ -1338,7 +1438,7 @@ service_iq(struct sge_iq *iq, int budget) * iWARP async notification. */ if (lq >= 1024) { - sc->an_handler(iq, &d->rsp); + t4_an_handler(iq, &d->rsp); break; } @@ -2789,6 +2889,8 @@ alloc_fwq(struct adapter *sc) init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); fwq->flags |= IQ_INTR; /* always */ intr_idx = sc->intr_count > 1 ? 1 : 0; + fwq->set_tcb_rpl = t4_filter_rpl; + fwq->l2t_write_rpl = do_l2t_write_rpl; rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); if (rc != 0) { device_printf(sc->dev, @@ -4674,10 +4776,10 @@ handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) const struct rss_header *rss2; rss2 = (const struct rss_header *)&cpl->data[0]; - return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); + return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); } - return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); + return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); } static int diff --git a/sys/dev/cxgbe/tom/t4_connect.c b/sys/dev/cxgbe/tom/t4_connect.c index c386a83..f550723 100644 --- a/sys/dev/cxgbe/tom/t4_connect.c +++ b/sys/dev/cxgbe/tom/t4_connect.c @@ -261,11 +261,11 @@ calc_opt2a(struct socket *so, struct toepcb *toep) } void -t4_init_connect_cpl_handlers(struct adapter *sc) +t4_init_connect_cpl_handlers(void) { - t4_register_cpl_handler(sc, CPL_ACT_ESTABLISH, do_act_establish); - t4_register_cpl_handler(sc, CPL_ACT_OPEN_RPL, do_act_open_rpl); + t4_register_cpl_handler(CPL_ACT_ESTABLISH, do_act_establish); + t4_register_cpl_handler(CPL_ACT_OPEN_RPL, do_act_open_rpl); } #define DONT_OFFLOAD_ACTIVE_OPEN(x) do { \ diff --git a/sys/dev/cxgbe/tom/t4_cpl_io.c b/sys/dev/cxgbe/tom/t4_cpl_io.c index 387ee51..f7ef499 100644 --- a/sys/dev/cxgbe/tom/t4_cpl_io.c +++ b/sys/dev/cxgbe/tom/t4_cpl_io.c @@ -1679,7 +1679,7 @@ do_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) return (0); } -static int +int do_set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) { struct adapter *sc = iq->adapter; @@ -1693,9 +1693,7 @@ do_set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) KASSERT(opcode == CPL_SET_TCB_RPL, ("%s: unexpected opcode 0x%x", __func__, opcode)); KASSERT(m == NULL, ("%s: wasn't expecting payload", __func__)); - - if (is_ftid(sc, tid)) - return (t4_filter_rpl(iq, rss, m)); /* TCB is a filter */ + MPASS(iq != &sc->sge.fwq); toep = lookup_tid(sc, tid); if (toep->ulp_mode == ULP_MODE_TCPDDP) { @@ -1720,47 +1718,26 @@ do_set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) } void -t4_set_tcb_field(struct adapter *sc, struct toepcb *toep, int ctrl, - uint16_t word, uint64_t mask, uint64_t val) +t4_set_tcb_field(struct adapter *sc, struct sge_wrq *wrq, int tid, + uint16_t word, uint64_t mask, uint64_t val, int reply, int cookie, int iqid) { struct wrqe *wr; struct cpl_set_tcb_field *req; - wr = alloc_wrqe(sizeof(*req), ctrl ? toep->ctrlq : toep->ofld_txq); - if (wr == NULL) { - /* XXX */ - panic("%s: allocation failure.", __func__); - } - req = wrtod(wr); - - INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, toep->tid); - req->reply_ctrl = htobe16(V_NO_REPLY(1) | - V_QUEUENO(toep->ofld_rxq->iq.abs_id)); - req->word_cookie = htobe16(V_WORD(word) | V_COOKIE(0)); - req->mask = htobe64(mask); - req->val = htobe64(val); - - t4_wrq_tx(sc, wr); -} - -void -t4_set_tcb_field_rpl(struct adapter *sc, struct toepcb *toep, int ctrl, - uint16_t word, uint64_t mask, uint64_t val, uint8_t cookie) -{ - struct wrqe *wr; - struct cpl_set_tcb_field *req; + MPASS((cookie & ~M_COOKIE) == 0); + MPASS((iqid & ~M_QUEUENO) == 0); - KASSERT((cookie & ~M_COOKIE) == 0, ("%s: invalid cookie %#x", __func__, - cookie)); - wr = alloc_wrqe(sizeof(*req), ctrl ? toep->ctrlq : toep->ofld_txq); + wr = alloc_wrqe(sizeof(*req), wrq); if (wr == NULL) { /* XXX */ panic("%s: allocation failure.", __func__); } req = wrtod(wr); - INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, toep->tid); - req->reply_ctrl = htobe16(V_QUEUENO(toep->ofld_rxq->iq.abs_id)); + INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, tid); + req->reply_ctrl = htobe16(V_QUEUENO(iqid)); + if (reply == 0) + req->reply_ctrl |= htobe16(F_NO_REPLY); req->word_cookie = htobe16(V_WORD(word) | V_COOKIE(cookie)); req->mask = htobe64(mask); req->val = htobe64(val); @@ -1769,22 +1746,26 @@ t4_set_tcb_field_rpl(struct adapter *sc, struct toepcb *toep, int ctrl, } void -t4_init_cpl_io_handlers(struct adapter *sc) +t4_init_cpl_io_handlers(void) { - t4_register_cpl_handler(sc, CPL_PEER_CLOSE, do_peer_close); - t4_register_cpl_handler(sc, CPL_CLOSE_CON_RPL, do_close_con_rpl); - t4_register_cpl_handler(sc, CPL_ABORT_REQ_RSS, do_abort_req); - t4_register_cpl_handler(sc, CPL_ABORT_RPL_RSS, do_abort_rpl); - t4_register_cpl_handler(sc, CPL_RX_DATA, do_rx_data); - t4_register_cpl_handler(sc, CPL_FW4_ACK, do_fw4_ack); - t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, do_set_tcb_rpl); + t4_register_cpl_handler(CPL_PEER_CLOSE, do_peer_close); + t4_register_cpl_handler(CPL_CLOSE_CON_RPL, do_close_con_rpl); + t4_register_cpl_handler(CPL_ABORT_REQ_RSS, do_abort_req); + t4_register_cpl_handler(CPL_ABORT_RPL_RSS, do_abort_rpl); + t4_register_cpl_handler(CPL_RX_DATA, do_rx_data); + t4_register_cpl_handler(CPL_FW4_ACK, do_fw4_ack); } void -t4_uninit_cpl_io_handlers(struct adapter *sc) +t4_uninit_cpl_io_handlers(void) { - t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, t4_filter_rpl); + t4_register_cpl_handler(CPL_PEER_CLOSE, do_peer_close); + t4_register_cpl_handler(CPL_CLOSE_CON_RPL, do_close_con_rpl); + t4_register_cpl_handler(CPL_ABORT_REQ_RSS, do_abort_req); + t4_register_cpl_handler(CPL_ABORT_RPL_RSS, do_abort_rpl); + t4_register_cpl_handler(CPL_RX_DATA, do_rx_data); + t4_register_cpl_handler(CPL_FW4_ACK, do_fw4_ack); } #endif diff --git a/sys/dev/cxgbe/tom/t4_ddp.c b/sys/dev/cxgbe/tom/t4_ddp.c index bcc8d1d..ff73c8b 100644 --- a/sys/dev/cxgbe/tom/t4_ddp.c +++ b/sys/dev/cxgbe/tom/t4_ddp.c @@ -786,6 +786,8 @@ handle_ddp_close(struct toepcb *toep, struct tcpcb *tp, __be32 rcv_nxt) F_DDP_INVALID_TAG | F_DDP_COLOR_ERR | F_DDP_TID_MISMATCH |\ F_DDP_INVALID_PPOD | F_DDP_HDRCRC_ERR | F_DDP_DATACRC_ERR) +extern cpl_handler_t t4_cpl_handler[]; + static int do_rx_data_ddp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) { @@ -807,7 +809,7 @@ do_rx_data_ddp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) } if (toep->ulp_mode == ULP_MODE_ISCSI) { - sc->cpl_handler[CPL_RX_ISCSI_DDP](iq, rss, m); + t4_cpl_handler[CPL_RX_ISCSI_DDP](iq, rss, m); return (0); } @@ -848,13 +850,14 @@ enable_ddp(struct adapter *sc, struct toepcb *toep) DDP_ASSERT_LOCKED(toep); toep->ddp_flags |= DDP_SC_REQ; - t4_set_tcb_field(sc, toep, 1, W_TCB_RX_DDP_FLAGS, + t4_set_tcb_field(sc, toep->ctrlq, toep->tid, W_TCB_RX_DDP_FLAGS, V_TF_DDP_OFF(1) | V_TF_DDP_INDICATE_OUT(1) | V_TF_DDP_BUF0_INDICATE(1) | V_TF_DDP_BUF1_INDICATE(1) | V_TF_DDP_BUF0_VALID(1) | V_TF_DDP_BUF1_VALID(1), - V_TF_DDP_BUF0_INDICATE(1) | V_TF_DDP_BUF1_INDICATE(1)); - t4_set_tcb_field(sc, toep, 1, W_TCB_T_FLAGS, - V_TF_RCV_COALESCE_ENABLE(1), 0); + V_TF_DDP_BUF0_INDICATE(1) | V_TF_DDP_BUF1_INDICATE(1), 0, 0, + toep->ofld_rxq->iq.abs_id); + t4_set_tcb_field(sc, toep->ctrlq, toep->tid, W_TCB_T_FLAGS, + V_TF_RCV_COALESCE_ENABLE(1), 0, 0, 0, toep->ofld_rxq->iq.abs_id); } static int @@ -1070,9 +1073,6 @@ t4_init_ddp(struct adapter *sc, struct tom_data *td) td->ppod_start = sc->vres.ddp.start; td->ppod_arena = vmem_create("DDP page pods", sc->vres.ddp.start, sc->vres.ddp.size, 1, 32, M_FIRSTFIT | M_NOWAIT); - - t4_register_cpl_handler(sc, CPL_RX_DATA_DDP, do_rx_data_ddp); - t4_register_cpl_handler(sc, CPL_RX_DDP_COMPLETE, do_rx_ddp_complete); } void @@ -1683,8 +1683,10 @@ t4_aio_cancel_active(struct kaiocb *job) */ valid_flag = i == 0 ? V_TF_DDP_BUF0_VALID(1) : V_TF_DDP_BUF1_VALID(1); - t4_set_tcb_field_rpl(sc, toep, 1, W_TCB_RX_DDP_FLAGS, - valid_flag, 0, i + DDP_BUF0_INVALIDATED); + t4_set_tcb_field(sc, toep->ctrlq, toep->tid, + W_TCB_RX_DDP_FLAGS, valid_flag, 0, 1, + i + DDP_BUF0_INVALIDATED, + toep->ofld_rxq->iq.abs_id); toep->db[i].cancel_pending = 1; CTR2(KTR_CXGBE, "%s: request %p marked pending", __func__, job); @@ -1756,6 +1758,8 @@ int t4_ddp_mod_load(void) { + t4_register_cpl_handler(CPL_RX_DATA_DDP, do_rx_data_ddp); + t4_register_cpl_handler(CPL_RX_DDP_COMPLETE, do_rx_ddp_complete); TAILQ_INIT(&ddp_orphan_pagesets); mtx_init(&ddp_orphan_pagesets_lock, "ddp orphans", NULL, MTX_DEF); TASK_INIT(&ddp_orphan_task, 0, ddp_free_orphan_pagesets, NULL); @@ -1769,5 +1773,7 @@ t4_ddp_mod_unload(void) taskqueue_drain(taskqueue_thread, &ddp_orphan_task); MPASS(TAILQ_EMPTY(&ddp_orphan_pagesets)); mtx_destroy(&ddp_orphan_pagesets_lock); + t4_register_cpl_handler(CPL_RX_DATA_DDP, NULL); + t4_register_cpl_handler(CPL_RX_DDP_COMPLETE, NULL); } #endif diff --git a/sys/dev/cxgbe/tom/t4_listen.c b/sys/dev/cxgbe/tom/t4_listen.c index 22f734a..4a1a062 100644 --- a/sys/dev/cxgbe/tom/t4_listen.c +++ b/sys/dev/cxgbe/tom/t4_listen.c @@ -1589,12 +1589,12 @@ reset: } void -t4_init_listen_cpl_handlers(struct adapter *sc) +t4_init_listen_cpl_handlers(void) { - t4_register_cpl_handler(sc, CPL_PASS_OPEN_RPL, do_pass_open_rpl); - t4_register_cpl_handler(sc, CPL_CLOSE_LISTSRV_RPL, do_close_server_rpl); - t4_register_cpl_handler(sc, CPL_PASS_ACCEPT_REQ, do_pass_accept_req); - t4_register_cpl_handler(sc, CPL_PASS_ESTABLISH, do_pass_establish); + t4_register_cpl_handler(CPL_PASS_OPEN_RPL, do_pass_open_rpl); + t4_register_cpl_handler(CPL_CLOSE_LISTSRV_RPL, do_close_server_rpl); + t4_register_cpl_handler(CPL_PASS_ACCEPT_REQ, do_pass_accept_req); + t4_register_cpl_handler(CPL_PASS_ESTABLISH, do_pass_establish); } #endif diff --git a/sys/dev/cxgbe/tom/t4_tom.c b/sys/dev/cxgbe/tom/t4_tom.c index 452c47e..2a8082e 100644 --- a/sys/dev/cxgbe/tom/t4_tom.c +++ b/sys/dev/cxgbe/tom/t4_tom.c @@ -381,8 +381,9 @@ t4_ctloutput(struct toedev *tod, struct tcpcb *tp, int dir, int name) switch (name) { case TCP_NODELAY: - t4_set_tcb_field(sc, toep, 1, W_TCB_T_FLAGS, V_TF_NAGLE(1), - V_TF_NAGLE(tp->t_flags & TF_NODELAY ? 0 : 1)); + t4_set_tcb_field(sc, toep->ctrlq, toep->tid, W_TCB_T_FLAGS, + V_TF_NAGLE(1), V_TF_NAGLE(tp->t_flags & TF_NODELAY ? 0 : 1), + 0, 0, toep->ofld_rxq->iq.abs_id); break; default: break; @@ -930,8 +931,6 @@ free_tom_data(struct adapter *sc, struct tom_data *td) KASSERT(td->lctx_count == 0, ("%s: lctx hash table is not empty.", __func__)); - t4_uninit_l2t_cpl_handlers(sc); - t4_uninit_cpl_io_handlers(sc); t4_uninit_ddp(sc, td); destroy_clip_table(sc, td); @@ -997,7 +996,8 @@ t4_tom_activate(struct adapter *sc) struct tom_data *td; struct toedev *tod; struct vi_info *vi; - int i, rc, v; + struct sge_ofld_rxq *ofld_rxq; + int i, j, rc, v; ASSERT_SYNCHRONIZED_OP(sc); @@ -1031,12 +1031,6 @@ t4_tom_activate(struct adapter *sc) /* CLIP table for IPv6 offload */ init_clip_table(sc, td); - /* CPL handlers */ - t4_init_connect_cpl_handlers(sc); - t4_init_l2t_cpl_handlers(sc); - t4_init_listen_cpl_handlers(sc); - t4_init_cpl_io_handlers(sc); - /* toedev ops */ tod = &td->tod; init_toedev(tod); @@ -1059,6 +1053,10 @@ t4_tom_activate(struct adapter *sc) for_each_port(sc, i) { for_each_vi(sc->port[i], v, vi) { TOEDEV(vi->ifp) = &td->tod; + for_each_ofld_rxq(vi, j, ofld_rxq) { + ofld_rxq->iq.set_tcb_rpl = do_set_tcb_rpl; + ofld_rxq->iq.l2t_write_rpl = do_l2t_write_rpl2; + } } } @@ -1127,6 +1125,11 @@ t4_tom_mod_load(void) int rc; struct protosw *tcp_protosw, *tcp6_protosw; + /* CPL handlers */ + t4_init_connect_cpl_handlers(); + t4_init_listen_cpl_handlers(); + t4_init_cpl_io_handlers(); + rc = t4_ddp_mod_load(); if (rc != 0) return (rc); diff --git a/sys/dev/cxgbe/tom/t4_tom.h b/sys/dev/cxgbe/tom/t4_tom.h index 09238a4..f114a3d 100644 --- a/sys/dev/cxgbe/tom/t4_tom.h +++ b/sys/dev/cxgbe/tom/t4_tom.h @@ -294,13 +294,13 @@ struct clip_entry *hold_lip(struct tom_data *, struct in6_addr *); void release_lip(struct tom_data *, struct clip_entry *); /* t4_connect.c */ -void t4_init_connect_cpl_handlers(struct adapter *); +void t4_init_connect_cpl_handlers(void); int t4_connect(struct toedev *, struct socket *, struct rtentry *, struct sockaddr *); void act_open_failure_cleanup(struct adapter *, u_int, u_int); /* t4_listen.c */ -void t4_init_listen_cpl_handlers(struct adapter *); +void t4_init_listen_cpl_handlers(void); int t4_listen_start(struct toedev *, struct tcpcb *); int t4_listen_stop(struct toedev *, struct tcpcb *); void t4_syncache_added(struct toedev *, void *); @@ -313,8 +313,8 @@ int do_abort_rpl_synqe(struct sge_iq *, const struct rss_header *, void t4_offload_socket(struct toedev *, void *, struct socket *); /* t4_cpl_io.c */ -void t4_init_cpl_io_handlers(struct adapter *); -void t4_uninit_cpl_io_handlers(struct adapter *); +void t4_init_cpl_io_handlers(void); +void t4_uninit_cpl_io_handlers(void); void send_abort_rpl(struct adapter *, struct sge_wrq *, int , int); void send_flowc_wr(struct toepcb *, struct flowc_tx_params *); void send_reset(struct adapter *, struct toepcb *, uint32_t); @@ -324,12 +324,11 @@ void t4_rcvd_locked(struct toedev *, struct tcpcb *); int t4_tod_output(struct toedev *, struct tcpcb *); int t4_send_fin(struct toedev *, struct tcpcb *); int t4_send_rst(struct toedev *, struct tcpcb *); -void t4_set_tcb_field(struct adapter *, struct toepcb *, int, uint16_t, - uint64_t, uint64_t); -void t4_set_tcb_field_rpl(struct adapter *, struct toepcb *, int, uint16_t, - uint64_t, uint64_t, uint8_t); +void t4_set_tcb_field(struct adapter *, struct sge_wrq *, int, uint16_t, + uint64_t, uint64_t, int, int, int); void t4_push_frames(struct adapter *sc, struct toepcb *toep, int drop); void t4_push_pdus(struct adapter *sc, struct toepcb *toep, int drop); +int do_set_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); /* t4_ddp.c */ void t4_init_ddp(struct adapter *, struct tom_data *); diff --git a/sys/dev/cxgbe/tom/t4_tom_l2t.c b/sys/dev/cxgbe/tom/t4_tom_l2t.c index 8aadf34..f89df02 100644 --- a/sys/dev/cxgbe/tom/t4_tom_l2t.c +++ b/sys/dev/cxgbe/tom/t4_tom_l2t.c @@ -219,7 +219,7 @@ update_entry(struct adapter *sc, struct l2t_entry *e, uint8_t *lladdr, memcpy(e->dmac, lladdr, ETHER_ADDR_LEN); e->vlan = vtag; - t4_write_l2e(sc, e, 1); + t4_write_l2e(e, 1); } e->state = L2T_STATE_VALID; } @@ -309,19 +309,7 @@ again: return (0); } -/* - * Called when an L2T entry has no more users. The entry is left in the hash - * table since it is likely to be reused but we also bump nfree to indicate - * that the entry can be reallocated for a different neighbor. We also drop - * the existing neighbor reference in case the neighbor is going away and is - * waiting on our reference. - * - * Because entries can be reallocated to other neighbors once their ref count - * drops to 0 we need to take the entry's lock to avoid races with a new - * incarnation. - */ - -static int +int do_l2t_write_rpl2(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) { @@ -329,11 +317,13 @@ do_l2t_write_rpl2(struct sge_iq *iq, const struct rss_header *rss, const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); unsigned int tid = GET_TID(rpl); unsigned int idx = tid % L2T_SIZE; - int rc; - rc = do_l2t_write_rpl(iq, rss, m); - if (rc != 0) - return (rc); + if (__predict_false(rpl->status != CPL_ERR_NONE)) { + log(LOG_ERR, + "Unexpected L2T_WRITE_RPL (%u) for entry at hw_idx %u\n", + rpl->status, idx); + return (EINVAL); + } if (tid & F_SYNC_WR) { struct l2t_entry *e = &sc->l2t->l2tab[idx - sc->vres.l2t.start]; @@ -349,20 +339,6 @@ do_l2t_write_rpl2(struct sge_iq *iq, const struct rss_header *rss, return (0); } -void -t4_init_l2t_cpl_handlers(struct adapter *sc) -{ - - t4_register_cpl_handler(sc, CPL_L2T_WRITE_RPL, do_l2t_write_rpl2); -} - -void -t4_uninit_l2t_cpl_handlers(struct adapter *sc) -{ - - t4_register_cpl_handler(sc, CPL_L2T_WRITE_RPL, do_l2t_write_rpl); -} - /* * The TOE wants an L2 table entry that it can use to reach the next hop over * the specified port. Produce such an entry - create one if needed. @@ -374,7 +350,8 @@ struct l2t_entry * t4_l2t_get(struct port_info *pi, struct ifnet *ifp, struct sockaddr *sa) { struct l2t_entry *e; - struct l2t_data *d = pi->adapter->l2t; + struct adapter *sc = pi->adapter; + struct l2t_data *d = sc->l2t; u_int hash, smt_idx = pi->port_id; KASSERT(sa->sa_family == AF_INET || sa->sa_family == AF_INET6, @@ -409,6 +386,8 @@ t4_l2t_get(struct port_info *pi, struct ifnet *ifp, struct sockaddr *sa) e->smt_idx = smt_idx; e->hash = hash; e->lport = pi->lport; + e->wrq = &sc->sge.ctrlq[pi->port_id]; + e->iqid = sc->sge.ofld_rxq[pi->vi[0].first_ofld_rxq].iq.abs_id; atomic_store_rel_int(&e->refcnt, 1); #ifdef VLAN_TAG if (ifp->if_type == IFT_L2VLAN) diff --git a/sys/dev/cxgbe/tom/t4_tom_l2t.h b/sys/dev/cxgbe/tom/t4_tom_l2t.h index 3d76735..9a7fb39 100644 --- a/sys/dev/cxgbe/tom/t4_tom_l2t.h +++ b/sys/dev/cxgbe/tom/t4_tom_l2t.h @@ -37,8 +37,8 @@ struct l2t_entry *t4_l2t_get(struct port_info *, struct ifnet *, struct sockaddr *); void t4_l2_update(struct toedev *, struct ifnet *, struct sockaddr *, uint8_t *, uint16_t); -void t4_init_l2t_cpl_handlers(struct adapter *); -void t4_uninit_l2t_cpl_handlers(struct adapter *); +int do_l2t_write_rpl2(struct sge_iq *, const struct rss_header *, + struct mbuf *); static inline int t4_l2t_send(struct adapter *sc, struct wrqe *wr, struct l2t_entry *e) diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index 14f5463..ddd651d 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -1214,7 +1214,8 @@ em_ioctl(if_t ifp, u_long command, caddr_t data) if_setmtu(ifp, ifr->ifr_mtu); adapter->hw.mac.max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; - em_init_locked(adapter); + if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) + em_init_locked(adapter); EM_CORE_UNLOCK(adapter); break; } diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c index 83e1e83..ef5256f 100644 --- a/sys/dev/e1000/if_igb.c +++ b/sys/dev/e1000/if_igb.c @@ -1106,7 +1106,8 @@ igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data) ifp->if_mtu = ifr->ifr_mtu; adapter->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; - igb_init_locked(adapter); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) + igb_init_locked(adapter); IGB_CORE_UNLOCK(adapter); break; } diff --git a/sys/dev/e1000/if_lem.c b/sys/dev/e1000/if_lem.c index 50b2cb0..55b8310 100644 --- a/sys/dev/e1000/if_lem.c +++ b/sys/dev/e1000/if_lem.c @@ -1053,7 +1053,8 @@ lem_ioctl(if_t ifp, u_long command, caddr_t data) if_setmtu(ifp, ifr->ifr_mtu); adapter->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; - lem_init_locked(adapter); + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING)) + lem_init_locked(adapter); EM_CORE_UNLOCK(adapter); break; } diff --git a/sys/dev/ioat/ioat.c b/sys/dev/ioat/ioat.c index 1a10c25..e3deed8 100644 --- a/sys/dev/ioat/ioat.c +++ b/sys/dev/ioat/ioat.c @@ -61,8 +61,8 @@ __FBSDID("$FreeBSD$"); #ifndef BUS_SPACE_MAXADDR_40BIT #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL #endif -#define IOAT_INTR_TIMO (hz / 10) #define IOAT_REFLK (&ioat->submit_lock) +#define IOAT_SHRINK_PERIOD (10 * hz) static int ioat_probe(device_t device); static int ioat_attach(device_t device); @@ -96,7 +96,8 @@ static int ring_grow(struct ioat_softc *, uint32_t oldorder, static int ring_shrink(struct ioat_softc *, uint32_t oldorder, struct ioat_descriptor **); static void ioat_halted_debug(struct ioat_softc *, uint32_t); -static void ioat_timer_callback(void *arg); +static void ioat_poll_timer_callback(void *arg); +static void ioat_shrink_timer_callback(void *arg); static void dump_descriptor(void *hw_desc); static void ioat_submit_single(struct ioat_softc *ioat); static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, @@ -325,6 +326,7 @@ ioat_detach(device_t device) ioat->quiescing = TRUE; ioat->destroying = TRUE; wakeup(&ioat->quiescing); + wakeup(&ioat->resetting); ioat_channel[ioat->chan_idx] = NULL; @@ -332,7 +334,8 @@ ioat_detach(device_t device) mtx_unlock(IOAT_REFLK); ioat_teardown_intr(ioat); - callout_drain(&ioat->timer); + callout_drain(&ioat->poll_timer); + callout_drain(&ioat->shrink_timer); pci_disable_busmaster(device); @@ -373,12 +376,32 @@ ioat_teardown_intr(struct ioat_softc *ioat) static int ioat_start_channel(struct ioat_softc *ioat) { + struct ioat_dma_hw_descriptor *hw_desc; + struct ioat_descriptor *desc; + struct bus_dmadesc *dmadesc; uint64_t status; uint32_t chanerr; int i; ioat_acquire(&ioat->dmaengine); - ioat_null(&ioat->dmaengine, NULL, NULL, 0); + + /* Submit 'NULL' operation manually to avoid quiescing flag */ + desc = ioat_get_ring_entry(ioat, ioat->head); + dmadesc = &desc->bus_dmadesc; + hw_desc = desc->u.dma; + + dmadesc->callback_fn = NULL; + dmadesc->callback_arg = NULL; + + hw_desc->u.control_raw = 0; + hw_desc->u.control_generic.op = IOAT_OP_COPY; + hw_desc->u.control_generic.completion_update = 1; + hw_desc->size = 8; + hw_desc->src_addr = 0; + hw_desc->dest_addr = 0; + hw_desc->u.control.null = 1; + + ioat_submit_single(ioat); ioat_release(&ioat->dmaengine); for (i = 0; i < 100; i++) { @@ -428,7 +451,8 @@ ioat3_attach(device_t device) mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); - callout_init(&ioat->timer, 1); + callout_init(&ioat->poll_timer, 1); + callout_init(&ioat->shrink_timer, 1); TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); /* Establish lock order for Witness */ @@ -492,6 +516,7 @@ ioat3_attach(device_t device) ioat->head = ioat->hw_head = 0; ioat->tail = 0; ioat->last_seen = 0; + *ioat->comp_update = 0; return (0); } @@ -634,16 +659,27 @@ ioat_process_events(struct ioat_softc *ioat) struct bus_dmadesc *dmadesc; uint64_t comp_update, status; uint32_t completed, chanerr; + boolean_t pending; int error; + CTR0(KTR_IOAT, __func__); + mtx_lock(&ioat->cleanup_lock); + /* + * Don't run while the hardware is being reset. Reset is responsible + * for blocking new work and draining & completing existing work, so + * there is nothing to do until new work is queued after reset anyway. + */ + if (ioat->resetting_cleanup) { + mtx_unlock(&ioat->cleanup_lock); + return; + } + completed = 0; comp_update = *ioat->comp_update; status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; - CTR0(KTR_IOAT, __func__); - if (status == ioat->last_seen) { /* * If we landed in process_events and nothing has been @@ -668,19 +704,33 @@ ioat_process_events(struct ioat_softc *ioat) } ioat->last_seen = desc->hw_desc_bus_addr; - - if (ioat->head == ioat->tail) { - ioat->is_completion_pending = FALSE; - callout_reset(&ioat->timer, IOAT_INTR_TIMO, - ioat_timer_callback, ioat); - } - ioat->stats.descriptors_processed += completed; out: ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); + + /* Perform a racy check first; only take the locks if it passes. */ + pending = (ioat_get_active(ioat) != 0); + if (!pending && ioat->is_completion_pending) { + mtx_unlock(&ioat->cleanup_lock); + mtx_lock(&ioat->submit_lock); + mtx_lock(&ioat->cleanup_lock); + + pending = (ioat_get_active(ioat) != 0); + if (!pending && ioat->is_completion_pending) { + ioat->is_completion_pending = FALSE; + callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, + ioat_shrink_timer_callback, ioat); + callout_stop(&ioat->poll_timer); + } + mtx_unlock(&ioat->submit_lock); + } mtx_unlock(&ioat->cleanup_lock); + if (pending) + callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, + ioat); + if (completed != 0) { ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); wakeup(&ioat->tail); @@ -1602,7 +1652,18 @@ ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) } static void -ioat_timer_callback(void *arg) +ioat_poll_timer_callback(void *arg) +{ + struct ioat_softc *ioat; + + ioat = arg; + ioat_log_message(3, "%s\n", __func__); + + ioat_process_events(ioat); +} + +static void +ioat_shrink_timer_callback(void *arg) { struct ioat_descriptor **newring; struct ioat_softc *ioat; @@ -1611,13 +1672,15 @@ ioat_timer_callback(void *arg) ioat = arg; ioat_log_message(1, "%s\n", __func__); - if (ioat->is_completion_pending) { - ioat_process_events(ioat); + /* Slowly scale the ring down if idle. */ + mtx_lock(&ioat->submit_lock); + + /* Don't run while the hardware is being reset. */ + if (ioat->resetting) { + mtx_unlock(&ioat->submit_lock); return; } - /* Slowly scale the ring down if idle. */ - mtx_lock(&ioat->submit_lock); order = ioat->ring_size_order; if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { mtx_unlock(&ioat->submit_lock); @@ -1641,8 +1704,8 @@ ioat_timer_callback(void *arg) out: if (ioat->ring_size_order > IOAT_MIN_ORDER) - callout_reset(&ioat->timer, 10 * hz, - ioat_timer_callback, ioat); + callout_reset(&ioat->poll_timer, IOAT_SHRINK_PERIOD, + ioat_shrink_timer_callback, ioat); } /* @@ -1658,8 +1721,9 @@ ioat_submit_single(struct ioat_softc *ioat) if (!ioat->is_completion_pending) { ioat->is_completion_pending = TRUE; - callout_reset(&ioat->timer, IOAT_INTR_TIMO, - ioat_timer_callback, ioat); + callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, + ioat); + callout_stop(&ioat->shrink_timer); } ioat->stats.descriptors_submitted++; @@ -1674,10 +1738,26 @@ ioat_reset_hw(struct ioat_softc *ioat) int error; mtx_lock(IOAT_REFLK); + while (ioat->resetting && !ioat->destroying) + msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); + if (ioat->destroying) { + mtx_unlock(IOAT_REFLK); + return (ENXIO); + } + ioat->resetting = TRUE; + ioat->quiescing = TRUE; ioat_drain_locked(ioat); mtx_unlock(IOAT_REFLK); + /* + * Suspend ioat_process_events while the hardware and softc are in an + * indeterminate state. + */ + mtx_lock(&ioat->cleanup_lock); + ioat->resetting_cleanup = TRUE; + mtx_unlock(&ioat->cleanup_lock); + status = ioat_get_chansts(ioat); if (is_ioat_active(status) || is_ioat_idle(status)) ioat_suspend(ioat); @@ -1759,6 +1839,7 @@ ioat_reset_hw(struct ioat_softc *ioat) */ ioat->tail = ioat->head = ioat->hw_head = 0; ioat->last_seen = 0; + *ioat->comp_update = 0; ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); @@ -1766,13 +1847,27 @@ ioat_reset_hw(struct ioat_softc *ioat) error = 0; out: + /* + * Resume completions now that ring state is consistent. + * ioat_start_channel will add a pending completion and if we are still + * blocking completions, we may livelock. + */ + mtx_lock(&ioat->cleanup_lock); + ioat->resetting_cleanup = FALSE; + mtx_unlock(&ioat->cleanup_lock); + + /* Enqueues a null operation and ensures it completes. */ + if (error == 0) + error = ioat_start_channel(ioat); + + /* Unblock submission of new work */ mtx_lock(IOAT_REFLK); ioat->quiescing = FALSE; wakeup(&ioat->quiescing); - mtx_unlock(IOAT_REFLK); - if (error == 0) - error = ioat_start_channel(ioat); + ioat->resetting = FALSE; + wakeup(&ioat->resetting); + mtx_unlock(IOAT_REFLK); return (error); } @@ -2126,12 +2221,19 @@ DB_SHOW_COMMAND(ioat, db_show_ioat) db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); - db_printf(" timer:\n"); - db_printf(" c_time: %ju\n", (uintmax_t)sc->timer.c_time); - db_printf(" c_arg: %p\n", sc->timer.c_arg); - db_printf(" c_func: %p\n", sc->timer.c_func); - db_printf(" c_lock: %p\n", sc->timer.c_lock); - db_printf(" c_flags: 0x%x\n", (unsigned)sc->timer.c_flags); + db_printf(" poll_timer:\n"); + db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); + db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); + db_printf(" c_func: %p\n", sc->poll_timer.c_func); + db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); + db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); + + db_printf(" shrink_timer:\n"); + db_printf(" c_time: %ju\n", (uintmax_t)sc->shrink_timer.c_time); + db_printf(" c_arg: %p\n", sc->shrink_timer.c_arg); + db_printf(" c_func: %p\n", sc->shrink_timer.c_func); + db_printf(" c_lock: %p\n", sc->shrink_timer.c_lock); + db_printf(" c_flags: 0x%x\n", (unsigned)sc->shrink_timer.c_flags); db_printf(" quiescing: %d\n", (int)sc->quiescing); db_printf(" destroying: %d\n", (int)sc->destroying); @@ -2140,6 +2242,7 @@ DB_SHOW_COMMAND(ioat, db_show_ioat) db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); + db_printf(" resetting: %d\n", (int)sc->resetting); db_printf(" head: %u\n", sc->head); db_printf(" tail: %u\n", sc->tail); diff --git a/sys/dev/ioat/ioat_internal.h b/sys/dev/ioat/ioat_internal.h index 9d0708d..0879a0e 100644 --- a/sys/dev/ioat/ioat_internal.h +++ b/sys/dev/ioat/ioat_internal.h @@ -480,16 +480,19 @@ struct ioat_softc { uint64_t *comp_update; bus_addr_t comp_update_bus_addr; - struct callout timer; + struct callout poll_timer; + struct callout shrink_timer; struct task reset_task; boolean_t quiescing; boolean_t destroying; boolean_t is_resize_pending; - boolean_t is_completion_pending; + boolean_t is_completion_pending; /* submit_lock */ boolean_t is_reset_pending; boolean_t is_channel_running; boolean_t intrdelay_supported; + boolean_t resetting; /* submit_lock */ + boolean_t resetting_cleanup; /* cleanup_lock */ uint32_t head; uint32_t tail; diff --git a/sys/dev/isci/scil/sati_passthrough.c b/sys/dev/isci/scil/sati_passthrough.c index a083bd5..88ff0bc 100644 --- a/sys/dev/isci/scil/sati_passthrough.c +++ b/sys/dev/isci/scil/sati_passthrough.c @@ -230,9 +230,9 @@ void sati_passthrough_construct_sense( // Command specific section sati_set_sense_data_byte(sense_data, sense_len, 8, (PASSTHROUGH_CDB_EXTEND(cdb) << 7) | (sector_count_upper << 6) | (lba_upper << 5)); - sati_set_sense_data_byte(sense_data, sense_len, 9, sati_get_ata_lba_high(register_fis)); + sati_set_sense_data_byte(sense_data, sense_len, 9, sati_get_ata_lba_low(register_fis)); sati_set_sense_data_byte(sense_data, sense_len, 10, sati_get_ata_lba_mid(register_fis)); - sati_set_sense_data_byte(sense_data, sense_len, 11, sati_get_ata_lba_low(register_fis)); + sati_set_sense_data_byte(sense_data, sense_len, 11, sati_get_ata_lba_high(register_fis)); sequence->is_sense_response_set = TRUE; } diff --git a/sys/dev/isci/scil/sati_util.c b/sys/dev/isci/scil/sati_util.c index 90b9bfa..e037c5c 100644 --- a/sys/dev/isci/scil/sati_util.c +++ b/sys/dev/isci/scil/sati_util.c @@ -932,7 +932,7 @@ void sati_scsi_fixed_sense_data_construct( sati_set_sense_data_byte(sense_data, sense_len, 4, 0); sati_set_sense_data_byte(sense_data, sense_len, 5, 0); sati_set_sense_data_byte(sense_data, sense_len, 6, 0); - sati_set_sense_data_byte(sense_data, sense_len, 7, 0); + sati_set_sense_data_byte(sense_data, sense_len, 7, (sense_len < 18 ? sense_len - 1 : 17) - 7); sati_set_sense_data_byte(sense_data, sense_len, 8, 0); sati_set_sense_data_byte(sense_data, sense_len, 9, 0); sati_set_sense_data_byte(sense_data, sense_len, 10, 0); @@ -981,7 +981,7 @@ void sati_scsi_common_fixed_sense_construct( //Bytes 3, 4, 5, 6 are set in read_error_sense_construct functions - sati_set_sense_data_byte(sense_data, sense_len, 7, 0); + sati_set_sense_data_byte(sense_data, sense_len, 7, (sense_len < 18 ? sense_len - 1 : 17) - 7); sati_set_sense_data_byte(sense_data, sense_len, 8, 0); sati_set_sense_data_byte(sense_data, sense_len, 9, 0); sati_set_sense_data_byte(sense_data, sense_len, 10, 0); diff --git a/sys/dev/ixgb/if_ixgb.c b/sys/dev/ixgb/if_ixgb.c index 4ef4929..4db272c 100644 --- a/sys/dev/ixgb/if_ixgb.c +++ b/sys/dev/ixgb/if_ixgb.c @@ -539,7 +539,8 @@ ixgb_ioctl(struct ifnet * ifp, IOCTL_CMD_TYPE command, caddr_t data) adapter->hw.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; - ixgb_init_locked(adapter); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + ixgb_init_locked(adapter); IXGB_UNLOCK(adapter); } break; diff --git a/sys/dev/ixgbe/if_ix.c b/sys/dev/ixgbe/if_ix.c index ddee699..cf2231d 100644 --- a/sys/dev/ixgbe/if_ix.c +++ b/sys/dev/ixgbe/if_ix.c @@ -893,7 +893,8 @@ ixgbe_ioctl(struct ifnet * ifp, u_long command, caddr_t data) ifp->if_mtu = ifr->ifr_mtu; adapter->max_frame_size = ifp->if_mtu + IXGBE_MTU_HDR; - ixgbe_init_locked(adapter); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + ixgbe_init_locked(adapter); #ifdef PCI_IOV ixgbe_recalculate_max_frame(adapter); #endif diff --git a/sys/dev/ixgbe/if_ixv.c b/sys/dev/ixgbe/if_ixv.c index 13c2bef..80fb1b3 100644 --- a/sys/dev/ixgbe/if_ixv.c +++ b/sys/dev/ixgbe/if_ixv.c @@ -578,7 +578,8 @@ ixv_ioctl(struct ifnet * ifp, u_long command, caddr_t data) ifp->if_mtu = ifr->ifr_mtu; adapter->max_frame_size = ifp->if_mtu + IXGBE_MTU_HDR; - ixv_init_locked(adapter); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + ixv_init_locked(adapter); IXGBE_CORE_UNLOCK(adapter); } break; diff --git a/sys/dev/ixl/if_ixl.c b/sys/dev/ixl/if_ixl.c index d759cfd..8e9ba80 100644 --- a/sys/dev/ixl/if_ixl.c +++ b/sys/dev/ixl/if_ixl.c @@ -980,7 +980,8 @@ ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data) vsi->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN; - ixl_init_locked(pf); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + ixl_init_locked(pf); IXL_PF_UNLOCK(pf); } break; diff --git a/sys/dev/ixl/if_ixlv.c b/sys/dev/ixl/if_ixlv.c index 9e5242c..9be8a36 100644 --- a/sys/dev/ixl/if_ixlv.c +++ b/sys/dev/ixl/if_ixlv.c @@ -676,7 +676,8 @@ ixlv_ioctl(struct ifnet *ifp, u_long command, caddr_t data) vsi->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN; - ixlv_init_locked(sc); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + ixlv_init_locked(sc); } mtx_unlock(&sc->mtx); break; diff --git a/sys/dev/usb/controller/dwc_otg.c b/sys/dev/usb/controller/dwc_otg.c index f28c2a6..5560f07 100644 --- a/sys/dev/usb/controller/dwc_otg.c +++ b/sys/dev/usb/controller/dwc_otg.c @@ -93,17 +93,6 @@ #define DWC_OTG_PC2UDEV(pc) \ (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) -#define DWC_OTG_MSK_GINT_ENABLED \ - (GINTMSK_ENUMDONEMSK | \ - GINTMSK_USBRSTMSK | \ - GINTMSK_USBSUSPMSK | \ - GINTMSK_IEPINTMSK | \ - GINTMSK_SESSREQINTMSK | \ - GINTMSK_RXFLVLMSK | \ - GINTMSK_HCHINTMSK | \ - GINTMSK_OTGINTMSK | \ - GINTMSK_PRTINTMSK) - #define DWC_OTG_MSK_GINT_THREAD_IRQ \ (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ @@ -376,6 +365,11 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) /* enable all host channel interrupts */ DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, (1U << sc->sc_host_ch_max) - 1U); + + /* enable proper host channel interrupts */ + sc->sc_irq_mask |= GINTMSK_HCHINTMSK; + sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK; + DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } if (mode == DWC_MODE_DEVICE) { @@ -436,6 +430,11 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) pf->usb.max_in_frame_size, pf->usb.max_out_frame_size); } + + /* enable proper device channel interrupts */ + sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK; + sc->sc_irq_mask |= GINTMSK_IEPINTMSK; + DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); } /* reset RX FIFO */ @@ -2870,10 +2869,13 @@ dwc_otg_filter_interrupt(void *arg) for (x = 0; x != sc->sc_dev_in_ep_max; x++) { temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); - if (temp & DIEPMSK_XFERCOMPLMSK) { - DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), - DIEPMSK_XFERCOMPLMSK); - } + /* + * NOTE: Need to clear all interrupt bits, + * because some appears to be unmaskable and + * can cause an interrupt loop: + */ + if (temp != 0) + DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp); } } @@ -3980,7 +3982,7 @@ dwc_otg_init(struct dwc_otg_softc *sc) } /* enable interrupts */ - sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; + sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ; DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { diff --git a/sys/dev/usb/controller/xhci.h b/sys/dev/usb/controller/xhci.h index ee5b4b0..e8bc9ad 100644 --- a/sys/dev/usb/controller/xhci.h +++ b/sys/dev/usb/controller/xhci.h @@ -30,7 +30,7 @@ #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ -#define XHCI_MAX_SCRATCHPADS 1024 +#define XHCI_MAX_SCRATCHPADS 256 /* theoretical max is 1023 */ #define XHCI_MAX_EVENTS (16 * 13) #define XHCI_MAX_COMMANDS (16 * 1) #define XHCI_MAX_RSEG 1 diff --git a/sys/fs/cuse/cuse.c b/sys/fs/cuse/cuse.c index 075b2d9..6035f8d 100644 --- a/sys/fs/cuse/cuse.c +++ b/sys/fs/cuse/cuse.c @@ -1656,7 +1656,7 @@ cuse_client_ioctl(struct cdev *dev, unsigned long cmd, cuse_cmd_lock(pccmd); - if (cmd & IOC_IN) + if (cmd & (IOC_IN | IOC_VOID)) memcpy(pcc->ioctl_buffer, data, len); /* diff --git a/sys/i386/conf/GENERIC b/sys/i386/conf/GENERIC index aefc507..da5e46d 100644 --- a/sys/i386/conf/GENERIC +++ b/sys/i386/conf/GENERIC @@ -81,15 +81,6 @@ options RCTL # Resource limits # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. -# For full debugger support use (turn off in stable branch): -options DDB # Support DDB. -options GDB # Support remote GDB. -options DEADLKRES # Enable the deadlock resolver -options INVARIANTS # Enable calls of extra sanity checking -options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS -options WITNESS # Enable checks to detect deadlocks and cycles -options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed -options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones # To make an SMP kernel, the next two lines are needed options SMP # Symmetric MultiProcessor Kernel diff --git a/sys/i386/include/counter.h b/sys/i386/include/counter.h index 01b09bb..86f3ec9 100644 --- a/sys/i386/include/counter.h +++ b/sys/i386/include/counter.h @@ -98,13 +98,13 @@ counter_u64_fetch_inline(uint64_t *p) * critical section as well. */ critical_enter(); - for (i = 0; i < mp_ncpus; i++) { + CPU_FOREACH(i) { res += *(uint64_t *)((char *)p + sizeof(struct pcpu) * i); } critical_exit(); } else { - for (i = 0; i < mp_ncpus; i++) + CPU_FOREACH(i) res += counter_u64_read_one_8b((uint64_t *)((char *)p + sizeof(struct pcpu) * i)); } @@ -144,7 +144,7 @@ counter_u64_zero_inline(counter_u64_t c) if ((cpu_feature & CPUID_CX8) == 0) { critical_enter(); - for (i = 0; i < mp_ncpus; i++) + CPU_FOREACH(i) *(uint64_t *)((char *)c + sizeof(struct pcpu) * i) = 0; critical_exit(); } else { diff --git a/sys/kern/imgact_elf.c b/sys/kern/imgact_elf.c index 1ee4e9b..df223bf 100644 --- a/sys/kern/imgact_elf.c +++ b/sys/kern/imgact_elf.c @@ -113,7 +113,8 @@ SYSCTL_INT(__CONCAT(_kern_elf, __ELF_WORD_SIZE), OID_AUTO, static int elf_legacy_coredump = 0; SYSCTL_INT(_debug, OID_AUTO, __elfN(legacy_coredump), CTLFLAG_RW, - &elf_legacy_coredump, 0, ""); + &elf_legacy_coredump, 0, + "include all and only RW pages in core dumps"); int __elfN(nxstack) = #if defined(__amd64__) || defined(__powerpc64__) /* both 64 and 32 bit */ || \ diff --git a/sys/kern/kern_mutex.c b/sys/kern/kern_mutex.c index d167205..012cf7c 100644 --- a/sys/kern/kern_mutex.c +++ b/sys/kern/kern_mutex.c @@ -657,8 +657,15 @@ thread_lock_flags_(struct thread *td, int opts, const char *file, int line) i = 0; tid = (uintptr_t)curthread; - if (SCHEDULER_STOPPED()) + if (SCHEDULER_STOPPED()) { + /* + * Ensure that spinlock sections are balanced even when the + * scheduler is stopped, since we may otherwise inadvertently + * re-enable interrupts while dumping core. + */ + spinlock_enter(); return; + } #ifdef KDTRACE_HOOKS spin_time -= lockstat_nsecs(&td->td_lock->lock_object); diff --git a/sys/kern/kern_shutdown.c b/sys/kern/kern_shutdown.c index 78227e7..a74a230 100644 --- a/sys/kern/kern_shutdown.c +++ b/sys/kern/kern_shutdown.c @@ -556,7 +556,7 @@ shutdown_reset(void *junk, int howto) /* NOTREACHED */ /* assuming reset worked */ } -#if defined(WITNESS) || defined(INVARIANTS) +#if defined(WITNESS) || defined(INVARIANT_SUPPORT) static int kassert_warn_only = 0; #ifdef KDB static int kassert_do_kdb = 0; diff --git a/sys/kern/kern_sig.c b/sys/kern/kern_sig.c index 059103dc..2a5e6de 100644 --- a/sys/kern/kern_sig.c +++ b/sys/kern/kern_sig.c @@ -1251,6 +1251,7 @@ kern_sigtimedwait(struct thread *td, sigset_t waitset, ksiginfo_t *ksi, mtx_lock(&ps->ps_mtx); sig = cursig(td); mtx_unlock(&ps->ps_mtx); + KASSERT(sig >= 0, ("sig %d", sig)); if (sig != 0 && SIGISMEMBER(waitset, sig)) { if (sigqueue_get(&td->td_sigqueue, sig, ksi) != 0 || sigqueue_get(&p->p_sigqueue, sig, ksi) != 0) { @@ -1512,8 +1513,10 @@ kern_sigsuspend(struct thread *td, sigset_t mask) /* void */; thread_suspend_check(0); mtx_lock(&p->p_sigacts->ps_mtx); - while ((sig = cursig(td)) != 0) + while ((sig = cursig(td)) != 0) { + KASSERT(sig >= 0, ("sig %d", sig)); has_sig += postsig(sig); + } mtx_unlock(&p->p_sigacts->ps_mtx); } PROC_UNLOCK(p); @@ -2476,11 +2479,9 @@ sig_suspend_threads(struct thread *td, struct proc *p, int sending) */ KASSERT(!TD_IS_SUSPENDED(td2), ("thread with deferred stops suspended")); - if ((td2->td_flags & (TDF_SERESTART | - TDF_SEINTR)) != 0 && sending) { - wakeup_swapper |= sleepq_abort(td, - (td2->td_flags & TDF_SERESTART) - != 0 ? ERESTART : EINTR); + if (TD_SBDRY_INTR(td2) && sending) { + wakeup_swapper |= sleepq_abort(td2, + TD_SBDRY_ERRNO(td2)); } } else if (!TD_IS_SUSPENDED(td2)) { thread_suspend_one(td2); @@ -2628,7 +2629,7 @@ sigdeferstop_curr_flags(int cflags) * accesses below. */ int -sigdeferstop(int mode) +sigdeferstop_impl(int mode) { struct thread *td; int cflags, nflags; @@ -2655,11 +2656,11 @@ sigdeferstop(int mode) panic("sigdeferstop: invalid mode %x", mode); break; } - if (cflags != nflags) { - thread_lock(td); - td->td_flags = (td->td_flags & ~cflags) | nflags; - thread_unlock(td); - } + if (cflags == nflags) + return (SIGDEFERSTOP_VAL_NCHG); + thread_lock(td); + td->td_flags = (td->td_flags & ~cflags) | nflags; + thread_unlock(td); return (cflags); } @@ -2670,11 +2671,12 @@ sigdeferstop(int mode) * either via ast() or a subsequent interruptible sleep. */ void -sigallowstop(int prev) +sigallowstop_impl(int prev) { struct thread *td; int cflags; + KASSERT(prev != SIGDEFERSTOP_VAL_NCHG, ("failed sigallowstop")); KASSERT((prev & ~(TDF_SBDRY | TDF_SEINTR | TDF_SERESTART)) == 0, ("sigallowstop: incorrect previous mode %x", prev)); td = curthread; @@ -2835,6 +2837,11 @@ issignal(struct thread *td) (p->p_pgrp->pg_jobc == 0 && prop & SA_TTYSTOP)) break; /* == ignore */ + if (TD_SBDRY_INTR(td)) { + KASSERT((td->td_flags & TDF_SBDRY) != 0, + ("lost TDF_SBDRY")); + return (-1); + } mtx_unlock(&ps->ps_mtx); WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, &p->p_mtx.lock_object, "Catching SIGSTOP"); diff --git a/sys/kern/kern_thread.c b/sys/kern/kern_thread.c index 5a2d392..89eb7db 100644 --- a/sys/kern/kern_thread.c +++ b/sys/kern/kern_thread.c @@ -894,7 +894,7 @@ thread_suspend_check(int return_instead) { struct thread *td; struct proc *p; - int wakeup_swapper, r; + int wakeup_swapper; td = curthread; p = td->td_proc; @@ -927,21 +927,10 @@ thread_suspend_check(int return_instead) if ((td->td_flags & TDF_SBDRY) != 0) { KASSERT(return_instead, ("TDF_SBDRY set for unsafe thread_suspend_check")); - switch (td->td_flags & (TDF_SEINTR | TDF_SERESTART)) { - case 0: - r = 0; - break; - case TDF_SEINTR: - r = EINTR; - break; - case TDF_SERESTART: - r = ERESTART; - break; - default: - panic("both TDF_SEINTR and TDF_SERESTART"); - break; - } - return (r); + KASSERT((td->td_flags & (TDF_SEINTR | TDF_SERESTART)) != + (TDF_SEINTR | TDF_SERESTART), + ("both TDF_SEINTR and TDF_SERESTART")); + return (TD_SBDRY_INTR(td) ? TD_SBDRY_ERRNO(td) : 0); } /* diff --git a/sys/kern/kern_timeout.c b/sys/kern/kern_timeout.c index 244e5c9..f8736c5 100644 --- a/sys/kern/kern_timeout.c +++ b/sys/kern/kern_timeout.c @@ -1166,7 +1166,7 @@ _callout_stop_safe(struct callout *c, int flags, void (*drain)(void *)) struct callout_cpu *cc, *old_cc; struct lock_class *class; int direct, sq_locked, use_lock; - int not_on_a_list; + int cancelled, not_on_a_list; if ((flags & CS_DRAIN) != 0) WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, c->c_lock, @@ -1236,28 +1236,14 @@ again: } /* - * If the callout isn't pending, it's not on the queue, so - * don't attempt to remove it from the queue. We can try to - * stop it by other means however. + * If the callout is running, try to stop it or drain it. */ - if (!(c->c_iflags & CALLOUT_PENDING)) { + if (cc_exec_curr(cc, direct) == c) { /* - * If it wasn't on the queue and it isn't the current - * callout, then we can't stop it, so just bail. - * It probably has already been run (if locking - * is properly done). You could get here if the caller - * calls stop twice in a row for example. The second - * call would fall here without CALLOUT_ACTIVE set. + * Succeed we to stop it or not, we must clear the + * active flag - this is what API users expect. */ c->c_flags &= ~CALLOUT_ACTIVE; - if (cc_exec_curr(cc, direct) != c) { - CTR3(KTR_CALLOUT, "failed to stop %p func %p arg %p", - c, c->c_func, c->c_arg); - CC_UNLOCK(cc); - if (sq_locked) - sleepq_release(&cc_exec_waiting(cc, direct)); - return (-1); - } if ((flags & CS_DRAIN) != 0) { /* @@ -1376,20 +1362,28 @@ again: cc_exec_drain(cc, direct) = drain; } CC_UNLOCK(cc); - return ((flags & CS_MIGRBLOCK) != 0); + return ((flags & CS_EXECUTING) != 0); } CTR3(KTR_CALLOUT, "failed to stop %p func %p arg %p", c, c->c_func, c->c_arg); if (drain) { cc_exec_drain(cc, direct) = drain; } - CC_UNLOCK(cc); KASSERT(!sq_locked, ("sleepqueue chain still locked")); - return (0); - } + cancelled = ((flags & CS_EXECUTING) != 0); + } else + cancelled = 1; + if (sq_locked) sleepq_release(&cc_exec_waiting(cc, direct)); + if ((c->c_iflags & CALLOUT_PENDING) == 0) { + CTR3(KTR_CALLOUT, "failed to stop %p func %p arg %p", + c, c->c_func, c->c_arg); + CC_UNLOCK(cc); + return (cancelled); + } + c->c_iflags &= ~CALLOUT_PENDING; c->c_flags &= ~CALLOUT_ACTIVE; @@ -1406,7 +1400,7 @@ again: } callout_cc_del(c, cc); CC_UNLOCK(cc); - return (1); + return (cancelled); } void diff --git a/sys/kern/subr_pcpu.c b/sys/kern/subr_pcpu.c index a01f67a..fbfa1a6 100644 --- a/sys/kern/subr_pcpu.c +++ b/sys/kern/subr_pcpu.c @@ -248,7 +248,7 @@ dpcpu_copy(void *s, int size) uintptr_t dpcpu; int i; - for (i = 0; i < mp_ncpus; ++i) { + CPU_FOREACH(i) { dpcpu = dpcpu_off[i]; if (dpcpu == 0) continue; @@ -289,7 +289,7 @@ sysctl_dpcpu_quad(SYSCTL_HANDLER_ARGS) int i; count = 0; - for (i = 0; i < mp_ncpus; ++i) { + CPU_FOREACH(i) { dpcpu = dpcpu_off[i]; if (dpcpu == 0) continue; @@ -306,7 +306,7 @@ sysctl_dpcpu_long(SYSCTL_HANDLER_ARGS) int i; count = 0; - for (i = 0; i < mp_ncpus; ++i) { + CPU_FOREACH(i) { dpcpu = dpcpu_off[i]; if (dpcpu == 0) continue; @@ -323,7 +323,7 @@ sysctl_dpcpu_int(SYSCTL_HANDLER_ARGS) int i; count = 0; - for (i = 0; i < mp_ncpus; ++i) { + CPU_FOREACH(i) { dpcpu = dpcpu_off[i]; if (dpcpu == 0) continue; diff --git a/sys/kern/subr_sleepqueue.c b/sys/kern/subr_sleepqueue.c index bd782b8..3ad2cf0 100644 --- a/sys/kern/subr_sleepqueue.c +++ b/sys/kern/subr_sleepqueue.c @@ -453,7 +453,16 @@ sleepq_catch_signals(void *wchan, int pri) ps = p->p_sigacts; mtx_lock(&ps->ps_mtx); sig = cursig(td); - if (sig == 0) { + if (sig == -1) { + mtx_unlock(&ps->ps_mtx); + KASSERT((td->td_flags & TDF_SBDRY) != 0, ("lost TDF_SBDRY")); + KASSERT(TD_SBDRY_INTR(td), + ("lost TDF_SERESTART of TDF_SEINTR")); + KASSERT((td->td_flags & (TDF_SEINTR | TDF_SERESTART)) != + (TDF_SEINTR | TDF_SERESTART), + ("both TDF_SEINTR and TDF_SERESTART")); + ret = TD_SBDRY_ERRNO(td); + } else if (sig == 0) { mtx_unlock(&ps->ps_mtx); ret = thread_suspend_check(1); MPASS(ret == 0 || ret == EINTR || ret == ERESTART); @@ -591,7 +600,7 @@ sleepq_check_timeout(void) * another CPU, so synchronize with it to avoid having it * accidentally wake up a subsequent sleep. */ - else if (_callout_stop_safe(&td->td_slpcallout, CS_MIGRBLOCK, NULL) + else if (_callout_stop_safe(&td->td_slpcallout, CS_EXECUTING, NULL) == 0) { td->td_flags |= TDF_TIMEOUT; TD_SET_SLEEPING(td); diff --git a/sys/kern/subr_taskqueue.c b/sys/kern/subr_taskqueue.c index 4be29f5..12124b8 100644 --- a/sys/kern/subr_taskqueue.c +++ b/sys/kern/subr_taskqueue.c @@ -832,6 +832,7 @@ static void taskqgroup_cpu_create(struct taskqgroup *qgroup, int idx) { struct taskqgroup_cpu *qcpu; + int i, j; qcpu = &qgroup->tqg_queue[idx]; LIST_INIT(&qcpu->tgc_tasks); @@ -839,7 +840,15 @@ taskqgroup_cpu_create(struct taskqgroup *qgroup, int idx) taskqueue_thread_enqueue, &qcpu->tgc_taskq); taskqueue_start_threads(&qcpu->tgc_taskq, 1, PI_SOFT, "%s_%d", qgroup->tqg_name, idx); - qcpu->tgc_cpu = idx * qgroup->tqg_stride; + + for (i = CPU_FIRST(), j = 0; j < idx * qgroup->tqg_stride; + j++, i = CPU_NEXT(i)) { + /* + * Wait: evaluate the idx * qgroup->tqg_stride'th CPU, + * potentially wrapping the actual count + */ + } + qcpu->tgc_cpu = i; } static void @@ -1017,13 +1026,14 @@ _taskqgroup_adjust(struct taskqgroup *qgroup, int cnt, int stride) LIST_HEAD(, grouptask) gtask_head = LIST_HEAD_INITIALIZER(NULL); cpuset_t mask; struct grouptask *gtask; - int i, old_cnt, qid; + int i, k, old_cnt, qid, cpu; mtx_assert(&qgroup->tqg_lock, MA_OWNED); if (cnt < 1 || cnt * stride > mp_ncpus || !smp_started) { - printf("taskqgroup_adjust failed cnt: %d stride: %d mp_ncpus: %d smp_started: %d\n", - cnt, stride, mp_ncpus, smp_started); + printf("taskqgroup_adjust failed cnt: %d stride: %d " + "mp_ncpus: %d smp_started: %d\n", cnt, stride, mp_ncpus, + smp_started); return (EINVAL); } if (qgroup->tqg_adjusting) { @@ -1081,8 +1091,11 @@ _taskqgroup_adjust(struct taskqgroup *qgroup, int cnt, int stride) /* * Set new CPU and IRQ affinity */ + cpu = CPU_FIRST(); for (i = 0; i < cnt; i++) { - qgroup->tqg_queue[i].tgc_cpu = i * qgroup->tqg_stride; + qgroup->tqg_queue[i].tgc_cpu = cpu; + for (k = 0; k < qgroup->tqg_stride; k++) + cpu = CPU_NEXT(cpu); CPU_ZERO(&mask); CPU_SET(qgroup->tqg_queue[i].tgc_cpu, &mask); LIST_FOREACH(gtask, &qgroup->tqg_queue[i].tgc_tasks, gt_list) { diff --git a/sys/kern/vfs_mount.c b/sys/kern/vfs_mount.c index 1f4592f..247714f 100644 --- a/sys/kern/vfs_mount.c +++ b/sys/kern/vfs_mount.c @@ -1205,6 +1205,28 @@ sys_unmount(struct thread *td, struct unmount_args *uap) } /* + * Return error if any of the vnodes, ignoring the root vnode + * and the syncer vnode, have non-zero usecount. + */ +static int +vfs_check_usecounts(struct mount *mp) +{ + struct vnode *vp, *mvp; + + MNT_VNODE_FOREACH_ALL(vp, mp, mvp) { + if ((vp->v_vflag & VV_ROOT) == 0 && vp->v_type != VNON && + vp->v_usecount != 0) { + VI_UNLOCK(vp); + MNT_VNODE_FOREACH_ALL_ABORT(mp, mvp); + return (EBUSY); + } + VI_UNLOCK(vp); + } + + return (0); +} + +/* * Do the actual filesystem unmount. */ int @@ -1260,6 +1282,21 @@ dounmount(struct mount *mp, int flags, struct thread *td) return (EBUSY); } mp->mnt_kern_flag |= MNTK_UNMOUNT | MNTK_NOINSMNTQ; + if (flags & MNT_NONBUSY) { + MNT_IUNLOCK(mp); + error = vfs_check_usecounts(mp); + MNT_ILOCK(mp); + if (error != 0) { + mp->mnt_kern_flag &= ~(MNTK_UNMOUNT | MNTK_NOINSMNTQ); + MNT_IUNLOCK(mp); + if (coveredvp != NULL) { + VOP_UNLOCK(coveredvp, 0); + vdrop(coveredvp); + } + vn_finished_write(mp); + return (error); + } + } /* Allow filesystems to detect that a forced unmount is in progress. */ if (flags & MNT_FORCE) { mp->mnt_kern_flag |= MNTK_UNMOUNTF; diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index 5f6dae3..5b4c8a7 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -2536,11 +2536,8 @@ vget(struct vnode *vp, int flags, struct thread *td) * * Upgrade our holdcnt to a usecount. */ - if (vp->v_type != VCHR && - vfs_refcount_acquire_if_not_zero(&vp->v_usecount)) { - VNASSERT((vp->v_iflag & VI_OWEINACT) == 0, vp, - ("vnode with usecount and VI_OWEINACT set")); - } else { + if (vp->v_type == VCHR || + !vfs_refcount_acquire_if_not_zero(&vp->v_usecount)) { VI_LOCK(vp); if ((vp->v_iflag & VI_OWEINACT) == 0) { oweinact = 0; diff --git a/sys/kern/vfs_vnops.c b/sys/kern/vfs_vnops.c index 1e42a3d..d2f779f 100644 --- a/sys/kern/vfs_vnops.c +++ b/sys/kern/vfs_vnops.c @@ -440,6 +440,7 @@ vn_close(vp, flags, file_cred, td) vn_start_write(vp, &mp, V_WAIT); vn_lock(vp, lock_flags | LK_RETRY); + AUDIT_ARG_VNODE1(vp); if ((flags & (FWRITE | FOPENFAILED)) == FWRITE) { VNASSERT(vp->v_writecount > 0, vp, ("vn_close: negative writecount")); @@ -1362,6 +1363,7 @@ vn_stat(vp, sb, active_cred, file_cred, td) int error; u_short mode; + AUDIT_ARG_VNODE1(vp); #ifdef MAC error = mac_vnode_check_stat(active_cred, file_cred, vp); if (error) @@ -1511,6 +1513,7 @@ vn_poll(fp, events, active_cred, td) vp = fp->f_vnode; #ifdef MAC vn_lock(vp, LK_EXCLUSIVE | LK_RETRY); + AUDIT_ARG_VNODE1(vp); error = mac_vnode_check_poll(active_cred, fp->f_cred, vp); VOP_UNLOCK(vp, 0); if (!error) diff --git a/sys/net/flowtable.c b/sys/net/flowtable.c index b837a8e..a40a4e6 100644 --- a/sys/net/flowtable.c +++ b/sys/net/flowtable.c @@ -739,6 +739,7 @@ flowtable_lookup_common(struct flowtable *ft, uint32_t *key, int keylen, static void flowtable_alloc(struct flowtable *ft) { + int i; ft->ft_table = malloc(ft->ft_size * sizeof(struct flist), M_FTABLE, M_WAITOK); @@ -746,7 +747,7 @@ flowtable_alloc(struct flowtable *ft) ft->ft_table[i] = uma_zalloc(pcpu_zone_ptr, M_WAITOK | M_ZERO); ft->ft_masks = uma_zalloc(pcpu_zone_ptr, M_WAITOK); - for (int i = 0; i < mp_ncpus; i++) { + CPU_FOREACH(i) { bitstr_t **b; b = zpcpu_get_cpu(ft->ft_masks, i); diff --git a/sys/net/iflib.c b/sys/net/iflib.c index 955a1b2..67282b7 100644 --- a/sys/net/iflib.c +++ b/sys/net/iflib.c @@ -3848,7 +3848,7 @@ iflib_queues_alloc(if_ctx_t ctx) iflib_txq_t txq; iflib_rxq_t rxq; iflib_fl_t fl = NULL; - int i, j, err, txconf, rxconf, fl_ifdi_offset; + int i, j, cpu, err, txconf, rxconf, fl_ifdi_offset; iflib_dma_info_t ifdip; uint32_t *rxqsizes = sctx->isc_rxqsizes; uint32_t *txqsizes = sctx->isc_txqsizes; @@ -3897,7 +3897,7 @@ iflib_queues_alloc(if_ctx_t ctx) /* * XXX handle allocation failure */ - for (txconf = i = 0; i < ntxqsets; i++, txconf++, txq++) { + for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { /* Set up some basics */ if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { @@ -3917,8 +3917,8 @@ iflib_queues_alloc(if_ctx_t ctx) txq->ift_ctx = ctx; txq->ift_id = i; /* XXX fix this */ - txq->ift_timer.c_cpu = i % mp_ncpus; - txq->ift_db_check.c_cpu = i % mp_ncpus; + txq->ift_timer.c_cpu = cpu; + txq->ift_db_check.c_cpu = cpu; txq->ift_nbr = nbuf_rings; if (iflib_txsd_alloc(txq)) { diff --git a/sys/netinet/ip_id.c b/sys/netinet/ip_id.c index 6a80b6e..97d5851 100644 --- a/sys/netinet/ip_id.c +++ b/sys/netinet/ip_id.c @@ -275,10 +275,12 @@ ip_fillid(struct ip *ip) static void ipid_sysinit(void) { + int i; mtx_init(&V_ip_id_mtx, "ip_id_mtx", NULL, MTX_DEF); V_ip_id = counter_u64_alloc(M_WAITOK); - for (int i = 0; i < mp_ncpus; i++) + + CPU_FOREACH(i) arc4rand(zpcpu_get_cpu(V_ip_id, i), sizeof(uint64_t), 0); } VNET_SYSINIT(ip_id, SI_SUB_PROTO_DOMAIN, SI_ORDER_ANY, ipid_sysinit, NULL); diff --git a/sys/netinet/tcp_pcap.c b/sys/netinet/tcp_pcap.c index 41a7fbf..5cb807c 100644 --- a/sys/netinet/tcp_pcap.c +++ b/sys/netinet/tcp_pcap.c @@ -42,9 +42,13 @@ #define M_LEADINGSPACE_NOWRITE(m) \ ((m)->m_data - M_START(m)) +int tcp_pcap_aggressive_free = 1; static int tcp_pcap_clusters_referenced_cur = 0; static int tcp_pcap_clusters_referenced_max = 0; +SYSCTL_INT(_net_inet_tcp, OID_AUTO, tcp_pcap_aggressive_free, + CTLFLAG_RW, &tcp_pcap_aggressive_free, 0, + "Free saved packets when the memory system comes under pressure"); SYSCTL_INT(_net_inet_tcp, OID_AUTO, tcp_pcap_clusters_referenced_cur, CTLFLAG_RD, &tcp_pcap_clusters_referenced_cur, 0, "Number of clusters currently referenced on TCP PCAP queues"); diff --git a/sys/netinet/tcp_pcap.h b/sys/netinet/tcp_pcap.h index ec8fdde..14c5851 100644 --- a/sys/netinet/tcp_pcap.h +++ b/sys/netinet/tcp_pcap.h @@ -36,4 +36,6 @@ void tcp_pcap_tcpcb_init(struct tcpcb *tp); void tcp_pcap_set_sock_max(struct mbufq *queue, int newval); int tcp_pcap_get_sock_max(struct mbufq *queue); +extern int tcp_pcap_aggressive_free; + #endif /* _NETINET_TCP_PCAP_H_ */ diff --git a/sys/netinet/tcp_subr.c b/sys/netinet/tcp_subr.c index 8764b38..12945ce 100644 --- a/sys/netinet/tcp_subr.c +++ b/sys/netinet/tcp_subr.c @@ -1605,6 +1605,13 @@ tcp_drain(void) if ((tcpb = intotcpcb(inpb)) != NULL) { tcp_reass_flush(tcpb); tcp_clean_sackreport(tcpb); +#ifdef TCPPCAP + if (tcp_pcap_aggressive_free) { + /* Free the TCP PCAP queues. */ + tcp_pcap_drain(&(tcpb->t_inpkts)); + tcp_pcap_drain(&(tcpb->t_outpkts)); + } +#endif } INP_WUNLOCK(inpb); } diff --git a/sys/netpfil/ipfw/dn_aqm_pie.c b/sys/netpfil/ipfw/dn_aqm_pie.c index c4b9401..c2e4d43 100644 --- a/sys/netpfil/ipfw/dn_aqm_pie.c +++ b/sys/netpfil/ipfw/dn_aqm_pie.c @@ -207,24 +207,6 @@ calculate_drop_prob(void *x) struct dn_aqm_pie_parms *pprms; struct pie_status *pst = (struct pie_status *) x; - /* dealing with race condition */ - if (callout_pending(&pst->aqm_pie_callout)) { - /* callout was reset */ - mtx_unlock(&pst->lock_mtx); - return; - } - - if (!callout_active(&pst->aqm_pie_callout)) { - /* callout was stopped */ - mtx_unlock(&pst->lock_mtx); - mtx_destroy(&pst->lock_mtx); - free(x, M_DUMMYNET); - //pst->pq->aqm_status = NULL; - pie_desc.ref_count--; - return; - } - callout_deactivate(&pst->aqm_pie_callout); - pprms = pst->parms; prob = pst->drop_prob; @@ -576,7 +558,7 @@ aqm_pie_init(struct dn_queue *q) do { /* exit with break when error occurs*/ if (!pprms){ - D("AQM_PIE is not configured"); + DX(2, "AQM_PIE is not configured"); err = EINVAL; break; } @@ -615,6 +597,22 @@ aqm_pie_init(struct dn_queue *q) } /* + * Callout function to destroy pie mtx and free PIE status memory + */ +static void +pie_callout_cleanup(void *x) +{ + struct pie_status *pst = (struct pie_status *) x; + + mtx_unlock(&pst->lock_mtx); + mtx_destroy(&pst->lock_mtx); + free(x, M_DUMMYNET); + DN_BH_WLOCK(); + pie_desc.ref_count--; + DN_BH_WUNLOCK(); +} + +/* * Clean up PIE status for queue 'q' * Destroy memory allocated for PIE status. */ @@ -640,22 +638,19 @@ aqm_pie_cleanup(struct dn_queue *q) return 1; } + /* + * Free PIE status allocated memory using pie_callout_cleanup() callout + * function to avoid any potential race. + * We reset aqm_pie_callout to call pie_callout_cleanup() in next 1um. This + * stops the scheduled calculate_drop_prob() callout and call pie_callout_cleanup() + * which does memory freeing. + */ mtx_lock(&pst->lock_mtx); + callout_reset_sbt(&pst->aqm_pie_callout, + SBT_1US, 0, pie_callout_cleanup, pst, 0); + q->aqm_status = NULL; + mtx_unlock(&pst->lock_mtx); - /* stop callout timer */ - if (callout_stop(&pst->aqm_pie_callout) || !(pst->sflags & PIE_ACTIVE)) { - mtx_unlock(&pst->lock_mtx); - mtx_destroy(&pst->lock_mtx); - free(q->aqm_status, M_DUMMYNET); - q->aqm_status = NULL; - pie_desc.ref_count--; - return 0; - } else { - q->aqm_status = NULL; - mtx_unlock(&pst->lock_mtx); - DX(2, "PIE callout has not been stoped from cleanup!"); - return EBUSY; - } return 0; } diff --git a/sys/powerpc/conf/GENERIC b/sys/powerpc/conf/GENERIC index d464ac7..b0703f2 100644 --- a/sys/powerpc/conf/GENERIC +++ b/sys/powerpc/conf/GENERIC @@ -85,14 +85,6 @@ options RCTL # Resource limits # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. -# For full debugger support use (turn off in stable branch): -options DDB #Support DDB -#options DEADLKRES #Enable the deadlock resolver -options INVARIANTS #Enable calls of extra sanity checking -options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS -options WITNESS #Enable checks to detect deadlocks and cycles -options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed -options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones # Make an SMP-capable kernel by default options SMP # Symmetric MultiProcessor Kernel diff --git a/sys/powerpc/conf/dpaa/config.dpaa b/sys/powerpc/conf/dpaa/config.dpaa index bc68498..1eafce9 100644 --- a/sys/powerpc/conf/dpaa/config.dpaa +++ b/sys/powerpc/conf/dpaa/config.dpaa @@ -1,6 +1,8 @@ # $FreeBSD$ -makeoptions DPAA_COMPILE_CMD_COMMON="${NORMAL_C} \ +files "dpaa/files.dpaa" + +makeoptions DPAA_COMPILE_CMD="${NORMAL_C} \ -Wno-cast-qual -Wno-unused-function -Wno-init-self -fms-extensions \ -include $S/contrib/ncsw/build/dflags.h \ -I$S/contrib/ncsw/build/ \ diff --git a/sys/powerpc/conf/dpaa/config.p2041 b/sys/powerpc/conf/dpaa/config.p2041 deleted file mode 100644 index 4e7bec1..0000000 --- a/sys/powerpc/conf/dpaa/config.p2041 +++ /dev/null @@ -1,11 +0,0 @@ -# $FreeBSD$ - -files "dpaa/files.dpaa" -files "dpaa/files.p2041" - -include "dpaa/config.dpaa" - -makeoptions DPAA_COMPILE_CMD="${DPAA_COMPILE_CMD_COMMON} \ - -I$S/contrib/ncsw/inc/integrations/P2041" - -device dpaa diff --git a/sys/powerpc/conf/dpaa/config.p3041 b/sys/powerpc/conf/dpaa/config.p3041 deleted file mode 100644 index 9334de6..0000000 --- a/sys/powerpc/conf/dpaa/config.p3041 +++ /dev/null @@ -1,11 +0,0 @@ -# $FreeBSD$ - -files "dpaa/files.dpaa" -files "dpaa/files.p3041" - -include "dpaa/config.dpaa" - -makeoptions DPAA_COMPILE_CMD="${DPAA_COMPILE_CMD_COMMON} \ - -I$S/contrib/ncsw/inc/integrations/P3041" - -device dpaa diff --git a/sys/powerpc/conf/dpaa/config.p5020 b/sys/powerpc/conf/dpaa/config.p5020 deleted file mode 100644 index 28eaeba..0000000 --- a/sys/powerpc/conf/dpaa/config.p5020 +++ /dev/null @@ -1,11 +0,0 @@ -# $FreeBSD$ - -files "dpaa/files.dpaa" -files "dpaa/files.p5020" - -include "dpaa/config.dpaa" - -makeoptions DPAA_COMPILE_CMD="${DPAA_COMPILE_CMD_COMMON} \ - -I$S/contrib/ncsw/inc/integrations/P5020" - -device dpaa diff --git a/sys/powerpc/conf/dpaa/files.p2041 b/sys/powerpc/conf/dpaa/files.p2041 deleted file mode 100644 index dfb4afc..0000000 --- a/sys/powerpc/conf/dpaa/files.p2041 +++ /dev/null @@ -1,3 +0,0 @@ -# $FreeBSD$ - -contrib/ncsw/integrations/P2041/module_strings.c optional dpaa diff --git a/sys/powerpc/conf/dpaa/files.p3041 b/sys/powerpc/conf/dpaa/files.p3041 deleted file mode 100644 index 89bb35c..0000000 --- a/sys/powerpc/conf/dpaa/files.p3041 +++ /dev/null @@ -1,3 +0,0 @@ -# $FreeBSD$ - -contrib/ncsw/integrations/P3041/module_strings.c optional dpaa diff --git a/sys/powerpc/conf/dpaa/files.p5020 b/sys/powerpc/conf/dpaa/files.p5020 deleted file mode 100644 index b442d2e..0000000 --- a/sys/powerpc/conf/dpaa/files.p5020 +++ /dev/null @@ -1,3 +0,0 @@ -# $FreeBSD$ - -contrib/ncsw/integrations/P5020/module_strings.c optional dpaa diff --git a/sys/powerpc/include/counter.h b/sys/powerpc/include/counter.h index 21a0577..500c376 100644 --- a/sys/powerpc/include/counter.h +++ b/sys/powerpc/include/counter.h @@ -54,7 +54,7 @@ counter_u64_fetch_inline(uint64_t *p) int i; r = 0; - for (i = 0; i < mp_ncpus; i++) + CPU_FOREACH(i) r += counter_u64_read_one((uint64_t *)p, i); return (r); diff --git a/sys/powerpc/mpc85xx/lbc.c b/sys/powerpc/mpc85xx/lbc.c index 2c5702b..576fe82 100644 --- a/sys/powerpc/mpc85xx/lbc.c +++ b/sys/powerpc/mpc85xx/lbc.c @@ -362,17 +362,17 @@ static int fdt_lbc_reg_decode(phandle_t node, struct lbc_softc *sc, struct lbc_devinfo *di) { - u_long start, end, count; + rman_res_t start, end, count; pcell_t *reg, *regptr; pcell_t addr_cells, size_cells; int tuple_size, tuples; - int i, rv, bank; + int i, j, rv, bank; if (fdt_addrsize_cells(OF_parent(node), &addr_cells, &size_cells) != 0) return (ENXIO); tuple_size = sizeof(pcell_t) * (addr_cells + size_cells); - tuples = OF_getprop_alloc(node, "reg", tuple_size, (void **)®); + tuples = OF_getencprop_alloc(node, "reg", tuple_size, (void **)®); debugf("addr_cells = %d, size_cells = %d\n", addr_cells, size_cells); debugf("tuples = %d, tuple size = %d\n", tuples, tuple_size); if (tuples <= 0) @@ -387,11 +387,14 @@ fdt_lbc_reg_decode(phandle_t node, struct lbc_softc *sc, reg += 1; /* Get address/size. */ - rv = fdt_data_to_res(reg, addr_cells - 1, size_cells, &start, - &count); - if (rv != 0) { - resource_list_free(&di->di_res); - goto out; + start = count = 0; + for (j = 0; j < addr_cells; j++) { + start <<= 32; + start |= reg[j]; + } + for (j = 0; j < size_cells; j++) { + count <<= 32; + count |= reg[addr_cells + j - 1]; } reg += addr_cells - 1 + size_cells; @@ -399,15 +402,14 @@ fdt_lbc_reg_decode(phandle_t node, struct lbc_softc *sc, start = sc->sc_banks[bank].kva + start; end = start + count - 1; - debugf("reg addr bank = %d, start = %lx, end = %lx, " - "count = %lx\n", bank, start, end, count); + debugf("reg addr bank = %d, start = %jx, end = %jx, " + "count = %jx\n", bank, start, end, count); /* Use bank (CS) cell as rid. */ resource_list_add(&di->di_res, SYS_RES_MEMORY, bank, start, end, count); } rv = 0; -out: OF_prop_free(regptr); return (rv); } @@ -442,13 +444,14 @@ lbc_attach(device_t dev) struct lbc_softc *sc; struct lbc_devinfo *di; struct rman *rm; - u_long offset, start, size; + uintmax_t offset, size; + vm_paddr_t start; device_t cdev; phandle_t node, child; pcell_t *ranges, *rangesptr; int tuple_size, tuples; int par_addr_cells; - int bank, error, i; + int bank, error, i, j; sc = device_get_softc(dev); sc->sc_dev = dev; @@ -540,7 +543,7 @@ lbc_attach(device_t dev) tuple_size = sizeof(pcell_t) * (sc->sc_addr_cells + par_addr_cells + sc->sc_size_cells); - tuples = OF_getprop_alloc(node, "ranges", tuple_size, + tuples = OF_getencprop_alloc(node, "ranges", tuple_size, (void **)&ranges); if (tuples < 0) { device_printf(dev, "could not retrieve 'ranges' property\n"); @@ -558,7 +561,7 @@ lbc_attach(device_t dev) for (i = 0; i < tuples; i++) { /* The first cell is the bank (chip select) number. */ - bank = fdt_data_get((void *)ranges, 1); + bank = fdt_data_get(ranges, 1); if (bank < 0 || bank > LBC_DEV_MAX) { device_printf(dev, "bank out of range: %d\n", bank); error = ERANGE; @@ -570,17 +573,25 @@ lbc_attach(device_t dev) * Remaining cells of the child address define offset into * this CS. */ - offset = fdt_data_get((void *)ranges, sc->sc_addr_cells - 1); - ranges += sc->sc_addr_cells - 1; + offset = 0; + for (j = 0; j < sc->sc_addr_cells - 1; j++) { + offset <<= sizeof(pcell_t) * 8; + offset |= *ranges; + ranges++; + } /* Parent bus start address of this bank. */ - start = fdt_data_get((void *)ranges, par_addr_cells); - ranges += par_addr_cells; + start = 0; + for (j = 0; j < par_addr_cells; j++) { + start <<= sizeof(pcell_t) * 8; + start |= *ranges; + ranges++; + } size = fdt_data_get((void *)ranges, sc->sc_size_cells); ranges += sc->sc_size_cells; - debugf("bank = %d, start = %lx, size = %lx\n", bank, - start, size); + debugf("bank = %d, start = %jx, size = %jx\n", bank, + (uintmax_t)start, size); sc->sc_banks[bank].addr = start + offset; sc->sc_banks[bank].size = size; diff --git a/sys/powerpc/powerpc/mp_machdep.c b/sys/powerpc/powerpc/mp_machdep.c index e219683..7d2dc95 100644 --- a/sys/powerpc/powerpc/mp_machdep.c +++ b/sys/powerpc/powerpc/mp_machdep.c @@ -113,20 +113,16 @@ cpu_mp_setmaxid(void) int error; mp_ncpus = 0; + mp_maxid = 0; error = platform_smp_first_cpu(&cpuref); while (!error) { mp_ncpus++; + mp_maxid = max(cpuref.cr_cpuid, mp_maxid); error = platform_smp_next_cpu(&cpuref); } /* Sanity. */ if (mp_ncpus == 0) mp_ncpus = 1; - - /* - * Set the largest cpuid we're going to use. This is necessary - * for VM initialization. - */ - mp_maxid = min(mp_ncpus, MAXCPU) - 1; } int diff --git a/sys/sparc64/conf/GENERIC b/sys/sparc64/conf/GENERIC index 27fea64..15cf021 100644 --- a/sys/sparc64/conf/GENERIC +++ b/sys/sparc64/conf/GENERIC @@ -75,15 +75,6 @@ options RCTL # Resource limits # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. -# For full debugger support use (turn off in stable branch): -options DDB # Support DDB. -options GDB # Support remote GDB. -options DEADLKRES # Enable the deadlock resolver -options INVARIANTS # Enable calls of extra sanity checking -options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS -options WITNESS # Enable checks to detect deadlocks and cycles -options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed -options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones # Make an SMP-capable kernel by default options SMP # Symmetric MultiProcessor Kernel diff --git a/sys/sys/callout.h b/sys/sys/callout.h index 689b547..d308d70 100644 --- a/sys/sys/callout.h +++ b/sys/sys/callout.h @@ -64,9 +64,8 @@ struct callout_handle { /* Flags for callout_stop_safe() */ #define CS_DRAIN 0x0001 /* callout_drain(), wait allowed */ -#define CS_MIGRBLOCK 0x0002 /* Block migration, return value - indicates that the callout was - executing */ +#define CS_EXECUTING 0x0002 /* Positive return value indicates that + the callout was executing */ #ifdef _KERNEL /* diff --git a/sys/sys/mount.h b/sys/sys/mount.h index 5438140..7c2856a 100644 --- a/sys/sys/mount.h +++ b/sys/sys/mount.h @@ -312,17 +312,21 @@ void __mnt_vnode_markerfree_active(struct vnode **mvp, struct mount *); * External filesystem command modifier flags. * Unmount can use the MNT_FORCE flag. * XXX: These are not STATES and really should be somewhere else. - * XXX: MNT_BYFSID collides with MNT_ACLS, but because MNT_ACLS is only used for - * mount(2) and MNT_BYFSID is only used for unmount(2) it's harmless. + * XXX: MNT_BYFSID and MNT_NONBUSY collide with MNT_ACLS and MNT_MULTILABEL, + * but because MNT_ACLS and MNT_MULTILABEL are only used for mount(2), + * and MNT_BYFSID and MNT_NONBUSY are only used for unmount(2), + * it's harmless. */ #define MNT_UPDATE 0x0000000000010000ULL /* not real mount, just update */ #define MNT_DELEXPORT 0x0000000000020000ULL /* delete export host lists */ #define MNT_RELOAD 0x0000000000040000ULL /* reload filesystem data */ #define MNT_FORCE 0x0000000000080000ULL /* force unmount or readonly */ #define MNT_SNAPSHOT 0x0000000001000000ULL /* snapshot the filesystem */ +#define MNT_NONBUSY 0x0000000004000000ULL /* check vnode use counts. */ #define MNT_BYFSID 0x0000000008000000ULL /* specify filesystem by ID. */ #define MNT_CMDFLAGS (MNT_UPDATE | MNT_DELEXPORT | MNT_RELOAD | \ - MNT_FORCE | MNT_SNAPSHOT | MNT_BYFSID) + MNT_FORCE | MNT_SNAPSHOT | MNT_NONBUSY | \ + MNT_BYFSID) /* * Internal filesystem control flags stored in mnt_kern_flag. * diff --git a/sys/sys/proc.h b/sys/sys/proc.h index 384c2f1..f533db6 100644 --- a/sys/sys/proc.h +++ b/sys/sys/proc.h @@ -511,6 +511,11 @@ do { \ #define TD_SET_RUNQ(td) (td)->td_state = TDS_RUNQ #define TD_SET_CAN_RUN(td) (td)->td_state = TDS_CAN_RUN +#define TD_SBDRY_INTR(td) \ + (((td)->td_flags & (TDF_SEINTR | TDF_SERESTART)) != 0) +#define TD_SBDRY_ERRNO(td) \ + (((td)->td_flags & TDF_SEINTR) != 0 ? EINTR : ERESTART) + /* * Process structure. */ @@ -597,7 +602,7 @@ struct proc { u_int p_magic; /* (b) Magic number. */ int p_osrel; /* (x) osreldate for the binary (from ELF note, if any) */ - char p_comm[MAXCOMLEN + 1]; /* (b) Process name. */ + char p_comm[MAXCOMLEN + 1]; /* (x) Process name. */ struct sysentvec *p_sysent; /* (b) Syscall dispatch info. */ struct pargs *p_args; /* (c) Process arguments. */ rlim_t p_cpulimit; /* (c) Current CPU limit in seconds. */ diff --git a/sys/sys/signalvar.h b/sys/sys/signalvar.h index 176bb2a..a8a975f 100644 --- a/sys/sys/signalvar.h +++ b/sys/sys/signalvar.h @@ -337,9 +337,29 @@ extern struct mtx sigio_lock; #define SIGDEFERSTOP_EINTR 3 /* ignore STOPs, return EINTR */ #define SIGDEFERSTOP_ERESTART 4 /* ignore STOPs, return ERESTART */ +#define SIGDEFERSTOP_VAL_NCHG (-1) /* placeholder indicating no state change */ +int sigdeferstop_impl(int mode); +void sigallowstop_impl(int prev); + +static inline int +sigdeferstop(int mode) +{ + + if (mode == SIGDEFERSTOP_NOP) + return (SIGDEFERSTOP_VAL_NCHG); + return (sigdeferstop_impl(mode)); +} + +static inline void +sigallowstop(int prev) +{ + + if (prev == SIGDEFERSTOP_VAL_NCHG) + return; + sigallowstop_impl(prev); +} + int cursig(struct thread *td); -int sigdeferstop(int mode); -void sigallowstop(int prev); void execsigs(struct proc *p); void gsignal(int pgid, int sig, ksiginfo_t *ksi); void killproc(struct proc *p, char *why); diff --git a/sys/sys/systm.h b/sys/sys/systm.h index 1f05f69..dae6adc 100644 --- a/sys/sys/systm.h +++ b/sys/sys/systm.h @@ -76,7 +76,7 @@ extern int vm_guest; /* Running as virtual machine guest? */ enum VM_GUEST { VM_GUEST_NO = 0, VM_GUEST_VM, VM_GUEST_XEN, VM_GUEST_HV, VM_GUEST_VMWARE, VM_LAST }; -#if defined(WITNESS) || defined(INVARIANTS) +#if defined(WITNESS) || defined(INVARIANT_SUPPORT) void kassert_panic(const char *fmt, ...) __printflike(1, 2); #endif diff --git a/sys/vm/uma.h b/sys/vm/uma.h index 6ac78ef..f4c2de8 100644 --- a/sys/vm/uma.h +++ b/sys/vm/uma.h @@ -276,7 +276,7 @@ uma_zone_t uma_zcache_create(char *name, int size, uma_ctor ctor, uma_dtor dtor, * mini-dumps. */ #define UMA_ZONE_PCPU 0x8000 /* - * Allocates mp_ncpus slabs sized to + * Allocates mp_maxid + 1 slabs sized to * sizeof(struct pcpu). */ diff --git a/sys/vm/uma_core.c b/sys/vm/uma_core.c index 0a56c55..1ae83c4 100644 --- a/sys/vm/uma_core.c +++ b/sys/vm/uma_core.c @@ -1227,7 +1227,7 @@ keg_small_init(uma_keg_t keg) u_int shsize; if (keg->uk_flags & UMA_ZONE_PCPU) { - u_int ncpus = mp_ncpus ? mp_ncpus : MAXCPU; + u_int ncpus = (mp_maxid + 1) ? (mp_maxid + 1) : MAXCPU; keg->uk_slabsize = sizeof(struct pcpu); keg->uk_ppera = howmany(ncpus * sizeof(struct pcpu), @@ -3265,9 +3265,10 @@ uma_large_free(uma_slab_t slab) static void uma_zero_item(void *item, uma_zone_t zone) { + int i; if (zone->uz_flags & UMA_ZONE_PCPU) { - for (int i = 0; i < mp_ncpus; i++) + CPU_FOREACH(i) bzero(zpcpu_get_cpu(item, i), zone->uz_size); } else bzero(item, zone->uz_size); diff --git a/sys/vm/uma_int.h b/sys/vm/uma_int.h index 461558b..2789e55 100644 --- a/sys/vm/uma_int.h +++ b/sys/vm/uma_int.h @@ -110,6 +110,8 @@ #define UMA_SLAB_SHIFT PAGE_SHIFT /* Number of bits PAGE_MASK */ #define UMA_BOOT_PAGES 64 /* Pages allocated for startup */ +#define UMA_BOOT_PAGES_ZONES 32 /* Multiplier for pages to reserve */ + /* if uma_zone > PAGE_SIZE */ /* Max waste percentage before going to off page slab management */ #define UMA_MAX_WASTE 10 diff --git a/sys/vm/vm_fault.c b/sys/vm/vm_fault.c index 5e81333..6b47e13 100644 --- a/sys/vm/vm_fault.c +++ b/sys/vm/vm_fault.c @@ -285,14 +285,14 @@ vm_fault_hold(vm_map_t map, vm_offset_t vaddr, vm_prot_t fault_type, { vm_prot_t prot; int alloc_req, era, faultcount, nera, result; - boolean_t growstack, is_first_object_locked, wired; + boolean_t dead, growstack, is_first_object_locked, wired; int map_generation; vm_object_t next_object; int hardfault; struct faultstate fs; struct vnode *vp; vm_page_t m; - int ahead, behind, cluster_offset, dead, error, locked; + int ahead, behind, cluster_offset, error, locked; hardfault = 0; growstack = TRUE; @@ -570,9 +570,9 @@ readrest: behind = 0; nera = VM_FAULT_READ_AHEAD_MAX; ahead = nera; - if (fs.pindex == fs.entry->next_read) + if (vaddr == fs.entry->next_read) vm_fault_dontneed(&fs, vaddr, ahead); - } else if (fs.pindex == fs.entry->next_read) { + } else if (vaddr == fs.entry->next_read) { /* * This is a sequential fault. Arithmetically * increase the requested number of pages in @@ -927,15 +927,15 @@ vnode_locked: prot &= retry_prot; } } + /* - * If the page was filled by a pager, update the map entry's - * last read offset. - * - * XXX The following assignment modifies the map - * without holding a write lock on it. + * If the page was filled by a pager, save the virtual address that + * should be faulted on next under a sequential access pattern to the + * map entry. A read lock on the map suffices to update this address + * safely. */ if (hardfault) - fs.entry->next_read = fs.pindex + ahead + 1; + fs.entry->next_read = vaddr + ptoa(ahead) + PAGE_SIZE; vm_fault_dirty(fs.entry, fs.m, prot, fault_type, fault_flags, TRUE); vm_page_assert_xbusied(fs.m); diff --git a/sys/vm/vm_map.c b/sys/vm/vm_map.c index 18404f8..a23468e 100644 --- a/sys/vm/vm_map.c +++ b/sys/vm/vm_map.c @@ -1330,7 +1330,7 @@ charged: new_entry->wired_count = 0; new_entry->wiring_thread = NULL; new_entry->read_ahead = VM_FAULT_READ_AHEAD_INIT; - new_entry->next_read = OFF_TO_IDX(offset); + new_entry->next_read = start; KASSERT(cred == NULL || !ENTRY_CHARGED(new_entry), ("OVERCOMMIT: vm_map_insert leaks vm_map %p", new_entry)); diff --git a/sys/vm/vm_map.h b/sys/vm/vm_map.h index 2c0a4ad..10e6564 100644 --- a/sys/vm/vm_map.h +++ b/sys/vm/vm_map.h @@ -104,6 +104,7 @@ struct vm_map_entry { vm_offset_t start; /* start address */ vm_offset_t end; /* end address */ vm_offset_t avail_ssize; /* amt can grow if this is a stack */ + vm_offset_t next_read; /* vaddr of the next sequential read */ vm_size_t adj_free; /* amount of adjacent free space */ vm_size_t max_free; /* max free space in subtree */ union vm_map_object object; /* object I point to */ @@ -114,7 +115,6 @@ struct vm_map_entry { vm_inherit_t inheritance; /* inheritance */ uint8_t read_ahead; /* pages in the read-ahead window */ int wired_count; /* can be paged if = 0 */ - vm_pindex_t next_read; /* index of the next sequential read */ struct ucred *cred; /* tmp storage for creator ref */ struct thread *wiring_thread; }; diff --git a/sys/vm/vm_page.c b/sys/vm/vm_page.c index 2c89cd9..4ecc0ea 100644 --- a/sys/vm/vm_page.c +++ b/sys/vm/vm_page.c @@ -99,6 +99,7 @@ __FBSDID("$FreeBSD$"); #include <sys/proc.h> #include <sys/rwlock.h> #include <sys/sbuf.h> +#include <sys/smp.h> #include <sys/sysctl.h> #include <sys/vmmeter.h> #include <sys/vnode.h> @@ -426,6 +427,7 @@ vm_page_startup(vm_offset_t vaddr) vm_paddr_t biggestsize; vm_paddr_t low_water, high_water; int biggestone; + int pages_per_zone; biggestsize = 0; biggestone = 0; @@ -470,6 +472,19 @@ vm_page_startup(vm_offset_t vaddr) vm_page_domain_init(&vm_dom[i]); /* + * Almost all of the pages needed for boot strapping UMA are used + * for zone structures, so if the number of CPUs results in those + * structures taking more than one page each, we set aside more pages + * in proportion to the zone structure size. + */ + pages_per_zone = howmany(sizeof(struct uma_zone) + + sizeof(struct uma_cache) * (mp_maxid + 1), UMA_SLAB_SIZE); + if (pages_per_zone > 1) { + /* Reserve more pages so that we don't run out. */ + boot_pages = UMA_BOOT_PAGES_ZONES * pages_per_zone; + } + + /* * Allocate memory for use when boot strapping the kernel memory * allocator. * diff --git a/sys/vm/vnode_pager.c b/sys/vm/vnode_pager.c index cc43976..a80a9c2 100644 --- a/sys/vm/vnode_pager.c +++ b/sys/vm/vnode_pager.c @@ -169,10 +169,21 @@ vnode_destroy_vobject(struct vnode *vp) /* * don't double-terminate the object */ - if ((obj->flags & OBJ_DEAD) == 0) + if ((obj->flags & OBJ_DEAD) == 0) { vm_object_terminate(obj); - else + } else { + /* + * Waiters were already handled during object + * termination. The exclusive vnode lock hopefully + * prevented new waiters from referencing the dying + * object. + */ + KASSERT((obj->flags & OBJ_DISCONNECTWNT) == 0, + ("OBJ_DISCONNECTWNT set obj %p flags %x", + obj, obj->flags)); + vp->v_object = NULL; VM_OBJECT_WUNLOCK(obj); + } } else { /* * Woe to the process that tries to page now :-). @@ -180,7 +191,7 @@ vnode_destroy_vobject(struct vnode *vp) vm_pager_deallocate(obj); VM_OBJECT_WUNLOCK(obj); } - vp->v_object = NULL; + KASSERT(vp->v_object == NULL, ("vp %p obj %p", vp, vp->v_object)); } diff --git a/tools/build/mk/OptionalObsoleteFiles.inc b/tools/build/mk/OptionalObsoleteFiles.inc index 5bda73c..779b0ef 100644 --- a/tools/build/mk/OptionalObsoleteFiles.inc +++ b/tools/build/mk/OptionalObsoleteFiles.inc @@ -1345,6 +1345,20 @@ OLD_FILES+=usr/sbin/fmtree OLD_FILES+=usr/share/man/man8/fmtree.8.gz .endif +.if ${MK_FTP} == no +OLD_FILES+=etc/ftpusers +OLD_FILES+=etc/rc.d/ftpd +OLD_FILES+=usr/bin/ftp +OLD_FILES+=usr/bin/gate-ftp +OLD_FILES+=usr/bin/pftp +OLD_FILES+=usr/libexec/ftpd +OLD_FILES+=usr/share/man/man1/ftp.1.gz +OLD_FILES+=usr/share/man/man1/gate-ftp.1.gz +OLD_FILES+=usr/share/man/man1/pftp.1.gz +OLD_FILES+=usr/share/man/man5/ftpchroot.5.gz +OLD_FILES+=usr/share/man/man8/ftpd.8.gz +.endif + .if ${MK_GNUCXX} == no OLD_FILES+=usr/bin/g++ OLD_FILES+=usr/include/c++/4.2/algorithm @@ -4796,6 +4810,12 @@ OLD_FILES+=usr/share/locale/en_ZA.ISO8859-1/LC_MESSAGES OLD_FILES+=usr/share/locale/en_ZA.ISO8859-1/LC_MONETARY OLD_FILES+=usr/share/locale/en_ZA.ISO8859-1/LC_NUMERIC OLD_FILES+=usr/share/locale/en_ZA.ISO8859-1/LC_TIME +OLD_FILES+=usr/share/locale/en_ZA.ISO8859-15/LC_COLLATE +OLD_FILES+=usr/share/locale/en_ZA.ISO8859-15/LC_CTYPE +OLD_FILES+=usr/share/locale/en_ZA.ISO8859-15/LC_MESSAGES +OLD_FILES+=usr/share/locale/en_ZA.ISO8859-15/LC_MONETARY +OLD_FILES+=usr/share/locale/en_ZA.ISO8859-15/LC_NUMERIC +OLD_FILES+=usr/share/locale/en_ZA.ISO8859-15/LC_TIME OLD_FILES+=usr/share/locale/en_ZA.US-ASCII/LC_COLLATE OLD_FILES+=usr/share/locale/en_ZA.US-ASCII/LC_CTYPE OLD_FILES+=usr/share/locale/en_ZA.US-ASCII/LC_MESSAGES @@ -5108,12 +5128,12 @@ OLD_FILES+=usr/share/locale/ja_JP.UTF-8/LC_MESSAGES OLD_FILES+=usr/share/locale/ja_JP.UTF-8/LC_MONETARY OLD_FILES+=usr/share/locale/ja_JP.UTF-8/LC_NUMERIC OLD_FILES+=usr/share/locale/ja_JP.UTF-8/LC_TIME -OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/kk_Cyrl_KZ.UTF-8/LC_TIME +OLD_FILES+=usr/share/locale/kk_KZ.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/kk_KZ.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/kk_KZ.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/kk_KZ.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/kk_KZ.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/kk_KZ.UTF-8/LC_TIME OLD_FILES+=usr/share/locale/ko_KR.CP949/LC_COLLATE OLD_FILES+=usr/share/locale/ko_KR.CP949/LC_CTYPE OLD_FILES+=usr/share/locale/ko_KR.CP949/LC_MESSAGES @@ -5156,12 +5176,12 @@ OLD_FILES+=usr/share/locale/lv_LV.UTF-8/LC_MESSAGES OLD_FILES+=usr/share/locale/lv_LV.UTF-8/LC_MONETARY OLD_FILES+=usr/share/locale/lv_LV.UTF-8/LC_NUMERIC OLD_FILES+=usr/share/locale/lv_LV.UTF-8/LC_TIME -OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/mn_Cyrl_MN.UTF-8/LC_TIME +OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/mn_MN.UTF-8/LC_TIME OLD_FILES+=usr/share/locale/nb_NO.ISO8859-1/LC_COLLATE OLD_FILES+=usr/share/locale/nb_NO.ISO8859-1/LC_CTYPE OLD_FILES+=usr/share/locale/nb_NO.ISO8859-1/LC_MESSAGES @@ -5354,30 +5374,30 @@ OLD_FILES+=usr/share/locale/sl_SI.UTF-8/LC_MESSAGES OLD_FILES+=usr/share/locale/sl_SI.UTF-8/LC_MONETARY OLD_FILES+=usr/share/locale/sl_SI.UTF-8/LC_NUMERIC OLD_FILES+=usr/share/locale/sl_SI.UTF-8/LC_TIME -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_COLLATE -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_CTYPE -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_MESSAGES -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_MONETARY -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_NUMERIC -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.ISO8859-5/LC_TIME -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/sr_Cyrl_RS.UTF-8/LC_TIME -OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_COLLATE -OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_CTYPE -OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_MESSAGES -OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_MONETARY -OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_NUMERIC -OLD_FILES+=usr/share/locale/sr_Latn_RS.ISO8859-2/LC_TIME -OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/sr_Latn_RS.UTF-8/LC_TIME +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-5/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-5/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-5/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-5/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-5/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-5/LC_TIME +OLD_FILES+=usr/share/locale/sr_RS.UTF-8/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_RS.UTF-8/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_RS.UTF-8/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_RS.UTF-8/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_RS.UTF-8/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_RS.UTF-8/LC_TIME +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-2/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-2/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-2/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-2/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-2/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_RS.ISO8859-2/LC_TIME +OLD_FILES+=usr/share/locale/sr_RS.UTF-8@latin/LC_COLLATE +OLD_FILES+=usr/share/locale/sr_RS.UTF-8@latin/LC_CTYPE +OLD_FILES+=usr/share/locale/sr_RS.UTF-8@latin/LC_MESSAGES +OLD_FILES+=usr/share/locale/sr_RS.UTF-8@latin/LC_MONETARY +OLD_FILES+=usr/share/locale/sr_RS.UTF-8@latin/LC_NUMERIC +OLD_FILES+=usr/share/locale/sr_RS.UTF-8@latin/LC_TIME OLD_FILES+=usr/share/locale/sv_FI.ISO8859-1/LC_COLLATE OLD_FILES+=usr/share/locale/sv_FI.ISO8859-1/LC_CTYPE OLD_FILES+=usr/share/locale/sv_FI.ISO8859-1/LC_MESSAGES @@ -5480,54 +5500,6 @@ OLD_FILES+=usr/share/locale/zh_CN.UTF-8/LC_MESSAGES OLD_FILES+=usr/share/locale/zh_CN.UTF-8/LC_MONETARY OLD_FILES+=usr/share/locale/zh_CN.UTF-8/LC_NUMERIC OLD_FILES+=usr/share/locale/zh_CN.UTF-8/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hans_CN.eucCN/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB18030/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hans_CN.GB2312/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hans_CN.GBK/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hans_CN.UTF-8/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hant_HK.UTF-8/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hant_TW.Big5/LC_TIME -OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_COLLATE -OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_CTYPE -OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_MESSAGES -OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_MONETARY -OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_NUMERIC -OLD_FILES+=usr/share/locale/zh_Hant_TW.UTF-8/LC_TIME OLD_FILES+=usr/share/locale/zh_HK.UTF-8/LC_COLLATE OLD_FILES+=usr/share/locale/zh_HK.UTF-8/LC_CTYPE OLD_FILES+=usr/share/locale/zh_HK.UTF-8/LC_MESSAGES diff --git a/tools/tools/locale/tools/cldr2def.pl b/tools/tools/locale/tools/cldr2def.pl index b48220e..21a88a7 100755 --- a/tools/tools/locale/tools/cldr2def.pl +++ b/tools/tools/locale/tools/cldr2def.pl @@ -848,7 +848,7 @@ sub make_makefile { my $MAPLOC; if ($TYPE eq "colldef") { $SRCOUT = "localedef -D -U -i \${.IMPSRC} \\\n" . - "\t-f \${MAPLOC}/map.\${.TARGET:T:R:E} " . + "\t-f \${MAPLOC}/map.\${.TARGET:T:R:E:C/@.*//} " . "\${.OBJDIR}/\${.IMPSRC:T:R}"; $MAPLOC = "MAPLOC=\t\t\${.CURDIR}/../../tools/tools/" . "locale/etc/final-maps\n"; @@ -859,7 +859,7 @@ sub make_makefile { "FILESDIR_\$t.LC_COLLATE=\t\${LOCALEDIR}/\$t\n" . "\$t.LC_COLLATE: \${.CURDIR}/\$f.src\n" . "\tlocaledef -D -U -i \${.ALLSRC} \\\n" . - "\t\t-f \${MAPLOC}/map.\${.TARGET:T:R:E} \\\n" . + "\t\t-f \${MAPLOC}/map.\${.TARGET:T:R:E:C/@.*//} \\\n" . "\t\t\${.OBJDIR}/\${.TARGET:T:R}\n" . ".endfor\n\n"; $SRCOUT4 = "## LOCALES_MAPPED\n"; diff --git a/tools/tools/locale/tools/finalize b/tools/tools/locale/tools/finalize index 709c6c2..37c8db8 100755 --- a/tools/tools/locale/tools/finalize +++ b/tools/tools/locale/tools/finalize @@ -8,6 +8,8 @@ # the generate makefile to pull the LOCALES first. # +set -e + usage () { echo "finalize <type>' to package standard localization" @@ -37,6 +39,56 @@ AWKCMD="/## PLACEHOLDER/ { \ while ( getline line < \"${TEMP4}\" ) {print line} } \ !/## / { print \$0 }" +# Rename the sources with 3 components name into the POSIX version of the name using @modifier +cd $old +for i in *_*_*.*.src; do + oldname=${i%.*} + nname=`echo $oldname | awk '{ split($0, a, "_"); print a[1]"_"a[3]"@"a[2];} '` + mv -i ${oldname}.src ${nname}.src +done + sed -i '' -Ee "s/([a-zA-Z]{2})_([a-zA-Z]+)_([a-zA-Z]{2}).([a-zA-Z0-9-]+)/\1_\3.\4@\2/g" ${old}/Makefile + +# For variable without @modifier ambiguity do not keep the @modifier +for i in *@*.src; do + oldname=${i%.*} + shortname=${oldname%@*} + if [ $(ls ${shortname}@* | wc -l) -eq 1 -a ! -f ${shortname}.src ] ; then + mv -i $i ${shortname}.src + sed -i '' -e "s/${oldname}/${shortname}/g" ${old}/Makefile + fi +done + +# Rename the modifiers into non abbreviated version +for i in *@Latn.src; do + if [ "$i" = "*@Latn.src" ]; then + break + fi + mv ${i} ${i%@*}@latin.src +done + sed -i '' -e "s/@Latn/@latin/g" ${old}/Makefile +for i in *@Cyrl.src; do + if [ "$i" = "*@Cyrl.src" ]; then + break + fi + mv ${i} ${i%@*}@cyrillic.src +done + sed -i '' -e "s/@Cyrl/@cyrillic/g" ${old}/Makefile + +# On locales with multiple modifiers rename the "default" version without the @modifier +default_locales="sr_RS@cyrillic" +for i in ${default_locales}; do + localename=${i%@*} + mod=${i#*@} + for l in ${localename}.*@${mod}.src; do + if [ "$l" = "${localename}.*@${mod}.src" ]; then + break + fi + mv ${l} ${l%@*}.src + sed -i '' -e "s/${l%.*}/${l%@*}/g" ${old}/Makefile + done +done +cd - + grep '^LOCALES+' ${old}/Makefile > ${TEMP} if [ $1 = "ctypedef" ] @@ -94,8 +146,9 @@ then done echo "" >> ${TEMP4} for enc in ${COLLATIONS_SPECIAL}; do - sed -i '' "/^.*${enc}$/d" ${TEMP4} - echo "LOCALES+= ${enc}" >> ${TEMP4} + nname=`echo $enc | sed -e 's/_Hans//g'` + sed -i '' "/^.*${nname}$/d" ${TEMP4} + echo "LOCALES+= ${nname}" >> ${TEMP4} done keep=$(cat ${TEMP} | awk '{ print $2 }') diff --git a/usr.bin/lastcomm/tests/legacy_test.sh b/usr.bin/lastcomm/tests/legacy_test.sh index 35ef78b..c7da326 100644 --- a/usr.bin/lastcomm/tests/legacy_test.sh +++ b/usr.bin/lastcomm/tests/legacy_test.sh @@ -14,7 +14,7 @@ check() shift # Remove tty field, which varies between systems. awk '{$4 = ""; print}' | - if diff -q - $1 + if diff -a - $1 >&2 then echo "ok $NUM" else diff --git a/usr.bin/lastcomm/tests/v1-i386.out b/usr.bin/lastcomm/tests/v1-i386.out index 86ec9e2..91a7d16 100644 --- a/usr.bin/lastcomm/tests/v1-i386.out +++ b/usr.bin/lastcomm/tests/v1-i386.out @@ -1,28 +1,28 @@ -core -FDX root 0.000 secs 0.000 us 0.000 sy 0.031 es Fri May 18 11:34 -core -DX root 0.000 secs 0.000 us 0.000 sy 0.031 es Fri May 18 11:34 -cc - root 0.000 secs 0.000 us 0.000 sy 0.469 es Fri May 18 11:34 -ld - root 0.000 secs 0.000 us 0.000 sy 0.109 es Fri May 18 11:34 -as - root 0.000 secs 0.000 us 0.000 sy 0.047 es Fri May 18 11:34 -cc1 - root 0.016 secs 0.016 us 0.000 sy 0.203 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -1234567890123456 - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -ln - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -1234567890123456 - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -ln - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -123456789012345 - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -ln - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 0.359 es Fri May 18 11:34 -diff - root 0.312 secs 0.297 us 0.016 sy 0.359 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 0.031 es Fri May 18 11:34 -dd - root 0.016 secs 0.000 us 0.016 sy 0.031 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 3.000 es Fri May 18 11:34 -sleep - root 0.000 secs 0.000 us 0.000 sy 3.000 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 3.406 es Fri May 18 11:34 -find - root 0.266 secs 0.062 us 0.203 sy 3.406 es Fri May 18 11:34 -time - root 0.000 secs 0.000 us 0.000 sy 5.047 es Fri May 18 11:33 -egrep - root 4.984 secs 4.984 us 0.000 sy 5.047 es Fri May 18 11:33 -time - root 0.000 secs 0.000 us 0.000 sy 0.484 es Fri May 18 11:33 -awk - root 0.453 secs 0.453 us 0.000 sy 0.453 es Fri May 18 11:33 -accton - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 11:33 +core -FDX root 0.000 secs 0.000 us 0.000 sy 0.031 es Fri May 18 08:34 +core -DX root 0.000 secs 0.000 us 0.000 sy 0.031 es Fri May 18 08:34 +cc - root 0.000 secs 0.000 us 0.000 sy 0.469 es Fri May 18 08:34 +ld - root 0.000 secs 0.000 us 0.000 sy 0.109 es Fri May 18 08:34 +as - root 0.000 secs 0.000 us 0.000 sy 0.047 es Fri May 18 08:34 +cc1 - root 0.016 secs 0.016 us 0.000 sy 0.203 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +1234567890123456 - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +ln - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +1234567890123456 - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +ln - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +123456789012345 - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +ln - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 0.359 es Fri May 18 08:34 +diff - root 0.312 secs 0.297 us 0.016 sy 0.359 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 0.031 es Fri May 18 08:34 +dd - root 0.016 secs 0.000 us 0.016 sy 0.031 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 3.000 es Fri May 18 08:34 +sleep - root 0.000 secs 0.000 us 0.000 sy 3.000 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 3.406 es Fri May 18 08:34 +find - root 0.266 secs 0.062 us 0.203 sy 3.406 es Fri May 18 08:34 +time - root 0.000 secs 0.000 us 0.000 sy 5.047 es Fri May 18 08:33 +egrep - root 4.984 secs 4.984 us 0.000 sy 5.047 es Fri May 18 08:33 +time - root 0.000 secs 0.000 us 0.000 sy 0.484 es Fri May 18 08:33 +awk - root 0.453 secs 0.453 us 0.000 sy 0.453 es Fri May 18 08:33 +accton - root 0.000 secs 0.000 us 0.000 sy 0.000 es Fri May 18 08:33 diff --git a/usr.bin/lastcomm/tests/v2-i386.out b/usr.bin/lastcomm/tests/v2-i386.out index 61bc811..e09fd71 100644 --- a/usr.bin/lastcomm/tests/v2-i386.out +++ b/usr.bin/lastcomm/tests/v2-i386.out @@ -1,28 +1,28 @@ -core -FDX root 0.000 secs 0.000 us 0.000 sy 0.005 es Fri May 18 15:13 -core -DX root 0.002 secs 0.000 us 0.002 sy 0.005 es Fri May 18 15:13 -cc - root 0.002 secs 0.000 us 0.002 sy 0.048 es Fri May 18 15:13 -ld - root 0.028 secs 0.019 us 0.009 sy 0.028 es Fri May 18 15:13 -as - root 0.002 secs 0.002 us 0.000 sy 0.002 es Fri May 18 15:13 -cc1 - root 0.016 secs 0.016 us 0.000 sy 0.016 es Fri May 18 15:13 -time - root 0.001 secs 0.000 us 0.001 sy 0.002 es Fri May 18 15:13 -1234567890123456 - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 15:13 -ln - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 15:13 -time - root 0.001 secs 0.001 us 0.000 sy 0.002 es Fri May 18 15:13 -1234567890123456 - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 15:13 -ln - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 15:13 -time - root 0.001 secs 0.000 us 0.001 sy 0.002 es Fri May 18 15:13 -123456789012345 - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 15:13 -ln - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 15:13 -time - root 0.001 secs 0.000 us 0.001 sy 0.425 es Fri May 18 15:13 -diff - root 0.423 secs 0.392 us 0.031 sy 0.424 es Fri May 18 15:13 -time - root 0.001 secs 0.000 us 0.001 sy 0.028 es Fri May 18 15:13 -dd - root 0.025 secs 0.000 us 0.025 sy 0.026 es Fri May 18 15:13 -time - root 0.001 secs 0.000 us 0.001 sy 3.002 es Fri May 18 15:13 -sleep - root 0.001 secs 0.000 us 0.001 sy 3.001 es Fri May 18 15:13 -time - root 0.001 secs 0.000 us 0.001 sy 0.250 es Fri May 18 15:13 -find - root 0.248 secs 0.078 us 0.171 sy 0.249 es Fri May 18 15:13 -time - root 0.001 secs 0.000 us 0.001 sy 6.724 es Fri May 18 15:12 -egrep - root 6.680 secs 6.680 us 0.000 sy 6.722 es Fri May 18 15:12 -time - root 0.001 secs 0.000 us 0.001 sy 0.450 es Fri May 18 15:12 -awk - root 0.448 secs 0.448 us 0.000 sy 0.449 es Fri May 18 15:12 -accton - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 15:12 +core -FDX root 0.000 secs 0.000 us 0.000 sy 0.005 es Fri May 18 12:13 +core -DX root 0.002 secs 0.000 us 0.002 sy 0.005 es Fri May 18 12:13 +cc - root 0.002 secs 0.000 us 0.002 sy 0.048 es Fri May 18 12:13 +ld - root 0.028 secs 0.019 us 0.009 sy 0.028 es Fri May 18 12:13 +as - root 0.002 secs 0.002 us 0.000 sy 0.002 es Fri May 18 12:13 +cc1 - root 0.016 secs 0.016 us 0.000 sy 0.016 es Fri May 18 12:13 +time - root 0.001 secs 0.000 us 0.001 sy 0.002 es Fri May 18 12:13 +1234567890123456 - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 12:13 +ln - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 12:13 +time - root 0.001 secs 0.001 us 0.000 sy 0.002 es Fri May 18 12:13 +1234567890123456 - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 12:13 +ln - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 12:13 +time - root 0.001 secs 0.000 us 0.001 sy 0.002 es Fri May 18 12:13 +123456789012345 - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 12:13 +ln - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 12:13 +time - root 0.001 secs 0.000 us 0.001 sy 0.425 es Fri May 18 12:13 +diff - root 0.423 secs 0.392 us 0.031 sy 0.424 es Fri May 18 12:13 +time - root 0.001 secs 0.000 us 0.001 sy 0.028 es Fri May 18 12:13 +dd - root 0.025 secs 0.000 us 0.025 sy 0.026 es Fri May 18 12:13 +time - root 0.001 secs 0.000 us 0.001 sy 3.002 es Fri May 18 12:13 +sleep - root 0.001 secs 0.000 us 0.001 sy 3.001 es Fri May 18 12:13 +time - root 0.001 secs 0.000 us 0.001 sy 0.250 es Fri May 18 12:13 +find - root 0.248 secs 0.078 us 0.171 sy 0.249 es Fri May 18 12:13 +time - root 0.001 secs 0.000 us 0.001 sy 6.724 es Fri May 18 12:12 +egrep - root 6.680 secs 6.680 us 0.000 sy 6.722 es Fri May 18 12:12 +time - root 0.001 secs 0.000 us 0.001 sy 0.450 es Fri May 18 12:12 +awk - root 0.448 secs 0.448 us 0.000 sy 0.449 es Fri May 18 12:12 +accton - root 0.001 secs 0.000 us 0.001 sy 0.001 es Fri May 18 12:12 diff --git a/usr.bin/lorder/lorder.sh b/usr.bin/lorder/lorder.sh index 8123c96..4b6243c 100644 --- a/usr.bin/lorder/lorder.sh +++ b/usr.bin/lorder/lorder.sh @@ -73,6 +73,7 @@ ${NM} ${NMFLAGS} -go $* | sed " d " +export LC_ALL=C # eliminate references that can be resolved by the same library. if [ $(expr "$*" : '.*\.a[[:>:]]') -ne 0 ]; then sort -u -o $S $S diff --git a/usr.sbin/autofs/autounmountd.c b/usr.sbin/autofs/autounmountd.c index 02971cf..e64736b 100644 --- a/usr.sbin/autofs/autounmountd.c +++ b/usr.sbin/autofs/autounmountd.c @@ -161,7 +161,7 @@ unmount_by_fsid(const fsid_t fsid, const char *mountpoint) if (ret < 0) log_err(1, "asprintf"); - error = unmount(fsid_str, MNT_BYFSID); + error = unmount(fsid_str, MNT_NONBUSY | MNT_BYFSID); if (error != 0) { if (errno == EBUSY) { log_debugx("cannot unmount %s (%s): %s", diff --git a/usr.sbin/bhyve/Makefile b/usr.sbin/bhyve/Makefile index 7d2e2f0..f010f3d 100644 --- a/usr.sbin/bhyve/Makefile +++ b/usr.sbin/bhyve/Makefile @@ -14,9 +14,11 @@ BHYVE_SYSDIR?=${SRCTOP} SRCS= \ atkbdc.c \ acpi.c \ + bhyvegc.c \ bhyverun.c \ block_if.c \ bootrom.c \ + console.c \ consport.c \ dbgport.c \ fwctl.c \ @@ -27,6 +29,7 @@ SRCS= \ mptbl.c \ pci_ahci.c \ pci_emul.c \ + pci_fbuf.c \ pci_hostbridge.c \ pci_irq.c \ pci_lpc.c \ @@ -35,20 +38,30 @@ SRCS= \ pci_virtio_net.c \ pci_virtio_rnd.c \ pci_uart.c \ + pci_xhci.c \ pm.c \ post.c \ + ps2kbd.c \ + ps2mouse.c \ + rfb.c \ rtc.c \ smbiostbl.c \ + sockstream.c \ task_switch.c \ uart_emul.c \ + usb_emul.c \ + usb_mouse.c \ virtio.c \ + vga.c \ xmsr.c \ spinup_ap.c .PATH: ${BHYVE_SYSDIR}/sys/amd64/vmm SRCS+= vmm_instruction_emul.c -LIBADD= vmmapi md pthread +LIBADD= vmmapi md pthread z + +CFLAGS+= -I${BHYVE_SYSDIR}/sys/dev/usb/controller WARNS?= 2 diff --git a/usr.sbin/bhyve/atkbdc.c b/usr.sbin/bhyve/atkbdc.c index 930b7af..8e71b05 100644 --- a/usr.sbin/bhyve/atkbdc.c +++ b/usr.sbin/bhyve/atkbdc.c @@ -1,5 +1,6 @@ /*- * Copyright (c) 2014 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * Copyright (c) 2015 Nahanni Systems Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -35,56 +36,548 @@ __FBSDID("$FreeBSD$"); #include <assert.h> #include <errno.h> +#include <stdbool.h> +#include <stdlib.h> #include <stdio.h> +#include <string.h> +#include <unistd.h> +#include <pthread.h> +#include <pthread_np.h> +#include "acpi.h" #include "inout.h" +#include "pci_emul.h" +#include "pci_irq.h" #include "pci_lpc.h" +#include "ps2kbd.h" +#include "ps2mouse.h" #define KBD_DATA_PORT 0x60 #define KBD_STS_CTL_PORT 0x64 -#define KBD_SYS_FLAG 0x4 #define KBDC_RESET 0xfe +#define KBD_DEV_IRQ 1 +#define AUX_DEV_IRQ 12 + +/* controller commands */ +#define KBDC_SET_COMMAND_BYTE 0x60 +#define KBDC_GET_COMMAND_BYTE 0x20 +#define KBDC_DISABLE_AUX_PORT 0xa7 +#define KBDC_ENABLE_AUX_PORT 0xa8 +#define KBDC_TEST_AUX_PORT 0xa9 +#define KBDC_TEST_CTRL 0xaa +#define KBDC_TEST_KBD_PORT 0xab +#define KBDC_DISABLE_KBD_PORT 0xad +#define KBDC_ENABLE_KBD_PORT 0xae +#define KBDC_READ_INPORT 0xc0 +#define KBDC_READ_OUTPORT 0xd0 +#define KBDC_WRITE_OUTPORT 0xd1 +#define KBDC_WRITE_KBD_OUTBUF 0xd2 +#define KBDC_WRITE_AUX_OUTBUF 0xd3 +#define KBDC_WRITE_TO_AUX 0xd4 + +/* controller command byte (set by KBDC_SET_COMMAND_BYTE) */ +#define KBD_TRANSLATION 0x40 +#define KBD_SYS_FLAG_BIT 0x04 +#define KBD_DISABLE_KBD_PORT 0x10 +#define KBD_DISABLE_AUX_PORT 0x20 +#define KBD_ENABLE_AUX_INT 0x02 +#define KBD_ENABLE_KBD_INT 0x01 +#define KBD_KBD_CONTROL_BITS (KBD_DISABLE_KBD_PORT | KBD_ENABLE_KBD_INT) +#define KBD_AUX_CONTROL_BITS (KBD_DISABLE_AUX_PORT | KBD_ENABLE_AUX_INT) + +/* controller status bits */ +#define KBDS_KBD_BUFFER_FULL 0x01 +#define KBDS_SYS_FLAG 0x04 +#define KBDS_CTRL_FLAG 0x08 +#define KBDS_AUX_BUFFER_FULL 0x20 + +/* controller output port */ +#define KBDO_KBD_OUTFULL 0x10 +#define KBDO_AUX_OUTFULL 0x20 + +#define RAMSZ 32 +#define FIFOSZ 15 +#define CTRL_CMD_FLAG 0x8000 + +struct kbd_dev { + bool irq_active; + int irq; + + uint8_t buffer[FIFOSZ]; + int brd, bwr; + int bcnt; +}; + +struct aux_dev { + bool irq_active; + int irq; +}; + +struct atkbdc_softc { + struct vmctx *ctx; + pthread_mutex_t mtx; + + struct ps2kbd_softc *ps2kbd_sc; + struct ps2mouse_softc *ps2mouse_sc; + + uint8_t status; /* status register */ + uint8_t outport; /* controller output port */ + uint8_t ram[RAMSZ]; /* byte0 = controller config */ + + uint32_t curcmd; /* current command for next byte */ + uint32_t ctrlbyte; + + struct kbd_dev kbd; + struct aux_dev aux; +}; + +static void +atkbdc_assert_kbd_intr(struct atkbdc_softc *sc) +{ + if ((sc->ram[0] & KBD_ENABLE_KBD_INT) != 0) { + sc->kbd.irq_active = true; + vm_isa_pulse_irq(sc->ctx, sc->kbd.irq, sc->kbd.irq); + } +} + +static void +atkbdc_assert_aux_intr(struct atkbdc_softc *sc) +{ + if ((sc->ram[0] & KBD_ENABLE_AUX_INT) != 0) { + sc->aux.irq_active = true; + vm_isa_pulse_irq(sc->ctx, sc->aux.irq, sc->aux.irq); + } +} + +static int +atkbdc_kbd_queue_data(struct atkbdc_softc *sc, uint8_t val) +{ + assert(pthread_mutex_isowned_np(&sc->mtx)); + + if (sc->kbd.bcnt < FIFOSZ) { + sc->kbd.buffer[sc->kbd.bwr] = val; + sc->kbd.bwr = (sc->kbd.bwr + 1) % FIFOSZ; + sc->kbd.bcnt++; + sc->status |= KBDS_KBD_BUFFER_FULL; + sc->outport |= KBDO_KBD_OUTFULL; + } else { + printf("atkbd data buffer full\n"); + } + + return (sc->kbd.bcnt < FIFOSZ); +} + +static void +atkbdc_kbd_read(struct atkbdc_softc *sc) +{ + const uint8_t translation[256] = { + 0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, + 0x64, 0x44, 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, + 0x65, 0x38, 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a, + 0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b, + 0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c, + 0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, + 0x69, 0x31, 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, + 0x6a, 0x72, 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f, + 0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60, + 0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61, + 0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, + 0x3a, 0x36, 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, + 0x55, 0x56, 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b, + 0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f, + 0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45, + 0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54, + 0x80, 0x81, 0x82, 0x41, 0x54, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff + }; + uint8_t val; + uint8_t release = 0; + + assert(pthread_mutex_isowned_np(&sc->mtx)); + + if (sc->ram[0] & KBD_TRANSLATION) { + while (ps2kbd_read(sc->ps2kbd_sc, &val) != -1) { + if (val == 0xf0) { + release = 0x80; + continue; + } else { + val = translation[val] | release; + } + atkbdc_kbd_queue_data(sc, val); + break; + } + } else { + while (sc->kbd.bcnt < FIFOSZ) { + if (ps2kbd_read(sc->ps2kbd_sc, &val) != -1) + atkbdc_kbd_queue_data(sc, val); + else + break; + } + } + + if (((sc->ram[0] & KBD_DISABLE_AUX_PORT) || + ps2mouse_fifocnt(sc->ps2mouse_sc) == 0) && sc->kbd.bcnt > 0) + atkbdc_assert_kbd_intr(sc); +} + +static void +atkbdc_aux_poll(struct atkbdc_softc *sc) +{ + if (ps2mouse_fifocnt(sc->ps2mouse_sc) > 0) { + sc->status |= KBDS_AUX_BUFFER_FULL | KBDS_KBD_BUFFER_FULL; + sc->outport |= KBDO_AUX_OUTFULL; + atkbdc_assert_aux_intr(sc); + } +} + +static void +atkbdc_kbd_poll(struct atkbdc_softc *sc) +{ + assert(pthread_mutex_isowned_np(&sc->mtx)); + + atkbdc_kbd_read(sc); +} + +static void +atkbdc_poll(struct atkbdc_softc *sc) +{ + atkbdc_aux_poll(sc); + atkbdc_kbd_poll(sc); +} + +static void +atkbdc_dequeue_data(struct atkbdc_softc *sc, uint8_t *buf) +{ + assert(pthread_mutex_isowned_np(&sc->mtx)); + + if (ps2mouse_read(sc->ps2mouse_sc, buf) == 0) { + if (ps2mouse_fifocnt(sc->ps2mouse_sc) == 0) { + if (sc->kbd.bcnt == 0) + sc->status &= ~(KBDS_AUX_BUFFER_FULL | + KBDS_KBD_BUFFER_FULL); + else + sc->status &= ~(KBDS_AUX_BUFFER_FULL); + sc->outport &= ~KBDO_AUX_OUTFULL; + } + + atkbdc_poll(sc); + return; + } + + if (sc->kbd.bcnt > 0) { + *buf = sc->kbd.buffer[sc->kbd.brd]; + sc->kbd.brd = (sc->kbd.brd + 1) % FIFOSZ; + sc->kbd.bcnt--; + if (sc->kbd.bcnt == 0) { + sc->status &= ~KBDS_KBD_BUFFER_FULL; + sc->outport &= ~KBDO_KBD_OUTFULL; + } + + atkbdc_poll(sc); + } + + if (ps2mouse_fifocnt(sc->ps2mouse_sc) == 0 && sc->kbd.bcnt == 0) { + sc->status &= ~(KBDS_AUX_BUFFER_FULL | KBDS_KBD_BUFFER_FULL); + } +} + static int atkbdc_data_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, uint32_t *eax, void *arg) { + struct atkbdc_softc *sc; + uint8_t buf; + int retval; + if (bytes != 1) return (-1); + sc = arg; + retval = 0; + + pthread_mutex_lock(&sc->mtx); + if (in) { + sc->curcmd = 0; + if (sc->ctrlbyte != 0) { + *eax = sc->ctrlbyte & 0xff; + sc->ctrlbyte = 0; + } else { + /* read device buffer; includes kbd cmd responses */ + atkbdc_dequeue_data(sc, &buf); + *eax = buf; + } + + sc->status &= ~KBDS_CTRL_FLAG; + pthread_mutex_unlock(&sc->mtx); + return (retval); + } + + if (sc->status & KBDS_CTRL_FLAG) { + /* + * Command byte for the controller. + */ + switch (sc->curcmd) { + case KBDC_SET_COMMAND_BYTE: + sc->ram[0] = *eax; + if (sc->ram[0] & KBD_SYS_FLAG_BIT) + sc->status |= KBDS_SYS_FLAG; + else + sc->status &= ~KBDS_SYS_FLAG; + break; + case KBDC_WRITE_OUTPORT: + sc->outport = *eax; + break; + case KBDC_WRITE_TO_AUX: + ps2mouse_write(sc->ps2mouse_sc, *eax, 0); + atkbdc_poll(sc); + break; + case KBDC_WRITE_KBD_OUTBUF: + atkbdc_kbd_queue_data(sc, *eax); + break; + case KBDC_WRITE_AUX_OUTBUF: + ps2mouse_write(sc->ps2mouse_sc, *eax, 1); + sc->status |= (KBDS_AUX_BUFFER_FULL | KBDS_KBD_BUFFER_FULL); + atkbdc_aux_poll(sc); + break; + default: + /* write to particular RAM byte */ + if (sc->curcmd >= 0x61 && sc->curcmd <= 0x7f) { + int byten; + + byten = (sc->curcmd - 0x60) & 0x1f; + sc->ram[byten] = *eax & 0xff; + } + break; + } - *eax = 0; + sc->curcmd = 0; + sc->status &= ~KBDS_CTRL_FLAG; + + pthread_mutex_unlock(&sc->mtx); + return (retval); + } - return (0); + /* + * Data byte for the device. + */ + ps2kbd_write(sc->ps2kbd_sc, *eax); + atkbdc_poll(sc); + + pthread_mutex_unlock(&sc->mtx); + + return (retval); } static int atkbdc_sts_ctl_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, uint32_t *eax, void *arg) { - int error, retval; + struct atkbdc_softc *sc; + int error, retval; if (bytes != 1) return (-1); + sc = arg; retval = 0; + + pthread_mutex_lock(&sc->mtx); + if (in) { - *eax = KBD_SYS_FLAG; /* system passed POST */ - } else { - switch (*eax) { - case KBDC_RESET: /* Pulse "reset" line. */ - error = vm_suspend(ctx, VM_SUSPEND_RESET); - assert(error == 0 || errno == EALREADY); - break; + /* read status register */ + *eax = sc->status; + pthread_mutex_unlock(&sc->mtx); + return (retval); + } + + + sc->curcmd = 0; + sc->status |= KBDS_CTRL_FLAG; + sc->ctrlbyte = 0; + + switch (*eax) { + case KBDC_GET_COMMAND_BYTE: + sc->ctrlbyte = CTRL_CMD_FLAG | sc->ram[0]; + break; + case KBDC_TEST_CTRL: + sc->ctrlbyte = CTRL_CMD_FLAG | 0x55; + break; + case KBDC_TEST_AUX_PORT: + case KBDC_TEST_KBD_PORT: + sc->ctrlbyte = CTRL_CMD_FLAG | 0; + break; + case KBDC_READ_INPORT: + sc->ctrlbyte = CTRL_CMD_FLAG | 0; + break; + case KBDC_READ_OUTPORT: + sc->ctrlbyte = CTRL_CMD_FLAG | sc->outport; + break; + case KBDC_SET_COMMAND_BYTE: + case KBDC_WRITE_OUTPORT: + case KBDC_WRITE_KBD_OUTBUF: + case KBDC_WRITE_AUX_OUTBUF: + sc->curcmd = *eax; + break; + case KBDC_DISABLE_KBD_PORT: + sc->ram[0] |= KBD_DISABLE_KBD_PORT; + break; + case KBDC_ENABLE_KBD_PORT: + sc->ram[0] &= ~KBD_DISABLE_KBD_PORT; + if (sc->kbd.bcnt > 0) + sc->status |= KBDS_KBD_BUFFER_FULL; + atkbdc_poll(sc); + break; + case KBDC_WRITE_TO_AUX: + sc->curcmd = *eax; + break; + case KBDC_DISABLE_AUX_PORT: + sc->ram[0] |= KBD_DISABLE_AUX_PORT; + ps2mouse_toggle(sc->ps2mouse_sc, 0); + sc->status &= ~(KBDS_AUX_BUFFER_FULL | KBDS_KBD_BUFFER_FULL); + sc->outport &= ~KBDS_AUX_BUFFER_FULL; + break; + case KBDC_ENABLE_AUX_PORT: + sc->ram[0] &= ~KBD_DISABLE_AUX_PORT; + ps2mouse_toggle(sc->ps2mouse_sc, 1); + if (ps2mouse_fifocnt(sc->ps2mouse_sc) > 0) + sc->status |= KBDS_AUX_BUFFER_FULL | KBDS_KBD_BUFFER_FULL; + break; + case KBDC_RESET: /* Pulse "reset" line */ + error = vm_suspend(ctx, VM_SUSPEND_RESET); + assert(error == 0 || errno == EALREADY); + break; + default: + if (*eax >= 0x21 && *eax <= 0x3f) { + /* read "byte N" from RAM */ + int byten; + + byten = (*eax - 0x20) & 0x1f; + sc->ctrlbyte = CTRL_CMD_FLAG | sc->ram[byten]; } + break; + } + + pthread_mutex_unlock(&sc->mtx); + + if (sc->ctrlbyte != 0) { + sc->status |= KBDS_KBD_BUFFER_FULL; + sc->status &= ~KBDS_AUX_BUFFER_FULL; + atkbdc_assert_kbd_intr(sc); + } else if (ps2mouse_fifocnt(sc->ps2mouse_sc) > 0 && + (sc->ram[0] & KBD_DISABLE_AUX_PORT) == 0) { + sc->status |= KBDS_AUX_BUFFER_FULL | KBDS_KBD_BUFFER_FULL; + atkbdc_assert_aux_intr(sc); + } else if (sc->kbd.bcnt > 0 && (sc->ram[0] & KBD_DISABLE_KBD_PORT) == 0) { + sc->status |= KBDS_KBD_BUFFER_FULL; + atkbdc_assert_kbd_intr(sc); } return (retval); } -INOUT_PORT(atkdbc, KBD_DATA_PORT, IOPORT_F_INOUT, atkbdc_data_handler); -SYSRES_IO(KBD_DATA_PORT, 1); -INOUT_PORT(atkbdc, KBD_STS_CTL_PORT, IOPORT_F_INOUT, - atkbdc_sts_ctl_handler); -SYSRES_IO(KBD_STS_CTL_PORT, 1); +void +atkbdc_event(struct atkbdc_softc *sc, int iskbd) +{ + pthread_mutex_lock(&sc->mtx); + + if (iskbd) + atkbdc_kbd_poll(sc); + else + atkbdc_aux_poll(sc); + pthread_mutex_unlock(&sc->mtx); +} + +void +atkbdc_init(struct vmctx *ctx) +{ + struct inout_port iop; + struct atkbdc_softc *sc; + int error; + + sc = calloc(1, sizeof(struct atkbdc_softc)); + sc->ctx = ctx; + + pthread_mutex_init(&sc->mtx, NULL); + + bzero(&iop, sizeof(struct inout_port)); + iop.name = "atkdbc"; + iop.port = KBD_STS_CTL_PORT; + iop.size = 1; + iop.flags = IOPORT_F_INOUT; + iop.handler = atkbdc_sts_ctl_handler; + iop.arg = sc; + + error = register_inout(&iop); + assert(error == 0); + + bzero(&iop, sizeof(struct inout_port)); + iop.name = "atkdbc"; + iop.port = KBD_DATA_PORT; + iop.size = 1; + iop.flags = IOPORT_F_INOUT; + iop.handler = atkbdc_data_handler; + iop.arg = sc; + + error = register_inout(&iop); + assert(error == 0); + + pci_irq_reserve(KBD_DEV_IRQ); + sc->kbd.irq = KBD_DEV_IRQ; + + pci_irq_reserve(AUX_DEV_IRQ); + sc->aux.irq = AUX_DEV_IRQ; + + sc->ps2kbd_sc = ps2kbd_init(sc); + sc->ps2mouse_sc = ps2mouse_init(sc); +} + +static void +atkbdc_dsdt(void) +{ + + dsdt_line(""); + dsdt_line("Device (KBD)"); + dsdt_line("{"); + dsdt_line(" Name (_HID, EisaId (\"PNP0303\"))"); + dsdt_line(" Name (_CRS, ResourceTemplate ()"); + dsdt_line(" {"); + dsdt_indent(2); + dsdt_fixed_ioport(KBD_DATA_PORT, 1); + dsdt_fixed_ioport(KBD_STS_CTL_PORT, 1); + dsdt_fixed_irq(1); + dsdt_unindent(2); + dsdt_line(" })"); + dsdt_line("}"); + + dsdt_line(""); + dsdt_line("Device (MOU)"); + dsdt_line("{"); + dsdt_line(" Name (_HID, EisaId (\"PNP0F13\"))"); + dsdt_line(" Name (_CRS, ResourceTemplate ()"); + dsdt_line(" {"); + dsdt_indent(2); + dsdt_fixed_ioport(KBD_DATA_PORT, 1); + dsdt_fixed_ioport(KBD_STS_CTL_PORT, 1); + dsdt_fixed_irq(12); + dsdt_unindent(2); + dsdt_line(" })"); + dsdt_line("}"); +} +LPC_DSDT(atkbdc_dsdt); + diff --git a/usr.sbin/bhyve/atkbdc.h b/usr.sbin/bhyve/atkbdc.h new file mode 100644 index 0000000..85c8a71 --- /dev/null +++ b/usr.sbin/bhyve/atkbdc.h @@ -0,0 +1,38 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _ATKBDC_H_ +#define _ATKBDC_H_ + +struct atkbdc_softc; +struct vmctx; + +void atkbdc_init(struct vmctx *ctx); +void atkbdc_event(struct atkbdc_softc *sc, int iskbd); + +#endif /* _ATKBDC_H_ */ diff --git a/usr.sbin/bhyve/bhyvegc.c b/usr.sbin/bhyve/bhyvegc.c new file mode 100644 index 0000000..377b05b --- /dev/null +++ b/usr.sbin/bhyve/bhyvegc.c @@ -0,0 +1,72 @@ +#include <sys/cdefs.h> + +#include <sys/types.h> + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> + +#include "bhyvegc.h" + +struct bhyvegc { + struct bhyvegc_image *gc_image; + int raw; +}; + +struct bhyvegc * +bhyvegc_init(int width, int height, void *fbaddr) +{ + struct bhyvegc *gc; + struct bhyvegc_image *gc_image; + + gc = calloc(1, sizeof (struct bhyvegc)); + + gc_image = calloc(1, sizeof(struct bhyvegc_image)); + gc_image->width = width; + gc_image->height = height; + if (fbaddr) { + gc_image->data = fbaddr; + gc->raw = 1; + } else { + gc_image->data = calloc(width * height, sizeof (uint32_t)); + gc->raw = 0; + } + + gc->gc_image = gc_image; + + return (gc); +} + +void +bhyvegc_set_fbaddr(struct bhyvegc *gc, void *fbaddr) +{ + gc->raw = 1; + if (gc->gc_image->data && gc->gc_image->data != fbaddr) + free(gc->gc_image->data); + gc->gc_image->data = fbaddr; +} + +void +bhyvegc_resize(struct bhyvegc *gc, int width, int height) +{ + struct bhyvegc_image *gc_image; + + gc_image = gc->gc_image; + + gc_image->width = width; + gc_image->height = height; + if (!gc->raw) { + gc_image->data = realloc(gc_image->data, + sizeof (uint32_t) * width * height); + memset(gc_image->data, 0, width * height * sizeof (uint32_t)); + } +} + +struct bhyvegc_image * +bhyvegc_get_image(struct bhyvegc *gc) +{ + if (gc == NULL) + return (NULL); + + return (gc->gc_image); +} diff --git a/usr.sbin/bhyve/bhyvegc.h b/usr.sbin/bhyve/bhyvegc.h new file mode 100644 index 0000000..fa2ab68 --- /dev/null +++ b/usr.sbin/bhyve/bhyvegc.h @@ -0,0 +1,46 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _BHYVEGC_H_ +#define _BHYVEGC_H_ + +struct bhyvegc; + +struct bhyvegc_image { + int vgamode; + int width; + int height; + uint32_t *data; +}; + +struct bhyvegc *bhyvegc_init(int width, int height, void *fbaddr); +void bhyvegc_set_fbaddr(struct bhyvegc *gc, void *fbaddr); +void bhyvegc_resize(struct bhyvegc *gc, int width, int height); +struct bhyvegc_image *bhyvegc_get_image(struct bhyvegc *gc); + +#endif /* _BHYVEGC_H_ */ diff --git a/usr.sbin/bhyve/bhyverun.c b/usr.sbin/bhyve/bhyverun.c index 9350748..193b0d9 100644 --- a/usr.sbin/bhyve/bhyverun.c +++ b/usr.sbin/bhyve/bhyverun.c @@ -54,6 +54,7 @@ __FBSDID("$FreeBSD$"); #include "bhyverun.h" #include "acpi.h" +#include "atkbdc.h" #include "inout.h" #include "dbgport.h" #include "fwctl.h" @@ -125,7 +126,7 @@ usage(int code) fprintf(stderr, "Usage: %s [-abehuwxACHPSWY] [-c vcpus] [-g <gdb port>] [-l <lpc>]\n" - " %*s [-m memsize[K|k|M|m|G|g|T|t]] [-p vcpu:hostcpu] [-s <pci>] [-U uuid] <vm>\n" + " %*s [-m mem] [-p vcpu:hostcpu] [-s <pci>] [-U uuid] <vm>\n" " -a: local apic is in xAPIC mode (deprecated)\n" " -A: create ACPI tables\n" " -c: # cpus (default 1)\n" @@ -135,7 +136,7 @@ usage(int code) " -h: help\n" " -H: vmexit from the guest on hlt\n" " -l: LPC device configuration\n" - " -m: memory size\n" + " -m: memory size in MB\n" " -p: pin 'vcpu' to 'hostcpu'\n" " -P: vmexit from the guest on pause\n" " -s: <slot,driver,configinfo> PCI slot config\n" @@ -387,13 +388,11 @@ vmexit_wrmsr(struct vmctx *ctx, struct vm_exit *vme, int *pvcpu) static int vmexit_spinup_ap(struct vmctx *ctx, struct vm_exit *vme, int *pvcpu) { - int newcpu; - int retval = VMEXIT_CONTINUE; - newcpu = spinup_ap(ctx, *pvcpu, - vme->u.spinup_ap.vcpu, vme->u.spinup_ap.rip); + (void)spinup_ap(ctx, *pvcpu, + vme->u.spinup_ap.vcpu, vme->u.spinup_ap.rip); - return (retval); + return (VMEXIT_CONTINUE); } #define DEBUG_EPT_MISCONFIG @@ -901,6 +900,7 @@ main(int argc, char *argv[]) init_mem(); init_inout(); + atkbdc_init(ctx); pci_irq_init(ctx); ioapic_init(ctx); diff --git a/usr.sbin/bhyve/bhyverun.h b/usr.sbin/bhyve/bhyverun.h index c51bf48..39e115d 100644 --- a/usr.sbin/bhyve/bhyverun.h +++ b/usr.sbin/bhyve/bhyverun.h @@ -29,12 +29,6 @@ #ifndef _FBSDRUN_H_ #define _FBSDRUN_H_ -#ifndef CTASSERT /* Allow lint to override */ -#define CTASSERT(x) _CTASSERT(x, __LINE__) -#define _CTASSERT(x, y) __CTASSERT(x, y) -#define __CTASSERT(x, y) typedef char __assert ## y[(x) ? 1 : -1] -#endif - #define VMEXIT_CONTINUE (0) #define VMEXIT_ABORT (-1) diff --git a/usr.sbin/bhyve/console.c b/usr.sbin/bhyve/console.c new file mode 100644 index 0000000..ebb9c92 --- /dev/null +++ b/usr.sbin/bhyve/console.c @@ -0,0 +1,118 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> + +#include "bhyvegc.h" +#include "console.h" + +static struct { + struct bhyvegc *gc; + + fb_render_func_t fb_render_cb; + void *fb_arg; + + kbd_event_func_t kbd_event_cb; + void *kbd_arg; + int kbd_priority; + + ptr_event_func_t ptr_event_cb; + void *ptr_arg; + int ptr_priority; +} console; + +void +console_init(int w, int h, void *fbaddr) +{ + console.gc = bhyvegc_init(w, h, fbaddr); +} + +void +console_set_fbaddr(void *fbaddr) +{ + bhyvegc_set_fbaddr(console.gc, fbaddr); +} + +struct bhyvegc_image * +console_get_image(void) +{ + struct bhyvegc_image *bhyvegc_image; + + bhyvegc_image = bhyvegc_get_image(console.gc); + + return (bhyvegc_image); +} + +void +console_fb_register(fb_render_func_t render_cb, void *arg) +{ + console.fb_render_cb = render_cb; + console.fb_arg = arg; +} + +void +console_refresh(void) +{ + if (console.fb_render_cb) + (*console.fb_render_cb)(console.gc, console.fb_arg); +} + +void +console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri) +{ + if (pri > console.kbd_priority) { + console.kbd_event_cb = event_cb; + console.kbd_arg = arg; + console.kbd_priority = pri; + } +} + +void +console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri) +{ + if (pri > console.ptr_priority) { + console.ptr_event_cb = event_cb; + console.ptr_arg = arg; + console.ptr_priority = pri; + } +} + +void +console_key_event(int down, uint32_t keysym) +{ + if (console.kbd_event_cb) + (*console.kbd_event_cb)(down, keysym, console.kbd_arg); +} + +void +console_ptr_event(uint8_t button, int x, int y) +{ + if (console.ptr_event_cb) + (*console.ptr_event_cb)(button, x, y, console.ptr_arg); +} diff --git a/usr.sbin/bhyve/console.h b/usr.sbin/bhyve/console.h new file mode 100644 index 0000000..4719393 --- /dev/null +++ b/usr.sbin/bhyve/console.h @@ -0,0 +1,53 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _CONSOLE_H_ +#define _CONSOLE_H_ + +struct bhyvegc; + +typedef void (*fb_render_func_t)(struct bhyvegc *gc, void *arg); +typedef void (*kbd_event_func_t)(int down, uint32_t keysym, void *arg); +typedef void (*ptr_event_func_t)(uint8_t mask, int x, int y, void *arg); + +void console_init(int w, int h, void *fbaddr); + +void console_set_fbaddr(void *fbaddr); + +struct bhyvegc_image *console_get_image(void); + +void console_fb_register(fb_render_func_t render_cb, void *arg); +void console_refresh(void); + +void console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri); +void console_key_event(int down, uint32_t keysym); + +void console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri); +void console_ptr_event(uint8_t button, int x, int y); + +#endif /* _CONSOLE_H_ */ diff --git a/usr.sbin/bhyve/pci_ahci.c b/usr.sbin/bhyve/pci_ahci.c index 9acb0da..1cf6f10 100644 --- a/usr.sbin/bhyve/pci_ahci.c +++ b/usr.sbin/bhyve/pci_ahci.c @@ -1717,19 +1717,25 @@ static void ahci_handle_slot(struct ahci_port *p, int slot) { struct ahci_cmd_hdr *hdr; +#ifdef AHCI_DEBUG struct ahci_prdt_entry *prdt; +#endif struct pci_ahci_softc *sc; uint8_t *cfis; +#ifdef AHCI_DEBUG int cfl; +#endif sc = p->pr_sc; hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); +#ifdef AHCI_DEBUG cfl = (hdr->flags & 0x1f) * 4; +#endif cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); +#ifdef AHCI_DEBUG prdt = (struct ahci_prdt_entry *)(cfis + 0x80); -#ifdef AHCI_DEBUG DPRINTF("\ncfis:"); for (i = 0; i < cfl; i++) { if (i % 10 == 0) diff --git a/usr.sbin/bhyve/pci_emul.c b/usr.sbin/bhyve/pci_emul.c index 523d7b0..4767915 100644 --- a/usr.sbin/bhyve/pci_emul.c +++ b/usr.sbin/bhyve/pci_emul.c @@ -31,9 +31,9 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> #include <sys/linker_set.h> -#include <sys/errno.h> #include <ctype.h> +#include <errno.h> #include <pthread.h> #include <stdio.h> #include <stdlib.h> @@ -760,8 +760,6 @@ pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) { int mmc; - CTASSERT(sizeof(struct msicap) == 14); - /* Number of msi messages must be a power of 2 between 1 and 32 */ assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); mmc = ffs(msgnum) - 1; @@ -786,7 +784,6 @@ static void pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, uint32_t msix_tab_size) { - CTASSERT(sizeof(struct msixcap) == 12); assert(msix_tab_size % 4096 == 0); @@ -937,8 +934,6 @@ pci_emul_add_pciecap(struct pci_devinst *pi, int type) int err; struct pciecap pciecap; - CTASSERT(sizeof(struct pciecap) == 60); - if (type != PCIEM_TYPE_ROOT_PORT) return (-1); diff --git a/usr.sbin/bhyve/pci_emul.h b/usr.sbin/bhyve/pci_emul.h index d6e5490..d74950b 100644 --- a/usr.sbin/bhyve/pci_emul.h +++ b/usr.sbin/bhyve/pci_emul.h @@ -160,6 +160,7 @@ struct msicap { uint32_t addrhi; uint16_t msgdata; } __packed; +static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); struct msixcap { uint8_t capid; @@ -168,6 +169,7 @@ struct msixcap { uint32_t table_info; /* bar index and offset within it */ uint32_t pba_info; /* bar index and offset within it */ } __packed; +static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); struct pciecap { uint8_t capid; @@ -202,6 +204,7 @@ struct pciecap { uint16_t slot_control2; uint16_t slot_status2; } __packed; +static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, int ioapic_irq, void *arg); diff --git a/usr.sbin/bhyve/pci_fbuf.c b/usr.sbin/bhyve/pci_fbuf.c new file mode 100644 index 0000000..22ec86c --- /dev/null +++ b/usr.sbin/bhyve/pci_fbuf.c @@ -0,0 +1,406 @@ +/*- + * Copyright (c) 2015 Nahanni Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <sys/mman.h> + +#include <machine/vmm.h> +#include <vmmapi.h> + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <errno.h> +#include <unistd.h> + +#include "bhyvegc.h" +#include "bhyverun.h" +#include "console.h" +#include "inout.h" +#include "pci_emul.h" +#include "rfb.h" +#include "vga.h" + +/* + * bhyve Framebuffer device emulation. + * BAR0 points to the current mode information. + * BAR1 is the 32-bit framebuffer address. + * + * -s <b>,fbuf,wait,tcp=<ip>:port,w=width,h=height + */ + +static int fbuf_debug = 1; +#define DEBUG_INFO 1 +#define DEBUG_VERBOSE 4 +#define DPRINTF(level, params) if (level <= fbuf_debug) printf params + + +#define KB (1024UL) +#define MB (1024 * 1024UL) + +#define DMEMSZ 128 + +#define FB_SIZE (16*MB) + +#define COLS_MAX 1920 +#define ROWS_MAX 1200 + +#define COLS_DEFAULT 1024 +#define ROWS_DEFAULT 768 + +#define COLS_MIN 640 +#define ROWS_MIN 480 + +struct pci_fbuf_softc { + struct pci_devinst *fsc_pi; + struct { + uint32_t fbsize; + uint16_t width; + uint16_t height; + uint16_t depth; + uint16_t refreshrate; + uint8_t reserved[116]; + } __packed memregs; + + /* rfb server */ + char *rfb_host; + int rfb_port; + int rfb_wait; + int use_vga; + + uint32_t fbaddr; + char *fb_base; + uint16_t gc_width; + uint16_t gc_height; + void *vgasc; + struct bhyvegc_image *gc_image; +}; + +static struct pci_fbuf_softc *fbuf_sc; + +#define PCI_FBUF_MSI_MSGS 4 + +static void +pci_fbuf_usage(char *opt) +{ + + fprintf(stderr, "Invalid fbuf emulation \"%s\"\r\n", opt); + fprintf(stderr, "fbuf: {wait,}tcp=<ip>:port\r\n"); +} + +static void +pci_fbuf_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, + int baridx, uint64_t offset, int size, uint64_t value) +{ + struct pci_fbuf_softc *sc; + uint8_t *p; + + assert(baridx == 0); + + sc = pi->pi_arg; + + DPRINTF(DEBUG_VERBOSE, + ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx\n", + offset, size, value)); + + if (offset + size > DMEMSZ) { + printf("fbuf: write too large, offset %ld size %d\n", + offset, size); + return; + } + + p = (uint8_t *)&sc->memregs + offset; + + switch (size) { + case 1: + *p = value; + break; + case 2: + *(uint16_t *)p = value; + break; + case 4: + *(uint32_t *)p = value; + break; + case 8: + *(uint64_t *)p = value; + break; + default: + printf("fbuf: write unknown size %d\n", size); + break; + } + + if (!sc->gc_image->vgamode && sc->memregs.width == 0 && + sc->memregs.height == 0) { + DPRINTF(DEBUG_INFO, ("switching to VGA mode\r\n")); + sc->gc_image->vgamode = 1; + sc->gc_width = 0; + sc->gc_height = 0; + } else if (sc->gc_image->vgamode && sc->memregs.width != 0 && + sc->memregs.height != 0) { + DPRINTF(DEBUG_INFO, ("switching to VESA mode\r\n")); + sc->gc_image->vgamode = 0; + } +} + +uint64_t +pci_fbuf_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, + int baridx, uint64_t offset, int size) +{ + struct pci_fbuf_softc *sc; + uint8_t *p; + uint64_t value; + + assert(baridx == 0); + + sc = pi->pi_arg; + + + if (offset + size > DMEMSZ) { + printf("fbuf: read too large, offset %ld size %d\n", + offset, size); + return (0); + } + + p = (uint8_t *)&sc->memregs + offset; + value = 0; + switch (size) { + case 1: + value = *p; + break; + case 2: + value = *(uint16_t *)p; + break; + case 4: + value = *(uint32_t *)p; + break; + case 8: + value = *(uint64_t *)p; + break; + default: + printf("fbuf: read unknown size %d\n", size); + break; + } + + DPRINTF(DEBUG_VERBOSE, + ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx\n", + offset, size, value)); + + return (value); +} + +static int +pci_fbuf_parse_opts(struct pci_fbuf_softc *sc, char *opts) +{ + char *uopts, *xopts, *config; + char *tmpstr; + int ret; + + ret = 0; + uopts = strdup(opts); + for (xopts = strtok(uopts, ","); + xopts != NULL; + xopts = strtok(NULL, ",")) { + if (strcmp(xopts, "wait") == 0) { + sc->rfb_wait = 1; + continue; + } + +#if 0 /* notyet */ + if (strcmp(xopts, "vga") == 0) { + sc->use_vga = 1; + continue; + } +#endif + + if ((config = strchr(xopts, '=')) == NULL) { + pci_fbuf_usage(xopts); + ret = -1; + goto done; + } + + *config++ = '\0'; + + DPRINTF(DEBUG_VERBOSE, ("pci_fbuf option %s = %s\r\n", + xopts, config)); + + if (!strcmp(xopts, "tcp")) { + /* parse host-ip:port */ + tmpstr = strsep(&config, ":"); + if (!config) + sc->rfb_port = atoi(tmpstr); + else { + sc->rfb_port = atoi(config); + sc->rfb_host = tmpstr; + } + } else if (!strcmp(xopts, "w")) { + sc->memregs.width = atoi(config); + if (sc->memregs.width > COLS_MAX) { + pci_fbuf_usage(xopts); + ret = -1; + goto done; + } else if (sc->memregs.width == 0) + sc->memregs.width = 1920; + } else if (!strcmp(xopts, "h")) { + sc->memregs.height = atoi(config); + if (sc->memregs.height > ROWS_MAX) { + pci_fbuf_usage(xopts); + ret = -1; + goto done; + } else if (sc->memregs.height == 0) + sc->memregs.height = 1080; + + } else { + pci_fbuf_usage(xopts); + ret = -1; + goto done; + } + } + +done: + return (ret); +} + + +extern void vga_render(struct bhyvegc *gc, void *arg); + +void +pci_fbuf_render(struct bhyvegc *gc, void *arg) +{ + struct pci_fbuf_softc *sc; + + sc = arg; + + if (sc->use_vga && sc->gc_image->vgamode) { + /* TODO: mode switching to vga and vesa should use the special + * EFI-bhyve protocol port. + */ + vga_render(gc, sc->vgasc); + return; + } + if (sc->gc_width != sc->memregs.width || + sc->gc_height != sc->memregs.height) { + bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height); + sc->gc_width = sc->memregs.width; + sc->gc_height = sc->memregs.height; + } + + return; +} + +static int +pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) +{ + int error, prot; + struct pci_fbuf_softc *sc; + + if (fbuf_sc != NULL) { + fprintf(stderr, "Only one frame buffer device is allowed.\n"); + return (-1); + } + + sc = calloc(1, sizeof(struct pci_fbuf_softc)); + + pi->pi_arg = sc; + + /* initialize config space */ + pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB); + pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D); + pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY); + pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA); + + error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ); + assert(error == 0); + + error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE); + assert(error == 0); + + error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS); + assert(error == 0); + + sc->fbaddr = pi->pi_bar[1].addr; + sc->memregs.fbsize = FB_SIZE; + sc->memregs.width = COLS_DEFAULT; + sc->memregs.height = ROWS_DEFAULT; + sc->memregs.depth = 32; + + sc->fsc_pi = pi; + + error = pci_fbuf_parse_opts(sc, opts); + if (error != 0) + goto done; + + sc->fb_base = vm_create_devmem(ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE); + if (sc->fb_base == MAP_FAILED) { + error = -1; + goto done; + } + DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]\r\n", + sc->fb_base, FB_SIZE)); + + /* + * Map the framebuffer into the guest address space. + * XXX This may fail if the BAR is different than a prior + * run. In this case flag the error. This will be fixed + * when a change_memseg api is available. + */ + prot = PROT_READ | PROT_WRITE; + if (vm_mmap_memseg(ctx, sc->fbaddr, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0) { + fprintf(stderr, "pci_fbuf: mapseg failed - try deleting VM and restarting\n"); + error = -1; + goto done; + } + + console_init(sc->memregs.width, sc->memregs.height, sc->fb_base); + console_fb_register(pci_fbuf_render, sc); + + sc->vgasc = vga_init(!sc->use_vga); + sc->gc_image = console_get_image(); + + fbuf_sc = sc; + + memset((void *)sc->fb_base, 0, FB_SIZE); + + error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait); +done: + if (error) + free(sc); + + return (error); +} + +struct pci_devemu pci_fbuf = { + .pe_emu = "fbuf", + .pe_init = pci_fbuf_init, + .pe_barwrite = pci_fbuf_write, + .pe_barread = pci_fbuf_read +}; +PCI_EMUL_SET(pci_fbuf); diff --git a/usr.sbin/bhyve/pci_passthru.c b/usr.sbin/bhyve/pci_passthru.c index 78c1eae..970fbab 100644 --- a/usr.sbin/bhyve/pci_passthru.c +++ b/usr.sbin/bhyve/pci_passthru.c @@ -361,7 +361,7 @@ msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc, uint64_t *dest64; size_t entry_offset; uint32_t vector_control; - int error, index; + int index; pi = sc->psc_pi; if (offset >= pi->pi_msix.pba_offset && @@ -416,8 +416,8 @@ msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc, /* If the entry is masked, don't set it up */ if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 || (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { - error = vm_setup_pptdev_msix(ctx, vcpu, - sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, + (void)vm_setup_pptdev_msix(ctx, vcpu, + sc->psc_sel.pc_bus, sc->psc_sel.pc_dev, sc->psc_sel.pc_func, index, entry->addr, entry->msg_data, entry->vector_control); } diff --git a/usr.sbin/bhyve/pci_xhci.c b/usr.sbin/bhyve/pci_xhci.c new file mode 100644 index 0000000..805c4cc --- /dev/null +++ b/usr.sbin/bhyve/pci_xhci.c @@ -0,0 +1,2823 @@ +/*- + * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + XHCI options: + -s <n>,xhci,{devices} + + devices: + ums USB tablet mouse + */ +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/uio.h> +#include <sys/types.h> +#include <sys/queue.h> + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <errno.h> +#include <pthread.h> +#include <unistd.h> + +#include <dev/usb/usbdi.h> +#include <dev/usb/usb.h> +#include <dev/usb/usb_freebsd.h> +#include <xhcireg.h> + +#include "bhyverun.h" +#include "pci_emul.h" +#include "pci_xhci.h" +#include "usb_emul.h" + + +static int xhci_debug = 0; +#define DPRINTF(params) if (xhci_debug) printf params +#define WPRINTF(params) printf params + + +#define XHCI_NAME "xhci" +#define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */ + +#define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */ + +/* + * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping + * to 4k to avoid going over the guest physical memory barrier. + */ +#define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */ + +#define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */ + +#define XHCI_CAPLEN (4*8) /* offset of op register space */ +#define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */ +#define XHCI_PORTREGS_START 0x400 +#define XHCI_DOORBELL_MAX 256 + +#define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */ + +/* caplength and hci-version registers */ +#define XHCI_SET_CAPLEN(x) ((x) & 0xFF) +#define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16) +#define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF) + +/* hcsparams1 register */ +#define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF) +#define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8) +#define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24) + +/* hcsparams2 register */ +#define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F) +#define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4) +#define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21) +#define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27) + +/* hcsparams3 register */ +#define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF) +#define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16) + +/* hccparams1 register */ +#define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01) +#define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1) +#define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2) +#define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3) +#define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4) +#define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5) +#define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6) +#define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7) +#define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8) +#define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9) +#define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10) +#define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11) +#define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12) +#define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16) + +/* hccparams2 register */ +#define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01) +#define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1) +#define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2) +#define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3) +#define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4) +#define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5) + +/* other registers */ +#define XHCI_SET_DOORBELL(x) ((x) & ~0x03) +#define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F) + +/* register masks */ +#define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */ +#define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */ +#define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */ + +/* port register set */ +#define XHCI_PORTREGS_BASE 0x400 /* base offset */ +#define XHCI_PORTREGS_PORT0 0x3F0 +#define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */ + +#define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL) +#define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL) + +#define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \ + (((b) & (m)) << (s))) +#define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \ + (((b) & ((m) << (s))))) + +struct pci_xhci_trb_ring { + uint64_t ringaddr; /* current dequeue guest address */ + uint32_t ccs; /* consumer cycle state */ +}; + +/* device endpoint transfer/stream rings */ +struct pci_xhci_dev_ep { + union { + struct xhci_trb *_epu_tr; + struct xhci_stream_ctx *_epu_sctx; + } _ep_trbsctx; +#define ep_tr _ep_trbsctx._epu_tr +#define ep_sctx _ep_trbsctx._epu_sctx + + union { + struct pci_xhci_trb_ring _epu_trb; + struct pci_xhci_trb_ring *_epu_sctx_trbs; + } _ep_trb_rings; +#define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr +#define ep_ccs _ep_trb_rings._epu_trb.ccs +#define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs + + struct usb_data_xfer *ep_xfer; /* transfer chain */ +}; + +/* device context base address array: maps slot->device context */ +struct xhci_dcbaa { + uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */ +}; + +/* port status registers */ +struct pci_xhci_portregs { + uint32_t portsc; /* port status and control */ + uint32_t portpmsc; /* port pwr mgmt status & control */ + uint32_t portli; /* port link info */ + uint32_t porthlpmc; /* port hardware LPM control */ +} __packed; +#define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10) + +/* xHC operational registers */ +struct pci_xhci_opregs { + uint32_t usbcmd; /* usb command */ + uint32_t usbsts; /* usb status */ + uint32_t pgsz; /* page size */ + uint32_t dnctrl; /* device notification control */ + uint64_t crcr; /* command ring control */ + uint64_t dcbaap; /* device ctx base addr array ptr */ + uint32_t config; /* configure */ + + /* guest mapped addresses: */ + struct xhci_trb *cr_p; /* crcr dequeue */ + struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */ +}; + +/* xHC runtime registers */ +struct pci_xhci_rtsregs { + uint32_t mfindex; /* microframe index */ + struct { /* interrupter register set */ + uint32_t iman; /* interrupter management */ + uint32_t imod; /* interrupter moderation */ + uint32_t erstsz; /* event ring segment table size */ + uint32_t rsvd; + uint64_t erstba; /* event ring seg-tbl base addr */ + uint64_t erdp; /* event ring dequeue ptr */ + } intrreg __packed; + + /* guest mapped addresses */ + struct xhci_event_ring_seg *erstba_p; + struct xhci_trb *erst_p; /* event ring segment tbl */ + int er_deq_seg; /* event ring dequeue segment */ + int er_enq_idx; /* event ring enqueue index - xHCI */ + int er_enq_seg; /* event ring enqueue segment */ + uint32_t er_events_cnt; /* number of events in ER */ + uint32_t event_pcs; /* producer cycle state flag */ +}; + + +struct pci_xhci_softc; + + +/* + * USB device emulation container. + * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each + * emulated device instance. + */ +struct pci_xhci_dev_emu { + struct pci_xhci_softc *xsc; + + /* XHCI contexts */ + struct xhci_dev_ctx *dev_ctx; + struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS]; + int dev_slotstate; + + struct usb_devemu *dev_ue; /* USB emulated dev */ + void *dev_sc; /* device's softc */ + + struct usb_hci hci; +}; + +struct pci_xhci_softc { + struct pci_devinst *xsc_pi; + + pthread_mutex_t mtx; + + uint32_t caplength; /* caplen & hciversion */ + uint32_t hcsparams1; /* structural parameters 1 */ + uint32_t hcsparams2; /* structural parameters 2 */ + uint32_t hcsparams3; /* structural parameters 3 */ + uint32_t hccparams1; /* capability parameters 1 */ + uint32_t dboff; /* doorbell offset */ + uint32_t rtsoff; /* runtime register space offset */ + uint32_t hccparams2; /* capability parameters 2 */ + + uint32_t regsend; /* end of configuration registers */ + + struct pci_xhci_opregs opregs; + struct pci_xhci_rtsregs rtsregs; + + struct pci_xhci_portregs *portregs; + struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */ + struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */ + int ndevices; + + int usb2_port_start; + int usb3_port_start; +}; + + +/* portregs and devices arrays are set up to start from idx=1 */ +#define XHCI_PORTREG_PTR(x,n) &(x)->portregs[(n)] +#define XHCI_DEVINST_PTR(x,n) (x)->devices[(n)] +#define XHCI_SLOTDEV_PTR(x,n) (x)->slots[(n)] + +#define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH) + +#define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \ + (a), \ + XHCI_PADDR_SZ - ((a) & (XHCI_PADDR_SZ-1))) + +static int xhci_in_use; + +/* map USB errors to XHCI */ +static const int xhci_usb_errors[USB_ERR_MAX] = { + [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS, + [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE, + [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON, + [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID, + [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE, + [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED, + [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER, + [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER, + [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER, + [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL, + [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE, + [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE, + [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE, + [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED, + [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED, + [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE, + [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON, + [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE, + [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB, + [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON, + [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED, + [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT, + [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL, + [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED, + [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF, + [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB, + [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED, + [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED, + [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED, +}; +#define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \ + XHCI_TRB_ERROR_INVALID) + +static int pci_xhci_insert_event(struct pci_xhci_softc *sc, + struct xhci_trb *evtrb, int do_intr); +static void pci_xhci_dump_trb(struct xhci_trb *trb); +static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc); +static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot); +static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm); +static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, + struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, + struct xhci_endp_ctx *ep_ctx, uint32_t streamid, + uint64_t ringaddr, int ccs); + +static void +pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode, + uint32_t evtype) +{ + evtrb->qwTrb0 = port << 24; + evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode); + evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype); +} + + +/* controller reset */ +static void +pci_xhci_reset(struct pci_xhci_softc *sc) +{ + int i; + + sc->rtsregs.er_enq_idx = 0; + sc->rtsregs.er_events_cnt = 0; + sc->rtsregs.event_pcs = 1; + + for (i = 1; i <= XHCI_MAX_SLOTS; i++) { + pci_xhci_reset_slot(sc, i); + } +} + +static uint32_t +pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd) +{ + int do_intr = 0; + int i; + + if (cmd & XHCI_CMD_RS) { + do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0; + + sc->opregs.usbcmd |= XHCI_CMD_RS; + sc->opregs.usbsts &= ~XHCI_STS_HCH; + sc->opregs.usbsts |= XHCI_STS_PCD; + + /* Queue port change event on controller run from stop */ + if (do_intr) + for (i = 1; i <= XHCI_MAX_DEVS; i++) { + struct pci_xhci_dev_emu *dev; + struct pci_xhci_portregs *port; + struct xhci_trb evtrb; + + if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL) + continue; + + port = XHCI_PORTREG_PTR(sc, i); + port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS; + port->portsc &= ~XHCI_PS_PLS_MASK; + + /* + * XHCI 4.19.3 USB2 RxDetect->Polling, + * USB3 Polling->U0 + */ + if (dev->dev_ue->ue_usbver == 2) + port->portsc |= + XHCI_PS_PLS_SET(UPS_PORT_LS_POLL); + else + port->portsc |= + XHCI_PS_PLS_SET(UPS_PORT_LS_U0); + + pci_xhci_set_evtrb(&evtrb, i, + XHCI_TRB_ERROR_SUCCESS, + XHCI_TRB_EVENT_PORT_STS_CHANGE); + + if (pci_xhci_insert_event(sc, &evtrb, 0) != + XHCI_TRB_ERROR_SUCCESS) + break; + } + } else { + sc->opregs.usbcmd &= ~XHCI_CMD_RS; + sc->opregs.usbsts |= XHCI_STS_HCH; + sc->opregs.usbsts &= ~XHCI_STS_PCD; + } + + /* start execution of schedule; stop when set to 0 */ + cmd |= sc->opregs.usbcmd & XHCI_CMD_RS; + + if (cmd & XHCI_CMD_HCRST) { + /* reset controller */ + pci_xhci_reset(sc); + cmd &= ~XHCI_CMD_HCRST; + } + + cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS); + + if (do_intr) + pci_xhci_assert_interrupt(sc); + + return (cmd); +} + +static void +pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset, + uint64_t value) +{ + struct xhci_trb evtrb; + struct pci_xhci_portregs *p; + int port; + uint32_t oldpls, newpls; + + if (sc->portregs == NULL) + return; + + port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ; + offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ; + + DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx\r\n", + offset, port, value)); + + assert(port >= 0); + + if (port > XHCI_MAX_DEVS) { + DPRINTF(("pci_xhci: portregs_write port %d > ndevices\r\n", + port)); + return; + } + + if (XHCI_DEVINST_PTR(sc, port) == NULL) { + DPRINTF(("pci_xhci: portregs_write to unattached port %d\r\n", + port)); + } + + p = XHCI_PORTREG_PTR(sc, port); + switch (offset) { + case 0: + /* port reset or warm reset */ + if (value & (XHCI_PS_PR | XHCI_PS_WPR)) { + pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR); + break; + } + + if ((p->portsc & XHCI_PS_PP) == 0) { + WPRINTF(("pci_xhci: portregs_write to unpowered " + "port %d\r\n", port)); + break; + } + + /* Port status and control register */ + oldpls = XHCI_PS_PLS_GET(p->portsc); + newpls = XHCI_PS_PLS_GET(value); + + p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK | + XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK; + + if (XHCI_DEVINST_PTR(sc, port)) + p->portsc |= XHCI_PS_CCS; + + p->portsc |= (value & + ~(XHCI_PS_OCA | + XHCI_PS_PR | + XHCI_PS_PED | + XHCI_PS_PLS_MASK | /* link state */ + XHCI_PS_SPEED_MASK | + XHCI_PS_PIC_MASK | /* port indicator */ + XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR)); + + /* clear control bits */ + p->portsc &= ~(value & + (XHCI_PS_CSC | + XHCI_PS_PEC | + XHCI_PS_WRC | + XHCI_PS_OCC | + XHCI_PS_PRC | + XHCI_PS_PLC | + XHCI_PS_CEC | + XHCI_PS_CAS)); + + /* port disable request; for USB3, don't care */ + if (value & XHCI_PS_PED) + DPRINTF(("Disable port %d request\r\n", port)); + + if (!(value & XHCI_PS_LWS)) + break; + + DPRINTF(("Port new PLS: %d\r\n", newpls)); + switch (newpls) { + case 0: /* U0 */ + case 3: /* U3 */ + if (oldpls != newpls) { + p->portsc &= ~XHCI_PS_PLS_MASK; + p->portsc |= XHCI_PS_PLS_SET(newpls) | + XHCI_PS_PLC; + + if (oldpls != 0 && newpls == 0) { + pci_xhci_set_evtrb(&evtrb, port, + XHCI_TRB_ERROR_SUCCESS, + XHCI_TRB_EVENT_PORT_STS_CHANGE); + + pci_xhci_insert_event(sc, &evtrb, 1); + } + } + break; + + default: + DPRINTF(("Unhandled change port %d PLS %u\r\n", + port, newpls)); + break; + } + break; + case 4: + /* Port power management status and control register */ + p->portpmsc = value; + break; + case 8: + /* Port link information register */ + DPRINTF(("pci_xhci attempted write to PORTLI, port %d\r\n", + port)); + break; + case 12: + /* + * Port hardware LPM control register. + * For USB3, this register is reserved. + */ + p->porthlpmc = value; + break; + } +} + +struct xhci_dev_ctx * +pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot) +{ + uint64_t devctx_addr; + struct xhci_dev_ctx *devctx; + + assert(slot > 0 && slot <= sc->ndevices); + assert(sc->opregs.dcbaa_p != NULL); + + devctx_addr = sc->opregs.dcbaa_p->dcba[slot]; + + if (devctx_addr == 0) { + DPRINTF(("get_dev_ctx devctx_addr == 0\r\n")); + return (NULL); + } + + DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx\r\n", + slot, devctx_addr)); + devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL); + + return (devctx); +} + +struct xhci_trb * +pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb, + uint64_t *guestaddr) +{ + struct xhci_trb *next; + + assert(curtrb != NULL); + + if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) { + if (guestaddr) + *guestaddr = curtrb->qwTrb0 & ~0xFUL; + + next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL); + } else { + if (guestaddr) + *guestaddr += sizeof(struct xhci_trb) & ~0xFUL; + + next = curtrb + 1; + } + + return (next); +} + +static void +pci_xhci_assert_interrupt(struct pci_xhci_softc *sc) +{ + + sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY; + sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND; + sc->opregs.usbsts |= XHCI_STS_EINT; + + /* only trigger interrupt if permitted */ + if ((sc->opregs.usbcmd & XHCI_CMD_INTE) && + (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) { + if (pci_msi_enabled(sc->xsc_pi)) + pci_generate_msi(sc->xsc_pi, 0); + else + pci_lintr_assert(sc->xsc_pi); + } +} + +static void +pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc) +{ + + if (!pci_msi_enabled(sc->xsc_pi)) + pci_lintr_assert(sc->xsc_pi); +} + +static void +pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid) +{ + struct xhci_dev_ctx *dev_ctx; + struct pci_xhci_dev_ep *devep; + struct xhci_endp_ctx *ep_ctx; + uint32_t pstreams; + int i; + + dev_ctx = dev->dev_ctx; + ep_ctx = &dev_ctx->ctx_ep[epid]; + devep = &dev->eps[epid]; + pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0); + if (pstreams > 0) { + DPRINTF(("init_ep %d with pstreams %d\r\n", epid, pstreams)); + assert(devep->ep_sctx_trbs == NULL); + + devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 & + XHCI_EPCTX_2_TR_DQ_PTR_MASK); + devep->ep_sctx_trbs = calloc(pstreams, + sizeof(struct pci_xhci_trb_ring)); + for (i = 0; i < pstreams; i++) { + devep->ep_sctx_trbs[i].ringaddr = + devep->ep_sctx[i].qwSctx0 & + XHCI_SCTX_0_TR_DQ_PTR_MASK; + devep->ep_sctx_trbs[i].ccs = + XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0); + } + } else { + DPRINTF(("init_ep %d with no pstreams\r\n", epid)); + devep->ep_ringaddr = ep_ctx->qwEpCtx2 & + XHCI_EPCTX_2_TR_DQ_PTR_MASK; + devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2); + devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr); + DPRINTF(("init_ep tr DCS %x\r\n", devep->ep_ccs)); + } + + if (devep->ep_xfer == NULL) { + devep->ep_xfer = malloc(sizeof(struct usb_data_xfer)); + USB_DATA_XFER_INIT(devep->ep_xfer); + } +} + +static void +pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid) +{ + struct xhci_dev_ctx *dev_ctx; + struct pci_xhci_dev_ep *devep; + struct xhci_endp_ctx *ep_ctx; + + DPRINTF(("pci_xhci disable_ep %d\r\n", epid)); + + dev_ctx = dev->dev_ctx; + ep_ctx = &dev_ctx->ctx_ep[epid]; + ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED; + + devep = &dev->eps[epid]; + if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) > 0 && + devep->ep_sctx_trbs != NULL) + free(devep->ep_sctx_trbs); + + if (devep->ep_xfer != NULL) { + free(devep->ep_xfer); + devep->ep_xfer = NULL; + } + + memset(devep, 0, sizeof(struct pci_xhci_dev_ep)); +} + + +/* reset device at slot and data structures related to it */ +static void +pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot) +{ + struct pci_xhci_dev_emu *dev; + + dev = XHCI_SLOTDEV_PTR(sc, slot); + + if (!dev) { + DPRINTF(("xhci reset unassigned slot (%d)?\r\n", slot)); + } else { + dev->dev_slotstate = XHCI_ST_DISABLED; + } + + /* TODO: reset ring buffer pointers */ +} + +static int +pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb, + int do_intr) +{ + struct pci_xhci_rtsregs *rts; + uint64_t erdp; + int erdp_idx; + int err; + struct xhci_trb *evtrbptr; + + err = XHCI_TRB_ERROR_SUCCESS; + + rts = &sc->rtsregs; + + erdp = rts->intrreg.erdp & ~0xF; + erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) / + sizeof(struct xhci_trb); + + DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]\r\n" + "\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u\r\n" + "\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)\r\n", + evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3, + erdp_idx, rts->er_deq_seg, rts->er_enq_idx, + rts->er_enq_seg, + rts->event_pcs, erdp, rts->erstba_p->qwEvrsTablePtr, + rts->erstba_p->dwEvrsTableSize, do_intr)); + + evtrbptr = &rts->erst_p[rts->er_enq_idx]; + + /* TODO: multi-segment table */ + if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) { + DPRINTF(("pci_xhci[%d] cannot insert event; ring full\r\n", + __LINE__)); + err = XHCI_TRB_ERROR_EV_RING_FULL; + goto done; + } + + if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) { + struct xhci_trb errev; + + if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) { + + DPRINTF(("pci_xhci[%d] insert evt err: ring full\r\n", + __LINE__)); + + errev.qwTrb0 = 0; + errev.dwTrb2 = XHCI_TRB_2_ERROR_SET( + XHCI_TRB_ERROR_EV_RING_FULL); + errev.dwTrb3 = XHCI_TRB_3_TYPE_SET( + XHCI_TRB_EVENT_HOST_CTRL) | + rts->event_pcs; + rts->er_events_cnt++; + memcpy(&rts->erst_p[rts->er_enq_idx], &errev, + sizeof(struct xhci_trb)); + rts->er_enq_idx = (rts->er_enq_idx + 1) % + rts->erstba_p->dwEvrsTableSize; + err = XHCI_TRB_ERROR_EV_RING_FULL; + do_intr = 1; + + goto done; + } + } else { + rts->er_events_cnt++; + } + + evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT; + evtrb->dwTrb3 |= rts->event_pcs; + + memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb)); + rts->er_enq_idx = (rts->er_enq_idx + 1) % + rts->erstba_p->dwEvrsTableSize; + + if (rts->er_enq_idx == 0) + rts->event_pcs ^= 1; + +done: + if (do_intr) + pci_xhci_assert_interrupt(sc); + + return (err); +} + +static uint32_t +pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot) +{ + struct pci_xhci_dev_emu *dev; + uint32_t cmderr; + int i; + + cmderr = XHCI_TRB_ERROR_NO_SLOTS; + if (sc->portregs != NULL) + for (i = 1; i <= XHCI_MAX_SLOTS; i++) { + dev = XHCI_SLOTDEV_PTR(sc, i); + if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) { + *slot = i; + dev->dev_slotstate = XHCI_ST_ENABLED; + cmderr = XHCI_TRB_ERROR_SUCCESS; + dev->hci.hci_address = i; + break; + } + } + + DPRINTF(("pci_xhci enable slot (error=%d) slot %u\r\n", + cmderr != XHCI_TRB_ERROR_SUCCESS, *slot)); + + return (cmderr); +} + +static uint32_t +pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot) +{ + struct pci_xhci_dev_emu *dev; + uint32_t cmderr; + + DPRINTF(("pci_xhci disable slot %u\r\n", slot)); + + cmderr = XHCI_TRB_ERROR_NO_SLOTS; + if (sc->portregs == NULL) + goto done; + + if (slot > sc->ndevices) { + cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; + goto done; + } + + dev = XHCI_SLOTDEV_PTR(sc, slot); + if (dev) { + if (dev->dev_slotstate == XHCI_ST_DISABLED) { + cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; + } else { + dev->dev_slotstate = XHCI_ST_DISABLED; + cmderr = XHCI_TRB_ERROR_SUCCESS; + /* TODO: reset events and endpoints */ + } + } + +done: + return (cmderr); +} + +static uint32_t +pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot) +{ + struct pci_xhci_dev_emu *dev; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep_ctx; + uint32_t cmderr; + int i; + + cmderr = XHCI_TRB_ERROR_NO_SLOTS; + if (sc->portregs == NULL) + goto done; + + DPRINTF(("pci_xhci reset device slot %u\r\n", slot)); + + dev = XHCI_SLOTDEV_PTR(sc, slot); + if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED) + cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; + else { + dev->dev_slotstate = XHCI_ST_DEFAULT; + + dev->hci.hci_address = 0; + dev_ctx = pci_xhci_get_dev_ctx(sc, slot); + + /* slot state */ + dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( + dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT, + 0x1F, 27); + + /* number of contexts */ + dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( + dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); + + /* reset all eps other than ep-0 */ + for (i = 2; i <= 31; i++) { + ep_ctx = &dev_ctx->ctx_ep[i]; + ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0, + XHCI_ST_EPCTX_DISABLED, 0x7, 0); + } + + cmderr = XHCI_TRB_ERROR_SUCCESS; + } + + pci_xhci_reset_slot(sc, slot); + +done: + return (cmderr); +} + +static uint32_t +pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot, + struct xhci_trb *trb) +{ + struct pci_xhci_dev_emu *dev; + struct xhci_input_dev_ctx *input_ctx; + struct xhci_slot_ctx *islot_ctx; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep0_ctx; + uint32_t cmderr; + + input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); + islot_ctx = &input_ctx->ctx_slot; + ep0_ctx = &input_ctx->ctx_ep[1]; + + cmderr = XHCI_TRB_ERROR_SUCCESS; + + DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,\r\n" + " slot %08x %08x %08x %08x\r\n" + " ep0 %08x %08x %016lx %08x\r\n", + input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1, + islot_ctx->dwSctx0, islot_ctx->dwSctx1, + islot_ctx->dwSctx2, islot_ctx->dwSctx3, + ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, + ep0_ctx->dwEpCtx4)); + + /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */ + if ((input_ctx->ctx_input.dwInCtx0 != 0) || + (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) { + DPRINTF(("pci_xhci: address device, input ctl invalid\r\n")); + cmderr = XHCI_TRB_ERROR_TRB; + goto done; + } + + /* assign address to slot */ + dev_ctx = pci_xhci_get_dev_ctx(sc, slot); + + DPRINTF(("pci_xhci: address device, dev ctx\r\n" + " slot %08x %08x %08x %08x\r\n", + dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, + dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); + + dev = XHCI_SLOTDEV_PTR(sc, slot); + assert(dev != NULL); + + dev->hci.hci_address = slot; + dev->dev_ctx = dev_ctx; + + if (dev->dev_ue->ue_reset == NULL || + dev->dev_ue->ue_reset(dev->dev_sc) < 0) { + cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; + goto done; + } + + memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx)); + + dev_ctx->ctx_slot.dwSctx3 = + XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) | + XHCI_SCTX_3_DEV_ADDR_SET(slot); + + memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx)); + ep0_ctx = &dev_ctx->ctx_ep[1]; + ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) | + XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING); + + pci_xhci_init_ep(dev, 1); + + dev->dev_slotstate = XHCI_ST_ADDRESSED; + + DPRINTF(("pci_xhci: address device, output ctx\r\n" + " slot %08x %08x %08x %08x\r\n" + " ep0 %08x %08x %016lx %08x\r\n", + dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, + dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3, + ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, + ep0_ctx->dwEpCtx4)); + +done: + return (cmderr); +} + +static uint32_t +pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot, + struct xhci_trb *trb) +{ + struct xhci_input_dev_ctx *input_ctx; + struct pci_xhci_dev_emu *dev; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep_ctx, *iep_ctx; + uint32_t cmderr; + int i; + + cmderr = XHCI_TRB_ERROR_SUCCESS; + + DPRINTF(("pci_xhci config_ep slot %u\r\n", slot)); + + dev = XHCI_SLOTDEV_PTR(sc, slot); + assert(dev != NULL); + + if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) { + DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u\r\n", + slot)); + if (dev->dev_ue->ue_stop != NULL) + dev->dev_ue->ue_stop(dev->dev_sc); + + dev->dev_slotstate = XHCI_ST_ADDRESSED; + + dev->hci.hci_address = 0; + dev_ctx = pci_xhci_get_dev_ctx(sc, slot); + + /* number of contexts */ + dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( + dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); + + /* slot state */ + dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( + dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED, + 0x1F, 27); + + /* disable endpoints */ + for (i = 2; i < 32; i++) + pci_xhci_disable_ep(dev, i); + + cmderr = XHCI_TRB_ERROR_SUCCESS; + + goto done; + } + + if (dev->dev_slotstate < XHCI_ST_ADDRESSED) { + DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed\r\n", + dev->dev_slotstate)); + cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; + goto done; + } + + /* In addressed/configured state; + * for each drop endpoint ctx flag: + * ep->state = DISABLED + * for each add endpoint ctx flag: + * cp(ep-in, ep-out) + * ep->state = RUNNING + * for each drop+add endpoint flag: + * reset ep resources + * cp(ep-in, ep-out) + * ep->state = RUNNING + * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled) + * slot->state = configured + */ + + input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); + dev_ctx = dev->dev_ctx; + DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x\r\n", + input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1, + input_ctx->ctx_input.dwInCtx7)); + + for (i = 2; i <= 31; i++) { + ep_ctx = &dev_ctx->ctx_ep[i]; + + if (input_ctx->ctx_input.dwInCtx0 & + XHCI_INCTX_0_DROP_MASK(i)) { + DPRINTF((" config ep - dropping ep %d\r\n", i)); + pci_xhci_disable_ep(dev, i); + } + + if (input_ctx->ctx_input.dwInCtx1 & + XHCI_INCTX_1_ADD_MASK(i)) { + iep_ctx = &input_ctx->ctx_ep[i]; + + DPRINTF((" enable ep[%d] %08x %08x %016lx %08x\r\n", + i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1, + iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4)); + + memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx)); + + pci_xhci_init_ep(dev, i); + + /* ep state */ + ep_ctx->dwEpCtx0 = FIELD_REPLACE( + ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); + } + } + + /* slot state to configured */ + dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( + dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27); + dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY( + dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27); + dev->dev_slotstate = XHCI_ST_CONFIGURED; + + DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x " + "[3]=0x%08x\r\n", + slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, + dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); + +done: + return (cmderr); +} + +static uint32_t +pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot, + struct xhci_trb *trb) +{ + struct pci_xhci_dev_emu *dev; + struct pci_xhci_dev_ep *devep; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep_ctx; + uint32_t cmderr, epid; + uint32_t type; + + epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); + + DPRINTF(("pci_xhci: reset ep %u: slot %u\r\n", epid, slot)); + + cmderr = XHCI_TRB_ERROR_SUCCESS; + + type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); + + dev = XHCI_SLOTDEV_PTR(sc, slot); + assert(dev != NULL); + + if (type == XHCI_TRB_TYPE_STOP_EP && + (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) { + /* XXX suspend endpoint for 10ms */ + } + + if (epid < 1 || epid > 31) { + DPRINTF(("pci_xhci: reset ep: invalid epid %u\r\n", epid)); + cmderr = XHCI_TRB_ERROR_TRB; + goto done; + } + + devep = &dev->eps[epid]; + if (devep->ep_xfer != NULL) + USB_DATA_XFER_RESET(devep->ep_xfer); + + dev_ctx = dev->dev_ctx; + assert(dev_ctx != NULL); + + ep_ctx = &dev_ctx->ctx_ep[epid]; + + ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; + + if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) == 0) + ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs; + + DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x\r\n", + epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, + ep_ctx->dwEpCtx4)); + + if (type == XHCI_TRB_TYPE_RESET_EP && + (dev->dev_ue->ue_reset == NULL || + dev->dev_ue->ue_reset(dev->dev_sc) < 0)) { + cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; + goto done; + } + +done: + return (cmderr); +} + + +static uint32_t +pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep, + uint32_t streamid, struct xhci_stream_ctx **osctx) +{ + struct xhci_stream_ctx *sctx; + uint32_t maxpstreams; + + maxpstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep->dwEpCtx0); + if (maxpstreams == 0) + return (XHCI_TRB_ERROR_TRB); + + if (maxpstreams > XHCI_STREAMS_MAX) + return (XHCI_TRB_ERROR_INVALID_SID); + + if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) { + DPRINTF(("pci_xhci: find_stream; LSA bit not set\r\n")); + return (XHCI_TRB_ERROR_INVALID_SID); + } + + /* only support primary stream */ + if (streamid > maxpstreams) + return (XHCI_TRB_ERROR_STREAM_TYPE); + + sctx = XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) + streamid; + if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0)) + return (XHCI_TRB_ERROR_STREAM_TYPE); + + *osctx = sctx; + + return (XHCI_TRB_ERROR_SUCCESS); +} + + +static uint32_t +pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot, + struct xhci_trb *trb) +{ + struct pci_xhci_dev_emu *dev; + struct pci_xhci_dev_ep *devep; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep_ctx; + uint32_t cmderr, epid; + uint32_t streamid; + + cmderr = XHCI_TRB_ERROR_SUCCESS; + + dev = XHCI_SLOTDEV_PTR(sc, slot); + assert(dev != NULL); + + DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u\r\n" + " stream-id %u, slot %u, epid %u, C %u\r\n", + (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7), + (uint32_t)(trb->qwTrb0 & 0x1), (trb->dwTrb2 >> 16) & 0xFFFF, + XHCI_TRB_3_SLOT_GET(trb->dwTrb3), + XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1)); + + epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); + if (epid < 1 || epid > 31) { + DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u\r\n", epid)); + cmderr = XHCI_TRB_ERROR_TRB; + goto done; + } + + dev_ctx = dev->dev_ctx; + assert(dev_ctx != NULL); + + ep_ctx = &dev_ctx->ctx_ep[epid]; + devep = &dev->eps[epid]; + + switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) { + case XHCI_ST_EPCTX_STOPPED: + case XHCI_ST_EPCTX_ERROR: + break; + default: + DPRINTF(("pci_xhci cmd set_tr invalid state %x\r\n", + XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0))); + cmderr = XHCI_TRB_ERROR_CONTEXT_STATE; + goto done; + } + + streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2); + if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) > 0) { + struct xhci_stream_ctx *sctx; + + sctx = NULL; + cmderr = pci_xhci_find_stream(sc, ep_ctx, streamid, &sctx); + if (sctx != NULL) { + assert(devep->ep_sctx != NULL); + + devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0; + devep->ep_sctx_trbs[streamid].ringaddr = + trb->qwTrb0 & ~0xF; + devep->ep_sctx_trbs[streamid].ccs = + XHCI_EPCTX_2_DCS_GET(trb->qwTrb0); + } + } else { + if (streamid != 0) { + DPRINTF(("pci_xhci cmd set_tr streamid %x != 0\r\n", + streamid)); + } + ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL; + devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL; + devep->ep_ccs = trb->qwTrb0 & 0x1; + devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr); + + DPRINTF(("pci_xhci set_tr first TRB:\r\n")); + pci_xhci_dump_trb(devep->ep_tr); + } + ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; + +done: + return (cmderr); +} + +static uint32_t +pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot, + struct xhci_trb *trb) +{ + struct xhci_input_dev_ctx *input_ctx; + struct xhci_slot_ctx *islot_ctx; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep0_ctx; + uint32_t cmderr; + + input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); + islot_ctx = &input_ctx->ctx_slot; + ep0_ctx = &input_ctx->ctx_ep[1]; + + cmderr = XHCI_TRB_ERROR_SUCCESS; + DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,\r\n" + " slot %08x %08x %08x %08x\r\n" + " ep0 %08x %08x %016lx %08x\r\n", + input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1, + islot_ctx->dwSctx0, islot_ctx->dwSctx1, + islot_ctx->dwSctx2, islot_ctx->dwSctx3, + ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, + ep0_ctx->dwEpCtx4)); + + /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */ + if ((input_ctx->ctx_input.dwInCtx0 != 0) || + (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) { + DPRINTF(("pci_xhci: eval ctx, input ctl invalid\r\n")); + cmderr = XHCI_TRB_ERROR_TRB; + goto done; + } + + /* assign address to slot; in this emulation, slot_id = address */ + dev_ctx = pci_xhci_get_dev_ctx(sc, slot); + + DPRINTF(("pci_xhci: eval ctx, dev ctx\r\n" + " slot %08x %08x %08x %08x\r\n", + dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, + dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); + + if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */ + /* set max exit latency */ + dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY( + dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1, + 0xFFFF, 0); + + /* set interrupter target */ + dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY( + dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2, + 0x3FF, 22); + } + if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */ + /* set max packet size */ + dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY( + dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1, + 0xFFFF, 16); + + ep0_ctx = &dev_ctx->ctx_ep[1]; + } + + DPRINTF(("pci_xhci: eval ctx, output ctx\r\n" + " slot %08x %08x %08x %08x\r\n" + " ep0 %08x %08x %016lx %08x\r\n", + dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, + dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3, + ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, + ep0_ctx->dwEpCtx4)); + +done: + return (cmderr); +} + +static int +pci_xhci_complete_commands(struct pci_xhci_softc *sc) +{ + struct xhci_trb evtrb; + struct xhci_trb *trb; + uint64_t crcr; + uint32_t ccs; /* cycle state (XHCI 4.9.2) */ + uint32_t type; + uint32_t slot; + uint32_t cmderr; + int error; + + error = 0; + sc->opregs.crcr |= XHCI_CRCR_LO_CRR; + + trb = sc->opregs.cr_p; + ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS; + crcr = sc->opregs.crcr & ~0xF; + + while (1) { + sc->opregs.cr_p = trb; + + type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); + + if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) != + (ccs & XHCI_TRB_3_CYCLE_BIT)) + break; + + DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x" + " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u\r\n", + type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3, + trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs)); + + cmderr = XHCI_TRB_ERROR_SUCCESS; + evtrb.dwTrb2 = 0; + evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) | + XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE); + slot = 0; + + switch (type) { + case XHCI_TRB_TYPE_LINK: /* 0x06 */ + if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) + ccs ^= XHCI_CRCR_LO_RCS; + break; + + case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */ + cmderr = pci_xhci_cmd_enable_slot(sc, &slot); + break; + + case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */ + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_disable_slot(sc, slot); + break; + + case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */ + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_address_device(sc, slot, trb); + break; + + case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */ + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_config_ep(sc, slot, trb); + break; + + case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */ + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb); + break; + + case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */ + DPRINTF(("Reset Endpoint on slot %d\r\n", slot)); + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); + break; + + case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */ + DPRINTF(("Stop Endpoint on slot %d\r\n", slot)); + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); + break; + + case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */ + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_set_tr(sc, slot, trb); + break; + + case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */ + slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); + cmderr = pci_xhci_cmd_reset_device(sc, slot); + break; + + case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */ + /* TODO: */ + break; + + case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */ + break; + + case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */ + break; + + case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */ + break; + + case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */ + break; + + case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */ + break; + + default: + DPRINTF(("pci_xhci: unsupported cmd %x\r\n", type)); + break; + } + + if (type != XHCI_TRB_TYPE_LINK) { + /* + * insert command completion event and assert intr + */ + evtrb.qwTrb0 = crcr; + evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr); + evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot); + DPRINTF(("pci_xhci: command 0x%x result: 0x%x\r\n", + type, cmderr)); + pci_xhci_insert_event(sc, &evtrb, 1); + } + + trb = pci_xhci_trb_next(sc, trb, &crcr); + } + + sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs; + sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR; + return (error); +} + +static void +pci_xhci_dump_trb(struct xhci_trb *trb) +{ + static const char *trbtypes[] = { + "RESERVED", + "NORMAL", + "SETUP_STAGE", + "DATA_STAGE", + "STATUS_STAGE", + "ISOCH", + "LINK", + "EVENT_DATA", + "NOOP", + "ENABLE_SLOT", + "DISABLE_SLOT", + "ADDRESS_DEVICE", + "CONFIGURE_EP", + "EVALUATE_CTX", + "RESET_EP", + "STOP_EP", + "SET_TR_DEQUEUE", + "RESET_DEVICE", + "FORCE_EVENT", + "NEGOTIATE_BW", + "SET_LATENCY_TOL", + "GET_PORT_BW", + "FORCE_HEADER", + "NOOP_CMD" + }; + uint32_t type; + + type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); + DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x\r\n", + trb, type, + type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID", + trb->qwTrb0, trb->dwTrb2, trb->dwTrb3)); +} + +static int +pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer, + uint32_t slot, uint32_t epid, int *do_intr) +{ + struct pci_xhci_dev_emu *dev; + struct pci_xhci_dev_ep *devep; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep_ctx; + struct xhci_trb *trb; + struct xhci_trb evtrb; + uint32_t trbflags; + uint32_t edtla; + int i, err; + + dev = XHCI_SLOTDEV_PTR(sc, slot); + devep = &dev->eps[epid]; + dev_ctx = pci_xhci_get_dev_ctx(sc, slot); + + assert(dev_ctx != NULL); + + ep_ctx = &dev_ctx->ctx_ep[epid]; + + err = XHCI_TRB_ERROR_SUCCESS; + *do_intr = 0; + edtla = 0; + + /* go through list of TRBs and insert event(s) */ + for (i = xfer->head; xfer->ndata > 0; ) { + evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data; + trb = XHCI_GADDR(sc, evtrb.qwTrb0); + trbflags = trb->dwTrb3; + + DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x " + "(err %d) IOC?%d\r\n", + i, xfer->data[i].processed, xfer->data[i].blen, + XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0, + trbflags, err, + trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0)); + + if (!xfer->data[i].processed) { + xfer->head = i; + break; + } + + xfer->ndata--; + edtla += xfer->data[i].bdone; + + trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs); + + pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx, + xfer->data[i].streamid, xfer->data[i].trbnext, + xfer->data[i].ccs); + + /* Only interrupt if IOC or short packet */ + if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) && + !((err == XHCI_TRB_ERROR_SHORT_PKT) && + (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) { + + i = (i + 1) % USB_MAX_XFER_BLOCKS; + continue; + } + + evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) | + XHCI_TRB_2_REM_SET(xfer->data[i].blen); + + evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) | + XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid); + + if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) { + DPRINTF(("pci_xhci EVENT_DATA edtla %u\r\n", edtla)); + evtrb.qwTrb0 = trb->qwTrb0; + evtrb.dwTrb2 = (edtla & 0xFFFFF) | + XHCI_TRB_2_ERROR_SET(err); + evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT; + edtla = 0; + } + + *do_intr = 1; + + err = pci_xhci_insert_event(sc, &evtrb, 0); + if (err != XHCI_TRB_ERROR_SUCCESS) { + break; + } + + i = (i + 1) % USB_MAX_XFER_BLOCKS; + } + + return (err); +} + +static void +pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, struct pci_xhci_dev_emu *dev, + struct pci_xhci_dev_ep *devep, struct xhci_endp_ctx *ep_ctx, + uint32_t streamid, uint64_t ringaddr, int ccs) +{ + + if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) != 0) { + devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) | + (ccs & 0x1); + + devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL; + devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1; + ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1); + + DPRINTF(("xhci update ep-ring stream %d, addr %lx\r\n", + streamid, devep->ep_sctx[streamid].qwSctx0)); + } else { + devep->ep_ringaddr = ringaddr & ~0xFUL; + devep->ep_ccs = ccs & 0x1; + devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL); + ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1); + + DPRINTF(("xhci update ep-ring, addr %lx\r\n", + (devep->ep_ringaddr | devep->ep_ccs))); + } +} + +/* + * Outstanding transfer still in progress (device NAK'd earlier) so retry + * the transfer again to see if it succeeds. + */ +static int +pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc, + struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, + struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid) +{ + struct usb_data_xfer *xfer; + int err; + int do_intr; + + ep_ctx->dwEpCtx0 = FIELD_REPLACE( + ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); + + err = 0; + do_intr = 0; + + xfer = devep->ep_xfer; + USB_DATA_XFER_LOCK(xfer); + + /* outstanding requests queued up */ + if (dev->dev_ue->ue_data != NULL) { + err = dev->dev_ue->ue_data(dev->dev_sc, xfer, + epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2); + if (err == USB_ERR_CANCELLED) { + if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) == + USB_NAK) + err = XHCI_TRB_ERROR_SUCCESS; + } else { + err = pci_xhci_xfer_complete(sc, xfer, slot, epid, + &do_intr); + if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) { + pci_xhci_assert_interrupt(sc); + } + + + /* XXX should not do it if error? */ + USB_DATA_XFER_RESET(xfer); + } + } + + USB_DATA_XFER_UNLOCK(xfer); + + + return (err); +} + + +static int +pci_xhci_handle_transfer(struct pci_xhci_softc *sc, + struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, + struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot, + uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid) +{ + struct xhci_trb *setup_trb; + struct usb_data_xfer *xfer; + struct usb_data_xfer_block *xfer_block; + uint64_t val; + uint32_t trbflags; + int do_intr, err; + int do_retry; + + ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0, + XHCI_ST_EPCTX_RUNNING, 0x7, 0); + + xfer = devep->ep_xfer; + USB_DATA_XFER_LOCK(xfer); + + DPRINTF(("pci_xhci handle_transfer slot %u\r\n", slot)); + +retry: + err = 0; + do_retry = 0; + do_intr = 0; + setup_trb = NULL; + + while (1) { + pci_xhci_dump_trb(trb); + + trbflags = trb->dwTrb3; + + if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK && + (trbflags & XHCI_TRB_3_CYCLE_BIT) != + (ccs & XHCI_TRB_3_CYCLE_BIT)) { + DPRINTF(("Cycle-bit changed trbflags %x, ccs %x\r\n", + trbflags & XHCI_TRB_3_CYCLE_BIT, ccs)); + break; + } + + xfer_block = NULL; + + switch (XHCI_TRB_3_TYPE_GET(trbflags)) { + case XHCI_TRB_TYPE_LINK: + if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) + ccs ^= 0x1; + + xfer_block = usb_data_xfer_append(xfer, NULL, 0, + (void *)addr, ccs); + xfer_block->processed = 1; + break; + + case XHCI_TRB_TYPE_SETUP_STAGE: + if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 || + XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) { + DPRINTF(("pci_xhci: invalid setup trb\r\n")); + err = XHCI_TRB_ERROR_TRB; + goto errout; + } + setup_trb = trb; + + val = trb->qwTrb0; + if (!xfer->ureq) + xfer->ureq = malloc( + sizeof(struct usb_device_request)); + memcpy(xfer->ureq, &val, + sizeof(struct usb_device_request)); + + xfer_block = usb_data_xfer_append(xfer, NULL, 0, + (void *)addr, ccs); + xfer_block->processed = 1; + break; + + case XHCI_TRB_TYPE_NORMAL: + case XHCI_TRB_TYPE_ISOCH: + if (setup_trb != NULL) { + DPRINTF(("pci_xhci: trb not supposed to be in " + "ctl scope\r\n")); + err = XHCI_TRB_ERROR_TRB; + goto errout; + } + /* fall through */ + + case XHCI_TRB_TYPE_DATA_STAGE: + xfer_block = usb_data_xfer_append(xfer, + (void *)(trbflags & XHCI_TRB_3_IDT_BIT ? + &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)), + trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs); + break; + + case XHCI_TRB_TYPE_STATUS_STAGE: + xfer_block = usb_data_xfer_append(xfer, NULL, 0, + (void *)addr, ccs); + break; + + case XHCI_TRB_TYPE_NOOP: + xfer_block = usb_data_xfer_append(xfer, NULL, 0, + (void *)addr, ccs); + xfer_block->processed = 1; + break; + + case XHCI_TRB_TYPE_EVENT_DATA: + xfer_block = usb_data_xfer_append(xfer, NULL, 0, + (void *)addr, ccs); + if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) { + xfer_block->processed = 1; + } + break; + + default: + DPRINTF(("pci_xhci: handle xfer unexpected trb type " + "0x%x\r\n", + XHCI_TRB_3_TYPE_GET(trbflags))); + err = XHCI_TRB_ERROR_TRB; + goto errout; + } + + trb = pci_xhci_trb_next(sc, trb, &addr); + + DPRINTF(("pci_xhci: next trb: 0x%lx\r\n", (uint64_t)trb)); + + if (xfer_block) { + xfer_block->trbnext = addr; + xfer_block->streamid = streamid; + } + + if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) && + XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) { + break; + } + + /* handle current batch that requires interrupt on complete */ + if (trbflags & XHCI_TRB_3_IOC_BIT) { + DPRINTF(("pci_xhci: trb IOC bit set\r\n")); + if (epid == 1) + do_retry = 1; + break; + } + } + + DPRINTF(("pci_xhci[%d]: xfer->ndata %u\r\n", __LINE__, xfer->ndata)); + + if (epid == 1) { + err = USB_ERR_NOT_STARTED; + if (dev->dev_ue->ue_request != NULL) + err = dev->dev_ue->ue_request(dev->dev_sc, xfer); + setup_trb = NULL; + } else { + /* handle data transfer */ + pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); + err = XHCI_TRB_ERROR_SUCCESS; + goto errout; + } + + err = USB_TO_XHCI_ERR(err); + if ((err == XHCI_TRB_ERROR_SUCCESS) || + (err == XHCI_TRB_ERROR_SHORT_PKT)) { + err = pci_xhci_xfer_complete(sc, xfer, slot, epid, &do_intr); + if (err != XHCI_TRB_ERROR_SUCCESS) + do_retry = 0; + } + +errout: + if (err == XHCI_TRB_ERROR_EV_RING_FULL) + DPRINTF(("pci_xhci[%d]: event ring full\r\n", __LINE__)); + + if (!do_retry) + USB_DATA_XFER_UNLOCK(xfer); + + if (do_intr) + pci_xhci_assert_interrupt(sc); + + if (do_retry) { + USB_DATA_XFER_RESET(xfer); + DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs\r\n", + __LINE__)); + goto retry; + } + + if (epid == 1) + USB_DATA_XFER_RESET(xfer); + + return (err); +} + +static void +pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot, + uint32_t epid, uint32_t streamid) +{ + struct pci_xhci_dev_emu *dev; + struct pci_xhci_dev_ep *devep; + struct xhci_dev_ctx *dev_ctx; + struct xhci_endp_ctx *ep_ctx; + struct pci_xhci_trb_ring *sctx_tr; + struct xhci_trb *trb; + uint64_t ringaddr; + uint32_t ccs; + + DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u\r\n", + slot, epid, streamid)); + + if (slot == 0 || slot > sc->ndevices) { + DPRINTF(("pci_xhci: invalid doorbell slot %u\r\n", slot)); + return; + } + + dev = XHCI_SLOTDEV_PTR(sc, slot); + devep = &dev->eps[epid]; + dev_ctx = pci_xhci_get_dev_ctx(sc, slot); + if (!dev_ctx) { + return; + } + ep_ctx = &dev_ctx->ctx_ep[epid]; + + sctx_tr = NULL; + + DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x\r\n", + epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, + ep_ctx->dwEpCtx4)); + + if (ep_ctx->qwEpCtx2 == 0) + return; + + /* handle pending transfers */ + if (devep->ep_xfer->ndata > 0) { + pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); + return; + } + + /* get next trb work item */ + if (XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0) != 0) { + sctx_tr = &devep->ep_sctx_trbs[streamid]; + ringaddr = sctx_tr->ringaddr; + ccs = sctx_tr->ccs; + trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL); + DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x\r\n", + streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, + trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); + } else { + ringaddr = devep->ep_ringaddr; + ccs = devep->ep_ccs; + trb = devep->ep_tr; + DPRINTF(("doorbell, ccs %lx, trb ccs %x\r\n", + ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, + trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); + } + + if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) { + DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?\r\n", + ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid)); + return; + } + + pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid, + ringaddr, ccs, streamid); +} + +static void +pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset, + uint64_t value) +{ + + offset = (offset - sc->dboff) / sizeof(uint32_t); + + DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx\r\n", + offset, value)); + + if (XHCI_HALTED(sc)) { + DPRINTF(("pci_xhci: controller halted\r\n")); + return; + } + + if (offset == 0) + pci_xhci_complete_commands(sc); + else if (sc->portregs != NULL) + pci_xhci_device_doorbell(sc, offset, + XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value)); +} + +static void +pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset, + uint64_t value) +{ + struct pci_xhci_rtsregs *rts; + + offset -= sc->rtsoff; + + if (offset == 0) { + DPRINTF(("pci_xhci attempted write to MFINDEX\r\n")); + return; + } + + DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx\r\n", + offset, value)); + + offset -= 0x20; /* start of intrreg */ + + rts = &sc->rtsregs; + + switch (offset) { + case 0x00: + if (value & XHCI_IMAN_INTR_PEND) + rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; + rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) | + (rts->intrreg.iman & XHCI_IMAN_INTR_PEND); + + if (!(value & XHCI_IMAN_INTR_ENA)) + pci_xhci_deassert_interrupt(sc); + + break; + + case 0x04: + rts->intrreg.imod = value; + break; + + case 0x08: + rts->intrreg.erstsz = value & 0xFFFF; + break; + + case 0x10: + /* ERSTBA low bits */ + rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) | + (value & ~0x3F); + break; + + case 0x14: + /* ERSTBA high bits */ + rts->intrreg.erstba = (value << 32) | + MASK_64_LO(sc->rtsregs.intrreg.erstba); + + rts->erstba_p = XHCI_GADDR(sc, + sc->rtsregs.intrreg.erstba & ~0x3FUL); + + rts->erst_p = XHCI_GADDR(sc, + sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL); + + rts->er_enq_idx = 0; + rts->er_events_cnt = 0; + + DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u\r\n", + rts->erstba_p, + rts->erstba_p->qwEvrsTablePtr, + rts->erstba_p->dwEvrsTableSize)); + break; + + case 0x18: + /* ERDP low bits */ + rts->intrreg.erdp = + MASK_64_HI(sc->rtsregs.intrreg.erdp) | + (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) | + (value & ~0xF); + if (value & XHCI_ERDP_LO_BUSY) { + rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY; + rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; + } + + rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value); + + break; + + case 0x1C: + /* ERDP high bits */ + rts->intrreg.erdp = (value << 32) | + MASK_64_LO(sc->rtsregs.intrreg.erdp); + + if (rts->er_events_cnt > 0) { + uint64_t erdp; + uint32_t erdp_i; + + erdp = rts->intrreg.erdp & ~0xF; + erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) / + sizeof(struct xhci_trb); + + if (erdp_i <= rts->er_enq_idx) + rts->er_events_cnt = rts->er_enq_idx - erdp_i; + else + rts->er_events_cnt = + rts->erstba_p->dwEvrsTableSize - + (erdp_i - rts->er_enq_idx); + + DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u\r\n", + erdp, rts->er_events_cnt)); + } + + break; + + default: + DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx\r\n", + offset)); + break; + } +} + +static uint64_t +pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset) +{ + int port; + uint32_t *p; + + if (sc->portregs == NULL) + return (0); + + port = (offset - 0x3F0) / 0x10; + + if (port > XHCI_MAX_DEVS) { + DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS\r\n", + port)); + + /* return default value for unused port */ + return (XHCI_PS_SPEED_SET(3)); + } + + offset = (offset - 0x3F0) % 0x10; + + p = &sc->portregs[port].portsc; + p += offset / sizeof(uint32_t); + + DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x\r\n", + offset, port, *p)); + + return (*p); +} + +static void +pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset, + uint64_t value) +{ + offset -= XHCI_CAPLEN; + + if (offset < 0x400) + DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx\r\n", + offset, value)); + + switch (offset) { + case XHCI_USBCMD: + sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F); + break; + + case XHCI_USBSTS: + /* clear bits on write */ + sc->opregs.usbsts &= ~(value & + (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS| + XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR)); + break; + + case XHCI_PAGESIZE: + /* read only */ + break; + + case XHCI_DNCTRL: + sc->opregs.dnctrl = value & 0xFFFF; + break; + + case XHCI_CRCR_LO: + if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) { + sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); + sc->opregs.crcr |= value & + (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); + } else { + sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) | + (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS)); + } + break; + + case XHCI_CRCR_HI: + if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) { + sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) | + (value << 32); + + sc->opregs.cr_p = XHCI_GADDR(sc, + sc->opregs.crcr & ~0xF); + } + + if (sc->opregs.crcr & XHCI_CRCR_LO_CS) { + /* Stop operation of Command Ring */ + } + + if (sc->opregs.crcr & XHCI_CRCR_LO_CA) { + /* Abort command */ + } + + break; + + case XHCI_DCBAAP_LO: + sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) | + (value & 0xFFFFFFC0); + break; + + case XHCI_DCBAAP_HI: + sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) | + (value << 32); + sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL); + + DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)\r\n", + sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p)); + break; + + case XHCI_CONFIG: + sc->opregs.config = value & 0x03FF; + break; + + default: + if (offset >= 0x400) + pci_xhci_portregs_write(sc, offset, value); + + break; + } +} + + +static void +pci_xhci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, + int baridx, uint64_t offset, int size, uint64_t value) +{ + struct pci_xhci_softc *sc; + + sc = pi->pi_arg; + + assert(baridx == 0); + + + pthread_mutex_lock(&sc->mtx); + if (offset < XHCI_CAPLEN) /* read only registers */ + WPRINTF(("pci_xhci: write RO-CAPs offset %ld\r\n", offset)); + else if (offset < sc->dboff) + pci_xhci_hostop_write(sc, offset, value); + else if (offset < sc->rtsoff) + pci_xhci_dbregs_write(sc, offset, value); + else if (offset < sc->regsend) + pci_xhci_rtsregs_write(sc, offset, value); + else + WPRINTF(("pci_xhci: write invalid offset %ld\r\n", offset)); + + pthread_mutex_unlock(&sc->mtx); +} + +static uint64_t +pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset) +{ + uint64_t value; + + switch (offset) { + case XHCI_CAPLENGTH: /* 0x00 */ + value = sc->caplength; + break; + + case XHCI_HCSPARAMS1: /* 0x04 */ + value = sc->hcsparams1; + break; + + case XHCI_HCSPARAMS2: /* 0x08 */ + value = sc->hcsparams2; + break; + + case XHCI_HCSPARAMS3: /* 0x0C */ + value = sc->hcsparams3; + break; + + case XHCI_HCSPARAMS0: /* 0x10 */ + value = sc->hccparams1; + break; + + case XHCI_DBOFF: /* 0x14 */ + value = sc->dboff; + break; + + case XHCI_RTSOFF: /* 0x18 */ + value = sc->rtsoff; + break; + + case XHCI_HCCPRAMS2: /* 0x1C */ + value = sc->hccparams2; + break; + + default: + value = 0; + break; + } + + DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx\r\n", + offset, value)); + + return (value); +} + +static uint64_t +pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset) +{ + uint64_t value; + + offset = (offset - XHCI_CAPLEN); + + switch (offset) { + case XHCI_USBCMD: /* 0x00 */ + value = sc->opregs.usbcmd; + break; + + case XHCI_USBSTS: /* 0x04 */ + value = sc->opregs.usbsts; + break; + + case XHCI_PAGESIZE: /* 0x08 */ + value = sc->opregs.pgsz; + break; + + case XHCI_DNCTRL: /* 0x14 */ + value = sc->opregs.dnctrl; + break; + + case XHCI_CRCR_LO: /* 0x18 */ + value = sc->opregs.crcr & XHCI_CRCR_LO_CRR; + break; + + case XHCI_CRCR_HI: /* 0x1C */ + value = 0; + break; + + case XHCI_DCBAAP_LO: /* 0x30 */ + value = sc->opregs.dcbaap & 0xFFFFFFFF; + break; + + case XHCI_DCBAAP_HI: /* 0x34 */ + value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF; + break; + + case XHCI_CONFIG: /* 0x38 */ + value = sc->opregs.config; + break; + + default: + if (offset >= 0x400) + value = pci_xhci_portregs_read(sc, offset); + else + value = 0; + + break; + } + + if (offset < 0x400) + DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx\r\n", + offset, value)); + + return (value); +} + +static uint64_t +pci_xhci_dbregs_read(struct pci_xhci_softc *sc, uint64_t offset) +{ + + /* read doorbell always returns 0 */ + return (0); +} + +static uint64_t +pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset) +{ + uint32_t value; + + offset -= sc->rtsoff; + value = 0; + + if (offset == XHCI_MFINDEX) { + value = sc->rtsregs.mfindex; + } else if (offset >= 0x20) { + int item; + uint32_t *p; + + offset -= 0x20; + item = offset % 32; + + assert(offset < sizeof(sc->rtsregs.intrreg)); + + p = &sc->rtsregs.intrreg.iman; + p += item / sizeof(uint32_t); + value = *p; + } + + DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x\r\n", + offset, value)); + + return (value); +} + +static uint64_t +pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset) +{ + uint32_t value; + + offset -= sc->regsend; + value = 0; + + switch (offset) { + case 0: + /* rev major | rev minor | next-cap | cap-id */ + value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS; + break; + case 4: + /* name string = "USB" */ + value = 0x20425355; + break; + case 8: + /* psic | proto-defined | compat # | compat offset */ + value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start; + break; + case 12: + break; + case 16: + /* rev major | rev minor | next-cap | cap-id */ + value = (0x03 << 24) | XHCI_ID_PROTOCOLS; + break; + case 20: + /* name string = "USB" */ + value = 0x20425355; + break; + case 24: + /* psic | proto-defined | compat # | compat offset */ + value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start; + break; + case 28: + break; + default: + DPRINTF(("pci_xhci: xecp invalid offset 0x%lx\r\n", offset)); + break; + } + + DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x\r\n", + offset, value)); + + return (value); +} + + +static uint64_t +pci_xhci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, + uint64_t offset, int size) +{ + struct pci_xhci_softc *sc; + uint32_t value; + + sc = pi->pi_arg; + + assert(baridx == 0); + + pthread_mutex_lock(&sc->mtx); + if (offset < XHCI_CAPLEN) + value = pci_xhci_hostcap_read(sc, offset); + else if (offset < sc->dboff) + value = pci_xhci_hostop_read(sc, offset); + else if (offset < sc->rtsoff) + value = pci_xhci_dbregs_read(sc, offset); + else if (offset < sc->regsend) + value = pci_xhci_rtsregs_read(sc, offset); + else if (offset < (sc->regsend + 4*32)) + value = pci_xhci_xecp_read(sc, offset); + else { + value = 0; + WPRINTF(("pci_xhci: read invalid offset %ld\r\n", offset)); + } + + pthread_mutex_unlock(&sc->mtx); + + switch (size) { + case 1: + value &= 0xFF; + break; + case 2: + value &= 0xFFFF; + break; + case 4: + value &= 0xFFFFFFFF; + break; + } + + return (value); +} + +static void +pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm) +{ + struct pci_xhci_portregs *port; + struct pci_xhci_dev_emu *dev; + struct xhci_trb evtrb; + int error; + + assert(portn <= XHCI_MAX_DEVS); + + DPRINTF(("xhci reset port %d\r\n", portn)); + + port = XHCI_PORTREG_PTR(sc, portn); + dev = XHCI_DEVINST_PTR(sc, portn); + if (dev) { + port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC); + port->portsc |= XHCI_PS_PED | + XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); + + if (warm && dev->dev_ue->ue_usbver == 3) { + port->portsc |= XHCI_PS_WRC; + } + + if ((port->portsc & XHCI_PS_PRC) == 0) { + port->portsc |= XHCI_PS_PRC; + + pci_xhci_set_evtrb(&evtrb, portn, + XHCI_TRB_ERROR_SUCCESS, + XHCI_TRB_EVENT_PORT_STS_CHANGE); + error = pci_xhci_insert_event(sc, &evtrb, 1); + if (error != XHCI_TRB_ERROR_SUCCESS) + DPRINTF(("xhci reset port insert event " + "failed\r\n")); + } + } +} + +static void +pci_xhci_init_port(struct pci_xhci_softc *sc, int portn) +{ + struct pci_xhci_portregs *port; + struct pci_xhci_dev_emu *dev; + + port = XHCI_PORTREG_PTR(sc, portn); + dev = XHCI_DEVINST_PTR(sc, portn); + if (dev) { + port->portsc = XHCI_PS_CCS | /* connected */ + XHCI_PS_PP; /* port power */ + + if (dev->dev_ue->ue_usbver == 2) { + port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) | + XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); + } else { + port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) | + XHCI_PS_PED | /* enabled */ + XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); + } + + DPRINTF(("Init port %d 0x%x\n", portn, port->portsc)); + } else { + port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP; + DPRINTF(("Init empty port %d 0x%x\n", portn, port->portsc)); + } +} + +static int +pci_xhci_dev_intr(struct usb_hci *hci, int epctx) +{ + struct pci_xhci_dev_emu *dev; + struct xhci_trb evtrb; + struct pci_xhci_softc *sc; + struct pci_xhci_portregs *p; + int error; + int dir_in; + int epid; + + dir_in = epctx & 0x80; + epid = epctx & ~0x80; + + /* HW endpoint contexts are 0-15; convert to epid based on dir */ + epid = (epid * 2) + (dir_in ? 1 : 0); + + assert(epid >= 1 && epid <= 31); + + dev = hci->hci_sc; + sc = dev->xsc; + + /* check if device is ready; OS has to initialise it */ + if (sc->rtsregs.erstba_p == NULL || + (sc->opregs.usbcmd & XHCI_CMD_RS) == 0) + return (0); + + p = XHCI_PORTREG_PTR(sc, hci->hci_port); + + /* raise event if link U3 (suspended) state */ + if (XHCI_PS_PLS_GET(p->portsc) == 3) { + p->portsc &= ~XHCI_PS_PLS_MASK; + p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME); + if ((p->portsc & XHCI_PS_PLC) != 0) + return (0); + + p->portsc |= XHCI_PS_PLC; + + pci_xhci_set_evtrb(&evtrb, hci->hci_port, + XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE); + error = pci_xhci_insert_event(sc, &evtrb, 0); + if (error != XHCI_TRB_ERROR_SUCCESS) + goto done; + } + + DPRINTF(("xhci device interrupt on endpoint %d\r\n", epid)); + + pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0); + +done: + return (error); +} + +static int +pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid, void *param) +{ + + DPRINTF(("xhci device event port %d\r\n", hci->hci_port)); + return (0); +} + + + +static void +pci_xhci_device_usage(char *opt) +{ + + fprintf(stderr, "Invalid USB emulation \"%s\"\r\n", opt); +} + +static int +pci_xhci_parse_opts(struct pci_xhci_softc *sc, char *opts) +{ + struct pci_xhci_dev_emu **devices; + struct pci_xhci_dev_emu *dev; + struct usb_devemu *ue; + void *devsc; + char *uopt, *xopts, *config; + int usb3_port, usb2_port, i; + + usb3_port = sc->usb3_port_start - 1; + usb2_port = sc->usb2_port_start - 1; + devices = NULL; + + if (opts == NULL) + goto portsfinal; + + devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *)); + + sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *)); + sc->devices = devices; + sc->ndevices = 0; + + uopt = strdup(opts); + for (xopts = strtok(uopt, ","); + xopts != NULL; + xopts = strtok(NULL, ",")) { + if (usb2_port == ((sc->usb2_port_start-1) + XHCI_MAX_DEVS/2) || + usb3_port == ((sc->usb3_port_start-1) + XHCI_MAX_DEVS/2)) { + WPRINTF(("pci_xhci max number of USB 2 or 3 " + "devices reached, max %d\r\n", XHCI_MAX_DEVS/2)); + usb2_port = usb3_port = -1; + goto done; + } + + /* device[=<config>] */ + if ((config = strchr(xopts, '=')) == NULL) + config = ""; /* no config */ + else + *config++ = '\0'; + + ue = usb_emu_finddev(xopts); + if (ue == NULL) { + pci_xhci_device_usage(xopts); + DPRINTF(("pci_xhci device not found %s\r\n", xopts)); + usb2_port = usb3_port = -1; + goto done; + } + + DPRINTF(("pci_xhci adding device %s, opts \"%s\"\r\n", + xopts, config)); + + dev = calloc(1, sizeof(struct pci_xhci_dev_emu)); + dev->xsc = sc; + dev->hci.hci_sc = dev; + dev->hci.hci_intr = pci_xhci_dev_intr; + dev->hci.hci_event = pci_xhci_dev_event; + + if (ue->ue_usbver == 2) { + dev->hci.hci_port = usb2_port + 1; + devices[usb2_port] = dev; + usb2_port++; + } else { + dev->hci.hci_port = usb3_port + 1; + devices[usb3_port] = dev; + usb3_port++; + } + + dev->hci.hci_address = 0; + devsc = ue->ue_init(&dev->hci, config); + if (devsc == NULL) { + pci_xhci_device_usage(xopts); + usb2_port = usb3_port = -1; + goto done; + } + + dev->dev_ue = ue; + dev->dev_sc = devsc; + + /* assign slot number to device */ + sc->slots[sc->ndevices] = dev; + + sc->ndevices++; + } + +portsfinal: + sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs)); + + if (sc->ndevices > 0) { + /* port and slot numbering start from 1 */ + sc->devices--; + sc->portregs--; + sc->slots--; + + for (i = 1; i <= XHCI_MAX_DEVS; i++) { + pci_xhci_init_port(sc, i); + } + } else { + WPRINTF(("pci_xhci no USB devices configured\r\n")); + sc->ndevices = 1; + } + +done: + if (devices != NULL) { + if (usb2_port <= 0 && usb3_port <= 0) { + sc->devices = NULL; + for (i = 0; devices[i] != NULL; i++) + free(devices[i]); + sc->ndevices = -1; + + free(devices); + } + } + return (sc->ndevices); +} + +static int +pci_xhci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) +{ + struct pci_xhci_softc *sc; + int error; + + if (xhci_in_use) { + WPRINTF(("pci_xhci controller already defined\r\n")); + return (-1); + } + xhci_in_use = 1; + + sc = calloc(1, sizeof(struct pci_xhci_softc)); + pi->pi_arg = sc; + sc->xsc_pi = pi; + + sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1; + sc->usb3_port_start = 1; + + /* discover devices */ + error = pci_xhci_parse_opts(sc, opts); + if (error < 0) + goto done; + else + error = 0; + + sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) | + XHCI_SET_HCIVERSION(0x0100); + sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) | + XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */ + XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS); + sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) | + XHCI_SET_HCSP2_IST(0x04); + sc->hcsparams3 = 0; /* no latency */ + sc->hccparams1 = XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */ + XHCI_SET_HCCP1_SPC(1) | /* short packet */ + XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX); + sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) | + XHCI_SET_HCCP2_U3C(1); + sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START + + XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs)); + + /* dboff must be 32-bit aligned */ + if (sc->dboff & 0x3) + sc->dboff = (sc->dboff + 0x3) & ~0x3; + + /* rtsoff must be 32-bytes aligned */ + sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32); + if (sc->rtsoff & 0x1F) + sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F; + + DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x\r\n", sc->dboff, + sc->rtsoff)); + + sc->opregs.usbsts = XHCI_STS_HCH; + sc->opregs.pgsz = XHCI_PAGESIZE_4K; + + pci_xhci_reset(sc); + + sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */ + + /* + * Set extended capabilities pointer to be after regsend; + * value of xecp field is 32-bit offset. + */ + sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4); + + pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31); + pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); + pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS); + pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB); + pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI); + pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0); + + pci_emul_add_msicap(pi, 1); + + /* regsend + xecp registers */ + pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32); + DPRINTF(("pci_xhci pci_emu_alloc: %d\r\n", sc->regsend + 4*32)); + + + pci_lintr_request(pi); + + pthread_mutex_init(&sc->mtx, NULL); + +done: + if (error) { + free(sc); + } + + return (error); +} + + + +struct pci_devemu pci_de_xhci = { + .pe_emu = "xhci", + .pe_init = pci_xhci_init, + .pe_barwrite = pci_xhci_write, + .pe_barread = pci_xhci_read +}; +PCI_EMUL_SET(pci_de_xhci); diff --git a/usr.sbin/bhyve/pci_xhci.h b/usr.sbin/bhyve/pci_xhci.h new file mode 100644 index 0000000..d5f05af --- /dev/null +++ b/usr.sbin/bhyve/pci_xhci.h @@ -0,0 +1,353 @@ +/*- + * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _PCI_XHCI_H_ +#define _PCI_XHCI_H_ + +#define PCI_USBREV 0x60 /* USB protocol revision */ + + +enum { /* dsc_slotstate */ + XHCI_ST_DISABLED, + XHCI_ST_ENABLED, + XHCI_ST_DEFAULT, + XHCI_ST_ADDRESSED, + XHCI_ST_CONFIGURED, + XHCI_ST_MAX +}; + +enum { + XHCI_ST_SLCTX_DISABLED, + XHCI_ST_SLCTX_DEFAULT, + XHCI_ST_SLCTX_ADDRESSED, + XHCI_ST_SLCTX_CONFIGURED +}; + +enum { + XHCI_ST_EPCTX_DISABLED, + XHCI_ST_EPCTX_RUNNING, + XHCI_ST_EPCTX_HALTED, + XHCI_ST_EPCTX_STOPPED, + XHCI_ST_EPCTX_ERROR +}; + +#define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) +#define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ +#define XHCI_MAX_SCRATCHPADS 32 +#define XHCI_MAX_EVENTS (16 * 13) +#define XHCI_MAX_COMMANDS (16 * 1) +#define XHCI_MAX_RSEG 1 +#define XHCI_MAX_TRANSFERS 4 +#if USB_MAX_EP_STREAMS == 8 +#define XHCI_MAX_STREAMS 8 +#define XHCI_MAX_STREAMS_LOG 3 +#elif USB_MAX_EP_STREAMS == 1 +#define XHCI_MAX_STREAMS 1 +#define XHCI_MAX_STREAMS_LOG 0 +#else +#error "The USB_MAX_EP_STREAMS value is not supported." +#endif +#define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ +#define XHCI_DEV_CTX_ALIGN 64 /* bytes */ +#define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ +#define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ +#define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ +#define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ +#define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ +#define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ +#define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ +#define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ +#define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE +#define XHCI_TRB_ALIGN 16 /* bytes */ +#define XHCI_TD_ALIGN 64 /* bytes */ +#define XHCI_PAGE_SIZE 4096 /* bytes */ + +struct xhci_slot_ctx { + volatile uint32_t dwSctx0; +#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) +#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) +#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) +#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) +#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) +#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) +#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) +#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) +#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) +#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) + volatile uint32_t dwSctx1; +#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) +#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) +#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) +#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) +#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) +#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) + volatile uint32_t dwSctx2; +#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) +#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) +#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) +#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) +#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) +#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) +#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) +#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) + volatile uint32_t dwSctx3; +#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) +#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) +#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) +#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) + volatile uint32_t dwSctx4; + volatile uint32_t dwSctx5; + volatile uint32_t dwSctx6; + volatile uint32_t dwSctx7; +}; + +struct xhci_endp_ctx { + volatile uint32_t dwEpCtx0; +#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) +#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) +#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) +#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) +#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) +#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) +#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) +#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) +#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) +#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) + volatile uint32_t dwEpCtx1; +#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) +#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) +#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) +#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) +#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) +#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) +#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) +#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) +#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) +#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) + volatile uint64_t qwEpCtx2; +#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) +#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) +#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U + volatile uint32_t dwEpCtx4; +#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) +#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) +#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) +#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) + volatile uint32_t dwEpCtx5; + volatile uint32_t dwEpCtx6; + volatile uint32_t dwEpCtx7; +}; + +struct xhci_input_ctx { +#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU + volatile uint32_t dwInCtx0; +#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) + volatile uint32_t dwInCtx1; +#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) + volatile uint32_t dwInCtx2; + volatile uint32_t dwInCtx3; + volatile uint32_t dwInCtx4; + volatile uint32_t dwInCtx5; + volatile uint32_t dwInCtx6; + volatile uint32_t dwInCtx7; +}; + +struct xhci_input_dev_ctx { + struct xhci_input_ctx ctx_input; + union { + struct xhci_slot_ctx u_slot; + struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS]; + } ctx_dev_slep; +}; + +struct xhci_dev_ctx { + union { + struct xhci_slot_ctx u_slot; + struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS]; + } ctx_dev_slep; +} __aligned(XHCI_DEV_CTX_ALIGN); +#define ctx_slot ctx_dev_slep.u_slot +#define ctx_ep ctx_dev_slep.u_ep + +struct xhci_stream_ctx { + volatile uint64_t qwSctx0; +#define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) +#define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) +#define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) +#define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) +#define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 +#define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 +#define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 +#define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 +#define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 +#define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 +#define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 +#define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 +#define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U + volatile uint32_t dwSctx2; + volatile uint32_t dwSctx3; +}; + +struct xhci_trb { + volatile uint64_t qwTrb0; +#define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) +#define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) + volatile uint32_t dwTrb2; +#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) +#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) +#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) +#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) +#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) +#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) +#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) +#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) +#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) +#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) +#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) +#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) + + volatile uint32_t dwTrb3; +#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) +#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) +#define XHCI_TRB_3_CYCLE_BIT (1U << 0) +#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ +#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ +#define XHCI_TRB_3_ISP_BIT (1U << 2) +#define XHCI_TRB_3_ED_BIT (1U << 2) +#define XHCI_TRB_3_NSNOOP_BIT (1U << 3) +#define XHCI_TRB_3_CHAIN_BIT (1U << 4) +#define XHCI_TRB_3_IOC_BIT (1U << 5) +#define XHCI_TRB_3_IDT_BIT (1U << 6) +#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) +#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) +#define XHCI_TRB_3_BEI_BIT (1U << 9) +#define XHCI_TRB_3_DCEP_BIT (1U << 9) +#define XHCI_TRB_3_PRSV_BIT (1U << 9) +#define XHCI_TRB_3_BSR_BIT (1U << 9) +#define XHCI_TRB_3_TRT_MASK (3U << 16) +#define XHCI_TRB_3_TRT_NONE (0U << 16) +#define XHCI_TRB_3_TRT_OUT (2U << 16) +#define XHCI_TRB_3_TRT_IN (3U << 16) +#define XHCI_TRB_3_DIR_IN (1U << 16) +#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) +#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) +#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) +#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) +#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) +#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) +#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) +#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) +#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) +#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) + +/* Commands */ +#define XHCI_TRB_TYPE_RESERVED 0x00 +#define XHCI_TRB_TYPE_NORMAL 0x01 +#define XHCI_TRB_TYPE_SETUP_STAGE 0x02 +#define XHCI_TRB_TYPE_DATA_STAGE 0x03 +#define XHCI_TRB_TYPE_STATUS_STAGE 0x04 +#define XHCI_TRB_TYPE_ISOCH 0x05 +#define XHCI_TRB_TYPE_LINK 0x06 +#define XHCI_TRB_TYPE_EVENT_DATA 0x07 +#define XHCI_TRB_TYPE_NOOP 0x08 +#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 +#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A +#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B +#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C +#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D +#define XHCI_TRB_TYPE_RESET_EP 0x0E +#define XHCI_TRB_TYPE_STOP_EP 0x0F +#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 +#define XHCI_TRB_TYPE_RESET_DEVICE 0x11 +#define XHCI_TRB_TYPE_FORCE_EVENT 0x12 +#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 +#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 +#define XHCI_TRB_TYPE_GET_PORT_BW 0x15 +#define XHCI_TRB_TYPE_FORCE_HEADER 0x16 +#define XHCI_TRB_TYPE_NOOP_CMD 0x17 + +/* Events */ +#define XHCI_TRB_EVENT_TRANSFER 0x20 +#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 +#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 +#define XHCI_TRB_EVENT_BW_REQUEST 0x23 +#define XHCI_TRB_EVENT_DOORBELL 0x24 +#define XHCI_TRB_EVENT_HOST_CTRL 0x25 +#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 +#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 + +/* Error codes */ +#define XHCI_TRB_ERROR_INVALID 0x00 +#define XHCI_TRB_ERROR_SUCCESS 0x01 +#define XHCI_TRB_ERROR_DATA_BUF 0x02 +#define XHCI_TRB_ERROR_BABBLE 0x03 +#define XHCI_TRB_ERROR_XACT 0x04 +#define XHCI_TRB_ERROR_TRB 0x05 +#define XHCI_TRB_ERROR_STALL 0x06 +#define XHCI_TRB_ERROR_RESOURCE 0x07 +#define XHCI_TRB_ERROR_BANDWIDTH 0x08 +#define XHCI_TRB_ERROR_NO_SLOTS 0x09 +#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A +#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B +#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C +#define XHCI_TRB_ERROR_SHORT_PKT 0x0D +#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E +#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F +#define XHCI_TRB_ERROR_VF_RING_FULL 0x10 +#define XHCI_TRB_ERROR_PARAMETER 0x11 +#define XHCI_TRB_ERROR_BW_OVERRUN 0x12 +#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 +#define XHCI_TRB_ERROR_NO_PING_RESP 0x14 +#define XHCI_TRB_ERROR_EV_RING_FULL 0x15 +#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 +#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 +#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 +#define XHCI_TRB_ERROR_CMD_ABORTED 0x19 +#define XHCI_TRB_ERROR_STOPPED 0x1A +#define XHCI_TRB_ERROR_LENGTH 0x1B +#define XHCI_TRB_ERROR_BAD_MELAT 0x1D +#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F +#define XHCI_TRB_ERROR_EVENT_LOST 0x20 +#define XHCI_TRB_ERROR_UNDEFINED 0x21 +#define XHCI_TRB_ERROR_INVALID_SID 0x22 +#define XHCI_TRB_ERROR_SEC_BW 0x23 +#define XHCI_TRB_ERROR_SPLIT_XACT 0x24 +} __aligned(4); + +struct xhci_dev_endpoint_trbs { + struct xhci_trb trb[(XHCI_MAX_STREAMS * + XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; +}; + +struct xhci_event_ring_seg { + volatile uint64_t qwEvrsTablePtr; + volatile uint32_t dwEvrsTableSize; + volatile uint32_t dwEvrsReserved; +}; + +#endif /* _PCI_XHCI_H_ */ diff --git a/usr.sbin/bhyve/ps2kbd.c b/usr.sbin/bhyve/ps2kbd.c new file mode 100644 index 0000000..96c71e6 --- /dev/null +++ b/usr.sbin/bhyve/ps2kbd.c @@ -0,0 +1,472 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * Copyright (c) 2015 Nahanni Systems Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> + +#include <assert.h> +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> +#include <strings.h> +#include <pthread.h> +#include <pthread_np.h> + +#include "atkbdc.h" +#include "console.h" + +/* keyboard device commands */ +#define PS2KC_RESET_DEV 0xff +#define PS2KC_DISABLE 0xf5 +#define PS2KC_ENABLE 0xf4 +#define PS2KC_SET_TYPEMATIC 0xf3 +#define PS2KC_SEND_DEV_ID 0xf2 +#define PS2KC_SET_SCANCODE_SET 0xf0 +#define PS2KC_ECHO 0xee +#define PS2KC_SET_LEDS 0xed + +#define PS2KC_BAT_SUCCESS 0xaa +#define PS2KC_ACK 0xfa + +#define PS2KBD_FIFOSZ 16 + +struct fifo { + uint8_t buf[PS2KBD_FIFOSZ]; + int rindex; /* index to read from */ + int windex; /* index to write to */ + int num; /* number of bytes in the fifo */ + int size; /* size of the fifo */ +}; + +struct ps2kbd_softc { + struct atkbdc_softc *atkbdc_sc; + pthread_mutex_t mtx; + + bool enabled; + struct fifo fifo; + + uint8_t curcmd; /* current command for next byte */ +}; + +static void +fifo_init(struct ps2kbd_softc *sc) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + fifo->size = sizeof(((struct fifo *)0)->buf); +} + +static void +fifo_reset(struct ps2kbd_softc *sc) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + bzero(fifo, sizeof(struct fifo)); + fifo->size = sizeof(((struct fifo *)0)->buf); +} + +static void +fifo_put(struct ps2kbd_softc *sc, uint8_t val) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + if (fifo->num < fifo->size) { + fifo->buf[fifo->windex] = val; + fifo->windex = (fifo->windex + 1) % fifo->size; + fifo->num++; + } +} + +static int +fifo_get(struct ps2kbd_softc *sc, uint8_t *val) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + if (fifo->num > 0) { + *val = fifo->buf[fifo->rindex]; + fifo->rindex = (fifo->rindex + 1) % fifo->size; + fifo->num--; + return (0); + } + + return (-1); +} + +int +ps2kbd_read(struct ps2kbd_softc *sc, uint8_t *val) +{ + int retval; + + pthread_mutex_lock(&sc->mtx); + retval = fifo_get(sc, val); + pthread_mutex_unlock(&sc->mtx); + + return (retval); +} + +void +ps2kbd_write(struct ps2kbd_softc *sc, uint8_t val) +{ + pthread_mutex_lock(&sc->mtx); + if (sc->curcmd) { + switch (sc->curcmd) { + case PS2KC_SET_TYPEMATIC: + fifo_put(sc, PS2KC_ACK); + break; + case PS2KC_SET_SCANCODE_SET: + fifo_put(sc, PS2KC_ACK); + break; + case PS2KC_SET_LEDS: + fifo_put(sc, PS2KC_ACK); + break; + default: + fprintf(stderr, "Unhandled ps2 keyboard current " + "command byte 0x%02x\n", val); + break; + } + sc->curcmd = 0; + } else { + switch (val) { + case 0x00: + fifo_put(sc, PS2KC_ACK); + break; + case PS2KC_RESET_DEV: + fifo_reset(sc); + fifo_put(sc, PS2KC_ACK); + fifo_put(sc, PS2KC_BAT_SUCCESS); + break; + case PS2KC_DISABLE: + sc->enabled = false; + fifo_put(sc, PS2KC_ACK); + break; + case PS2KC_ENABLE: + sc->enabled = true; + fifo_reset(sc); + fifo_put(sc, PS2KC_ACK); + break; + case PS2KC_SET_TYPEMATIC: + sc->curcmd = val; + fifo_put(sc, PS2KC_ACK); + break; + case PS2KC_SEND_DEV_ID: + fifo_put(sc, PS2KC_ACK); + fifo_put(sc, 0xab); + fifo_put(sc, 0x83); + break; + case PS2KC_SET_SCANCODE_SET: + sc->curcmd = val; + fifo_put(sc, PS2KC_ACK); + break; + case PS2KC_ECHO: + fifo_put(sc, PS2KC_ECHO); + break; + case PS2KC_SET_LEDS: + sc->curcmd = val; + fifo_put(sc, PS2KC_ACK); + break; + default: + fprintf(stderr, "Unhandled ps2 keyboard command " + "0x%02x\n", val); + break; + } + } + pthread_mutex_unlock(&sc->mtx); +} + +/* + * Translate keysym to type 2 scancode and insert into keyboard buffer. + */ +static void +ps2kbd_keysym_queue(struct ps2kbd_softc *sc, + int down, uint32_t keysym) +{ + /* ASCII to type 2 scancode lookup table */ + const uint8_t translation[128] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x29, 0x16, 0x52, 0x26, 0x25, 0x2e, 0x3d, 0x52, + 0x46, 0x45, 0x3e, 0x55, 0x41, 0x4e, 0x49, 0x4a, + 0x45, 0x16, 0x1e, 0x26, 0x25, 0x2e, 0x36, 0x3d, + 0x3e, 0x46, 0x4c, 0x4c, 0x41, 0x55, 0x49, 0x4a, + 0x1e, 0x1c, 0x32, 0x21, 0x23, 0x24, 0x2b, 0x34, + 0x33, 0x43, 0x3b, 0x42, 0x4b, 0x3a, 0x31, 0x44, + 0x4d, 0x15, 0x2d, 0x1b, 0x2c, 0x3c, 0x2a, 0x1d, + 0x22, 0x35, 0x1a, 0x54, 0x5d, 0x5b, 0x36, 0x4e, + 0x0e, 0x1c, 0x32, 0x21, 0x23, 0x24, 0x2b, 0x34, + 0x33, 0x43, 0x3b, 0x42, 0x4b, 0x3a, 0x31, 0x44, + 0x4d, 0x15, 0x2d, 0x1b, 0x2c, 0x3c, 0x2a, 0x1d, + 0x22, 0x35, 0x1a, 0x54, 0x5d, 0x5b, 0x0e, 0x00, + }; + + assert(pthread_mutex_isowned_np(&sc->mtx)); + + switch (keysym) { + case 0x0 ... 0x7f: + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, translation[keysym]); + break; + case 0xff08: /* Back space */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x66); + break; + case 0xff09: /* Tab */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x0d); + break; + case 0xff0d: /* Return */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x5a); + break; + case 0xff1b: /* Escape */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x76); + break; + case 0xff50: /* Home */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x6c); + break; + case 0xff51: /* Left arrow */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x6b); + break; + case 0xff52: /* Up arrow */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x75); + break; + case 0xff53: /* Right arrow */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x74); + break; + case 0xff54: /* Down arrow */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x72); + break; + case 0xff55: /* PgUp */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x7d); + break; + case 0xff56: /* PgDwn */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x7a); + break; + case 0xff57: /* End */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x69); + break; + case 0xff63: /* Ins */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x70); + break; + case 0xff8d: /* Keypad Enter */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x5a); + break; + case 0xffe1: /* Left shift */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x12); + break; + case 0xffe2: /* Right shift */ + /* XXX */ + break; + case 0xffe3: /* Left control */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x14); + break; + case 0xffe4: /* Right control */ + /* XXX */ + break; + case 0xffe7: /* Left meta */ + /* XXX */ + break; + case 0xffe8: /* Right meta */ + /* XXX */ + break; + case 0xffe9: /* Left alt */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x11); + break; + case 0xffea: /* Right alt */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x11); + break; + case 0xffeb: /* Left Windows */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x1f); + break; + case 0xffec: /* Right Windows */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x27); + break; + case 0xffbe: /* F1 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x05); + break; + case 0xffbf: /* F2 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x06); + break; + case 0xffc0: /* F3 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x04); + break; + case 0xffc1: /* F4 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x0C); + break; + case 0xffc2: /* F5 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x03); + break; + case 0xffc3: /* F6 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x0B); + break; + case 0xffc4: /* F7 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x83); + break; + case 0xffc5: /* F8 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x0A); + break; + case 0xffc6: /* F9 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x01); + break; + case 0xffc7: /* F10 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x09); + break; + case 0xffc8: /* F11 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x78); + break; + case 0xffc9: /* F12 */ + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x07); + break; + case 0xffff: /* Del */ + fifo_put(sc, 0xe0); + if (!down) + fifo_put(sc, 0xf0); + fifo_put(sc, 0x71); + break; + default: + fprintf(stderr, "Unhandled ps2 keyboard keysym 0x%x\n", + keysym); + break; + } +} + +static void +ps2kbd_event(int down, uint32_t keysym, void *arg) +{ + struct ps2kbd_softc *sc = arg; + int fifo_full; + + pthread_mutex_lock(&sc->mtx); + if (!sc->enabled) { + pthread_mutex_unlock(&sc->mtx); + return; + } + fifo_full = sc->fifo.num == PS2KBD_FIFOSZ; + ps2kbd_keysym_queue(sc, down, keysym); + pthread_mutex_unlock(&sc->mtx); + + if (!fifo_full) + atkbdc_event(sc->atkbdc_sc, 1); +} + +struct ps2kbd_softc * +ps2kbd_init(struct atkbdc_softc *atkbdc_sc) +{ + struct ps2kbd_softc *sc; + + sc = calloc(1, sizeof (struct ps2kbd_softc)); + pthread_mutex_init(&sc->mtx, NULL); + fifo_init(sc); + sc->atkbdc_sc = atkbdc_sc; + + console_kbd_register(ps2kbd_event, sc, 1); + + return (sc); +} + diff --git a/usr.sbin/bhyve/ps2kbd.h b/usr.sbin/bhyve/ps2kbd.h new file mode 100644 index 0000000..34c31b1 --- /dev/null +++ b/usr.sbin/bhyve/ps2kbd.h @@ -0,0 +1,39 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _PS2KBD_H_ +#define _PS2KBD_H_ + +struct atkbdc_softc; + +struct ps2kbd_softc *ps2kbd_init(struct atkbdc_softc *sc); + +int ps2kbd_read(struct ps2kbd_softc *sc, uint8_t *val); +void ps2kbd_write(struct ps2kbd_softc *sc, uint8_t val); + +#endif /* _PS2KBD_H_ */ diff --git a/usr.sbin/bhyve/ps2mouse.c b/usr.sbin/bhyve/ps2mouse.c new file mode 100644 index 0000000..e207a93 --- /dev/null +++ b/usr.sbin/bhyve/ps2mouse.c @@ -0,0 +1,405 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * Copyright (c) 2015 Nahanni Systems Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> + +#include <assert.h> +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> +#include <strings.h> +#include <pthread.h> +#include <pthread_np.h> + +#include "atkbdc.h" +#include "console.h" + +/* mouse device commands */ +#define PS2MC_RESET_DEV 0xff +#define PS2MC_SET_DEFAULTS 0xf6 +#define PS2MC_DISABLE 0xf5 +#define PS2MC_ENABLE 0xf4 +#define PS2MC_SET_SAMPLING_RATE 0xf3 +#define PS2MC_SEND_DEV_ID 0xf2 +#define PS2MC_SET_REMOTE_MODE 0xf0 +#define PS2MC_SEND_DEV_DATA 0xeb +#define PS2MC_SET_STREAM_MODE 0xea +#define PS2MC_SEND_DEV_STATUS 0xe9 +#define PS2MC_SET_RESOLUTION 0xe8 +#define PS2MC_SET_SCALING1 0xe7 +#define PS2MC_SET_SCALING2 0xe6 + +#define PS2MC_BAT_SUCCESS 0xaa +#define PS2MC_ACK 0xfa + +/* mouse device id */ +#define PS2MOUSE_DEV_ID 0x0 + +/* mouse status bits */ +#define PS2M_STS_REMOTE_MODE 0x40 +#define PS2M_STS_ENABLE_DEV 0x20 +#define PS2M_STS_SCALING_21 0x10 +#define PS2M_STS_MID_BUTTON 0x04 +#define PS2M_STS_RIGHT_BUTTON 0x02 +#define PS2M_STS_LEFT_BUTTON 0x01 + +#define PS2MOUSE_FIFOSZ 16 + +struct fifo { + uint8_t buf[PS2MOUSE_FIFOSZ]; + int rindex; /* index to read from */ + int windex; /* index to write to */ + int num; /* number of bytes in the fifo */ + int size; /* size of the fifo */ +}; + +struct ps2mouse_softc { + struct atkbdc_softc *atkbdc_sc; + pthread_mutex_t mtx; + + uint8_t status; + uint8_t resolution; + uint8_t sampling_rate; + int ctrlenable; + struct fifo fifo; + + uint8_t curcmd; /* current command for next byte */ + + int cur_x, cur_y; + int delta_x, delta_y; +}; + +static void +fifo_init(struct ps2mouse_softc *sc) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + fifo->size = sizeof(((struct fifo *)0)->buf); +} + +static void +fifo_reset(struct ps2mouse_softc *sc) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + bzero(fifo, sizeof(struct fifo)); + fifo->size = sizeof(((struct fifo *)0)->buf); +} + +static void +fifo_put(struct ps2mouse_softc *sc, uint8_t val) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + if (fifo->num < fifo->size) { + fifo->buf[fifo->windex] = val; + fifo->windex = (fifo->windex + 1) % fifo->size; + fifo->num++; + } +} + +static int +fifo_get(struct ps2mouse_softc *sc, uint8_t *val) +{ + struct fifo *fifo; + + fifo = &sc->fifo; + if (fifo->num > 0) { + *val = fifo->buf[fifo->rindex]; + fifo->rindex = (fifo->rindex + 1) % fifo->size; + fifo->num--; + return (0); + } + + return (-1); +} + +static void +movement_reset(struct ps2mouse_softc *sc) +{ + assert(pthread_mutex_isowned_np(&sc->mtx)); + + sc->delta_x = 0; + sc->delta_y = 0; +} + +static void +movement_update(struct ps2mouse_softc *sc, int x, int y) +{ + sc->delta_x += x - sc->cur_x; + sc->delta_y += sc->cur_y - y; + sc->cur_x = x; + sc->cur_y = y; +} + +static void +movement_get(struct ps2mouse_softc *sc) +{ + uint8_t val0, val1, val2; + + assert(pthread_mutex_isowned_np(&sc->mtx)); + + val0 = sc->status & (PS2M_STS_LEFT_BUTTON | + PS2M_STS_RIGHT_BUTTON | PS2M_STS_MID_BUTTON); + + if (sc->delta_x >= 0) { + if (sc->delta_x > 255) { + val0 |= (1 << 6); + val1 = 255; + } else + val1 = sc->delta_x; + } else { + val0 |= (1 << 4); + if (sc->delta_x < -255) { + val0 |= (1 << 6); + val1 = 255; + } else + val1 = sc->delta_x; + } + sc->delta_x = 0; + + if (sc->delta_y >= 0) { + if (sc->delta_y > 255) { + val0 |= (1 << 7); + val2 = 255; + } else + val2 = sc->delta_y; + } else { + val0 |= (1 << 5); + if (sc->delta_y < -255) { + val0 |= (1 << 7); + val2 = 255; + } else + val2 = sc->delta_y; + } + sc->delta_y = 0; + + if (sc->fifo.num < (sc->fifo.size - 3)) { + fifo_put(sc, val0); + fifo_put(sc, val1); + fifo_put(sc, val2); + } +} + +static void +ps2mouse_reset(struct ps2mouse_softc *sc) +{ + assert(pthread_mutex_isowned_np(&sc->mtx)); + fifo_reset(sc); + movement_reset(sc); + sc->status = PS2M_STS_ENABLE_DEV; + sc->resolution = 4; + sc->sampling_rate = 100; + + sc->cur_x = 0; + sc->cur_y = 0; + sc->delta_x = 0; + sc->delta_y = 0; +} + +int +ps2mouse_read(struct ps2mouse_softc *sc, uint8_t *val) +{ + int retval; + + pthread_mutex_lock(&sc->mtx); + retval = fifo_get(sc, val); + pthread_mutex_unlock(&sc->mtx); + + return (retval); +} + +int +ps2mouse_fifocnt(struct ps2mouse_softc *sc) +{ + return (sc->fifo.num); +} + +void +ps2mouse_toggle(struct ps2mouse_softc *sc, int enable) +{ + pthread_mutex_lock(&sc->mtx); + if (enable) + sc->ctrlenable = 1; + else { + sc->ctrlenable = 0; + sc->fifo.rindex = 0; + sc->fifo.windex = 0; + sc->fifo.num = 0; + } + pthread_mutex_unlock(&sc->mtx); +} + +void +ps2mouse_write(struct ps2mouse_softc *sc, uint8_t val, int insert) +{ + pthread_mutex_lock(&sc->mtx); + fifo_reset(sc); + if (sc->curcmd) { + switch (sc->curcmd) { + case PS2MC_SET_SAMPLING_RATE: + sc->sampling_rate = val; + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_SET_RESOLUTION: + sc->resolution = val; + fifo_put(sc, PS2MC_ACK); + break; + default: + fprintf(stderr, "Unhandled ps2 mouse current " + "command byte 0x%02x\n", val); + break; + } + sc->curcmd = 0; + + } else if (insert) { + fifo_put(sc, val); + } else { + switch (val) { + case 0x00: + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_RESET_DEV: + ps2mouse_reset(sc); + fifo_put(sc, PS2MC_ACK); + fifo_put(sc, PS2MC_BAT_SUCCESS); + fifo_put(sc, PS2MOUSE_DEV_ID); + break; + case PS2MC_SET_DEFAULTS: + ps2mouse_reset(sc); + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_DISABLE: + fifo_reset(sc); + sc->status &= ~PS2M_STS_ENABLE_DEV; + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_ENABLE: + fifo_reset(sc); + sc->status |= PS2M_STS_ENABLE_DEV; + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_SET_SAMPLING_RATE: + sc->curcmd = val; + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_SEND_DEV_ID: + fifo_put(sc, PS2MC_ACK); + fifo_put(sc, PS2MOUSE_DEV_ID); + break; + case PS2MC_SET_REMOTE_MODE: + sc->status |= PS2M_STS_REMOTE_MODE; + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_SEND_DEV_DATA: + fifo_put(sc, PS2MC_ACK); + movement_get(sc); + break; + case PS2MC_SET_STREAM_MODE: + sc->status &= ~PS2M_STS_REMOTE_MODE; + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_SEND_DEV_STATUS: + fifo_put(sc, PS2MC_ACK); + fifo_put(sc, sc->status); + fifo_put(sc, sc->resolution); + fifo_put(sc, sc->sampling_rate); + break; + case PS2MC_SET_RESOLUTION: + sc->curcmd = val; + fifo_put(sc, PS2MC_ACK); + break; + case PS2MC_SET_SCALING1: + case PS2MC_SET_SCALING2: + fifo_put(sc, PS2MC_ACK); + break; + default: + fifo_put(sc, PS2MC_ACK); + fprintf(stderr, "Unhandled ps2 mouse command " + "0x%02x\n", val); + break; + } + } + pthread_mutex_unlock(&sc->mtx); +} + +static void +ps2mouse_event(uint8_t button, int x, int y, void *arg) +{ + struct ps2mouse_softc *sc = arg; + + pthread_mutex_lock(&sc->mtx); + movement_update(sc, x, y); + + sc->status &= ~(PS2M_STS_LEFT_BUTTON | + PS2M_STS_RIGHT_BUTTON | PS2M_STS_MID_BUTTON); + if (button & (1 << 0)) + sc->status |= PS2M_STS_LEFT_BUTTON; + if (button & (1 << 1)) + sc->status |= PS2M_STS_MID_BUTTON; + if (button & (1 << 2)) + sc->status |= PS2M_STS_RIGHT_BUTTON; + + if ((sc->status & PS2M_STS_ENABLE_DEV) == 0 || !sc->ctrlenable) { + /* no data reporting */ + pthread_mutex_unlock(&sc->mtx); + return; + } + + movement_get(sc); + pthread_mutex_unlock(&sc->mtx); + + if (sc->fifo.num > 0) + atkbdc_event(sc->atkbdc_sc, 0); +} + +struct ps2mouse_softc * +ps2mouse_init(struct atkbdc_softc *atkbdc_sc) +{ + struct ps2mouse_softc *sc; + + sc = calloc(1, sizeof (struct ps2mouse_softc)); + pthread_mutex_init(&sc->mtx, NULL); + fifo_init(sc); + sc->atkbdc_sc = atkbdc_sc; + + pthread_mutex_lock(&sc->mtx); + ps2mouse_reset(sc); + pthread_mutex_unlock(&sc->mtx); + + console_ptr_register(ps2mouse_event, sc, 1); + + return (sc); +} + + diff --git a/usr.sbin/bhyve/ps2mouse.h b/usr.sbin/bhyve/ps2mouse.h new file mode 100644 index 0000000..10d5698 --- /dev/null +++ b/usr.sbin/bhyve/ps2mouse.h @@ -0,0 +1,41 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _PS2MOUSE_H_ +#define _PS2MOUSE_H_ + +struct atkbdc_softc; + +struct ps2mouse_softc *ps2mouse_init(struct atkbdc_softc *sc); + +int ps2mouse_read(struct ps2mouse_softc *sc, uint8_t *val); +void ps2mouse_write(struct ps2mouse_softc *sc, uint8_t val, int insert); +void ps2mouse_toggle(struct ps2mouse_softc *sc, int enable); +int ps2mouse_fifocnt(struct ps2mouse_softc *sc); + +#endif /* _PS2MOUSE_H_ */ diff --git a/usr.sbin/bhyve/rfb.c b/usr.sbin/bhyve/rfb.c new file mode 100644 index 0000000..fc63a33 --- /dev/null +++ b/usr.sbin/bhyve/rfb.c @@ -0,0 +1,926 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * Copyright (c) 2015 Leon Dang + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/socket.h> +#include <sys/select.h> +#include <sys/time.h> +#include <arpa/inet.h> +#include <machine/cpufunc.h> +#include <machine/specialreg.h> +#include <netinet/in.h> + +#include <assert.h> +#include <pthread.h> +#include <pthread_np.h> +#include <signal.h> +#include <stdbool.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <unistd.h> + +#include <zlib.h> + +#include "bhyvegc.h" +#include "console.h" +#include "rfb.h" +#include "sockstream.h" + +static int rfb_debug = 0; +#define DPRINTF(params) if (rfb_debug) printf params +#define WPRINTF(params) printf params + +struct rfb_softc { + int sfd; + pthread_t tid; + + int cfd; + + int width, height; + + bool enc_raw_ok; + bool enc_zlib_ok; + bool enc_resize_ok; + + z_stream zstream; + uint8_t *zbuf; + int zbuflen; + + int conn_wait; + int sending; + pthread_mutex_t mtx; + pthread_cond_t cond; + + int hw_crc; + uint32_t *crc; /* WxH crc cells */ + uint32_t *crc_tmp; /* buffer to store single crc row */ + int crc_width, crc_height; +}; + +struct rfb_pixfmt { + uint8_t bpp; + uint8_t depth; + uint8_t bigendian; + uint8_t truecolor; + uint16_t red_max; + uint16_t green_max; + uint16_t blue_max; + uint8_t red_shift; + uint8_t green_shift; + uint8_t blue_shift; + uint8_t pad[3]; +}; + +struct rfb_srvr_info { + uint16_t width; + uint16_t height; + struct rfb_pixfmt pixfmt; + uint32_t namelen; +}; + +struct rfb_pixfmt_msg { + uint8_t type; + uint8_t pad[3]; + struct rfb_pixfmt pixfmt; +}; + +#define RFB_ENCODING_RAW 0 +#define RFB_ENCODING_ZLIB 6 +#define RFB_ENCODING_RESIZE -223 + +#define RFB_MAX_WIDTH 2000 +#define RFB_MAX_HEIGHT 1200 +#define RFB_ZLIB_BUFSZ RFB_MAX_WIDTH*RFB_MAX_HEIGHT*4 + +/* percentage changes to screen before sending the entire screen */ +#define RFB_SEND_ALL_THRESH 25 + +struct rfb_enc_msg { + uint8_t type; + uint8_t pad; + uint16_t numencs; +}; + +struct rfb_updt_msg { + uint8_t type; + uint8_t incremental; + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; +}; + +struct rfb_key_msg { + uint8_t type; + uint8_t down; + uint16_t pad; + uint32_t code; +}; + +struct rfb_ptr_msg { + uint8_t type; + uint8_t button; + uint16_t x; + uint16_t y; +}; + +struct rfb_srvr_updt_msg { + uint8_t type; + uint8_t pad; + uint16_t numrects; +}; + +struct rfb_srvr_rect_hdr { + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; + uint32_t encoding; +}; + +struct rfb_cuttext_msg { + uint8_t type; + uint8_t padding[3]; + uint32_t length; +}; + + +static void +rfb_send_server_init_msg(int cfd) +{ + struct bhyvegc_image *gc_image; + struct rfb_srvr_info sinfo; + + gc_image = console_get_image(); + + sinfo.width = htons(gc_image->width); + sinfo.height = htons(gc_image->height); + sinfo.pixfmt.bpp = 32; + sinfo.pixfmt.depth = 32; + sinfo.pixfmt.bigendian = 0; + sinfo.pixfmt.truecolor = 1; + sinfo.pixfmt.red_max = htons(255); + sinfo.pixfmt.green_max = htons(255); + sinfo.pixfmt.blue_max = htons(255); + sinfo.pixfmt.red_shift = 16; + sinfo.pixfmt.green_shift = 8; + sinfo.pixfmt.blue_shift = 0; + sinfo.namelen = htonl(strlen("bhyve")); + (void)stream_write(cfd, &sinfo, sizeof(sinfo)); + (void)stream_write(cfd, "bhyve", strlen("bhyve")); +} + +static void +rfb_send_resize_update_msg(struct rfb_softc *rc, int cfd) +{ + struct rfb_srvr_updt_msg supdt_msg; + struct rfb_srvr_rect_hdr srect_hdr; + + /* Number of rectangles: 1 */ + supdt_msg.type = 0; + supdt_msg.pad = 0; + supdt_msg.numrects = htons(1); + stream_write(cfd, &supdt_msg, sizeof(struct rfb_srvr_updt_msg)); + + /* Rectangle header */ + srect_hdr.x = htons(0); + srect_hdr.y = htons(0); + srect_hdr.width = htons(rc->width); + srect_hdr.height = htons(rc->height); + srect_hdr.encoding = htonl(RFB_ENCODING_RESIZE); + stream_write(cfd, &srect_hdr, sizeof(struct rfb_srvr_rect_hdr)); +} + +static void +rfb_recv_set_pixfmt_msg(struct rfb_softc *rc, int cfd) +{ + struct rfb_pixfmt_msg pixfmt_msg; + + (void)stream_read(cfd, ((void *)&pixfmt_msg)+1, sizeof(pixfmt_msg)-1); +} + + +static void +rfb_recv_set_encodings_msg(struct rfb_softc *rc, int cfd) +{ + struct rfb_enc_msg enc_msg; + int i; + uint32_t encoding; + + assert((sizeof(enc_msg) - 1) == 3); + (void)stream_read(cfd, ((void *)&enc_msg)+1, sizeof(enc_msg)-1); + + for (i = 0; i < htons(enc_msg.numencs); i++) { + (void)stream_read(cfd, &encoding, sizeof(encoding)); + switch (htonl(encoding)) { + case RFB_ENCODING_RAW: + rc->enc_raw_ok = true; + break; + case RFB_ENCODING_ZLIB: + rc->enc_zlib_ok = true; + deflateInit(&rc->zstream, Z_BEST_SPEED); + break; + case RFB_ENCODING_RESIZE: + rc->enc_resize_ok = true; + break; + } + } +} + +/* + * Calculate CRC32 using SSE4.2; Intel or AMD Bulldozer+ CPUs only + */ +static __inline uint32_t +fast_crc32(void *buf, int len, uint32_t crcval) +{ + uint32_t q = len / sizeof(uint32_t); + uint32_t *p = (uint32_t *)buf; + + while (q--) { + asm volatile ( + ".byte 0xf2, 0xf, 0x38, 0xf1, 0xf1;" + :"=S" (crcval) + :"0" (crcval), "c" (*p) + ); + p++; + } + + return (crcval); +} + + +static int +rfb_send_rect(struct rfb_softc *rc, int cfd, struct bhyvegc_image *gc, + int x, int y, int w, int h) +{ + struct rfb_srvr_updt_msg supdt_msg; + struct rfb_srvr_rect_hdr srect_hdr; + unsigned long zlen; + ssize_t nwrite, total; + int err; + uint32_t *p; + uint8_t *zbufp; + + /* + * Send a single rectangle of the given x, y, w h dimensions. + */ + + /* Number of rectangles: 1 */ + supdt_msg.type = 0; + supdt_msg.pad = 0; + supdt_msg.numrects = htons(1); + nwrite = stream_write(cfd, &supdt_msg, + sizeof(struct rfb_srvr_updt_msg)); + if (nwrite <= 0) + return (nwrite); + + + /* Rectangle header */ + srect_hdr.x = htons(x); + srect_hdr.y = htons(y); + srect_hdr.width = htons(w); + srect_hdr.height = htons(h); + + h = y + h; + w *= sizeof(uint32_t); + if (rc->enc_zlib_ok) { + zbufp = rc->zbuf; + rc->zstream.total_in = 0; + rc->zstream.total_out = 0; + for (p = &gc->data[y * gc->width + x]; y < h; y++) { + rc->zstream.next_in = (Bytef *)p; + rc->zstream.avail_in = w; + rc->zstream.next_out = (Bytef *)zbufp; + rc->zstream.avail_out = RFB_ZLIB_BUFSZ + 16 - + rc->zstream.total_out; + rc->zstream.data_type = Z_BINARY; + + /* Compress with zlib */ + err = deflate(&rc->zstream, Z_SYNC_FLUSH); + if (err != Z_OK) { + WPRINTF(("zlib[rect] deflate err: %d\n", err)); + rc->enc_zlib_ok = false; + deflateEnd(&rc->zstream); + goto doraw; + } + zbufp = rc->zbuf + rc->zstream.total_out; + p += gc->width; + } + srect_hdr.encoding = htonl(RFB_ENCODING_ZLIB); + nwrite = stream_write(cfd, &srect_hdr, + sizeof(struct rfb_srvr_rect_hdr)); + if (nwrite <= 0) + return (nwrite); + + zlen = htonl(rc->zstream.total_out); + nwrite = stream_write(cfd, &zlen, sizeof(uint32_t)); + if (nwrite <= 0) + return (nwrite); + return (stream_write(cfd, rc->zbuf, rc->zstream.total_out)); + } + +doraw: + + total = 0; + zbufp = rc->zbuf; + for (p = &gc->data[y * gc->width + x]; y < h; y++) { + memcpy(zbufp, p, w); + zbufp += w; + total += w; + p += gc->width; + } + + srect_hdr.encoding = htonl(RFB_ENCODING_RAW); + nwrite = stream_write(cfd, &srect_hdr, + sizeof(struct rfb_srvr_rect_hdr)); + if (nwrite <= 0) + return (nwrite); + + total = stream_write(cfd, rc->zbuf, total); + + return (total); +} + +static int +rfb_send_all(struct rfb_softc *rc, int cfd, struct bhyvegc_image *gc) +{ + struct rfb_srvr_updt_msg supdt_msg; + struct rfb_srvr_rect_hdr srect_hdr; + ssize_t nwrite; + unsigned long zlen; + int err; + + /* + * Send the whole thing + */ + + /* Number of rectangles: 1 */ + supdt_msg.type = 0; + supdt_msg.pad = 0; + supdt_msg.numrects = htons(1); + nwrite = stream_write(cfd, &supdt_msg, + sizeof(struct rfb_srvr_updt_msg)); + if (nwrite <= 0) + return (nwrite); + + /* Rectangle header */ + srect_hdr.x = 0; + srect_hdr.y = 0; + srect_hdr.width = htons(gc->width); + srect_hdr.height = htons(gc->height); + if (rc->enc_zlib_ok) { + rc->zstream.next_in = (Bytef *)gc->data; + rc->zstream.avail_in = gc->width * gc->height * + sizeof(uint32_t); + rc->zstream.next_out = (Bytef *)rc->zbuf; + rc->zstream.avail_out = RFB_ZLIB_BUFSZ + 16; + rc->zstream.data_type = Z_BINARY; + + rc->zstream.total_in = 0; + rc->zstream.total_out = 0; + + /* Compress with zlib */ + err = deflate(&rc->zstream, Z_SYNC_FLUSH); + if (err != Z_OK) { + WPRINTF(("zlib deflate err: %d\n", err)); + rc->enc_zlib_ok = false; + deflateEnd(&rc->zstream); + goto doraw; + } + + srect_hdr.encoding = htonl(RFB_ENCODING_ZLIB); + nwrite = stream_write(cfd, &srect_hdr, + sizeof(struct rfb_srvr_rect_hdr)); + if (nwrite <= 0) + return (nwrite); + + zlen = htonl(rc->zstream.total_out); + nwrite = stream_write(cfd, &zlen, sizeof(uint32_t)); + if (nwrite <= 0) + return (nwrite); + return (stream_write(cfd, rc->zbuf, rc->zstream.total_out)); + } + +doraw: + srect_hdr.encoding = htonl(RFB_ENCODING_RAW); + nwrite = stream_write(cfd, &srect_hdr, + sizeof(struct rfb_srvr_rect_hdr)); + if (nwrite <= 0) + return (nwrite); + + nwrite = stream_write(cfd, gc->data, + gc->width * gc->height * sizeof(uint32_t)); + + return (nwrite); +} + +#define PIX_PER_CELL 32 +#define PIXCELL_SHIFT 5 +#define PIXCELL_MASK 0x1F + +static int +rfb_send_screen(struct rfb_softc *rc, int cfd, int all) +{ + struct bhyvegc_image *gc_image; + ssize_t nwrite; + int x, y; + int celly, cellwidth; + int xcells, ycells; + int w, h; + uint32_t *p; + int rem_x, rem_y; /* remainder for resolutions not x32 pixels ratio */ + int retval; + uint32_t *crc_p, *orig_crc; + int changes; + + console_refresh(); + gc_image = console_get_image(); + + pthread_mutex_lock(&rc->mtx); + if (rc->sending) { + pthread_mutex_unlock(&rc->mtx); + return (1); + } + rc->sending = 1; + pthread_mutex_unlock(&rc->mtx); + + retval = 0; + + if (all) { + retval = rfb_send_all(rc, cfd, gc_image); + goto done; + } + + /* + * Calculate the checksum for each 32x32 cell. Send each that + * has changed since the last scan. + */ + + /* Resolution changed */ + + rc->crc_width = gc_image->width; + rc->crc_height = gc_image->height; + + w = rc->crc_width; + h = rc->crc_height; + xcells = howmany(rc->crc_width, PIX_PER_CELL); + ycells = howmany(rc->crc_height, PIX_PER_CELL); + + rem_x = w & PIXCELL_MASK; + + rem_y = h & PIXCELL_MASK; + if (!rem_y) + rem_y = PIX_PER_CELL; + + p = gc_image->data; + + /* + * Go through all cells and calculate crc. If significant number + * of changes, then send entire screen. + * crc_tmp is dual purpose: to store the new crc and to flag as + * a cell that has changed. + */ + crc_p = rc->crc_tmp - xcells; + orig_crc = rc->crc - xcells; + changes = 0; + memset(rc->crc_tmp, 0, sizeof(uint32_t) * xcells * ycells); + for (y = 0; y < h; y++) { + if ((y & PIXCELL_MASK) == 0) { + crc_p += xcells; + orig_crc += xcells; + } + + for (x = 0; x < xcells; x++) { + if (rc->hw_crc) + crc_p[x] = fast_crc32(p, + PIX_PER_CELL * sizeof(uint32_t), + crc_p[x]); + else + crc_p[x] = (uint32_t)crc32(crc_p[x], + (Bytef *)p, + PIX_PER_CELL * sizeof(uint32_t)); + + p += PIX_PER_CELL; + + /* check for crc delta if last row in cell */ + if ((y & PIXCELL_MASK) == PIXCELL_MASK || y == (h-1)) { + if (orig_crc[x] != crc_p[x]) { + orig_crc[x] = crc_p[x]; + crc_p[x] = 1; + changes++; + } else { + crc_p[x] = 0; + } + } + } + + if (rem_x) { + if (rc->hw_crc) + crc_p[x] = fast_crc32(p, + rem_x * sizeof(uint32_t), + crc_p[x]); + else + crc_p[x] = (uint32_t)crc32(crc_p[x], + (Bytef *)p, + rem_x * sizeof(uint32_t)); + p += rem_x; + + if ((y & PIXCELL_MASK) == PIXCELL_MASK || y == (h-1)) { + if (orig_crc[x] != crc_p[x]) { + orig_crc[x] = crc_p[x]; + crc_p[x] = 1; + changes++; + } else { + crc_p[x] = 0; + } + } + } + } + + /* If number of changes is > THRESH percent, send the whole screen */ + if (((changes * 100) / (xcells * ycells)) >= RFB_SEND_ALL_THRESH) { + retval = rfb_send_all(rc, cfd, gc_image); + goto done; + } + + /* Go through all cells, and send only changed ones */ + crc_p = rc->crc_tmp; + for (y = 0; y < h; y += PIX_PER_CELL) { + /* previous cell's row */ + celly = (y >> PIXCELL_SHIFT); + + /* Delta check crc to previous set */ + for (x = 0; x < xcells; x++) { + if (*crc_p++ == 0) + continue; + + if (x == (xcells - 1) && rem_x > 0) + cellwidth = rem_x; + else + cellwidth = PIX_PER_CELL; + nwrite = rfb_send_rect(rc, cfd, + gc_image, + x * PIX_PER_CELL, + celly * PIX_PER_CELL, + cellwidth, + y + PIX_PER_CELL >= h ? rem_y : PIX_PER_CELL); + if (nwrite <= 0) { + retval = nwrite; + goto done; + } + } + } + retval = 1; + +done: + pthread_mutex_lock(&rc->mtx); + rc->sending = 0; + pthread_mutex_unlock(&rc->mtx); + + return (retval); +} + + +static void +rfb_recv_update_msg(struct rfb_softc *rc, int cfd, int discardonly) +{ + struct rfb_updt_msg updt_msg; + struct bhyvegc_image *gc_image; + + (void)stream_read(cfd, ((void *)&updt_msg) + 1 , sizeof(updt_msg) - 1); + + console_refresh(); + gc_image = console_get_image(); + + updt_msg.x = htons(updt_msg.x); + updt_msg.y = htons(updt_msg.y); + updt_msg.width = htons(updt_msg.width); + updt_msg.height = htons(updt_msg.height); + + if (updt_msg.width != gc_image->width || + updt_msg.height != gc_image->height) { + rc->width = gc_image->width; + rc->height = gc_image->height; + if (rc->enc_resize_ok) + rfb_send_resize_update_msg(rc, cfd); + } + + if (discardonly) + return; + + rfb_send_screen(rc, cfd, 1); +} + +static void +rfb_recv_key_msg(struct rfb_softc *rc, int cfd) +{ + struct rfb_key_msg key_msg; + + (void)stream_read(cfd, ((void *)&key_msg) + 1, sizeof(key_msg) - 1); + + console_key_event(key_msg.down, htonl(key_msg.code)); +} + +static void +rfb_recv_ptr_msg(struct rfb_softc *rc, int cfd) +{ + struct rfb_ptr_msg ptr_msg; + + (void)stream_read(cfd, ((void *)&ptr_msg) + 1, sizeof(ptr_msg) - 1); + + console_ptr_event(ptr_msg.button, htons(ptr_msg.x), htons(ptr_msg.y)); +} + +static void +rfb_recv_cuttext_msg(struct rfb_softc *rc, int cfd) +{ + struct rfb_cuttext_msg ct_msg; + unsigned char buf[32]; + int len; + + len = stream_read(cfd, ((void *)&ct_msg) + 1, sizeof(ct_msg) - 1); + ct_msg.length = htonl(ct_msg.length); + while (ct_msg.length > 0) { + len = stream_read(cfd, buf, ct_msg.length > sizeof(buf) ? + sizeof(buf) : ct_msg.length); + ct_msg.length -= len; + } +} + +static int64_t +timeval_delta(struct timeval *prev, struct timeval *now) +{ + int64_t n1, n2; + n1 = now->tv_sec * 1000000 + now->tv_usec; + n2 = prev->tv_sec * 1000000 + prev->tv_usec; + return (n1 - n2); +} + +static void * +rfb_wr_thr(void *arg) +{ + struct rfb_softc *rc; + fd_set rfds; + struct timeval tv; + struct timeval prev_tv; + int64_t tdiff; + int cfd; + int err; + + rc = arg; + cfd = rc->cfd; + + prev_tv.tv_sec = 0; + prev_tv.tv_usec = 0; + while (rc->cfd >= 0) { + FD_ZERO(&rfds); + FD_SET(cfd, &rfds); + tv.tv_sec = 0; + tv.tv_usec = 10000; + + err = select(cfd+1, &rfds, NULL, NULL, &tv); + if (err < 0) + return (NULL); + + /* Determine if its time to push screen; ~24hz */ + gettimeofday(&tv, NULL); + tdiff = timeval_delta(&prev_tv, &tv); + if (tdiff > 40000) { + prev_tv.tv_sec = tv.tv_sec; + prev_tv.tv_usec = tv.tv_usec; + if (rfb_send_screen(rc, cfd, 0) <= 0) { + return (NULL); + } + } else { + /* sleep */ + usleep(40000 - tdiff); + } + } + + return (NULL); +} + +void +rfb_handle(struct rfb_softc *rc, int cfd) +{ + const char *vbuf = "RFB 003.008\n"; + unsigned char buf[80]; + pthread_t tid; + uint32_t sres; + int len; + + rc->cfd = cfd; + + /* 1a. Send server version */ + stream_write(cfd, vbuf, strlen(vbuf)); + + /* 1b. Read client version */ + len = read(cfd, buf, sizeof(buf)); + + /* 2a. Send security type 'none' */ + buf[0] = 1; + buf[1] = 1; /* none */ + stream_write(cfd, buf, 2); + + + /* 2b. Read agreed security type */ + len = stream_read(cfd, buf, 1); + + /* 2c. Write back a status of 0 */ + sres = 0; + stream_write(cfd, &sres, 4); + + /* 3a. Read client shared-flag byte */ + len = stream_read(cfd, buf, 1); + + /* 4a. Write server-init info */ + rfb_send_server_init_msg(cfd); + + if (!rc->zbuf) { + rc->zbuf = malloc(RFB_ZLIB_BUFSZ + 16); + assert(rc->zbuf != NULL); + } + + rfb_send_screen(rc, cfd, 1); + + pthread_create(&tid, NULL, rfb_wr_thr, rc); + pthread_set_name_np(tid, "rfbout"); + + /* Now read in client requests. 1st byte identifies type */ + for (;;) { + len = read(cfd, buf, 1); + if (len <= 0) { + DPRINTF(("rfb client exiting\r\n")); + break; + } + + switch (buf[0]) { + case 0: + rfb_recv_set_pixfmt_msg(rc, cfd); + break; + case 2: + rfb_recv_set_encodings_msg(rc, cfd); + break; + case 3: + rfb_recv_update_msg(rc, cfd, 1); + break; + case 4: + rfb_recv_key_msg(rc, cfd); + break; + case 5: + rfb_recv_ptr_msg(rc, cfd); + break; + case 6: + rfb_recv_cuttext_msg(rc, cfd); + break; + default: + WPRINTF(("rfb unknown cli-code %d!\n", buf[0] & 0xff)); + goto done; + } + } +done: + rc->cfd = -1; + pthread_join(tid, NULL); + if (rc->enc_zlib_ok) + deflateEnd(&rc->zstream); +} + +static void * +rfb_thr(void *arg) +{ + struct rfb_softc *rc; + sigset_t set; + + int cfd; + + rc = arg; + + sigemptyset(&set); + sigaddset(&set, SIGPIPE); + if (pthread_sigmask(SIG_BLOCK, &set, NULL) != 0) { + perror("pthread_sigmask"); + return (NULL); + } + + for (;;) { + rc->enc_raw_ok = false; + rc->enc_zlib_ok = false; + rc->enc_resize_ok = false; + + cfd = accept(rc->sfd, NULL, NULL); + if (rc->conn_wait) { + pthread_mutex_lock(&rc->mtx); + pthread_cond_signal(&rc->cond); + pthread_mutex_unlock(&rc->mtx); + rc->conn_wait = 0; + } + rfb_handle(rc, cfd); + close(cfd); + } + + /* NOTREACHED */ + return (NULL); +} + +static int +sse42_supported(void) +{ + u_int cpu_registers[4], ecx; + + do_cpuid(1, cpu_registers); + + ecx = cpu_registers[2]; + + return ((ecx & CPUID2_SSE42) != 0); +} + +int +rfb_init(char *hostname, int port, int wait) +{ + struct rfb_softc *rc; + struct sockaddr_in sin; + int on = 1; + + rc = calloc(1, sizeof(struct rfb_softc)); + + rc->crc = calloc(howmany(RFB_MAX_WIDTH * RFB_MAX_HEIGHT, 32), + sizeof(uint32_t)); + rc->crc_tmp = calloc(howmany(RFB_MAX_WIDTH * RFB_MAX_HEIGHT, 32), + sizeof(uint32_t)); + rc->crc_width = RFB_MAX_WIDTH; + rc->crc_height = RFB_MAX_HEIGHT; + + rc->sfd = socket(AF_INET, SOCK_STREAM, 0); + if (rc->sfd < 0) { + perror("socket"); + return (-1); + } + + setsockopt(rc->sfd, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on)); + + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_port = htons(port); + if (hostname && strlen(hostname) > 0) + inet_pton(AF_INET, hostname, &(sin.sin_addr)); + else + sin.sin_addr.s_addr = htonl(INADDR_ANY); + + if (bind(rc->sfd, (struct sockaddr *)&sin, sizeof(sin)) < 0) { + perror("bind"); + return (-1); + } + + if (listen(rc->sfd, 1) < 0) { + perror("listen"); + return (-1); + } + + rc->hw_crc = sse42_supported(); + + rc->conn_wait = wait; + if (wait) { + pthread_mutex_init(&rc->mtx, NULL); + pthread_cond_init(&rc->cond, NULL); + } + + pthread_create(&rc->tid, NULL, rfb_thr, rc); + pthread_set_name_np(rc->tid, "rfb"); + + if (wait) { + DPRINTF(("Waiting for rfb client...\n")); + pthread_mutex_lock(&rc->mtx); + pthread_cond_wait(&rc->cond, &rc->mtx); + pthread_mutex_unlock(&rc->mtx); + } + + return (0); +} diff --git a/usr.sbin/bhyve/rfb.h b/usr.sbin/bhyve/rfb.h new file mode 100644 index 0000000..b3d3786 --- /dev/null +++ b/usr.sbin/bhyve/rfb.h @@ -0,0 +1,36 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _RFB_H_ +#define _RFB_H_ + +#define RFB_PORT 5900 + +int rfb_init(char *hostname, int port, int wait); + +#endif /* _RFB_H_ */ diff --git a/usr.sbin/bhyve/sockstream.c b/usr.sbin/bhyve/sockstream.c new file mode 100644 index 0000000..1789206 --- /dev/null +++ b/usr.sbin/bhyve/sockstream.c @@ -0,0 +1,86 @@ +/*- + * Copyright (c) 2015 Nahanni Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <unistd.h> + +#include <errno.h> + +#include "sockstream.h" + +ssize_t +stream_read(int fd, void *buf, ssize_t nbytes) +{ + uint8_t *p; + ssize_t len = 0; + ssize_t n; + + p = buf; + + while (len < nbytes) { + n = read(fd, p + len, nbytes - len); + if (n == 0) + break; + + if (n < 0) { + if (errno == EINTR || errno == EAGAIN) + continue; + return (n); + } + len += n; + } + return (len); +} + +ssize_t +stream_write(int fd, const void *buf, ssize_t nbytes) +{ + const uint8_t *p; + ssize_t len = 0; + ssize_t n; + + p = buf; + + while (len < nbytes) { + n = write(fd, p + len, nbytes - len); + if (n == 0) + break; + if (n < 0) { + if (errno == EINTR || errno == EAGAIN) + continue; + return (n); + } + len += n; + } + return (len); +} + + diff --git a/usr.sbin/bhyve/sockstream.h b/usr.sbin/bhyve/sockstream.h new file mode 100644 index 0000000..bb0b3b0 --- /dev/null +++ b/usr.sbin/bhyve/sockstream.h @@ -0,0 +1,33 @@ +/*- + * Copyright (c) 2015 Nahanni Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include <sys/types.h> +#include <unistd.h> + +ssize_t stream_read(int fd, void *buf, ssize_t nbytes); +ssize_t stream_write(int fd, const void *buf, ssize_t nbytes); diff --git a/usr.sbin/bhyve/task_switch.c b/usr.sbin/bhyve/task_switch.c index 69dfaae..6138bcd 100644 --- a/usr.sbin/bhyve/task_switch.c +++ b/usr.sbin/bhyve/task_switch.c @@ -37,11 +37,11 @@ __FBSDID("$FreeBSD$"); #include <machine/vmm.h> #include <machine/vmm_instruction_emul.h> +#include <assert.h> +#include <errno.h> #include <stdbool.h> #include <stdio.h> #include <stdlib.h> -#include <assert.h> -#include <errno.h> #include <vmmapi.h> @@ -91,7 +91,7 @@ struct tss32 { uint16_t tss_trap; uint16_t tss_iomap; }; -CTASSERT(sizeof(struct tss32) == 104); +static_assert(sizeof(struct tss32) == 104, "compile-time assertion failed"); #define SEL_START(sel) (((sel) & ~0x7)) #define SEL_LIMIT(sel) (((sel) | 0x7)) diff --git a/usr.sbin/bhyve/usb_emul.c b/usr.sbin/bhyve/usb_emul.c new file mode 100644 index 0000000..3dc12a5 --- /dev/null +++ b/usr.sbin/bhyve/usb_emul.c @@ -0,0 +1,76 @@ +/*- + * Copyright (c) 2014 Nahanni Systems Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <sys/queue.h> + +#include <assert.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <pthread.h> + +#include "usb_emul.h" + +SET_DECLARE(usb_emu_set, struct usb_devemu); + +struct usb_devemu * +usb_emu_finddev(char *name) +{ + struct usb_devemu **udpp, *udp; + + SET_FOREACH(udpp, usb_emu_set) { + udp = *udpp; + if (!strcmp(udp->ue_emu, name)) + return (udp); + } + + return (NULL); +} + +struct usb_data_xfer_block * +usb_data_xfer_append(struct usb_data_xfer *xfer, void *buf, int blen, + void *hci_data, int ccs) +{ + struct usb_data_xfer_block *xb; + + if (xfer->ndata >= USB_MAX_XFER_BLOCKS) + return (NULL); + + xb = &xfer->data[xfer->tail]; + xb->buf = buf; + xb->blen = blen; + xb->hci_data = hci_data; + xb->ccs = ccs; + xb->processed = 0; + xb->bdone = 0; + xfer->ndata++; + xfer->tail = (xfer->tail + 1) % USB_MAX_XFER_BLOCKS; + return (xb); +} diff --git a/usr.sbin/bhyve/usb_emul.h b/usr.sbin/bhyve/usb_emul.h new file mode 100644 index 0000000..69df135 --- /dev/null +++ b/usr.sbin/bhyve/usb_emul.h @@ -0,0 +1,156 @@ +/*- + * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _USB_EMUL_H_ +#define _USB_EMUL_H_ + +#include <stdlib.h> +#include <sys/linker_set.h> +#include <pthread.h> + +#define USB_MAX_XFER_BLOCKS 8 + +#define USB_XFER_OUT 0 +#define USB_XFER_IN 1 + + + +struct usb_hci; +struct usb_device_request; +struct usb_data_xfer; + +/* Device emulation handlers */ +struct usb_devemu { + char *ue_emu; /* name of device emulation */ + int ue_usbver; /* usb version: 2 or 3 */ + int ue_usbspeed; /* usb device speed */ + + /* instance creation */ + void *(*ue_init)(struct usb_hci *hci, char *opt); + + /* handlers */ + int (*ue_request)(void *sc, struct usb_data_xfer *xfer); + int (*ue_data)(void *sc, struct usb_data_xfer *xfer, int dir, + int epctx); + int (*ue_reset)(void *sc); + int (*ue_remove)(void *sc); + int (*ue_stop)(void *sc); +}; +#define USB_EMUL_SET(x) DATA_SET(usb_emu_set, x); + +/* + * USB device events to notify HCI when state changes + */ +enum hci_usbev { + USBDEV_ATTACH, + USBDEV_RESET, + USBDEV_STOP, + USBDEV_REMOVE, +}; + +/* usb controller, ie xhci, ehci */ +struct usb_hci { + int (*hci_intr)(struct usb_hci *hci, int epctx); + int (*hci_event)(struct usb_hci *hci, enum hci_usbev evid, + void *param); + void *hci_sc; /* private softc for hci */ + + /* controller managed fields */ + int hci_address; + int hci_port; +}; + +/* + * Each xfer block is mapped to the hci transfer block. + * On input into the device handler, blen is set to the lenght of buf. + * The device handler is to update blen to reflect on the residual size + * of the buffer, i.e. len(buf) - len(consumed). + */ +struct usb_data_xfer_block { + void *buf; /* IN or OUT pointer */ + int blen; /* in:len(buf), out:len(remaining) */ + int bdone; /* bytes transferred */ + uint32_t processed; /* device processed this + errcode */ + void *hci_data; /* HCI private reference */ + int ccs; + uint32_t streamid; + uint64_t trbnext; /* next TRB guest address */ +}; + +struct usb_data_xfer { + struct usb_data_xfer_block data[USB_MAX_XFER_BLOCKS]; + struct usb_device_request *ureq; /* setup ctl request */ + int ndata; /* # of data items */ + int head; + int tail; + pthread_mutex_t mtx; +}; + +enum USB_ERRCODE { + USB_ACK, + USB_NAK, + USB_STALL, + USB_NYET, + USB_ERR, + USB_SHORT +}; + +#define USB_DATA_GET_ERRCODE(x) (x)->processed >> 8 +#define USB_DATA_SET_ERRCODE(x,e) do { \ + (x)->processed = ((x)->processed & 0xFF) | (e << 8); \ + } while (0) + +#define USB_DATA_OK(x,i) ((x)->data[(i)].buf != NULL) + +#define USB_DATA_XFER_INIT(x) do { \ + memset((x), 0, sizeof(*(x))); \ + pthread_mutex_init(&((x)->mtx), NULL); \ + } while (0) + +#define USB_DATA_XFER_RESET(x) do { \ + memset((x)->data, 0, sizeof((x)->data)); \ + (x)->ndata = 0; \ + (x)->head = (x)->tail = 0; \ + } while (0) + +#define USB_DATA_XFER_LOCK(x) do { \ + pthread_mutex_lock(&((x)->mtx)); \ + } while (0) + +#define USB_DATA_XFER_UNLOCK(x) do { \ + pthread_mutex_unlock(&((x)->mtx)); \ + } while (0) + + +struct usb_devemu *usb_emu_finddev(char *name); + +struct usb_data_xfer_block *usb_data_xfer_append(struct usb_data_xfer *xfer, + void *buf, int blen, void *hci_data, int ccs); + + +#endif /* _USB_EMUL_H_ */ diff --git a/usr.sbin/bhyve/usb_mouse.c b/usr.sbin/bhyve/usb_mouse.c new file mode 100644 index 0000000..633fc57 --- /dev/null +++ b/usr.sbin/bhyve/usb_mouse.c @@ -0,0 +1,800 @@ +/*- + * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/time.h> + +#include <pthread.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <dev/usb/usb.h> +#include <dev/usb/usbdi.h> + +#include "usb_emul.h" +#include "console.h" +#include "bhyvegc.h" + +static int umouse_debug = 0; +#define DPRINTF(params) if (umouse_debug) printf params +#define WPRINTF(params) printf params + +/* USB endpoint context (1-15) for reporting mouse data events*/ +#define UMOUSE_INTR_ENDPT 1 + +#define UMOUSE_REPORT_DESC_TYPE 0x22 + +#define UMOUSE_GET_REPORT 0x01 +#define UMOUSE_GET_IDLE 0x02 +#define UMOUSE_GET_PROTOCOL 0x03 +#define UMOUSE_SET_REPORT 0x09 +#define UMOUSE_SET_IDLE 0x0A +#define UMOUSE_SET_PROTOCOL 0x0B + +#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } + +enum { + UMSTR_LANG, + UMSTR_MANUFACTURER, + UMSTR_PRODUCT, + UMSTR_SERIAL, + UMSTR_CONFIG, + UMSTR_MAX +}; + +static const char *umouse_desc_strings[] = { + "\x04\x09", + "BHYVE", + "HID Tablet", + "01", + "HID Tablet Device", +}; + +struct umouse_hid_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bcdHID[2]; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bReportDescriptorType; + uint8_t wItemLength[2]; +} __packed; + +struct umouse_config_desc { + struct usb_config_descriptor confd; + struct usb_interface_descriptor ifcd; + struct umouse_hid_descriptor hidd; + struct usb_endpoint_descriptor endpd; + struct usb_endpoint_ss_comp_descriptor sscompd; +} __packed; + +#define MOUSE_MAX_X 0x8000 +#define MOUSE_MAX_Y 0x8000 + +static const uint8_t umouse_report_desc[] = { + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x02, /* USAGE (Mouse) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x09, 0x01, /* USAGE (Pointer) */ + 0xa1, 0x00, /* COLLECTION (Physical) */ + 0x05, 0x09, /* USAGE_PAGE (Button) */ + 0x19, 0x01, /* USAGE_MINIMUM (Button 1) */ + 0x29, 0x03, /* USAGE_MAXIMUM (Button 3) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x95, 0x03, /* REPORT_COUNT (3) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs); 3 buttons */ + 0x75, 0x05, /* REPORT_SIZE (5) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs); padding */ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x30, /* USAGE (X) */ + 0x09, 0x31, /* USAGE (Y) */ + 0x35, 0x00, /* PHYSICAL_MINIMUM (0) */ + 0x46, 0xff, 0x7f, /* PHYSICAL_MAXIMUM (0x7fff) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xff, 0x7f, /* LOGICAL_MAXIMUM (0x7fff) */ + 0x75, 0x10, /* REPORT_SIZE (16) */ + 0x95, 0x02, /* REPORT_COUNT (2) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + 0x05, 0x01, /* USAGE Page (Generic Desktop) */ + 0x09, 0x38, /* USAGE (Wheel) */ + 0x35, 0x00, /* PHYSICAL_MINIMUM (0) */ + 0x45, 0x00, /* PHYSICAL_MAXIMUM (0) */ + 0x15, 0x81, /* LOGICAL_MINIMUM (-127) */ + 0x25, 0x7f, /* LOGICAL_MAXIMUM (127) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x81, 0x06, /* INPUT (Data,Var,Rel) */ + 0xc0, /* END_COLLECTION */ + 0xc0 /* END_COLLECTION */ +}; + +struct umouse_report { + uint8_t buttons; /* bits: 0 left, 1 right, 2 middle */ + int16_t x; /* x position */ + int16_t y; /* y position */ + int8_t z; /* z wheel position */ +} __packed; + + +#define MSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } + +static struct usb_device_descriptor umouse_dev_desc = { + .bLength = sizeof(umouse_dev_desc), + .bDescriptorType = UDESC_DEVICE, + MSETW(.bcdUSB, UD_USB_3_0), + .bMaxPacketSize = 8, /* max packet size */ + MSETW(.idVendor, 0xFB5D), /* vendor */ + MSETW(.idProduct, 0x0001), /* product */ + MSETW(.bcdDevice, 0), /* device version */ + .iManufacturer = UMSTR_MANUFACTURER, + .iProduct = UMSTR_PRODUCT, + .iSerialNumber = UMSTR_SERIAL, + .bNumConfigurations = 1, +}; + +static struct umouse_config_desc umouse_confd = { + .confd = { + .bLength = sizeof(umouse_confd.confd), + .bDescriptorType = UDESC_CONFIG, + .wTotalLength[0] = sizeof(umouse_confd), + .bNumInterface = 1, + .bConfigurationValue = 1, + .iConfiguration = UMSTR_CONFIG, + .bmAttributes = UC_BUS_POWERED | UC_REMOTE_WAKEUP, + .bMaxPower = 0, + }, + .ifcd = { + .bLength = sizeof(umouse_confd.ifcd), + .bDescriptorType = UDESC_INTERFACE, + .bNumEndpoints = 1, + .bInterfaceClass = UICLASS_HID, + .bInterfaceSubClass = UISUBCLASS_BOOT, + .bInterfaceProtocol = UIPROTO_MOUSE, + }, + .hidd = { + .bLength = sizeof(umouse_confd.hidd), + .bDescriptorType = 0x21, + .bcdHID = { 0x01, 0x10 }, + .bCountryCode = 0, + .bNumDescriptors = 1, + .bReportDescriptorType = UMOUSE_REPORT_DESC_TYPE, + .wItemLength = { sizeof(umouse_report_desc), 0 }, + }, + .endpd = { + .bLength = sizeof(umouse_confd.endpd), + .bDescriptorType = UDESC_ENDPOINT, + .bEndpointAddress = UE_DIR_IN | UMOUSE_INTR_ENDPT, + .bmAttributes = UE_INTERRUPT, + .wMaxPacketSize[0] = 8, + .bInterval = 0xA, + }, + .sscompd = { + .bLength = sizeof(umouse_confd.sscompd), + .bDescriptorType = UDESC_ENDPOINT_SS_COMP, + .bMaxBurst = 0, + .bmAttributes = 0, + MSETW(.wBytesPerInterval, 0), + }, +}; + + +struct umouse_bos_desc { + struct usb_bos_descriptor bosd; + struct usb_devcap_ss_descriptor usbssd; +} __packed; + + +struct umouse_bos_desc umouse_bosd = { + .bosd = { + .bLength = sizeof(umouse_bosd.bosd), + .bDescriptorType = UDESC_BOS, + HSETW(.wTotalLength, sizeof(umouse_bosd)), + .bNumDeviceCaps = 1, + }, + .usbssd = { + .bLength = sizeof(umouse_bosd.usbssd), + .bDescriptorType = UDESC_DEVICE_CAPABILITY, + .bDevCapabilityType = 3, + .bmAttributes = 0, + HSETW(.wSpeedsSupported, 0x08), + .bFunctionalitySupport = 3, + .bU1DevExitLat = 0xa, /* dummy - not used */ + .wU2DevExitLat = { 0x20, 0x00 }, + } +}; + + +struct umouse_softc { + struct usb_hci *hci; + + char *opt; + + struct umouse_report um_report; + int newdata; + struct { + uint8_t idle; + uint8_t protocol; + uint8_t feature; + } hid; + + pthread_mutex_t mtx; + pthread_mutex_t ev_mtx; + int polling; + struct timeval prev_evt; +}; + +static void +umouse_event(uint8_t button, int x, int y, void *arg) +{ + struct umouse_softc *sc; + struct bhyvegc_image *gc; + + gc = console_get_image(); + if (gc == NULL) { + /* not ready */ + return; + } + + sc = arg; + + pthread_mutex_lock(&sc->mtx); + + sc->um_report.buttons = 0; + sc->um_report.z = 0; + + if (button & 0x01) + sc->um_report.buttons |= 0x01; /* left */ + if (button & 0x02) + sc->um_report.buttons |= 0x04; /* middle */ + if (button & 0x04) + sc->um_report.buttons |= 0x02; /* right */ + if (button & 0x8) + sc->um_report.z = 1; + if (button & 0x10) + sc->um_report.z = -1; + + /* scale coords to mouse resolution */ + sc->um_report.x = MOUSE_MAX_X * x / gc->width; + sc->um_report.y = MOUSE_MAX_X * y / gc->height; + sc->newdata = 1; + pthread_mutex_unlock(&sc->mtx); + + pthread_mutex_lock(&sc->ev_mtx); + sc->hci->hci_intr(sc->hci, UE_DIR_IN | UMOUSE_INTR_ENDPT); + pthread_mutex_unlock(&sc->ev_mtx); +} + +static void * +umouse_init(struct usb_hci *hci, char *opt) +{ + struct umouse_softc *sc; + + sc = calloc(1, sizeof(struct umouse_softc)); + sc->hci = hci; + + sc->hid.protocol = 1; /* REPORT protocol */ + sc->opt = strdup(opt); + pthread_mutex_init(&sc->mtx, NULL); + pthread_mutex_init(&sc->ev_mtx, NULL); + + console_ptr_register(umouse_event, sc, 10); + + return (sc); +} + +#define UREQ(x,y) ((x) | ((y) << 8)) + +static int +umouse_request(void *scarg, struct usb_data_xfer *xfer) +{ + struct umouse_softc *sc; + struct usb_data_xfer_block *data; + const char *str; + uint16_t value; + uint16_t index; + uint16_t len; + uint16_t slen; + uint8_t *udata; + int err; + int i, idx; + int eshort; + + sc = scarg; + + data = NULL; + udata = NULL; + idx = xfer->head; + for (i = 0; i < xfer->ndata; i++) { + xfer->data[idx].bdone = 0; + if (data == NULL && USB_DATA_OK(xfer,i)) { + data = &xfer->data[idx]; + udata = data->buf; + } + + xfer->data[idx].processed = 1; + idx = (idx + 1) % USB_MAX_XFER_BLOCKS; + } + + err = USB_ERR_NORMAL_COMPLETION; + eshort = 0; + + if (!xfer->ureq) { + DPRINTF(("umouse_request: port %d\r\n", sc->hci->hci_port)); + goto done; + } + + value = UGETW(xfer->ureq->wValue); + index = UGETW(xfer->ureq->wIndex); + len = UGETW(xfer->ureq->wLength); + + DPRINTF(("umouse_request: port %d, type 0x%x, req 0x%x, val 0x%x, " + "idx 0x%x, len %u\r\n", + sc->hci->hci_port, xfer->ureq->bmRequestType, + xfer->ureq->bRequest, value, index, len)); + + switch (UREQ(xfer->ureq->bRequest, xfer->ureq->bmRequestType)) { + case UREQ(UR_GET_CONFIG, UT_READ_DEVICE): + DPRINTF(("umouse: (UR_GET_CONFIG, UT_READ_DEVICE)\r\n")); + if (!data) + break; + + *udata = umouse_confd.confd.bConfigurationValue; + data->blen = len > 0 ? len - 1 : 0; + eshort = data->blen > 0; + data->bdone += 1; + break; + + case UREQ(UR_GET_DESCRIPTOR, UT_READ_DEVICE): + DPRINTF(("umouse: (UR_GET_DESCRIPTOR, UT_READ_DEVICE) val %x\r\n", + value >> 8)); + if (!data) + break; + + switch (value >> 8) { + case UDESC_DEVICE: + DPRINTF(("umouse: (->UDESC_DEVICE) len %u ?= " + "sizeof(umouse_dev_desc) %lu\r\n", + len, sizeof(umouse_dev_desc))); + if ((value & 0xFF) != 0) { + err = USB_ERR_IOERROR; + goto done; + } + if (len > sizeof(umouse_dev_desc)) { + data->blen = len - sizeof(umouse_dev_desc); + len = sizeof(umouse_dev_desc); + } else + data->blen = 0; + memcpy(data->buf, &umouse_dev_desc, len); + data->bdone += len; + break; + + case UDESC_CONFIG: + DPRINTF(("umouse: (->UDESC_CONFIG)\r\n")); + if ((value & 0xFF) != 0) { + err = USB_ERR_IOERROR; + goto done; + } + if (len > sizeof(umouse_confd)) { + data->blen = len - sizeof(umouse_confd); + len = sizeof(umouse_confd); + } else + data->blen = 0; + + memcpy(data->buf, &umouse_confd, len); + data->bdone += len; + break; + + case UDESC_STRING: + DPRINTF(("umouse: (->UDESC_STRING)\r\n")); + str = NULL; + if ((value & 0xFF) < UMSTR_MAX) + str = umouse_desc_strings[value & 0xFF]; + else + goto done; + + if ((value & 0xFF) == UMSTR_LANG) { + udata[0] = 4; + udata[1] = UDESC_STRING; + data->blen = len - 2; + len -= 2; + data->bdone += 2; + + if (len >= 2) { + udata[2] = str[0]; + udata[3] = str[1]; + data->blen -= 2; + data->bdone += 2; + } else + data->blen = 0; + + goto done; + } + + slen = 2 + strlen(str) * 2; + udata[0] = slen; + udata[1] = UDESC_STRING; + + if (len > slen) { + data->blen = len - slen; + len = slen; + } else + data->blen = 0; + for (i = 2; i < len; i += 2) { + udata[i] = *str++; + udata[i+1] = '\0'; + } + data->bdone += slen; + + break; + + case UDESC_BOS: + DPRINTF(("umouse: USB3 BOS\r\n")); + if (len > sizeof(umouse_bosd)) { + data->blen = len - sizeof(umouse_bosd); + len = sizeof(umouse_bosd); + } else + data->blen = 0; + memcpy(udata, &umouse_bosd, len); + data->bdone += len; + break; + + default: + DPRINTF(("umouse: unknown(%d)->ERROR\r\n", value >> 8)); + err = USB_ERR_IOERROR; + goto done; + } + eshort = data->blen > 0; + break; + + case UREQ(UR_GET_DESCRIPTOR, UT_READ_INTERFACE): + DPRINTF(("umouse: (UR_GET_DESCRIPTOR, UT_READ_INTERFACE) " + "0x%x\r\n", (value >> 8))); + if (!data) + break; + + switch (value >> 8) { + case UMOUSE_REPORT_DESC_TYPE: + if (len > sizeof(umouse_report_desc)) { + data->blen = len - sizeof(umouse_report_desc); + len = sizeof(umouse_report_desc); + } else + data->blen = 0; + memcpy(data->buf, umouse_report_desc, len); + data->bdone += len; + break; + default: + DPRINTF(("umouse: IO ERROR\r\n")); + err = USB_ERR_IOERROR; + goto done; + } + eshort = data->blen > 0; + break; + + case UREQ(UR_GET_INTERFACE, UT_READ_INTERFACE): + DPRINTF(("umouse: (UR_GET_INTERFACE, UT_READ_INTERFACE)\r\n")); + if (index != 0) { + DPRINTF(("umouse get_interface, invalid index %d\r\n", + index)); + err = USB_ERR_IOERROR; + goto done; + } + + if (!data) + break; + + if (len > 0) { + *udata = 0; + data->blen = len - 1; + } + eshort = data->blen > 0; + data->bdone += 1; + break; + + case UREQ(UR_GET_STATUS, UT_READ_DEVICE): + DPRINTF(("umouse: (UR_GET_STATUS, UT_READ_DEVICE)\r\n")); + if (data != NULL && len > 1) { + if (sc->hid.feature == UF_DEVICE_REMOTE_WAKEUP) + USETW(udata, UDS_REMOTE_WAKEUP); + else + USETW(udata, 0); + data->blen = len - 2; + data->bdone += 2; + } + + eshort = data->blen > 0; + break; + + case UREQ(UR_GET_STATUS, UT_READ_INTERFACE): + case UREQ(UR_GET_STATUS, UT_READ_ENDPOINT): + DPRINTF(("umouse: (UR_GET_STATUS, UT_READ_INTERFACE)\r\n")); + if (data != NULL && len > 1) { + USETW(udata, 0); + data->blen = len - 2; + data->bdone += 2; + } + eshort = data->blen > 0; + break; + + case UREQ(UR_SET_ADDRESS, UT_WRITE_DEVICE): + /* XXX Controller should've handled this */ + DPRINTF(("umouse set address %u\r\n", value)); + break; + + case UREQ(UR_SET_CONFIG, UT_WRITE_DEVICE): + DPRINTF(("umouse set config %u\r\n", value)); + break; + + case UREQ(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): + DPRINTF(("umouse set descriptor %u\r\n", value)); + break; + + + case UREQ(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): + DPRINTF(("umouse: (UR_SET_FEATURE, UT_WRITE_DEVICE) %x\r\n", value)); + if (value == UF_DEVICE_REMOTE_WAKEUP) + sc->hid.feature = 0; + break; + + case UREQ(UR_SET_FEATURE, UT_WRITE_DEVICE): + DPRINTF(("umouse: (UR_SET_FEATURE, UT_WRITE_DEVICE) %x\r\n", value)); + if (value == UF_DEVICE_REMOTE_WAKEUP) + sc->hid.feature = UF_DEVICE_REMOTE_WAKEUP; + break; + + case UREQ(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): + case UREQ(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): + case UREQ(UR_SET_FEATURE, UT_WRITE_INTERFACE): + case UREQ(UR_SET_FEATURE, UT_WRITE_ENDPOINT): + DPRINTF(("umouse: (UR_CLEAR_FEATURE, UT_WRITE_INTERFACE)\r\n")); + err = USB_ERR_IOERROR; + goto done; + + case UREQ(UR_SET_INTERFACE, UT_WRITE_INTERFACE): + DPRINTF(("umouse set interface %u\r\n", value)); + break; + + case UREQ(UR_ISOCH_DELAY, UT_WRITE_DEVICE): + DPRINTF(("umouse set isoch delay %u\r\n", value)); + break; + + case UREQ(UR_SET_SEL, 0): + DPRINTF(("umouse set sel\r\n")); + break; + + case UREQ(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): + DPRINTF(("umouse synch frame\r\n")); + break; + + /* HID device requests */ + + case UREQ(UMOUSE_GET_REPORT, UT_READ_CLASS_INTERFACE): + DPRINTF(("umouse: (UMOUSE_GET_REPORT, UT_READ_CLASS_INTERFACE) " + "0x%x\r\n", (value >> 8))); + if (!data) + break; + + if ((value >> 8) == 0x01 && len >= sizeof(sc->um_report)) { + /* TODO read from backend */ + + if (len > sizeof(sc->um_report)) { + data->blen = len - sizeof(sc->um_report); + len = sizeof(sc->um_report); + } else + data->blen = 0; + + memcpy(data->buf, &sc->um_report, len); + data->bdone += len; + } else { + err = USB_ERR_IOERROR; + goto done; + } + eshort = data->blen > 0; + break; + + case UREQ(UMOUSE_GET_IDLE, UT_READ_CLASS_INTERFACE): + if (data != NULL && len > 0) { + *udata = sc->hid.idle; + data->blen = len - 1; + data->bdone += 1; + } + eshort = data->blen > 0; + break; + + case UREQ(UMOUSE_GET_PROTOCOL, UT_READ_CLASS_INTERFACE): + if (data != NULL && len > 0) { + *udata = sc->hid.protocol; + data->blen = len - 1; + data->bdone += 1; + } + eshort = data->blen > 0; + break; + + case UREQ(UMOUSE_SET_REPORT, UT_WRITE_CLASS_INTERFACE): + DPRINTF(("umouse: (UMOUSE_SET_REPORT, UT_WRITE_CLASS_INTERFACE) ignored\r\n")); + break; + + case UREQ(UMOUSE_SET_IDLE, UT_WRITE_CLASS_INTERFACE): + sc->hid.idle = UGETW(xfer->ureq->wValue) >> 8; + DPRINTF(("umouse: (UMOUSE_SET_IDLE, UT_WRITE_CLASS_INTERFACE) %x\r\n", + sc->hid.idle)); + break; + + case UREQ(UMOUSE_SET_PROTOCOL, UT_WRITE_CLASS_INTERFACE): + sc->hid.protocol = UGETW(xfer->ureq->wValue) >> 8; + DPRINTF(("umouse: (UR_CLEAR_FEATURE, UT_WRITE_CLASS_INTERFACE) %x\r\n", + sc->hid.protocol)); + break; + + default: + DPRINTF(("**** umouse request unhandled\r\n")); + err = USB_ERR_IOERROR; + break; + } + +done: + if (xfer->ureq && (xfer->ureq->bmRequestType & UT_WRITE) && + (err == USB_ERR_NORMAL_COMPLETION) && (data != NULL)) + data->blen = 0; + else if (eshort) + err = USB_ERR_SHORT_XFER; + + DPRINTF(("umouse request error code %d (0=ok), blen %u txlen %u\r\n", + err, (data ? data->blen : 0), (data ? data->bdone : 0))); + + return (err); +} + +static int +umouse_data_handler(void *scarg, struct usb_data_xfer *xfer, int dir, + int epctx) +{ + struct umouse_softc *sc; + struct usb_data_xfer_block *data; + uint8_t *udata; + int len, i, idx; + int err; + + DPRINTF(("umouse handle data - DIR=%s|EP=%d, blen %d\r\n", + dir ? "IN" : "OUT", epctx, xfer->data[0].blen)); + + + /* find buffer to add data */ + udata = NULL; + err = USB_ERR_NORMAL_COMPLETION; + + /* handle xfer at first unprocessed item with buffer */ + data = NULL; + idx = xfer->head; + for (i = 0; i < xfer->ndata; i++) { + data = &xfer->data[idx]; + if (data->buf != NULL && data->blen != 0) { + break; + } else { + data->processed = 1; + data = NULL; + } + idx = (idx + 1) % USB_MAX_XFER_BLOCKS; + } + if (!data) + goto done; + + udata = data->buf; + len = data->blen; + + if (udata == NULL) { + DPRINTF(("umouse no buffer provided for input\r\n")); + err = USB_ERR_NOMEM; + goto done; + } + + sc = scarg; + + if (dir) { + + pthread_mutex_lock(&sc->mtx); + + if (!sc->newdata) { + err = USB_ERR_CANCELLED; + USB_DATA_SET_ERRCODE(&xfer->data[xfer->head], USB_NAK); + pthread_mutex_unlock(&sc->mtx); + goto done; + } + + if (sc->polling) { + err = USB_ERR_STALLED; + USB_DATA_SET_ERRCODE(data, USB_STALL); + pthread_mutex_unlock(&sc->mtx); + goto done; + } + sc->polling = 1; + + if (len > 0) { + sc->newdata = 0; + + data->processed = 1; + data->bdone += 6; + memcpy(udata, &sc->um_report, 6); + data->blen = len - 6; + if (data->blen > 0) + err = USB_ERR_SHORT_XFER; + } + + sc->polling = 0; + pthread_mutex_unlock(&sc->mtx); + } else { + USB_DATA_SET_ERRCODE(data, USB_STALL); + err = USB_ERR_STALLED; + } + +done: + return (err); +} + +static int +umouse_reset(void *scarg) +{ + struct umouse_softc *sc; + + sc = scarg; + + sc->newdata = 0; + + return (0); +} + +static int +umouse_remove(void *scarg) +{ + + return (0); +} + +static int +umouse_stop(void *scarg) +{ + + return (0); +} + + +struct usb_devemu ue_mouse = { + .ue_emu = "tablet", + .ue_usbver = 3, + .ue_usbspeed = USB_SPEED_HIGH, + .ue_init = umouse_init, + .ue_request = umouse_request, + .ue_data = umouse_data_handler, + .ue_reset = umouse_reset, + .ue_remove = umouse_remove, + .ue_stop = umouse_stop +}; +USB_EMUL_SET(ue_mouse); diff --git a/usr.sbin/bhyve/vga.c b/usr.sbin/bhyve/vga.c new file mode 100644 index 0000000..208064b --- /dev/null +++ b/usr.sbin/bhyve/vga.c @@ -0,0 +1,1331 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> + +#include <assert.h> +#include <pthread.h> +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <machine/vmm.h> + +#include "bhyvegc.h" +#include "console.h" +#include "inout.h" +#include "mem.h" +#include "vga.h" + +#define KB (1024UL) +#define MB (1024 * 1024UL) + +struct vga_softc { + struct mem_range mr; + + struct bhyvegc *gc; + int gc_width; + int gc_height; + struct bhyvegc_image *gc_image; + + uint8_t *vga_ram; + + /* + * General registers + */ + uint8_t vga_misc; + uint8_t vga_sts1; + + /* + * Sequencer + */ + struct { + int seq_index; + uint8_t seq_reset; + uint8_t seq_clock_mode; + int seq_cm_dots; + uint8_t seq_map_mask; + uint8_t seq_cmap_sel; + int seq_cmap_pri_off; + int seq_cmap_sec_off; + uint8_t seq_mm; + } vga_seq; + + /* + * CRT Controller + */ + struct { + int crtc_index; + uint8_t crtc_mode_ctrl; + uint8_t crtc_horiz_total; + uint8_t crtc_horiz_disp_end; + uint8_t crtc_start_horiz_blank; + uint8_t crtc_end_horiz_blank; + uint8_t crtc_start_horiz_retrace; + uint8_t crtc_end_horiz_retrace; + uint8_t crtc_vert_total; + uint8_t crtc_overflow; + uint8_t crtc_present_row_scan; + uint8_t crtc_max_scan_line; + uint8_t crtc_cursor_start; + uint8_t crtc_cursor_on; + uint8_t crtc_cursor_end; + uint8_t crtc_start_addr_high; + uint8_t crtc_start_addr_low; + uint16_t crtc_start_addr; + uint8_t crtc_cursor_loc_low; + uint8_t crtc_cursor_loc_high; + uint16_t crtc_cursor_loc; + uint8_t crtc_vert_retrace_start; + uint8_t crtc_vert_retrace_end; + uint8_t crtc_vert_disp_end; + uint8_t crtc_offset; + uint8_t crtc_underline_loc; + uint8_t crtc_start_vert_blank; + uint8_t crtc_end_vert_blank; + uint8_t crtc_line_compare; + } vga_crtc; + + /* + * Graphics Controller + */ + struct { + int gc_index; + uint8_t gc_set_reset; + uint8_t gc_enb_set_reset; + uint8_t gc_color_compare; + uint8_t gc_rotate; + uint8_t gc_op; + uint8_t gc_read_map_sel; + uint8_t gc_mode; + bool gc_mode_c4; /* chain 4 */ + bool gc_mode_oe; /* odd/even */ + uint8_t gc_mode_rm; /* read mode */ + uint8_t gc_mode_wm; /* write mode */ + uint8_t gc_misc; + uint8_t gc_misc_gm; /* graphics mode */ + uint8_t gc_misc_mm; /* memory map */ + uint8_t gc_color_dont_care; + uint8_t gc_bit_mask; + uint8_t gc_latch0; + uint8_t gc_latch1; + uint8_t gc_latch2; + uint8_t gc_latch3; + } vga_gc; + + /* + * Attribute Controller + */ + struct { + int atc_flipflop; + int atc_index; + uint8_t atc_palette[16]; + uint8_t atc_mode; + uint8_t atc_overscan_color; + uint8_t atc_color_plane_enb; + uint8_t atc_horiz_pixel_panning; + uint8_t atc_color_select; + uint8_t atc_color_select_45; + uint8_t atc_color_select_67; + } vga_atc; + + /* + * DAC + */ + struct { + uint8_t dac_state; + int dac_rd_index; + int dac_rd_subindex; + int dac_wr_index; + int dac_wr_subindex; + uint8_t dac_palette[3 * 256]; + uint32_t dac_palette_rgb[256]; + } vga_dac; +}; + +static bool +vga_in_reset(struct vga_softc *sc) +{ + return (((sc->vga_seq.seq_clock_mode & SEQ_CM_SO) != 0) || + ((sc->vga_seq.seq_reset & SEQ_RESET_ASYNC) == 0) || + ((sc->vga_seq.seq_reset & SEQ_RESET_SYNC) == 0) || + ((sc->vga_crtc.crtc_mode_ctrl & CRTC_MC_TE) == 0)); +} + +static void +vga_check_size(struct bhyvegc *gc, struct vga_softc *sc) +{ + int old_width, old_height; + + if (vga_in_reset(sc)) + return; + + //old_width = sc->gc_width; + //old_height = sc->gc_height; + old_width = sc->gc_image->width; + old_height = sc->gc_image->height; + + /* + * Horizontal Display End: For text modes this is the number + * of characters. For graphics modes this is the number of + * pixels per scanlines divided by the number of pixels per + * character clock. + */ + sc->gc_width = (sc->vga_crtc.crtc_horiz_disp_end + 1) * + sc->vga_seq.seq_cm_dots; + + sc->gc_height = (sc->vga_crtc.crtc_vert_disp_end | + (((sc->vga_crtc.crtc_overflow & CRTC_OF_VDE8) >> CRTC_OF_VDE8_SHIFT) << 8) | + (((sc->vga_crtc.crtc_overflow & CRTC_OF_VDE9) >> CRTC_OF_VDE9_SHIFT) << 9)) + 1; + + if (old_width != sc->gc_width || old_height != sc->gc_height) + bhyvegc_resize(gc, sc->gc_width, sc->gc_height); +} + +static uint32_t +vga_get_pixel(struct vga_softc *sc, int x, int y) +{ + int offset; + int bit; + uint8_t data; + uint8_t idx; + + offset = (y * sc->gc_width / 8) + (x / 8); + bit = 7 - (x % 8); + + data = (((sc->vga_ram[offset + 0 * 64*KB] >> bit) & 0x1) << 0) | + (((sc->vga_ram[offset + 1 * 64*KB] >> bit) & 0x1) << 1) | + (((sc->vga_ram[offset + 2 * 64*KB] >> bit) & 0x1) << 2) | + (((sc->vga_ram[offset + 3 * 64*KB] >> bit) & 0x1) << 3); + + data &= sc->vga_atc.atc_color_plane_enb; + + if (sc->vga_atc.atc_mode & ATC_MC_IPS) { + idx = sc->vga_atc.atc_palette[data] & 0x0f; + idx |= sc->vga_atc.atc_color_select_45; + } else { + idx = sc->vga_atc.atc_palette[data]; + } + idx |= sc->vga_atc.atc_color_select_67; + + return (sc->vga_dac.dac_palette_rgb[idx]); +} + +static void +vga_render_graphics(struct vga_softc *sc) +{ + int x, y; + + for (y = 0; y < sc->gc_height; y++) { + for (x = 0; x < sc->gc_width; x++) { + int offset; + + offset = y * sc->gc_width + x; + sc->gc_image->data[offset] = vga_get_pixel(sc, x, y); + } + } +} + +static uint32_t +vga_get_text_pixel(struct vga_softc *sc, int x, int y) +{ + int dots, offset, bit, font_offset; + uint8_t ch, attr, font; + uint8_t idx; + + dots = sc->vga_seq.seq_cm_dots; + + offset = 2 * sc->vga_crtc.crtc_start_addr; + offset += (y / 16 * sc->gc_width / dots) * 2 + (x / dots) * 2; + + bit = 7 - (x % dots > 7 ? 7 : x % dots); + + ch = sc->vga_ram[offset + 0 * 64*KB]; + attr = sc->vga_ram[offset + 1 * 64*KB]; + + if (sc->vga_crtc.crtc_cursor_on && + (offset == (sc->vga_crtc.crtc_cursor_loc * 2)) && + ((y % 16) >= (sc->vga_crtc.crtc_cursor_start & CRTC_CS_CS)) && + ((y % 16) <= (sc->vga_crtc.crtc_cursor_end & CRTC_CE_CE))) { + idx = sc->vga_atc.atc_palette[attr & 0xf]; + return (sc->vga_dac.dac_palette_rgb[idx]); + } + + if ((sc->vga_seq.seq_mm & SEQ_MM_EM) && + sc->vga_seq.seq_cmap_pri_off != sc->vga_seq.seq_cmap_sec_off) { + if (attr & 0x8) + font_offset = sc->vga_seq.seq_cmap_pri_off + + (ch << 5) + y % 16; + else + font_offset = sc->vga_seq.seq_cmap_sec_off + + (ch << 5) + y % 16; + attr &= ~0x8; + } else { + font_offset = (ch << 5) + y % 16; + } + + font = sc->vga_ram[font_offset + 2 * 64*KB]; + + if (font & (1 << bit)) + idx = sc->vga_atc.atc_palette[attr & 0xf]; + else + idx = sc->vga_atc.atc_palette[attr >> 4]; + + return (sc->vga_dac.dac_palette_rgb[idx]); +} + +static void +vga_render_text(struct vga_softc *sc) +{ + int x, y; + + for (y = 0; y < sc->gc_height; y++) { + for (x = 0; x < sc->gc_width; x++) { + int offset; + + offset = y * sc->gc_width + x; + sc->gc_image->data[offset] = vga_get_text_pixel(sc, x, y); + } + } +} + +void +vga_render(struct bhyvegc *gc, void *arg) +{ + struct vga_softc *sc = arg; + + vga_check_size(gc, sc); + + if (vga_in_reset(sc)) { + memset(sc->gc_image->data, 0, + sc->gc_image->width * sc->gc_image->height * + sizeof (uint32_t)); + return; + } + + if (sc->vga_gc.gc_misc_gm && (sc->vga_atc.atc_mode & ATC_MC_GA)) + vga_render_graphics(sc); + else + vga_render_text(sc); +} + +static uint64_t +vga_mem_rd_handler(struct vmctx *ctx, uint64_t addr, void *arg1) +{ + struct vga_softc *sc = arg1; + uint8_t map_sel; + int offset; + + offset = addr; + switch (sc->vga_gc.gc_misc_mm) { + case 0x0: + /* + * extended mode: base 0xa0000 size 128k + */ + offset -=0xa0000; + offset &= (128 * KB - 1); + break; + case 0x1: + /* + * EGA/VGA mode: base 0xa0000 size 64k + */ + offset -=0xa0000; + offset &= (64 * KB - 1); + break; + case 0x2: + /* + * monochrome text mode: base 0xb0000 size 32kb + */ + assert(0); + case 0x3: + /* + * color text mode and CGA: base 0xb8000 size 32kb + */ + offset -=0xb8000; + offset &= (32 * KB - 1); + break; + } + + /* Fill latches. */ + sc->vga_gc.gc_latch0 = sc->vga_ram[offset + 0*64*KB]; + sc->vga_gc.gc_latch1 = sc->vga_ram[offset + 1*64*KB]; + sc->vga_gc.gc_latch2 = sc->vga_ram[offset + 2*64*KB]; + sc->vga_gc.gc_latch3 = sc->vga_ram[offset + 3*64*KB]; + + if (sc->vga_gc.gc_mode_rm) { + /* read mode 1 */ + assert(0); + } + + map_sel = sc->vga_gc.gc_read_map_sel; + if (sc->vga_gc.gc_mode_oe) { + map_sel |= (offset & 1); + offset &= ~1; + } + + /* read mode 0: return the byte from the selected plane. */ + offset += map_sel * 64*KB; + + return (sc->vga_ram[offset]); +} + +static void +vga_mem_wr_handler(struct vmctx *ctx, uint64_t addr, uint8_t val, void *arg1) +{ + struct vga_softc *sc = arg1; + uint8_t c0, c1, c2, c3; + uint8_t m0, m1, m2, m3; + uint8_t set_reset; + uint8_t enb_set_reset; + uint8_t mask; + int offset; + + offset = addr; + switch (sc->vga_gc.gc_misc_mm) { + case 0x0: + /* + * extended mode: base 0xa0000 size 128kb + */ + offset -=0xa0000; + offset &= (128 * KB - 1); + break; + case 0x1: + /* + * EGA/VGA mode: base 0xa0000 size 64kb + */ + offset -=0xa0000; + offset &= (64 * KB - 1); + break; + case 0x2: + /* + * monochrome text mode: base 0xb0000 size 32kb + */ + assert(0); + case 0x3: + /* + * color text mode and CGA: base 0xb8000 size 32kb + */ + offset -=0xb8000; + offset &= (32 * KB - 1); + break; + } + + set_reset = sc->vga_gc.gc_set_reset; + enb_set_reset = sc->vga_gc.gc_enb_set_reset; + + c0 = sc->vga_gc.gc_latch0; + c1 = sc->vga_gc.gc_latch1; + c2 = sc->vga_gc.gc_latch2; + c3 = sc->vga_gc.gc_latch3; + + switch (sc->vga_gc.gc_mode_wm) { + case 0: + /* write mode 0 */ + mask = sc->vga_gc.gc_bit_mask; + + val = (val >> sc->vga_gc.gc_rotate) | + (val << (8 - sc->vga_gc.gc_rotate)); + + switch (sc->vga_gc.gc_op) { + case 0x00: /* replace */ + m0 = (set_reset & 1) ? mask : 0x00; + m1 = (set_reset & 2) ? mask : 0x00; + m2 = (set_reset & 4) ? mask : 0x00; + m3 = (set_reset & 8) ? mask : 0x00; + + c0 = (enb_set_reset & 1) ? (c0 & ~mask) : (val & mask); + c1 = (enb_set_reset & 2) ? (c1 & ~mask) : (val & mask); + c2 = (enb_set_reset & 4) ? (c2 & ~mask) : (val & mask); + c3 = (enb_set_reset & 8) ? (c3 & ~mask) : (val & mask); + + c0 |= m0; + c1 |= m1; + c2 |= m2; + c3 |= m3; + break; + case 0x08: /* AND */ + m0 = set_reset & 1 ? 0xff : ~mask; + m1 = set_reset & 2 ? 0xff : ~mask; + m2 = set_reset & 4 ? 0xff : ~mask; + m3 = set_reset & 8 ? 0xff : ~mask; + + c0 = enb_set_reset & 1 ? c0 & m0 : val & m0; + c1 = enb_set_reset & 2 ? c1 & m1 : val & m1; + c2 = enb_set_reset & 4 ? c2 & m2 : val & m2; + c3 = enb_set_reset & 8 ? c3 & m3 : val & m3; + break; + case 0x10: /* OR */ + m0 = set_reset & 1 ? mask : 0x00; + m1 = set_reset & 2 ? mask : 0x00; + m2 = set_reset & 4 ? mask : 0x00; + m3 = set_reset & 8 ? mask : 0x00; + + c0 = enb_set_reset & 1 ? c0 | m0 : val | m0; + c1 = enb_set_reset & 2 ? c1 | m1 : val | m1; + c2 = enb_set_reset & 4 ? c2 | m2 : val | m2; + c3 = enb_set_reset & 8 ? c3 | m3 : val | m3; + break; + case 0x18: /* XOR */ + m0 = set_reset & 1 ? mask : 0x00; + m1 = set_reset & 2 ? mask : 0x00; + m2 = set_reset & 4 ? mask : 0x00; + m3 = set_reset & 8 ? mask : 0x00; + + c0 = enb_set_reset & 1 ? c0 ^ m0 : val ^ m0; + c1 = enb_set_reset & 2 ? c1 ^ m1 : val ^ m1; + c2 = enb_set_reset & 4 ? c2 ^ m2 : val ^ m2; + c3 = enb_set_reset & 8 ? c3 ^ m3 : val ^ m3; + break; + } + break; + case 1: + /* write mode 1 */ + break; + case 2: + /* write mode 2 */ + mask = sc->vga_gc.gc_bit_mask; + + switch (sc->vga_gc.gc_op) { + case 0x00: /* replace */ + m0 = (val & 1 ? 0xff : 0x00) & mask; + m1 = (val & 2 ? 0xff : 0x00) & mask; + m2 = (val & 4 ? 0xff : 0x00) & mask; + m3 = (val & 8 ? 0xff : 0x00) & mask; + + c0 &= ~mask; + c1 &= ~mask; + c2 &= ~mask; + c3 &= ~mask; + + c0 |= m0; + c1 |= m1; + c2 |= m2; + c3 |= m3; + break; + case 0x08: /* AND */ + m0 = (val & 1 ? 0xff : 0x00) | ~mask; + m1 = (val & 2 ? 0xff : 0x00) | ~mask; + m2 = (val & 4 ? 0xff : 0x00) | ~mask; + m3 = (val & 8 ? 0xff : 0x00) | ~mask; + + c0 &= m0; + c1 &= m1; + c2 &= m2; + c3 &= m3; + break; + case 0x10: /* OR */ + m0 = (val & 1 ? 0xff : 0x00) & mask; + m1 = (val & 2 ? 0xff : 0x00) & mask; + m2 = (val & 4 ? 0xff : 0x00) & mask; + m3 = (val & 8 ? 0xff : 0x00) & mask; + + c0 |= m0; + c1 |= m1; + c2 |= m2; + c3 |= m3; + break; + case 0x18: /* XOR */ + m0 = (val & 1 ? 0xff : 0x00) & mask; + m1 = (val & 2 ? 0xff : 0x00) & mask; + m2 = (val & 4 ? 0xff : 0x00) & mask; + m3 = (val & 8 ? 0xff : 0x00) & mask; + + c0 ^= m0; + c1 ^= m1; + c2 ^= m2; + c3 ^= m3; + break; + } + break; + case 3: + /* write mode 3 */ + mask = sc->vga_gc.gc_bit_mask & val; + + val = (val >> sc->vga_gc.gc_rotate) | + (val << (8 - sc->vga_gc.gc_rotate)); + + switch (sc->vga_gc.gc_op) { + case 0x00: /* replace */ + m0 = (set_reset & 1 ? 0xff : 0x00) & mask; + m1 = (set_reset & 2 ? 0xff : 0x00) & mask; + m2 = (set_reset & 4 ? 0xff : 0x00) & mask; + m3 = (set_reset & 8 ? 0xff : 0x00) & mask; + + c0 &= ~mask; + c1 &= ~mask; + c2 &= ~mask; + c3 &= ~mask; + + c0 |= m0; + c1 |= m1; + c2 |= m2; + c3 |= m3; + break; + case 0x08: /* AND */ + m0 = (set_reset & 1 ? 0xff : 0x00) | ~mask; + m1 = (set_reset & 2 ? 0xff : 0x00) | ~mask; + m2 = (set_reset & 4 ? 0xff : 0x00) | ~mask; + m3 = (set_reset & 8 ? 0xff : 0x00) | ~mask; + + c0 &= m0; + c1 &= m1; + c2 &= m2; + c3 &= m3; + break; + case 0x10: /* OR */ + m0 = (set_reset & 1 ? 0xff : 0x00) & mask; + m1 = (set_reset & 2 ? 0xff : 0x00) & mask; + m2 = (set_reset & 4 ? 0xff : 0x00) & mask; + m3 = (set_reset & 8 ? 0xff : 0x00) & mask; + + c0 |= m0; + c1 |= m1; + c2 |= m2; + c3 |= m3; + break; + case 0x18: /* XOR */ + m0 = (set_reset & 1 ? 0xff : 0x00) & mask; + m1 = (set_reset & 2 ? 0xff : 0x00) & mask; + m2 = (set_reset & 4 ? 0xff : 0x00) & mask; + m3 = (set_reset & 8 ? 0xff : 0x00) & mask; + + c0 ^= m0; + c1 ^= m1; + c2 ^= m2; + c3 ^= m3; + break; + } + break; + } + + if (sc->vga_gc.gc_mode_oe) { + if (offset & 1) { + offset &= ~1; + if (sc->vga_seq.seq_map_mask & 2) + sc->vga_ram[offset + 1*64*KB] = c1; + if (sc->vga_seq.seq_map_mask & 8) + sc->vga_ram[offset + 3*64*KB] = c3; + } else { + if (sc->vga_seq.seq_map_mask & 1) + sc->vga_ram[offset + 0*64*KB] = c0; + if (sc->vga_seq.seq_map_mask & 4) + sc->vga_ram[offset + 2*64*KB] = c2; + } + } else { + if (sc->vga_seq.seq_map_mask & 1) + sc->vga_ram[offset + 0*64*KB] = c0; + if (sc->vga_seq.seq_map_mask & 2) + sc->vga_ram[offset + 1*64*KB] = c1; + if (sc->vga_seq.seq_map_mask & 4) + sc->vga_ram[offset + 2*64*KB] = c2; + if (sc->vga_seq.seq_map_mask & 8) + sc->vga_ram[offset + 3*64*KB] = c3; + } +} + +static int +vga_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, + int size, uint64_t *val, void *arg1, long arg2) +{ + if (dir == MEM_F_WRITE) { + switch (size) { + case 1: + vga_mem_wr_handler(ctx, addr, *val, arg1); + break; + case 2: + vga_mem_wr_handler(ctx, addr, *val, arg1); + vga_mem_wr_handler(ctx, addr + 1, *val >> 8, arg1); + break; + case 4: + vga_mem_wr_handler(ctx, addr, *val, arg1); + vga_mem_wr_handler(ctx, addr + 1, *val >> 8, arg1); + vga_mem_wr_handler(ctx, addr + 2, *val >> 16, arg1); + vga_mem_wr_handler(ctx, addr + 3, *val >> 24, arg1); + break; + case 8: + vga_mem_wr_handler(ctx, addr, *val, arg1); + vga_mem_wr_handler(ctx, addr + 1, *val >> 8, arg1); + vga_mem_wr_handler(ctx, addr + 2, *val >> 16, arg1); + vga_mem_wr_handler(ctx, addr + 3, *val >> 24, arg1); + vga_mem_wr_handler(ctx, addr + 4, *val >> 32, arg1); + vga_mem_wr_handler(ctx, addr + 5, *val >> 40, arg1); + vga_mem_wr_handler(ctx, addr + 6, *val >> 48, arg1); + vga_mem_wr_handler(ctx, addr + 7, *val >> 56, arg1); + break; + } + } else { + switch (size) { + case 1: + *val = vga_mem_rd_handler(ctx, addr, arg1); + break; + case 2: + *val = vga_mem_rd_handler(ctx, addr, arg1); + *val |= vga_mem_rd_handler(ctx, addr + 1, arg1) << 8; + break; + case 4: + *val = vga_mem_rd_handler(ctx, addr, arg1); + *val |= vga_mem_rd_handler(ctx, addr + 1, arg1) << 8; + *val |= vga_mem_rd_handler(ctx, addr + 2, arg1) << 16; + *val |= vga_mem_rd_handler(ctx, addr + 3, arg1) << 24; + break; + case 8: + *val = vga_mem_rd_handler(ctx, addr, arg1); + *val |= vga_mem_rd_handler(ctx, addr + 1, arg1) << 8; + *val |= vga_mem_rd_handler(ctx, addr + 2, arg1) << 16; + *val |= vga_mem_rd_handler(ctx, addr + 3, arg1) << 24; + *val |= vga_mem_rd_handler(ctx, addr + 4, arg1) << 32; + *val |= vga_mem_rd_handler(ctx, addr + 5, arg1) << 40; + *val |= vga_mem_rd_handler(ctx, addr + 6, arg1) << 48; + *val |= vga_mem_rd_handler(ctx, addr + 7, arg1) << 56; + break; + } + } + + return (0); +} + +static int +vga_port_in_handler(struct vmctx *ctx, int in, int port, int bytes, + uint8_t *val, void *arg) +{ + struct vga_softc *sc = arg; + + switch (port) { + case CRTC_IDX_MONO_PORT: + case CRTC_IDX_COLOR_PORT: + *val = sc->vga_crtc.crtc_index; + break; + case CRTC_DATA_MONO_PORT: + case CRTC_DATA_COLOR_PORT: + switch (sc->vga_crtc.crtc_index) { + case CRTC_HORIZ_TOTAL: + *val = sc->vga_crtc.crtc_horiz_total; + break; + case CRTC_HORIZ_DISP_END: + *val = sc->vga_crtc.crtc_horiz_disp_end; + break; + case CRTC_START_HORIZ_BLANK: + *val = sc->vga_crtc.crtc_start_horiz_blank; + break; + case CRTC_END_HORIZ_BLANK: + *val = sc->vga_crtc.crtc_end_horiz_blank; + break; + case CRTC_START_HORIZ_RETRACE: + *val = sc->vga_crtc.crtc_start_horiz_retrace; + break; + case CRTC_END_HORIZ_RETRACE: + *val = sc->vga_crtc.crtc_end_horiz_retrace; + break; + case CRTC_VERT_TOTAL: + *val = sc->vga_crtc.crtc_vert_total; + break; + case CRTC_OVERFLOW: + *val = sc->vga_crtc.crtc_overflow; + break; + case CRTC_PRESET_ROW_SCAN: + *val = sc->vga_crtc.crtc_present_row_scan; + break; + case CRTC_MAX_SCAN_LINE: + *val = sc->vga_crtc.crtc_max_scan_line; + break; + case CRTC_CURSOR_START: + *val = sc->vga_crtc.crtc_cursor_start; + break; + case CRTC_CURSOR_END: + *val = sc->vga_crtc.crtc_cursor_end; + break; + case CRTC_START_ADDR_HIGH: + *val = sc->vga_crtc.crtc_start_addr_high; + break; + case CRTC_START_ADDR_LOW: + *val = sc->vga_crtc.crtc_start_addr_low; + break; + case CRTC_CURSOR_LOC_HIGH: + *val = sc->vga_crtc.crtc_cursor_loc_high; + break; + case CRTC_CURSOR_LOC_LOW: + *val = sc->vga_crtc.crtc_cursor_loc_low; + break; + case CRTC_VERT_RETRACE_START: + *val = sc->vga_crtc.crtc_vert_retrace_start; + break; + case CRTC_VERT_RETRACE_END: + *val = sc->vga_crtc.crtc_vert_retrace_end; + break; + case CRTC_VERT_DISP_END: + *val = sc->vga_crtc.crtc_vert_disp_end; + break; + case CRTC_OFFSET: + *val = sc->vga_crtc.crtc_offset; + break; + case CRTC_UNDERLINE_LOC: + *val = sc->vga_crtc.crtc_underline_loc; + break; + case CRTC_START_VERT_BLANK: + *val = sc->vga_crtc.crtc_start_vert_blank; + break; + case CRTC_END_VERT_BLANK: + *val = sc->vga_crtc.crtc_end_vert_blank; + break; + case CRTC_MODE_CONTROL: + *val = sc->vga_crtc.crtc_mode_ctrl; + break; + case CRTC_LINE_COMPARE: + *val = sc->vga_crtc.crtc_line_compare; + break; + default: + //printf("XXX VGA CRTC: inb 0x%04x at index %d\n", port, sc->vga_crtc.crtc_index); + assert(0); + break; + } + break; + case ATC_IDX_PORT: + *val = sc->vga_atc.atc_index; + break; + case ATC_DATA_PORT: + switch (sc->vga_atc.atc_index) { + case ATC_PALETTE0 ... ATC_PALETTE15: + *val = sc->vga_atc.atc_palette[sc->vga_atc.atc_index]; + break; + case ATC_MODE_CONTROL: + *val = sc->vga_atc.atc_mode; + break; + case ATC_OVERSCAN_COLOR: + *val = sc->vga_atc.atc_overscan_color; + break; + case ATC_COLOR_PLANE_ENABLE: + *val = sc->vga_atc.atc_color_plane_enb; + break; + case ATC_HORIZ_PIXEL_PANNING: + *val = sc->vga_atc.atc_horiz_pixel_panning; + break; + case ATC_COLOR_SELECT: + *val = sc->vga_atc.atc_color_select; + break; + default: + //printf("XXX VGA ATC inb 0x%04x at index %d\n", port , sc->vga_atc.atc_index); + assert(0); + break; + } + break; + case SEQ_IDX_PORT: + *val = sc->vga_seq.seq_index; + break; + case SEQ_DATA_PORT: + switch (sc->vga_seq.seq_index) { + case SEQ_RESET: + *val = sc->vga_seq.seq_reset; + break; + case SEQ_CLOCKING_MODE: + *val = sc->vga_seq.seq_clock_mode; + break; + case SEQ_MAP_MASK: + *val = sc->vga_seq.seq_map_mask; + break; + case SEQ_CHAR_MAP_SELECT: + *val = sc->vga_seq.seq_cmap_sel; + break; + case SEQ_MEMORY_MODE: + *val = sc->vga_seq.seq_mm; + break; + default: + //printf("XXX VGA SEQ: inb 0x%04x at index %d\n", port, sc->vga_seq.seq_index); + assert(0); + break; + } + break; + case DAC_DATA_PORT: + *val = sc->vga_dac.dac_palette[3 * sc->vga_dac.dac_rd_index + + sc->vga_dac.dac_rd_subindex]; + sc->vga_dac.dac_rd_subindex++; + if (sc->vga_dac.dac_rd_subindex == 3) { + sc->vga_dac.dac_rd_index++; + sc->vga_dac.dac_rd_subindex = 0; + } + break; + case GC_IDX_PORT: + *val = sc->vga_gc.gc_index; + break; + case GC_DATA_PORT: + switch (sc->vga_gc.gc_index) { + case GC_SET_RESET: + *val = sc->vga_gc.gc_set_reset; + break; + case GC_ENABLE_SET_RESET: + *val = sc->vga_gc.gc_enb_set_reset; + break; + case GC_COLOR_COMPARE: + *val = sc->vga_gc.gc_color_compare; + break; + case GC_DATA_ROTATE: + *val = sc->vga_gc.gc_rotate; + break; + case GC_READ_MAP_SELECT: + *val = sc->vga_gc.gc_read_map_sel; + break; + case GC_MODE: + *val = sc->vga_gc.gc_mode; + break; + case GC_MISCELLANEOUS: + *val = sc->vga_gc.gc_misc; + break; + case GC_COLOR_DONT_CARE: + *val = sc->vga_gc.gc_color_dont_care; + break; + case GC_BIT_MASK: + *val = sc->vga_gc.gc_bit_mask; + break; + default: + //printf("XXX VGA GC: inb 0x%04x at index %d\n", port, sc->vga_crtc.crtc_index); + assert(0); + break; + } + break; + case GEN_MISC_OUTPUT_PORT: + *val = sc->vga_misc; + break; + case GEN_INPUT_STS0_PORT: + assert(0); + break; + case GEN_INPUT_STS1_MONO_PORT: + case GEN_INPUT_STS1_COLOR_PORT: + sc->vga_atc.atc_flipflop = 0; + sc->vga_sts1 = GEN_IS1_VR | GEN_IS1_DE; + //sc->vga_sts1 ^= (GEN_IS1_VR | GEN_IS1_DE); + *val = sc->vga_sts1; + break; + case GEN_FEATURE_CTRL_PORT: + // OpenBSD calls this with bytes = 1 + //assert(0); + *val = 0; + break; + case 0x3c3: + *val = 0; + break; + default: + printf("XXX vga_port_in_handler() unhandled port 0x%x\n", port); + //assert(0); + return (-1); + } + + return (0); +} + +static int +vga_port_out_handler(struct vmctx *ctx, int in, int port, int bytes, + uint8_t val, void *arg) +{ + struct vga_softc *sc = arg; + + switch (port) { + case CRTC_IDX_MONO_PORT: + case CRTC_IDX_COLOR_PORT: + sc->vga_crtc.crtc_index = val; + break; + case CRTC_DATA_MONO_PORT: + case CRTC_DATA_COLOR_PORT: + switch (sc->vga_crtc.crtc_index) { + case CRTC_HORIZ_TOTAL: + sc->vga_crtc.crtc_horiz_total = val; + break; + case CRTC_HORIZ_DISP_END: + sc->vga_crtc.crtc_horiz_disp_end = val; + break; + case CRTC_START_HORIZ_BLANK: + sc->vga_crtc.crtc_start_horiz_blank = val; + break; + case CRTC_END_HORIZ_BLANK: + sc->vga_crtc.crtc_end_horiz_blank = val; + break; + case CRTC_START_HORIZ_RETRACE: + sc->vga_crtc.crtc_start_horiz_retrace = val; + break; + case CRTC_END_HORIZ_RETRACE: + sc->vga_crtc.crtc_end_horiz_retrace = val; + break; + case CRTC_VERT_TOTAL: + sc->vga_crtc.crtc_vert_total = val; + break; + case CRTC_OVERFLOW: + sc->vga_crtc.crtc_overflow = val; + break; + case CRTC_PRESET_ROW_SCAN: + sc->vga_crtc.crtc_present_row_scan = val; + break; + case CRTC_MAX_SCAN_LINE: + sc->vga_crtc.crtc_max_scan_line = val; + break; + case CRTC_CURSOR_START: + sc->vga_crtc.crtc_cursor_start = val; + sc->vga_crtc.crtc_cursor_on = (val & CRTC_CS_CO) == 0; + break; + case CRTC_CURSOR_END: + sc->vga_crtc.crtc_cursor_end = val; + break; + case CRTC_START_ADDR_HIGH: + sc->vga_crtc.crtc_start_addr_high = val; + sc->vga_crtc.crtc_start_addr &= 0x00ff; + sc->vga_crtc.crtc_start_addr |= (val << 8); + break; + case CRTC_START_ADDR_LOW: + sc->vga_crtc.crtc_start_addr_low = val; + sc->vga_crtc.crtc_start_addr &= 0xff00; + sc->vga_crtc.crtc_start_addr |= (val & 0xff); + break; + case CRTC_CURSOR_LOC_HIGH: + sc->vga_crtc.crtc_cursor_loc_high = val; + sc->vga_crtc.crtc_cursor_loc &= 0x00ff; + sc->vga_crtc.crtc_cursor_loc |= (val << 8); + break; + case CRTC_CURSOR_LOC_LOW: + sc->vga_crtc.crtc_cursor_loc_low = val; + sc->vga_crtc.crtc_cursor_loc &= 0xff00; + sc->vga_crtc.crtc_cursor_loc |= (val & 0xff); + break; + case CRTC_VERT_RETRACE_START: + sc->vga_crtc.crtc_vert_retrace_start = val; + break; + case CRTC_VERT_RETRACE_END: + sc->vga_crtc.crtc_vert_retrace_end = val; + break; + case CRTC_VERT_DISP_END: + sc->vga_crtc.crtc_vert_disp_end = val; + break; + case CRTC_OFFSET: + sc->vga_crtc.crtc_offset = val; + break; + case CRTC_UNDERLINE_LOC: + sc->vga_crtc.crtc_underline_loc = val; + break; + case CRTC_START_VERT_BLANK: + sc->vga_crtc.crtc_start_vert_blank = val; + break; + case CRTC_END_VERT_BLANK: + sc->vga_crtc.crtc_end_vert_blank = val; + break; + case CRTC_MODE_CONTROL: + sc->vga_crtc.crtc_mode_ctrl = val; + break; + case CRTC_LINE_COMPARE: + sc->vga_crtc.crtc_line_compare = val; + break; + default: + //printf("XXX VGA CRTC: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_crtc.crtc_index); + assert(0); + break; + } + break; + case ATC_IDX_PORT: + if (sc->vga_atc.atc_flipflop == 0) { + if (sc->vga_atc.atc_index & 0x20) + assert(0); + sc->vga_atc.atc_index = val & ATC_IDX_MASK; + } else { + switch (sc->vga_atc.atc_index) { + case ATC_PALETTE0 ... ATC_PALETTE15: + sc->vga_atc.atc_palette[sc->vga_atc.atc_index] = val & 0x3f; + break; + case ATC_MODE_CONTROL: + sc->vga_atc.atc_mode = val; + break; + case ATC_OVERSCAN_COLOR: + sc->vga_atc.atc_overscan_color = val; + break; + case ATC_COLOR_PLANE_ENABLE: + sc->vga_atc.atc_color_plane_enb = val; + break; + case ATC_HORIZ_PIXEL_PANNING: + sc->vga_atc.atc_horiz_pixel_panning = val; + break; + case ATC_COLOR_SELECT: + sc->vga_atc.atc_color_select = val; + sc->vga_atc.atc_color_select_45 = + (val & ATC_CS_C45) << 4; + sc->vga_atc.atc_color_select_67 = + (val & ATC_CS_C67) << 6; + break; + default: + //printf("XXX VGA ATC: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_atc.atc_index); + assert(0); + break; + } + } + sc->vga_atc.atc_flipflop ^= 1; + break; + case ATC_DATA_PORT: + break; + case SEQ_IDX_PORT: + sc->vga_seq.seq_index = val & 0x1f; + break; + case SEQ_DATA_PORT: + switch (sc->vga_seq.seq_index) { + case SEQ_RESET: + sc->vga_seq.seq_reset = val; + break; + case SEQ_CLOCKING_MODE: + sc->vga_seq.seq_clock_mode = val; + sc->vga_seq.seq_cm_dots = (val & SEQ_CM_89) ? 8 : 9; + break; + case SEQ_MAP_MASK: + sc->vga_seq.seq_map_mask = val; + break; + case SEQ_CHAR_MAP_SELECT: + sc->vga_seq.seq_cmap_sel = val; + + sc->vga_seq.seq_cmap_pri_off = ((((val & SEQ_CMS_SA) >> SEQ_CMS_SA_SHIFT) * 2) + ((val & SEQ_CMS_SAH) >> SEQ_CMS_SAH_SHIFT)) * 8 * KB; + sc->vga_seq.seq_cmap_sec_off = ((((val & SEQ_CMS_SB) >> SEQ_CMS_SB_SHIFT) * 2) + ((val & SEQ_CMS_SBH) >> SEQ_CMS_SBH_SHIFT)) * 8 * KB; + break; + case SEQ_MEMORY_MODE: + sc->vga_seq.seq_mm = val; + /* Windows queries Chain4 */ + //assert((sc->vga_seq.seq_mm & SEQ_MM_C4) == 0); + break; + default: + //printf("XXX VGA SEQ: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_seq.seq_index); + assert(0); + break; + } + break; + case DAC_MASK: + break; + case DAC_IDX_RD_PORT: + sc->vga_dac.dac_rd_index = val; + sc->vga_dac.dac_rd_subindex = 0; + break; + case DAC_IDX_WR_PORT: + sc->vga_dac.dac_wr_index = val; + sc->vga_dac.dac_wr_subindex = 0; + break; + case DAC_DATA_PORT: + sc->vga_dac.dac_palette[3 * sc->vga_dac.dac_wr_index + + sc->vga_dac.dac_wr_subindex] = val; + sc->vga_dac.dac_wr_subindex++; + if (sc->vga_dac.dac_wr_subindex == 3) { + sc->vga_dac.dac_palette_rgb[sc->vga_dac.dac_wr_index] = + ((((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 0] << 2) | + ((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 0] & 0x1) << 1) | + (sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 0] & 0x1)) << 16) | + (((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 1] << 2) | + ((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 1] & 0x1) << 1) | + (sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 1] & 0x1)) << 8) | + (((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 2] << 2) | + ((sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 2] & 0x1) << 1) | + (sc->vga_dac.dac_palette[3*sc->vga_dac.dac_wr_index + 2] & 0x1)) << 0)); + + sc->vga_dac.dac_wr_index++; + sc->vga_dac.dac_wr_subindex = 0; + } + break; + case GC_IDX_PORT: + sc->vga_gc.gc_index = val; + break; + case GC_DATA_PORT: + switch (sc->vga_gc.gc_index) { + case GC_SET_RESET: + sc->vga_gc.gc_set_reset = val; + break; + case GC_ENABLE_SET_RESET: + sc->vga_gc.gc_enb_set_reset = val; + break; + case GC_COLOR_COMPARE: + sc->vga_gc.gc_color_compare = val; + break; + case GC_DATA_ROTATE: + sc->vga_gc.gc_rotate = val; + sc->vga_gc.gc_op = (val >> 3) & 0x3; + break; + case GC_READ_MAP_SELECT: + sc->vga_gc.gc_read_map_sel = val; + break; + case GC_MODE: + sc->vga_gc.gc_mode = val; + sc->vga_gc.gc_mode_c4 = (val & GC_MODE_C4) != 0; + assert(!sc->vga_gc.gc_mode_c4); + sc->vga_gc.gc_mode_oe = (val & GC_MODE_OE) != 0; + sc->vga_gc.gc_mode_rm = (val >> 3) & 0x1; + sc->vga_gc.gc_mode_wm = val & 0x3; + + if (sc->gc_image) + sc->gc_image->vgamode = 1; + break; + case GC_MISCELLANEOUS: + sc->vga_gc.gc_misc = val; + sc->vga_gc.gc_misc_gm = val & GC_MISC_GM; + sc->vga_gc.gc_misc_mm = (val & GC_MISC_MM) >> + GC_MISC_MM_SHIFT; + break; + case GC_COLOR_DONT_CARE: + sc->vga_gc.gc_color_dont_care = val; + break; + case GC_BIT_MASK: + sc->vga_gc.gc_bit_mask = val; + break; + default: + //printf("XXX VGA GC: outb 0x%04x, 0x%02x at index %d\n", port, val, sc->vga_gc.gc_index); + assert(0); + break; + } + break; + case GEN_INPUT_STS0_PORT: + /* write to Miscellaneous Output Register */ + sc->vga_misc = val; + break; + case GEN_INPUT_STS1_MONO_PORT: + case GEN_INPUT_STS1_COLOR_PORT: + /* write to Feature Control Register */ + break; +// case 0x3c3: +// break; + default: + printf("XXX vga_port_out_handler() unhandled port 0x%x, val 0x%x\n", port, val); + //assert(0); + return (-1); + } + return (0); +} + +static int +vga_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, + uint32_t *eax, void *arg) +{ + uint8_t val; + int error; + + switch (bytes) { + case 1: + if (in) { + *eax &= ~0xff; + error = vga_port_in_handler(ctx, in, port, 1, + &val, arg); + if (!error) { + *eax |= val & 0xff; + } + } else { + val = *eax & 0xff; + error = vga_port_out_handler(ctx, in, port, 1, + val, arg); + } + break; + case 2: + if (in) { + *eax &= ~0xffff; + error = vga_port_in_handler(ctx, in, port, 1, + &val, arg); + if (!error) { + *eax |= val & 0xff; + } + error = vga_port_in_handler(ctx, in, port + 1, 1, + &val, arg); + if (!error) { + *eax |= (val & 0xff) << 8; + } + } else { + val = *eax & 0xff; + error = vga_port_out_handler(ctx, in, port, 1, + val, arg); + val = (*eax >> 8) & 0xff; + error =vga_port_out_handler(ctx, in, port + 1, 1, + val, arg); + } + break; + default: + assert(0); + return (-1); + } + + return (error); +} + +void * +vga_init(int io_only) +{ + struct inout_port iop; + struct vga_softc *sc; + int port, error; + + sc = calloc(1, sizeof(struct vga_softc)); + + bzero(&iop, sizeof(struct inout_port)); + iop.name = "VGA"; + for (port = VGA_IOPORT_START; port <= VGA_IOPORT_END; port++) { + iop.port = port; + iop.size = 1; + iop.flags = IOPORT_F_INOUT; + iop.handler = vga_port_handler; + iop.arg = sc; + + error = register_inout(&iop); + assert(error == 0); + } + + sc->gc_image = console_get_image(); + + /* only handle io ports; vga graphics is disabled */ + if (io_only) + return(sc); + + sc->mr.name = "VGA memory"; + sc->mr.flags = MEM_F_RW; + sc->mr.base = 640 * KB; + sc->mr.size = 128 * KB; + sc->mr.handler = vga_mem_handler; + sc->mr.arg1 = sc; + error = register_mem_fallback(&sc->mr); + assert(error == 0); + + sc->vga_ram = malloc(256 * KB); + memset(sc->vga_ram, 0, 256 * KB); + + { + static uint8_t palette[] = { + 0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a, + 0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x2a,0x00, 0x2a,0x2a,0x2a, + 0x00,0x00,0x15, 0x00,0x00,0x3f, 0x00,0x2a,0x15, 0x00,0x2a,0x3f, + 0x2a,0x00,0x15, 0x2a,0x00,0x3f, 0x2a,0x2a,0x15, 0x2a,0x2a,0x3f, + }; + int i; + + memcpy(sc->vga_dac.dac_palette, palette, 16 * 3 * sizeof (uint8_t)); + for (i = 0; i < 16; i++) { + sc->vga_dac.dac_palette_rgb[i] = + ((((sc->vga_dac.dac_palette[3*i + 0] << 2) | + ((sc->vga_dac.dac_palette[3*i + 0] & 0x1) << 1) | + (sc->vga_dac.dac_palette[3*i + 0] & 0x1)) << 16) | + (((sc->vga_dac.dac_palette[3*i + 1] << 2) | + ((sc->vga_dac.dac_palette[3*i + 1] & 0x1) << 1) | + (sc->vga_dac.dac_palette[3*i + 1] & 0x1)) << 8) | + (((sc->vga_dac.dac_palette[3*i + 2] << 2) | + ((sc->vga_dac.dac_palette[3*i + 2] & 0x1) << 1) | + (sc->vga_dac.dac_palette[3*i + 2] & 0x1)) << 0)); + } + } + + return (sc); +} diff --git a/usr.sbin/bhyve/vga.h b/usr.sbin/bhyve/vga.h new file mode 100644 index 0000000..4364f1b --- /dev/null +++ b/usr.sbin/bhyve/vga.h @@ -0,0 +1,160 @@ +/*- + * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _VGA_H_ +#define _VGA_H_ + +#define VGA_IOPORT_START 0x3c0 +#define VGA_IOPORT_END 0x3df + +/* General registers */ +#define GEN_INPUT_STS0_PORT 0x3c2 +#define GEN_FEATURE_CTRL_PORT 0x3ca +#define GEN_MISC_OUTPUT_PORT 0x3cc +#define GEN_INPUT_STS1_MONO_PORT 0x3ba +#define GEN_INPUT_STS1_COLOR_PORT 0x3da +#define GEN_IS1_VR 0x08 /* Vertical retrace */ +#define GEN_IS1_DE 0x01 /* Display enable not */ + +/* Attribute controller registers. */ +#define ATC_IDX_PORT 0x3c0 +#define ATC_DATA_PORT 0x3c1 + +#define ATC_IDX_MASK 0x1f +#define ATC_PALETTE0 0 +#define ATC_PALETTE15 15 +#define ATC_MODE_CONTROL 16 +#define ATC_MC_IPS 0x80 /* Internal palette size */ +#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */ +#define ATC_OVERSCAN_COLOR 17 +#define ATC_COLOR_PLANE_ENABLE 18 +#define ATC_HORIZ_PIXEL_PANNING 19 +#define ATC_COLOR_SELECT 20 +#define ATC_CS_C67 0x0c /* Color select bits 6+7 */ +#define ATC_CS_C45 0x03 /* Color select bits 4+5 */ + +/* Sequencer registers. */ +#define SEQ_IDX_PORT 0x3c4 +#define SEQ_DATA_PORT 0x3c5 + +#define SEQ_RESET 0 +#define SEQ_RESET_ASYNC 0x1 +#define SEQ_RESET_SYNC 0x2 +#define SEQ_CLOCKING_MODE 1 +#define SEQ_CM_SO 0x20 /* Screen off */ +#define SEQ_CM_89 0x01 /* 8/9 dot clock */ +#define SEQ_MAP_MASK 2 +#define SEQ_CHAR_MAP_SELECT 3 +#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */ +#define SEQ_CMS_SAH_SHIFT 5 +#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */ +#define SEQ_CMS_SA_SHIFT 2 +#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */ +#define SEQ_CMS_SBH_SHIFT 4 +#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */ +#define SEQ_CMS_SB_SHIFT 0 +#define SEQ_MEMORY_MODE 4 +#define SEQ_MM_C4 0x08 /* Chain 4 */ +#define SEQ_MM_OE 0x04 /* Odd/even */ +#define SEQ_MM_EM 0x02 /* Extended memory */ + +/* Graphics controller registers. */ +#define GC_IDX_PORT 0x3ce +#define GC_DATA_PORT 0x3cf + +#define GC_SET_RESET 0 +#define GC_ENABLE_SET_RESET 1 +#define GC_COLOR_COMPARE 2 +#define GC_DATA_ROTATE 3 +#define GC_READ_MAP_SELECT 4 +#define GC_MODE 5 +#define GC_MODE_OE 0x10 /* Odd/even */ +#define GC_MODE_C4 0x04 /* Chain 4 */ + +#define GC_MISCELLANEOUS 6 +#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */ +#define GC_MISC_MM 0x0c /* memory map */ +#define GC_MISC_MM_SHIFT 2 +#define GC_COLOR_DONT_CARE 7 +#define GC_BIT_MASK 8 + +/* CRT controller registers. */ +#define CRTC_IDX_MONO_PORT 0x3b4 +#define CRTC_DATA_MONO_PORT 0x3b5 +#define CRTC_IDX_COLOR_PORT 0x3d4 +#define CRTC_DATA_COLOR_PORT 0x3d5 + +#define CRTC_HORIZ_TOTAL 0 +#define CRTC_HORIZ_DISP_END 1 +#define CRTC_START_HORIZ_BLANK 2 +#define CRTC_END_HORIZ_BLANK 3 +#define CRTC_START_HORIZ_RETRACE 4 +#define CRTC_END_HORIZ_RETRACE 5 +#define CRTC_VERT_TOTAL 6 +#define CRTC_OVERFLOW 7 +#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */ +#define CRTC_OF_VRS9_SHIFT 7 +#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */ +#define CRTC_OF_VDE9_SHIFT 6 +#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */ +#define CRTC_OF_VRS8_SHIFT 2 +#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */ +#define CRTC_OF_VDE8_SHIFT 1 +#define CRTC_PRESET_ROW_SCAN 8 +#define CRTC_MAX_SCAN_LINE 9 +#define CRTC_MSL_MSL 0x1f +#define CRTC_CURSOR_START 10 +#define CRTC_CS_CO 0x20 /* Cursor off */ +#define CRTC_CS_CS 0x1f /* Cursor start */ +#define CRTC_CURSOR_END 11 +#define CRTC_CE_CE 0x1f /* Cursor end */ +#define CRTC_START_ADDR_HIGH 12 +#define CRTC_START_ADDR_LOW 13 +#define CRTC_CURSOR_LOC_HIGH 14 +#define CRTC_CURSOR_LOC_LOW 15 +#define CRTC_VERT_RETRACE_START 16 +#define CRTC_VERT_RETRACE_END 17 +#define CRTC_VRE_MASK 0xf +#define CRTC_VERT_DISP_END 18 +#define CRTC_OFFSET 19 +#define CRTC_UNDERLINE_LOC 20 +#define CRTC_START_VERT_BLANK 21 +#define CRTC_END_VERT_BLANK 22 +#define CRTC_MODE_CONTROL 23 +#define CRTC_MC_TE 0x80 /* Timing enable */ +#define CRTC_LINE_COMPARE 24 + +/* DAC registers */ +#define DAC_MASK 0x3c6 +#define DAC_IDX_RD_PORT 0x3c7 +#define DAC_IDX_WR_PORT 0x3c8 +#define DAC_DATA_PORT 0x3c9 + +void *vga_init(int io_only); + +#endif /* _VGA_H_ */ diff --git a/usr.sbin/bsdinstall/scripts/auto b/usr.sbin/bsdinstall/scripts/auto index 5e3f5b1..d8ecd62 100755 --- a/usr.sbin/bsdinstall/scripts/auto +++ b/usr.sbin/bsdinstall/scripts/auto @@ -184,7 +184,7 @@ if f_interactive; then case "$sys_maker" in "LENOVO") case "$sys_version" in - "ThinkPad X220"|"ThinkPad T420"|"ThinkPad T520") + "ThinkPad X220"|"ThinkPad T420"|"ThinkPad T520"|"ThinkPad W520") dialog_workaround "$msg_lenovo_fix" retval=$? f_dprintf "lenovofix_prompt=[%s]" "$retval" @@ -197,7 +197,7 @@ if f_interactive; then ;; "Dell Inc.") case "$sys_model" in - "Latitude E7440"|"Latitude E7240"|"Precision Tower 5810") + "Latitude E6330"|"Latitude E7440"|"Latitude E7240"|"Precision Tower 5810") dialog_workaround "$msg_gpt_active_fix" retval=$? f_dprintf "gpt_active_fix_prompt=[%s]" "$retval" diff --git a/usr.sbin/bsdinstall/scripts/zfsboot b/usr.sbin/bsdinstall/scripts/zfsboot index db28284..d2de12b 100755 --- a/usr.sbin/bsdinstall/scripts/zfsboot +++ b/usr.sbin/bsdinstall/scripts/zfsboot @@ -218,6 +218,7 @@ SWAP_GMIRROR_LABEL='gmirror label swap %s' SYSCTL_ZFS_MIN_ASHIFT_12='sysctl vfs.zfs.min_auto_ashift=12' UMOUNT='umount "%s"' ZFS_CREATE_WITH_OPTIONS='zfs create %s "%s"' +ZFS_MOUNT='zfs mount "%s"' ZFS_SET='zfs set "%s" "%s"' ZFS_UNMOUNT='zfs unmount "%s"' ZPOOL_CREATE_WITH_OPTIONS='zpool create %s "%s" %s %s' @@ -1350,13 +1351,6 @@ zfs_create_boot() $BSDINSTALL_CHROOT$dir || return $FAILURE done - # Create symlink(s) - if [ "$ZFSBOOT_BOOT_POOL" ]; then - f_dprintf "$funcname: Creating /boot symlink for boot pool..." - f_eval_catch $funcname ln "$LN_SF" "$bootpool_name/boot" \ - $BSDINSTALL_CHROOT/boot || return $FAILURE - fi - # Set bootfs property local zroot_bootfs="$ZFSBOOT_BEROOT_NAME/$ZFSBOOT_BOOTFS_NAME" f_dprintf "$funcname: Setting bootfs property..." @@ -1396,7 +1390,16 @@ zfs_create_boot() fi fi - # While this is apparently not needed, it seems to help MBR + # Remount bootpool and create symlink(s) + if [ "$ZFSBOOT_BOOT_POOL" ]; then + f_eval_catch $funcname zfs "$ZFS_MOUNT" "$bootpool_name" || + return $FAILURE + f_dprintf "$funcname: Creating /boot symlink for boot pool..." + f_eval_catch $funcname ln "$LN_SF" "$bootpool_name/boot" \ + $BSDINSTALL_CHROOT/boot || return $FAILURE + fi + + # zpool.cache is required to mount more than one pool at boot time f_dprintf "$funcname: Configuring zpool.cache for zroot..." f_eval_catch $funcname mkdir "$MKDIR_P" $BSDINSTALL_CHROOT/boot/zfs || return $FAILURE diff --git a/usr.sbin/ppp/Makefile b/usr.sbin/ppp/Makefile index 1dcd3b5..540eb45 100644 --- a/usr.sbin/ppp/Makefile +++ b/usr.sbin/ppp/Makefile @@ -107,6 +107,7 @@ SRCS+= netgraph.c .if defined(PPP_NO_PAM) CFLAGS+=-DNOPAM +LIBADD+= crypt .else LIBADD+= pam .endif |
