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| author | dim <dim@FreeBSD.org> | 2011-10-20 21:10:27 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2011-10-20 21:10:27 +0000 |
| commit | 7b3392326c40c3c20697816acae597ba7b3144eb (patch) | |
| tree | 2cbcf22585e99f8a87d12d5ff94f392c0d266819 /test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll | |
| parent | 1176aa52646fe641a4243a246aa7f960c708a274 (diff) | |
| download | FreeBSD-src-7b3392326c40c3c20697816acae597ba7b3144eb.zip FreeBSD-src-7b3392326c40c3c20697816acae597ba7b3144eb.tar.gz | |
Vendor import of llvm release_30 branch r142614:
http://llvm.org/svn/llvm-project/llvm/branches/release_30@142614
Diffstat (limited to 'test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll')
| -rw-r--r-- | test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll b/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll new file mode 100644 index 0000000..c3fbdf5 --- /dev/null +++ b/test/Transforms/ScalarRepl/vectors-with-mismatched-elements.ll @@ -0,0 +1,27 @@ +; RUN: opt -scalarrepl -S < %s | FileCheck %s +; rdar://9786827 + +; SROA should be able to handle the mixed types and eliminate the allocas here. + +; TODO: Currently it does this by falling back to integer "bags of bits". +; With enough cleverness, it should be possible to convert between <3 x i32> +; and <2 x i64> by using a combination of a bitcast and a shuffle. + +; CHECK: { +; CHECK-NOT: alloca +; CHECK: } + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin11.0.0" + +define <2 x i64> @foo() nounwind { +entry: + %retval = alloca <3 x i32>, align 16 + %z = alloca <4 x i32>, align 16 + %tmp = load <4 x i32>* %z + %tmp1 = shufflevector <4 x i32> %tmp, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> + store <3 x i32> %tmp1, <3 x i32>* %retval + %0 = bitcast <3 x i32>* %retval to <2 x i64>* + %1 = load <2 x i64>* %0, align 1 + ret <2 x i64> %1 +} |
