+; BASIC-NEXT: 0x00000022

+; BASIC-NEXT: '41210000 00616561 62690001 17000000 060a0741 08010902 14011501 17031801 1901'

+; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s

+

+; tail call inside a function where byval argument is splitted between

+; registers and stack is currently unsupported.

+; XFAIL: *

+

+; CHECK: vst1.64

+; CHECK-NEXT: vst1.64

+; CHECK: vld1.64 {{.*}}, [r1, :128]

+; CHECK: vst1.64 {{.*}}

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+; CHECK: vld1.64 {{.*}}, :128

+; CHECK: vst1.64

+; CHECK: vld1.64

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: vst1.64

+define void @test_floor(<4 x float>* %X) nounwind {

+

+; CHECK: test_floor:

+

+; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}

+; CHECK: movt [[reg0]], :upper16:{{.*}}

+; CHECK: vld1.64

+

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: bl {{.*}}floorf

+

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: bl {{.*}}floorf

+

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: bl {{.*}}floorf

+

+; CHECK: {{v?mov(.32)?}} r0,

+; CHECK: bl {{.*}}floorf

+

+; CHECK: vst1.64

+

+L.entry:

+ %0 = load <4 x float>* @A, align 16

+ %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)

+ store <4 x float> %1, <4 x float>* %X, align 16

+ ret void

+}

+

+declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readonly

+

+; RUN: llc -O1 -march=arm -mcpu=cortex-a9 < %s | FileCheck -check-prefix=A9-CHECK %s

+; RUN: llc -O1 -march=arm -mcpu=swift < %s | FileCheck -check-prefix=SWIFT-CHECK %s

+; Check that swift doesn't use vmov.32. <rdar://problem/10453003>.

+

+define <2 x i32> @testuvec(<2 x i32> %A, <2 x i32> %B) nounwind {

+entry:

+ %div = udiv <2 x i32> %A, %B

+ ret <2 x i32> %div

+; A9-CHECK: vmov.32

+; SWIFT-CHECK-NOT: vmov.32

+}

+; RUN: llc -march=arm -mcpu=swift < %s | FileCheck %s

+; <rdar://problem/10451892>

+

+define void @f(i32 %x, i32* %p) nounwind ssp {

+entry:

+; CHECK-NOT: vdup.32

+ %vecinit.i = insertelement <2 x i32> undef, i32 %x, i32 0

+ %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %x, i32 1

+ %0 = bitcast i32* %p to i8*

+ tail call void @llvm.arm.neon.vst1.v2i32(i8* %0, <2 x i32> %vecinit1.i, i32 4)

+ ret void

+}

+

+declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind

+; RUN: llc < %s -mcpu=cortex-a8 -march=thumb

+; Test that this doesn't crash.

+; <rdar://problem/12183003>

+

+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"

+target triple = "thumbv7-apple-ios5.1.0"

+

+declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly

+

+declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind

+

+define void @findEdges(i8*) nounwind ssp {

+ %2 = icmp sgt i32 undef, 0

+ br i1 %2, label %5, label %3

+

+; <label>:3 ; preds = %5, %1

+ %4 = phi i8* [ %0, %1 ], [ %19, %5 ]

+ ret void

+

+; <label>:5 ; preds = %5, %1

+ %6 = phi i8* [ %19, %5 ], [ %0, %1 ]

+ %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1)

+ %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0

+ %9 = getelementptr inbounds i8* null, i32 3

+ %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1)

+ %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2

+ %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1)

+ %13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0

+ %14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1

+ %15 = getelementptr inbounds i8* %6, i32 3

+ %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1)

+ %17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1

+ %18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2

+ %19 = getelementptr inbounds i8* %6, i32 48

+ %20 = bitcast <16 x i8> %13 to <2 x i64>

+ %21 = bitcast <16 x i8> %8 to <2 x i64>

+ %22 = bitcast <16 x i8> %14 to <2 x i64>

+ %23 = shufflevector <2 x i64> %22, <2 x i64> undef, <1 x i32> zeroinitializer

+ %24 = bitcast <1 x i64> %23 to <8 x i8>

+ %25 = zext <8 x i8> %24 to <8 x i16>

+ %26 = sub <8 x i16> zeroinitializer, %25

+ %27 = bitcast <16 x i8> %17 to <2 x i64>

+ %28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind

+ %29 = mul <8 x i16> %28, %28

+ %30 = add <8 x i16> zeroinitializer, %29

+ %31 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> undef, <8 x i16> %30) nounwind

+ %32 = bitcast <16 x i8> %11 to <2 x i64>

+ %33 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> zeroinitializer

+ %34 = bitcast <1 x i64> %33 to <8 x i8>

+ %35 = zext <8 x i8> %34 to <8 x i16>

+ %36 = sub <8 x i16> %35, zeroinitializer

+ %37 = bitcast <16 x i8> %18 to <2 x i64>

+ %38 = shufflevector <2 x i64> %37, <2 x i64> undef, <1 x i32> zeroinitializer

+ %39 = bitcast <1 x i64> %38 to <8 x i8>

+ %40 = zext <8 x i8> %39 to <8 x i16>

+ %41 = sub <8 x i16> zeroinitializer, %40

+ %42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind

+ %43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind

+ %44 = mul <8 x i16> %42, %42

+ %45 = mul <8 x i16> %43, %43

+ %46 = add <8 x i16> %45, %44

+ %47 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %31, <8 x i16> %46) nounwind

+ %48 = bitcast <8 x i16> %47 to <2 x i64>

+ %49 = shufflevector <2 x i64> %48, <2 x i64> undef, <1 x i32> zeroinitializer

+ %50 = bitcast <1 x i64> %49 to <4 x i16>

+ %51 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %50, <4 x i16> undef) nounwind

+ %52 = tail call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %51, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)

+ %53 = bitcast <4 x i16> %52 to <1 x i64>

+ %54 = shufflevector <1 x i64> %53, <1 x i64> undef, <2 x i32> <i32 0, i32 1>

+ %55 = bitcast <2 x i64> %54 to <8 x i16>

+ %56 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %55, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)

+ %57 = shufflevector <2 x i64> %20, <2 x i64> undef, <1 x i32> <i32 1>

+ %58 = bitcast <1 x i64> %57 to <8 x i8>

+ %59 = zext <8 x i8> %58 to <8 x i16>

+ %60 = sub <8 x i16> zeroinitializer, %59

+ %61 = shufflevector <2 x i64> %21, <2 x i64> undef, <1 x i32> <i32 1>

+ %62 = bitcast <1 x i64> %61 to <8 x i8>

+ %63 = zext <8 x i8> %62 to <8 x i16>

+ %64 = sub <8 x i16> %63, zeroinitializer

+ %65 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %60) nounwind

+ %66 = mul <8 x i16> %65, %65

+ %67 = add <8 x i16> zeroinitializer, %66

+ %68 = shufflevector <2 x i64> %27, <2 x i64> undef, <1 x i32> <i32 1>

+ %69 = bitcast <1 x i64> %68 to <8 x i8>

+ %70 = zext <8 x i8> %69 to <8 x i16>

+ %71 = sub <8 x i16> zeroinitializer, %70

+ %72 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> undef) nounwind

+ %73 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %71) nounwind

+ %74 = mul <8 x i16> %72, %72

+ %75 = mul <8 x i16> %73, %73

+ %76 = add <8 x i16> %75, %74

+ %77 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> <i32 1>

+ %78 = bitcast <1 x i64> %77 to <8 x i8>

+ %79 = zext <8 x i8> %78 to <8 x i16>

+ %80 = sub <8 x i16> %79, zeroinitializer

+ %81 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %80) nounwind

+ %82 = mul <8 x i16> %81, %81

+ %83 = add <8 x i16> zeroinitializer, %82

+ %84 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %76, <8 x i16> %83) nounwind

+ %85 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %67, <8 x i16> %84) nounwind

+ %86 = bitcast <8 x i16> %85 to <2 x i64>

+ %87 = shufflevector <2 x i64> %86, <2 x i64> undef, <1 x i32> <i32 1>

+ %88 = bitcast <1 x i64> %87 to <4 x i16>

+ %89 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %88, <4 x i16> undef) nounwind

+ %90 = tail call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %89, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)

+ %91 = bitcast <4 x i16> %90 to <1 x i64>

+ %92 = shufflevector <1 x i64> undef, <1 x i64> %91, <2 x i32> <i32 0, i32 1>

+ %93 = bitcast <2 x i64> %92 to <8 x i16>

+ %94 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %93, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)

+ %95 = bitcast <8 x i8> %56 to <1 x i64>

+ %96 = bitcast <8 x i8> %94 to <1 x i64>

+ %97 = shufflevector <1 x i64> %95, <1 x i64> %96, <2 x i32> <i32 0, i32 1>

+ %98 = bitcast <2 x i64> %97 to <16 x i8>

+ tail call void @llvm.arm.neon.vst1.v16i8(i8* null, <16 x i8> %98, i32 1)

+ %99 = icmp slt i32 undef, undef

+ br i1 %99, label %5, label %3

+}

+

+declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone

+

+declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone

+

+declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone

+

+declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone

+

+declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone

+

+declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone

+; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s

+; rdar://12201387

+

+;CHECK: select_s_v_v

+;CHECK: it ne

+;CHECK-NEXT: vmovne.i32

+;CHECK: bx

+define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) {

+entry:

+ %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1)

+ %and = and i32 %avail, 1

+ %tobool = icmp eq i32 %and, 0

+ %vld1. = select i1 %tobool, <16 x i8> %vld1, <16 x i8> zeroinitializer

+ ret <16 x i8> %vld1.

+}

+

+declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 )

+

+; RUN: llc < %s -march=arm -mcpu=arm7tdmi | FileCheck %s

+

+; movw is only legal for V6T2 and later.

+; rdar://12300648

+

+define i32 @t(i32 %x) {

+; CHECK: t:

+; CHECK-NOT: movw

+ %tmp = add i32 %x, -65535

+ ret i32 %tmp

+}

+; RUN: llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s

+

+; Check for error message:

+; CHECK: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type

+

+define void @f() nounwind ssp {

+ %1 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } asm "vldm $4, { ${0:q}, ${1:q}, ${2:q}, ${3:q} }", "=r,=r,=r,=r,r"(i64* undef) nounwind, !srcloc !0

+ ret void

+}

+

+!0 = metadata !{i32 318437}

+; RUN: llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s

+

+; Check for error message:

+; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type

+

+define hidden void @f(i32* %corr, i32 %order) nounwind ssp {

+ tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, <2 x i64>* undef) nounwind, !srcloc !0

+ ret void

+}

+

+!0 = metadata !{i32 257}

+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s

+; Test that we correctly use registers and align elements when using va_arg

+

+%struct_t = type { double, double, double }

+@static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }

+

+declare void @llvm.va_start(i8*) nounwind

+declare void @llvm.va_end(i8*) nounwind

+

+; CHECK: test_byval_8_bytes_alignment:

+define void @test_byval_8_bytes_alignment(i32 %i, ...) {

+entry:

+; CHECK: stm r0, {r1, r2, r3}

+ %g = alloca i8*

+ %g1 = bitcast i8** %g to i8*

+ call void @llvm.va_start(i8* %g1)

+

+; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7

+; CHECK: bfc [[REG]], #0, #3

+ %0 = va_arg i8** %g, double

+ call void @llvm.va_end(i8* %g1)

+

+ ret void

+}

+

+; CHECK: main:

+; CHECK: ldm r0, {r2, r3}

+define i32 @main() {

+entry:

+ call void (i32, ...)* @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)

+ ret i32 0

+}

+

+declare void @f(double);

+

+; CHECK: test_byval_8_bytes_alignment_fixed_arg:

+; CHECK-NOT: str r1

+; CHECK: str r3, [sp, #12]

+; CHECK: str r2, [sp, #8]

+; CHECK-NOT: str r1

+define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind {

+entry:

+ %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0

+ %0 = load double* %a

+ call void (double)* @f(double %0)

+ ret void

+}

+

+; CHECK: main_fixed_arg:

+; CHECK: ldm r0, {r2, r3}

+define i32 @main_fixed_arg() {

+entry:

+ call void (i32, %struct_t*)* @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val)

+ ret i32 0

+}

+

+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s

+

+@.str = private unnamed_addr constant [12 x i8] c"val.a = %f\0A\00"

+%struct_t = type { double, double, double }

+@static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }

+

+declare i32 @printf(i8*, ...)

+

+; CHECK: test_byval_usage_scheduling:

+; CHECK: str r3, [sp, #12]

+; CHECK: str r2, [sp, #8]

+; CHECK: vldr d16, [sp, #8]

+define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind {

+entry:

+ %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0

+ %0 = load double* %a

+ %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %0)

+ ret void

+}

+; RUN: llc < %s -mtriple=armv7-none-linux- | FileCheck %s

+; Check that LDRB_POST_IMM instruction emitted properly.

+

+%my_struct_t = type { i8, i8, i8, i8, i8 }

+@main.val = private unnamed_addr constant %my_struct_t { i8 1, i8 2, i8 3, i8 4, i8 5 }

+

+declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);

+

+; CHECK: main:

+define i32 @main() nounwind {

+entry:

+; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1

+ call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval @main.val)

+ ret i32 0

+}

+

+; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s

+

+%struct.s = type { [4 x i32] }

+@v = constant %struct.s zeroinitializer;

+

+declare void @f(%struct.s* %p);

+

+; CHECK: t:

+define void @t(i32 %a, %struct.s* byval %s) nounwind {

+entry:

+

+; Here we need to only check proper start address of restored %s argument.

+; CHECK: sub sp, sp, #16

+; CHECK: push {r11, lr}

+; CHECK: add r0, sp, #12

+; CHECK: stm r0, {r1, r2, r3}

+; CHECK: add r0, sp, #12

+; CHECK-NEXT: bl f

+ call void @f(%struct.s* %s)

+ ret void

+}

+

+; CHECK: caller:

+define void @caller() {

+

+; CHECK: ldm r0, {r1, r2, r3}

+ call void @t(i32 0, %struct.s* @v);

+ ret void

+}

+; RUN: llc < %s -march=arm -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp | FileCheck %s

+

+; This test checks that the VMLxForwarting feature is disabled for A15.

+; CHECK: fun_a

+define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{

+ %1 = add <4 x i32> %x, %y

+; CHECK-NOT: vmul

+; CHECK: vmla

+ %2 = mul <4 x i32> %1, %1

+ %3 = add <4 x i32> %y, %2

+ ret <4 x i32> %3

+}

+; RUN: llc < %s -mcpu=cortex-a15 | FileCheck %s

+

+; CHECK: a

+define i32 @a(i32 %x) {

+ ret i32 %x;

+}

+

+; CHECK: func4

+; This function should not need to use callee-saved registers.

+; rdar://problem/12203728

+; CHECK-NOT: r4

+define i32 @func4(i32* %p) nounwind optsize ssp {

+entry:

+ %0 = atomicrmw add i32* %p, i32 1 monotonic

+ ret i32 %0

+}

+; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s

+

+; CHECK: max:

+define i32 @max(i8 %ctx, i32* %ptr, i32 %val)

+{

+; CHECK: ldrex

+; CHECK: cmp [[old:r[0-9]*]], [[val:r[0-9]*]]

+; CHECK: movhi {{r[0-9]*}}, [[old]]

+ %old = atomicrmw umax i32* %ptr, i32 %val monotonic

+ ret i32 %old

+}

+

+; CHECK: min:

+define i32 @min(i8 %ctx, i32* %ptr, i32 %val)

+{

+; CHECK: ldrex

+; CHECK: cmp [[old:r[0-9]*]], [[val:r[0-9]*]]

+; CHECK: movlo {{r[0-9]*}}, [[old]]

+ %old = atomicrmw umin i32* %ptr, i32 %val monotonic

+ ret i32 %old

+}

+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s

+; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM

+; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT

+; rdar://12348580

+

+define void @t1() noreturn minsize nounwind ssp {

+entry:

+; ARM: t1:

+; ARM: bl _bar

+

+; SWIFT: t1:

+; SWIFT: bl _bar

+ tail call void @bar() noreturn nounwind

+ unreachable

+}

+

+define void @t2() noreturn minsize nounwind ssp {

+entry:

+; ARM: t2:

+; ARM: bl _t1

+

+; SWIFT: t2:

+; SWIFT: bl _t1

+ tail call void @t1() noreturn nounwind

+ unreachable

+}

+

+declare void @bar() noreturn

+; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM

+; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT

+; rdar://8979299

+

+define void @t1() noreturn nounwind ssp {

+entry:

+; ARM: t1:

+; ARM: mov lr, pc

+; ARM: b _bar

+

+; SWIFT: t1:

+; SWIFT: mov lr, pc

+; SWIFT: b _bar

+ tail call void @bar() noreturn nounwind

+ unreachable

+}

+

+define void @t2() noreturn nounwind ssp {

+entry:

+; ARM: t2:

+; ARM: mov lr, pc

+; ARM: b _t1

+

+; SWIFT: t2:

+; SWIFT: mov lr, pc

+; SWIFT: b _t1

+ tail call void @t1() noreturn nounwind

+ unreachable

+}

+

+declare void @bar() noreturn

+

+; rdar://12559385

+define i64 @f5(i32 %vi) {

+entry:

+; CHECK: f5:

+; CHECK: movw [[REG:r[0-9]+]], #36102

+; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]

+ %v0 = zext i32 %vi to i64

+ %v1 = xor i64 %v0, -155057456198619

+ %v4 = add i64 %v1, 155057456198619

+ %v5 = add i64 %v4, %v1

+ ret i64 %v5

+}

+; RUN: llc < %s -mcpu=cortex-a9 -verify-coalescing -verify-machineinstrs | FileCheck %s

+

+; CHECK: f3

+; This function has lane insertions that span basic blocks.

+; The trivial REG_SEQUENCE lowering can't handle that, but the coalescer can.

+;

+; void f3(float *p, float *q) {

+; float32x2_t x;

+; x[1] = p[3];

+; if (q)

+; x[0] = q[0] + q[1];

+; else

+; x[0] = p[2];

+; vst1_f32(p+4, x);

+; }

+;

+; CHECK-NOT: vmov

+; CHECK-NOT: vorr

+define void @f3(float* %p, float* %q) nounwind ssp {

+entry:

+ %arrayidx = getelementptr inbounds float* %p, i32 3

+ %0 = load float* %arrayidx, align 4

+ %vecins = insertelement <2 x float> undef, float %0, i32 1

+ %tobool = icmp eq float* %q, null

+ br i1 %tobool, label %if.else, label %if.then

+

+if.then: ; preds = %entry

+ %1 = load float* %q, align 4

+ %arrayidx2 = getelementptr inbounds float* %q, i32 1

+ %2 = load float* %arrayidx2, align 4

+ %add = fadd float %1, %2

+ %vecins3 = insertelement <2 x float> %vecins, float %add, i32 0

+ br label %if.end

+

+if.else: ; preds = %entry

+ %arrayidx4 = getelementptr inbounds float* %p, i32 2

+ %3 = load float* %arrayidx4, align 4

+ %vecins5 = insertelement <2 x float> %vecins, float %3, i32 0

+ br label %if.end

+

+if.end: ; preds = %if.else, %if.then

+ %x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ]

+ %add.ptr = getelementptr inbounds float* %p, i32 4

+ %4 = bitcast float* %add.ptr to i8*

+ tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4)

+ ret void

+}

+

+declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind

+declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly

+

+; CHECK: f4

+; This function inserts a lane into a fully defined vector.

+; The destination lane isn't read, so the subregs can coalesce.

+; CHECK-NOT: vmov

+; CHECK-NOT: vorr

+define void @f4(float* %p, float* %q) nounwind ssp {

+entry:

+ %0 = bitcast float* %p to i8*

+ %vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %0, i32 4)

+ %tobool = icmp eq float* %q, null

+ br i1 %tobool, label %if.end, label %if.then

+

+if.then: ; preds = %entry

+ %1 = load float* %q, align 4

+ %arrayidx1 = getelementptr inbounds float* %q, i32 1

+ %2 = load float* %arrayidx1, align 4

+ %add = fadd float %1, %2

+ %vecins = insertelement <2 x float> %vld1, float %add, i32 1

+ br label %if.end

+

+if.end: ; preds = %entry, %if.then

+ %x.0 = phi <2 x float> [ %vecins, %if.then ], [ %vld1, %entry ]

+ tail call void @llvm.arm.neon.vst1.v2f32(i8* %0, <2 x float> %x.0, i32 4)

+ ret void

+}

+

+; CHECK: f5

+; Coalesce vector lanes through phis.

+; CHECK: vmov.f32 {{.*}}, #1.0

+; CHECK-NOT: vmov

+; CHECK-NOT: vorr

+; CHECK: %if.end

+; We may leave the last insertelement in the if.end block.

+; It is inserting the %add value into a dead lane, but %add causes interference

+; in the entry block, and we don't do dead lane checks across basic blocks.

+define void @f5(float* %p, float* %q) nounwind ssp {

+entry:

+ %0 = bitcast float* %p to i8*

+ %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %0, i32 4)

+ %vecext = extractelement <4 x float> %vld1, i32 0

+ %vecext1 = extractelement <4 x float> %vld1, i32 1

+ %vecext2 = extractelement <4 x float> %vld1, i32 2

+ %vecext3 = extractelement <4 x float> %vld1, i32 3

+ %add = fadd float %vecext3, 1.000000e+00

+ %tobool = icmp eq float* %q, null

+ br i1 %tobool, label %if.end, label %if.then

+

+if.then: ; preds = %entry

+ %arrayidx = getelementptr inbounds float* %q, i32 1

+ %1 = load float* %arrayidx, align 4

+ %add4 = fadd float %vecext, %1

+ %2 = load float* %q, align 4

+ %add6 = fadd float %vecext1, %2

+ %arrayidx7 = getelementptr inbounds float* %q, i32 2

+ %3 = load float* %arrayidx7, align 4

+ %add8 = fadd float %vecext2, %3

+ br label %if.end

+

+if.end: ; preds = %entry, %if.then

+ %a.0 = phi float [ %add4, %if.then ], [ %vecext, %entry ]

+ %b.0 = phi float [ %add6, %if.then ], [ %vecext1, %entry ]

+ %c.0 = phi float [ %add8, %if.then ], [ %vecext2, %entry ]

+ %vecinit = insertelement <4 x float> undef, float %a.0, i32 0

+ %vecinit9 = insertelement <4 x float> %vecinit, float %b.0, i32 1

+ %vecinit10 = insertelement <4 x float> %vecinit9, float %c.0, i32 2

+ %vecinit11 = insertelement <4 x float> %vecinit10, float %add, i32 3

+ tail call void @llvm.arm.neon.vst1.v4f32(i8* %0, <4 x float> %vecinit11, i32 4)

+ ret void

+}

+

+declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly

+

+declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind

+

+; CHECK: pr13999

+define void @pr13999() nounwind readonly {

+entry:

+ br i1 true, label %outer_loop, label %loop.end

+

+outer_loop:

+ %d = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]

+ %0 = insertelement <2 x double> <double 0.0, double 0.0>, double %d, i32 0

+ br i1 undef, label %after_inner_loop, label %inner_loop

+

+inner_loop:

+ br i1 true, label %after_inner_loop, label %inner_loop

+

+after_inner_loop:

+ %1 = phi <2 x double> [ %0, %outer_loop ], [ <double 0.0, double 0.0>,

+%inner_loop ]

+ %2 = extractelement <2 x double> %1, i32 1

+ %add = fadd double 1.0, %2

+ br i1 false, label %loop.end, label %outer_loop

+

+loop.end:

+ %d.end = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]

+ ret void

+}

+

+; CHECK: pr14078

+define arm_aapcs_vfpcc i32 @pr14078(i8* nocapture %arg, i8* nocapture %arg1, i32 %arg2) nounwind uwtable readonly {

+bb:

+ br i1 undef, label %bb31, label %bb3

+

+bb3: ; preds = %bb12, %bb

+ %tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer

+ %tmp4 = bitcast <1 x i64> %tmp to <2 x float>

+ %tmp5 = shufflevector <2 x float> %tmp4, <2 x float> undef, <4 x i32> zeroinitializer

+ %tmp6 = bitcast <4 x float> %tmp5 to <2 x i64>

+ %tmp7 = shufflevector <2 x i64> %tmp6, <2 x i64> undef, <1 x i32> zeroinitializer

+ %tmp8 = bitcast <1 x i64> %tmp7 to <2 x float>

+ %tmp9 = tail call <2 x float> @baz(<2 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00>, <2 x float> %tmp8, <2 x float> zeroinitializer) nounwind

+ br i1 undef, label %bb10, label %bb12

+

+bb10: ; preds = %bb3

+ %tmp11 = load <4 x float>* undef, align 8

+ br label %bb12

+

+bb12: ; preds = %bb10, %bb3

+ %tmp13 = shufflevector <2 x float> %tmp9, <2 x float> zeroinitializer, <2 x i32> <i32 0, i32 2>

+ %tmp14 = bitcast <2 x float> %tmp13 to <1 x i64>

+ %tmp15 = shufflevector <1 x i64> %tmp14, <1 x i64> zeroinitializer, <2 x i32> <i32 0, i32 1>

+ %tmp16 = bitcast <2 x i64> %tmp15 to <4 x float>

+ %tmp17 = fmul <4 x float> zeroinitializer, %tmp16

+ %tmp18 = bitcast <4 x float> %tmp17 to <2 x i64>

+ %tmp19 = shufflevector <2 x i64> %tmp18, <2 x i64> undef, <1 x i32> zeroinitializer

+ %tmp20 = bitcast <1 x i64> %tmp19 to <2 x float>

+ %tmp21 = tail call <2 x float> @baz67(<2 x float> %tmp20, <2 x float> undef) nounwind

+ %tmp22 = tail call <2 x float> @baz67(<2 x float> %tmp21, <2 x float> %tmp21) nounwind

+ %tmp23 = shufflevector <2 x float> %tmp22, <2 x float> undef, <4 x i32> zeroinitializer

+ %tmp24 = bitcast <4 x float> %tmp23 to <2 x i64>

+ %tmp25 = shufflevector <2 x i64> %tmp24, <2 x i64> undef, <1 x i32> zeroinitializer

+ %tmp26 = bitcast <1 x i64> %tmp25 to <2 x float>

+ %tmp27 = extractelement <2 x float> %tmp26, i32 0

+ %tmp28 = fcmp olt float %tmp27, 0.000000e+00

+ %tmp29 = select i1 %tmp28, i32 0, i32 undef

+ %tmp30 = icmp ult i32 undef, %arg2

+ br i1 %tmp30, label %bb3, label %bb31

+

+bb31: ; preds = %bb12, %bb

+ %tmp32 = phi i32 [ 1, %bb ], [ %tmp29, %bb12 ]

+ ret i32 %tmp32

+}

+

+declare <2 x float> @baz(<2 x float>, <2 x float>, <2 x float>) nounwind readnone

+

+declare <2 x float> @baz67(<2 x float>, <2 x float>) nounwind readnone

+

+%struct.wombat.5 = type { %struct.quux, %struct.quux, %struct.quux, %struct.quux }

+%struct.quux = type { <4 x float> }

+

+; CHECK: pr14079

+define linkonce_odr arm_aapcs_vfpcc %struct.wombat.5 @pr14079(i8* nocapture %arg, i8* nocapture %arg1, i8* nocapture %arg2) nounwind uwtable inlinehint {

+bb:

+ %tmp = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer

+ %tmp3 = bitcast <1 x i64> %tmp to <2 x float>

+ %tmp4 = shufflevector <2 x float> %tmp3, <2 x float> zeroinitializer, <2 x i32> <i32 1, i32 3>

+ %tmp5 = shufflevector <2 x float> %tmp4, <2 x float> undef, <2 x i32> <i32 1, i32 3>

+ %tmp6 = bitcast <2 x float> %tmp5 to <1 x i64>

+ %tmp7 = shufflevector <1 x i64> undef, <1 x i64> %tmp6, <2 x i32> <i32 0, i32 1>

+ %tmp8 = bitcast <2 x i64> %tmp7 to <4 x float>

+ %tmp9 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> <i32 1>

+ %tmp10 = bitcast <1 x i64> %tmp9 to <2 x float>

+ %tmp11 = shufflevector <2 x float> %tmp10, <2 x float> undef, <2 x i32> <i32 0, i32 2>

+ %tmp12 = shufflevector <2 x float> %tmp11, <2 x float> undef, <2 x i32> <i32 0, i32 2>

+ %tmp13 = bitcast <2 x float> %tmp12 to <1 x i64>

+ %tmp14 = shufflevector <1 x i64> %tmp13, <1 x i64> undef, <2 x i32> <i32 0, i32 1>

+ %tmp15 = bitcast <2 x i64> %tmp14 to <4 x float>

+ %tmp16 = insertvalue %struct.wombat.5 undef, <4 x float> %tmp8, 1, 0

+ %tmp17 = insertvalue %struct.wombat.5 %tmp16, <4 x float> %tmp15, 2, 0

+ %tmp18 = insertvalue %struct.wombat.5 %tmp17, <4 x float> undef, 3, 0

+ ret %struct.wombat.5 %tmp18

+}

+

+; CHECK: adjustCopiesBackFrom

+; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom

+; is tempted to remove it.

+; CHECK: %if.else3

+; CHECK: vorr d

+define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret %agg.result, <2 x i64> %in) {

+entry:

+ %0 = extractelement <2 x i64> %in, i32 0

+ %cmp = icmp slt i64 %0, 1

+ %.in = select i1 %cmp, <2 x i64> <i64 0, i64 undef>, <2 x i64> %in

+ %1 = extractelement <2 x i64> %in, i32 1

+ %cmp1 = icmp slt i64 %1, 1

+ br i1 %cmp1, label %if.then2, label %if.else3

+

+if.then2: ; preds = %entry

+ %2 = insertelement <2 x i64> %.in, i64 0, i32 1

+ br label %if.end4

+

+if.else3: ; preds = %entry

+ %3 = shufflevector <2 x i64> %.in, <2 x i64> %in, <2 x i32> <i32 0, i32 3>

+ br label %if.end4

+

+if.end4: ; preds = %if.else3, %if.then2

+ %result.2 = phi <2 x i64> [ %2, %if.then2 ], [ %3, %if.else3 ]

+ store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128

+ ret void

+}

+

+; <rdar://problem/12758887>

+; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than

+; once under rare circumstances. When widening a register from QPR to DTriple

+; with the original virtual register in dsub_1_dsub_2, the double rewrite would

+; produce an invalid sub-register.

+;

+; This is because dsub_1_dsub_2 is not an idempotent sub-register index.

+; It will translate %vr:dsub_0 -> %vr:dsub_1.

+define hidden fastcc void @radar12758887() nounwind optsize ssp {

+entry:

+ br i1 undef, label %for.body, label %for.end70

+

+for.body: ; preds = %for.end, %entry

+ br i1 undef, label %for.body29, label %for.end

+

+for.body29: ; preds = %for.body29, %for.body

+ %0 = load <2 x double>* null, align 1

+ %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer

+ %mul41 = fmul <2 x double> undef, %splat40

+ %add42 = fadd <2 x double> undef, %mul41

+ %splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 1, i32 1>

+ %mul45 = fmul <2 x double> undef, %splat44

+ %add46 = fadd <2 x double> undef, %mul45

+ br i1 undef, label %for.end, label %for.body29

+

+for.end: ; preds = %for.body29, %for.body

+ %accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ]

+ %accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ]

+ %1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> <i32 1, i32 0>

+ %add58 = fadd <2 x double> undef, %1

+ %mul61 = fmul <2 x double> %add58, undef

+ %add63 = fadd <2 x double> undef, %mul61

+ %add64 = fadd <2 x double> undef, %add63

+ %add67 = fadd <2 x double> undef, %add64

+ store <2 x double> %add67, <2 x double>* undef, align 1

+ br i1 undef, label %for.end70, label %for.body

+

+for.end70: ; preds = %for.end, %entry

+ ret void

+}

+; RUN: llc < %s -mtriple=armv4t-unknown-linux-gnueabi -disable-cgp-branch-opts -verify-machineinstrs | FileCheck %s

+define i32 @f8() nounwind {

+; Check that constant propagation through (i32)-1 => (float)Nan => (i32)-1

+; gives expected result

+; CHECK: f8

+; CHECK: mvn r0, #0

+ %tmp0 = bitcast i32 -1 to float

+ %tmp1 = bitcast float %tmp0 to i32

+ ret i32 %tmp1

+}

+

+; RUN: llc < %s -mtriple=armv7

+

+declare void @g(<16 x i8>)

+define void @f(<4 x i8> %param1, <4 x i8> %param2) {

+ %y1 = shufflevector <4 x i8> %param1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

+ %y2 = shufflevector <4 x i8> %param2, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

+ %z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>

+ call void @g(<16 x i8> %z)

+ ret void

+} \ No newline at end of file

+; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s

+

+; CHECK: .section __TEXT,__text,regular,pure_instructions

+; CHECK: .section __TEXT,myprecious

+; CHECK: .section __TEXT,__textcoal_nt,coalesced,pure_instructions

+; CHECK: .section __TEXT,__const_coal,coalesced

+; CHECK: .section __TEXT,__picsymbolstub4,symbol_stubs,none,16

+; CHECK: .section __TEXT,__StaticInit,regular,pure_instructions

+

+

+define void @normal() nounwind readnone {

+; CHECK: .section __TEXT,__text,regular,pure_instructions

+; CHECK: _normal:

+ ret void

+}

+

+define void @special() nounwind readnone section "__TEXT,myprecious" {

+; CHECK: .section __TEXT,myprecious

+; CHECK: _special:

+ ret void

+}

+; RUN: llc < %s -march=arm -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard -mtriple armv7-linux-gnueabi | FileCheck %s

+

+;; This test checks that the ExecutionDepsFix pass performs the domain changes

+;; even when some dependencies are propagated through implicit definitions.

+

+; CHECK: fun_a

+define <4 x float> @fun_a(<4 x float> %in, <4 x float> %x, float %y) nounwind {

+; CHECK: vext

+; CHECK: vext

+; CHECK: vadd.f32

+ %1 = insertelement <4 x float> %in, float %y, i32 0

+ %2 = fadd <4 x float> %1, %x

+ ret <4 x float> %2

+}

+; CHECK: fun_b

+define <4 x i32> @fun_b(<4 x i32> %in, <4 x i32> %x, i32 %y) nounwind {

+; CHECK: vmov.32

+; CHECK: vadd.i32

+ %1 = insertelement <4 x i32> %in, i32 %y, i32 0

+ %2 = add <4 x i32> %1, %x

+ ret <4 x i32> %2

+}

+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM

+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-SWIFT

+

+; CHECK-SWIFT: f1

+; CHECK-SWIFT: sdiv

+

+; CHECK-SWIFT: f2

+; CHECK-SWIFT: udiv

+

+; CHECK-SWIFT: f3

+; CHECK-SWIFT: sdiv

+; CHECK-SWIFT: mls

+

+; CHECK-SWIFT: f4

+; CHECK-SWIFT: udiv

+; CHECK-SWIFT: mls

+; RUN: llc < %s -mtriple=arm-apple-ios5.0 -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8

+; RUN: llc < %s -mtriple=arm-apple-ios5.0 -mcpu=swift | FileCheck %s -check-prefix=SWIFT

+

+; rdar://12481395

+; A8: foo:

+; A8: bl ___divmodsi4

+; A8-NOT: bl ___divmodsi4

+

+; SWIFT: foo:

+; SWIFT: sdiv

+; SWIFT: mls

+; SWIFT-NOT: bl __divmodsi4

+; A8: bar:

+; A8: bl ___udivmodsi4

+; A8-NOT: bl ___udivmodsi4

+

+; SWIFT: bar:

+; SWIFT: udiv

+; SWIFT: mls

+; SWIFT-NOT: bl __udivmodsi4

+; A8: do_indent:

+; SWIFT: do_indent:

+; A8: bl ___divmodsi4

+; SWIFT: sdiv

+; SWIFT: mls

+; SWIFT-NOT: bl __divmodsi4

+; A8: howmany:

+; A8: bl ___udivmodsi4

+; A8-NOT: ___udivsi3

+

+; SWIFT: howmany:

+; SWIFT: udiv

+; SWIFT: mls

+; SWIFT-NOT: bl __udivmodsi4

+; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s

+

+define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {

+; CHECK: test_vmovs_via_vext_lane0to0:

+ %vec = insertelement <2 x float> %in, float %arg, i32 0

+ %res = fadd <2 x float> %vec, %vec

+

+; CHECK: vext.32 d1, d1, d0, #1

+; CHECK: vext.32 d1, d1, d1, #1

+; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1

+

+ ret <2 x float> %res

+}

+

+define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {

+; CHECK: test_vmovs_via_vext_lane0to1:

+ %vec = insertelement <2 x float> %in, float %arg, i32 1

+ %res = fadd <2 x float> %vec, %vec

+

+; CHECK: vext.32 d1, d1, d1, #1

+; CHECK: vext.32 d1, d1, d0, #1

+; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1

+

+ ret <2 x float> %res

+}

+

+define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) {

+; CHECK: test_vmovs_via_vext_lane1to0:

+ %vec = insertelement <2 x float> %in, float %arg, i32 0

+ %res = fadd <2 x float> %vec, %vec

+

+; CHECK: vext.32 d1, d1, d1, #1

+; CHECK: vext.32 d1, d0, d1, #1

+; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1

+

+ ret <2 x float> %res

+}

+

+define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) {

+; CHECK: test_vmovs_via_vext_lane1to1:

+ %vec = insertelement <2 x float> %in, float %arg, i32 1

+ %res = fadd <2 x float> %vec, %vec

+

+; CHECK: vext.32 d1, d0, d1, #1

+; CHECK: vext.32 d1, d1, d1, #1

+; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1

+

+ ret <2 x float> %res

+}

+

+

+define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) {

+; CHECK: test_vmovs_via_vdup:

+

+ ; Do an operation (which will end up NEON because of +neonfp) to convince the

+ ; execution-domain pass that NEON is a good thing to use.

+ %res = fadd float %ret, %ret

+ ; It makes sense for LLVM to do the addition in d0 here, because it's going

+ ; to be returned. This means it will want a "vmov s0, s1":

+; CHECK: vdup.32 d0, d0[1]

+

+ ret float %res

+}

+

+declare float @llvm.sqrt.f32(float)

+

+declare void @bar()

+

+; This is a comp

+define float @test_ineligible(float, float %in) {

+; CHECK: test_ineligible:

+

+ %sqrt = call float @llvm.sqrt.f32(float %in)

+ %val = fadd float %sqrt, %sqrt

+

+ ; This call forces a move from a callee-saved register to the return-reg. That

+ ; move is not eligible for conversion to a d-register instructions because the

+ ; use-def chains would be messed up. Primarily a compile-test (we used to

+ ; internal fault).

+ call void @bar()

+; CHECL: bl bar

+; CHECK: vext.32

+; CHECK: vext.32

+ ret float %val

+}

+

+define i32 @test_vmovs_no_sreg(i32 %in) {

+; CHECK: test_vmovs_no_sreg:

+

+ ; Check that the movement to and from GPRs takes place in the NEON domain.

+; CHECK: vmov.32 d

+ %x = bitcast i32 %in to float

+

+ %res = fadd float %x, %x

+

+; CHECK: vmov.32 r{{[0-9]+}}, d

+ %resi = bitcast float %res to i32

+

+ ret i32 %resi

+}

+; VFP2: vabs.f32 s2, s2

+; NFP0: vabs.f32 s2, s2

+; VFP2: vadd.f32 s

+; NFP1: vadd.f32 d

+; NFP0: vadd.f32 s

+; CORTEXA8: vadd.f32 d

+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB

+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM

+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7

+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF

+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF

+

+@g = global i32 0, align 4

+

+define i32 @LoadGV() {

+entry:

+; THUMB: LoadGV

+; THUMB: movw [[reg0:r[0-9]+]],

+; THUMB: movt [[reg0]],

+; THUMB: add [[reg0]], pc

+; THUMB-ELF: LoadGV

+; THUMB-ELF: ldr.n r[[reg0:[0-9]+]],

+; THUMB-ELF: ldr.n r[[reg1:[0-9]+]],

+; THUMB-ELF: ldr r[[reg0]], [r[[reg1]], r[[reg0]]]

+; ARM: LoadGV

+; ARM: ldr [[reg1:r[0-9]+]],

+; ARM: add [[reg1]], pc, [[reg1]]

+; ARMv7: LoadGV

+; ARMv7: movw [[reg2:r[0-9]+]],

+; ARMv7: movt [[reg2]],

+; ARMv7: add [[reg2]], pc, [[reg2]]

+; ARMv7-ELF: LoadGV

+; ARMv7-ELF: ldr r[[reg2:[0-9]+]],

+; ARMv7-ELF: ldr r[[reg3:[0-9]+]],

+; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]

+ %tmp = load i32* @g

+ ret i32 %tmp

+}

+

+@i = external global i32

+

+define i32 @LoadIndirectSymbol() {

+entry:

+; THUMB: LoadIndirectSymbol

+; THUMB: movw r[[reg3:[0-9]+]],

+; THUMB: movt r[[reg3]],

+; THUMB: add r[[reg3]], pc

+; THUMB: ldr r[[reg3]], [r[[reg3]]]

+; THUMB-ELF: LoadIndirectSymbol

+; THUMB-ELF: ldr.n r[[reg3:[0-9]+]],

+; THUMB-ELF: ldr.n r[[reg4:[0-9]+]],

+; THUMB-ELF: ldr r[[reg3]], [r[[reg4]], r[[reg3]]]

+; ARM: LoadIndirectSymbol

+; ARM: ldr [[reg4:r[0-9]+]],

+; ARM: ldr [[reg4]], [pc, [[reg4]]]

+; ARMv7: LoadIndirectSymbol

+; ARMv7: movw r[[reg5:[0-9]+]],

+; ARMv7: movt r[[reg5]],

+; ARMv7: add r[[reg5]], pc, r[[reg5]]

+; ARMv7: ldr r[[reg5]], [r[[reg5]]]

+; ARMv7-ELF: LoadIndirectSymbol

+; ARMv7-ELF: ldr r[[reg5:[0-9]+]],

+; ARMv7-ELF: ldr r[[reg6:[0-9]+]],

+; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]

+ %tmp = load i32* @i

+ ret i32 %tmp

+}

+; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM-STRICT-ALIGN

+; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN

+

+define void @unaligned_i16_store(i16 %x, i16* %y) nounwind {

+entry:

+; ARM-STRICT-ALIGN: @unaligned_i16_store

+; ARM-STRICT-ALIGN: strb

+; ARM-STRICT-ALIGN: strb

+

+; THUMB-STRICT-ALIGN: @unaligned_i16_store

+; THUMB-STRICT-ALIGN: strb

+; THUMB-STRICT-ALIGN: strb

+

+ store i16 %x, i16* %y, align 1

+ ret void

+}

+

+define i16 @unaligned_i16_load(i16* %x) nounwind {

+entry:

+; ARM-STRICT-ALIGN: @unaligned_i16_load

+; ARM-STRICT-ALIGN: ldrb

+; ARM-STRICT-ALIGN: ldrb

+

+; THUMB-STRICT-ALIGN: @unaligned_i16_load

+; THUMB-STRICT-ALIGN: ldrb

+; THUMB-STRICT-ALIGN: ldrb

+

+ %0 = load i16* %x, align 1

+ ret i16 %0

+}

+

+define void @unaligned_i32_store(i32 %x, i32* %y) nounwind {

+entry:

+; ARM-STRICT-ALIGN: @unaligned_i32_store

+; ARM-STRICT-ALIGN: strb

+; ARM-STRICT-ALIGN: strb

+; ARM-STRICT-ALIGN: strb

+; ARM-STRICT-ALIGN: strb

+

+; THUMB-STRICT-ALIGN: @unaligned_i32_store

+; THUMB-STRICT-ALIGN: strb

+; THUMB-STRICT-ALIGN: strb

+; THUMB-STRICT-ALIGN: strb

+; THUMB-STRICT-ALIGN: strb

+

+ store i32 %x, i32* %y, align 1

+ ret void

+}

+

+define i32 @unaligned_i32_load(i32* %x) nounwind {

+entry:

+; ARM-STRICT-ALIGN: @unaligned_i32_load

+; ARM-STRICT-ALIGN: ldrb

+; ARM-STRICT-ALIGN: ldrb

+; ARM-STRICT-ALIGN: ldrb

+; ARM-STRICT-ALIGN: ldrb

+

+; THUMB-STRICT-ALIGN: @unaligned_i32_load

+; THUMB-STRICT-ALIGN: ldrb

+; THUMB-STRICT-ALIGN: ldrb

+; THUMB-STRICT-ALIGN: ldrb

+; THUMB-STRICT-ALIGN: ldrb

+

+ %0 = load i32* %x, align 1

+ ret i32 %0

+}

+; VFP2: vdiv.f32 s0, s2, s0

+; NFP1: vdiv.f32 s0, s2, s0

+; NFP0: vdiv.f32 s0, s2, s0

+; CORTEXA8: vdiv.f32 s0, s2, s0

+; VFP2: vmul.f32 s

+; NFP1: vmul.f32 d

+; NFP0: vmul.f32 s

+; CORTEXA8: vmul.f32 d

+; RUN: llc -march=arm -mcpu=cortex-a9 -mattr=+vfp4 -enable-unsafe-fp-math < %s | FileCheck %s

+

+; CHECK: test1

+define float @test1(float %x) {

+; CHECK-NOT: vfma

+; CHECK: vmul.f32

+; CHECK-NOT: vfma

+ %t1 = fmul float %x, 3.0

+ %t2 = call float @llvm.fma.f32(float %x, float 2.0, float %t1)

+ ret float %t2

+}

+

+; CHECK: test2

+define float @test2(float %x, float %y) {

+; CHECK-NOT: vmul

+; CHECK: vfma.f32

+; CHECK-NOT: vmul

+ %t1 = fmul float %x, 3.0

+ %t2 = call float @llvm.fma.f32(float %t1, float 2.0, float %y)

+ ret float %t2

+}

+

+; CHECK: test3

+define float @test3(float %x, float %y) {

+; CHECK-NOT: vfma

+; CHECK: vadd.f32

+; CHECK-NOT: vfma

+ %t2 = call float @llvm.fma.f32(float %x, float 1.0, float %y)

+ ret float %t2

+}

+

+; CHECK: test4

+define float @test4(float %x, float %y) {

+; CHECK-NOT: vfma

+; CHECK: vsub.f32

+; CHECK-NOT: vfma

+ %t2 = call float @llvm.fma.f32(float %x, float -1.0, float %y)

+ ret float %t2

+}

+

+; CHECK: test5

+define float @test5(float %x) {

+; CHECK-NOT: vfma

+; CHECK: vmul.f32

+; CHECK-NOT: vfma

+ %t2 = call float @llvm.fma.f32(float %x, float 2.0, float %x)

+ ret float %t2

+}

+

+; CHECK: test6

+define float @test6(float %x) {

+; CHECK-NOT: vfma

+; CHECK: vmul.f32

+; CHECK-NOT: vfma

+ %t1 = fsub float -0.0, %x

+ %t2 = call float @llvm.fma.f32(float %x, float 5.0, float %t1)

+ ret float %t2

+}

+

+declare float @llvm.fma.f32(float, float, float)

+; NEON: vcvt.f32.u32 d

+; NEON: vcvt.f32.s32 d

+; VFP2: vsub.f32 s

+; NFP1: vsub.f32 d

+; NFP0: vsub.f32 s

+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8

+; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -check-prefix=SWIFT

+; A8: t1:

+; SWIFT: t1:

+; A8: subeq r0, r1, #1

+; SWIFT: sub r0, r1, #1

+; A8: addne r0, r1, #1

+; SWIFT: addne r0, r1, #1

+; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s

+define i32 @f1(i32 %a, i32 %b, i32 %c) {

+; CHECK: f1:

+; CHECK: mlsne r0, r0, r1, r2

+ %tmp1 = icmp eq i32 %a, 0

+ br i1 %tmp1, label %cond_false, label %cond_true

+

+cond_true:

+ %tmp2 = mul i32 %a, %b

+ %tmp3 = sub i32 %c, %tmp2

+ ret i32 %tmp3

+

+cond_false:

+ ret i32 %a

+}

+; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8

+; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT

+; rdar://8402126

+; A8: t1:

+; A8: poplt {r7, pc}

+

+; SWIFT: t1:

+; SWIFT: pop {r7, pc}

+; SWIFT: pop {r7, pc}

+; RUN: llc < %s -O0 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s

+; <rdar://problem/12529625>

+

+@foo = global i32 34879, align 4

+@DWJumpTable2808 = global [2 x i32] [i32 sub (i32 ptrtoint (i8* blockaddress(@func, %14) to i32), i32 ptrtoint (i8* blockaddress(@func, %4) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@func, %13) to i32), i32 ptrtoint (i8* blockaddress(@func, %4) to i32))]

+@0 = internal constant [45 x i8] c"func XXXXXXXXXXX :: bb xxxxxxxxxxxxxxxxxxxx\0A\00"

+

+; The indirect branch has the two destinations as successors. The lone PHI

+; statement shouldn't be implicitly defined.

+

+; CHECK: func:

+; CHECK: Ltmp1: @ Block address taken

+; CHECK-NOT: @ implicit-def: R0

+; CHECK: @ 4-byte Reload

+

+define i32 @func() nounwind ssp {

+ %1 = alloca i32, align 4

+ %2 = load i32* @foo, align 4

+ %3 = icmp eq i32 %2, 34879

+ br label %4

+

+; <label>:4 ; preds = %0

+ %5 = zext i1 %3 to i32

+ %6 = mul i32 %5, 287

+ %7 = add i32 %6, 2

+ %8 = getelementptr [2 x i32]* @DWJumpTable2808, i32 0, i32 %5

+ %9 = load i32* %8

+ %10 = add i32 %9, ptrtoint (i8* blockaddress(@func, %4) to i32)

+ %11 = inttoptr i32 %10 to i8*

+ %12 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([45 x i8]* @0, i32 0, i32 0))

+ indirectbr i8* %11, [label %13, label %14]

+

+; <label>:13 ; preds = %4

+ %tmp14 = phi i32 [ %7, %4 ]

+ store i32 23958, i32* @foo, align 4

+ %tmp15 = load i32* %1, align 4

+ %tmp16 = icmp eq i32 %tmp15, 0

+ %tmp17 = zext i1 %tmp16 to i32

+ %tmp21 = add i32 %tmp17, %tmp14

+ ret i32 %tmp21

+

+; <label>:14 ; preds = %4

+ ret i32 42

+}

+

+declare i32 @printf(i8*, ...)

+; RUN: llc %s -o - -march=arm -mattr=+neon | FileCheck %s

+

+; This test checks that when inserting one (integer) element into a vector,

+; the vector is not spuriously copied. "vorr dX, dY, dY" is the way of moving

+; one DPR to another that we check for.

+

+; CHECK: @f

+; CHECK-NOT: vorr d

+; CHECK: vmov.32 d

+; CHECK-NOT: vorr d

+; CHECK: mov pc, lr

+define <4 x i32> @f(<4 x i32> %in) {

+ %1 = insertelement <4 x i32> %in, i32 255, i32 3

+ ret <4 x i32> %1

+}

+

+; CHECK: @g

+; CHECK-NOT: vorr d

+; CHECK: vmov.16 d

+; CHECK-NOT: vorr d

+; CHECK: mov pc, lr

+define <8 x i16> @g(<8 x i16> %in) {

+ %1 = insertelement <8 x i16> %in, i16 255, i32 7

+ ret <8 x i16> %1

+}

+

+; CHECK: @h

+; CHECK-NOT: vorr d

+; CHECK: vmov.8 d

+; CHECK-NOT: vorr d

+; CHECK: mov pc, lr

+define <16 x i8> @h(<16 x i8> %in) {

+ %1 = insertelement <16 x i8> %in, i8 255, i32 15

+ ret <16 x i8> %1

+}

+; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s

+; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s

+; RUN: llc < %s -march=arm | FileCheck %s

+; Check generated signed and unsigned multiply accumulate long.

+

+define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {

+;CHECK: MACLongTest1:

+;CHECK: umlal

+ %conv = zext i32 %a to i64

+ %conv1 = zext i32 %b to i64

+ %mul = mul i64 %conv1, %conv

+ %add = add i64 %mul, %c

+ ret i64 %add

+}

+

+define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {

+;CHECK: MACLongTest2:

+;CHECK: smlal

+ %conv = sext i32 %a to i64

+ %conv1 = sext i32 %b to i64

+ %mul = mul nsw i64 %conv1, %conv

+ %add = add nsw i64 %mul, %c

+ ret i64 %add

+}

+

+define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {

+;CHECK: MACLongTest3:

+;CHECK: umlal

+ %conv = zext i32 %b to i64

+ %conv1 = zext i32 %a to i64

+ %mul = mul i64 %conv, %conv1

+ %conv2 = zext i32 %c to i64

+ %add = add i64 %mul, %conv2

+ ret i64 %add

+}

+

+define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {

+;CHECK: MACLongTest4:

+;CHECK: smlal

+ %conv = sext i32 %b to i64

+ %conv1 = sext i32 %a to i64

+ %mul = mul nsw i64 %conv, %conv1

+ %conv2 = sext i32 %c to i64

+ %add = add nsw i64 %mul, %conv2

+ ret i64 %add

+}

+; RUN: llc < %s -march=arm -mattr=+v6t2 -arm-use-mulops=false | FileCheck %s -check-prefix=NO_MULOPS

+; CHECK: f1:

+; NO_MULOPS: f1:

+; NO_MULOPS: mul r0, r0, r1

+; NO_MULOPS-NEXT: sub r0, r2, r0

+

+; CHECK: f2:

+; CHECK: mul r0, r0, r1

+; CHECK-NEXT: sub r0, r0, r2

+; NO_MULOPS: f2:

+; NO_MULOPS: mul r0, r0, r1

+; NO_MULOPS-NEXT: sub r0, r0, r2

+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=swift | FileCheck %s

+

+; CHECK: test_v2f32

+; CHECK: vfma.f32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}

+

+define <2 x float> @test_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone ssp {

+entry:

+ %call = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone

+ ret <2 x float> %call

+}

+

+; CHECK: test_v4f32

+; CHECK: vfma.f32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}

+

+define <4 x float> @test_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone ssp {

+entry:

+ %call = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone

+ ret <4 x float> %call

+}

+

+declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone

+declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone

+; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s --check-prefix=SWIFT

+; CHECK: vld1.64

+; CHECK: vld1.64

+; CHECK: vst1.64

+; SWIFT: t1

+; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}

+; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}

+; SWIFT: vadd.i64 q

+; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}

+; CHECK: vld1.64

+; CHECK: vld1.64

+; SWIFT: t2

+; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}

+; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}

+; SWIFT: vsub.i64 q

+; SWIFT: vmov r0, r1, d

+; SWIFT: vmov r2, r3, d

+; Limited alignment.

+; SWIFT: t3

+; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}

+; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}

+; SWIFT: vadd.i64 q

+; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}}

+define void @t3(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {

+entry:

+ %0 = load <2 x i64>* %a, align 8

+ %1 = load <2 x i64>* %b, align 8

+ %2 = add <2 x i64> %0, %1

+ %3 = bitcast <2 x i64> %2 to <4 x i32>

+ store <4 x i32> %3, <4 x i32>* %r, align 8

+ ret void

+}

+; CHECK: bx lr

+; CHECK: bx lr

+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s

+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s

+; CHECK: vld1.32

+; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128]

+; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128]

+; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4

+; T2: addle r1, r0

+; T2: suble r1, #10

+; ARM: andge r3, r3, r2

+; ARM: mov r0, r3

+; T2: andge r3, r2

+; T2: mov r0, r3

+; ARM: orrge r3, r3, r2

+; ARM: mov r0, r3

+; T2: orrge r3, r2

+; T2: mov r0, r3

+; T2: eorlt r3, r2

+

+; Handle frame index operands.

+define void @pr13628() nounwind uwtable align 2 {

+ %x3 = alloca i8, i32 256, align 8

+ %x4 = load i8* undef, align 1

+ %x5 = icmp ne i8 %x4, 0

+ %x6 = select i1 %x5, i8* %x3, i8* null

+ call void @bar(i8* %x6) nounwind

+ ret void

+}

+declare void @bar(i8*)

+

+; Fold zext i1 into predicated add

+define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {

+entry:

+; ARM: t13

+; ARM: cmp r1, #10

+; ARM: addgt r0, r0, #1

+

+; T2: t13

+; T2: cmp r1, #10

+; T2: addgt r0, #1

+ %cmp = icmp sgt i32 %a, 10

+ %conv = zext i1 %cmp to i32

+ %add = add i32 %conv, %c

+ ret i32 %add

+}

+

+; Fold sext i1 into predicated sub

+define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {

+entry:

+; ARM: t14

+; ARM: cmp r1, #10

+; ARM: subgt r0, r0, #1

+

+; T2: t14

+; T2: cmp r1, #10

+; T2: subgt r0, #1

+ %cmp = icmp sgt i32 %a, 10

+ %conv = sext i1 %cmp to i32

+ %add = add i32 %conv, %c

+ ret i32 %add

+}

+

+; rdar://12442472

+; We can't do tail call since address of s is passed to the callee and part of

+; s is in caller's local frame.

+define void @f3(%struct.SmallStruct* nocapture byval %s) nounwind optsize {

+; CHECK: f3

+; CHECK: bl _consumestruct

+entry:

+ %0 = bitcast %struct.SmallStruct* %s to i8*

+ tail call void @consumestruct(i8* %0, i32 80) optsize

+ ret void

+}

+

+define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize {

+; CHECK: f4

+; CHECK: bl _consumestruct

+entry:

+ %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0

+ %0 = bitcast i32* %addr to i8*

+ tail call void @consumestruct(i8* %0, i32 80) optsize

+ ret void

+}

+

+; We can do tail call here since s is in the incoming argument area.

+define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize {

+; CHECK: f5

+; CHECK: b _consumestruct

+entry:

+ %0 = bitcast %struct.SmallStruct* %s to i8*

+ tail call void @consumestruct(i8* %0, i32 80) optsize

+ ret void

+}

+

+define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize {

+; CHECK: f6

+; CHECK: b _consumestruct

+entry:

+ %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0

+ %0 = bitcast i32* %addr to i8*

+ tail call void @consumestruct(i8* %0, i32 80) optsize

+ ret void

+}

+

+declare void @consumestruct(i8* nocapture %structp, i32 %structsize) nounwind

+

+; If the sub/rsb instruction is predicated, we can't use the flags.

+; <rdar://problem/12263428>

+; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s

+; CHECK: bc_raise

+; CHECK: rsbeq

+; CHECK: cmp

+define i32 @bc_raise() nounwind ssp {

+entry:

+ %val.2.i = select i1 undef, i32 0, i32 undef

+ %sub.i = sub nsw i32 0, %val.2.i

+ %retval.0.i = select i1 undef, i32 %val.2.i, i32 %sub.i

+ %cmp1 = icmp eq i32 %retval.0.i, 0

+ br i1 %cmp1, label %land.lhs.true, label %if.end11

+

+land.lhs.true: ; preds = %num2long.exit

+ ret i32 17

+

+if.end11: ; preds = %num2long.exit

+ ret i32 23

+}

+; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s

+; %vreg6:ssub_1<def> = ...

+; CHECK: vmov d0, r0, r0

+define void @t2() nounwind {

+entry:

+; INSTR: t2:

+; INSTR: trap

+

+; FUNC: t2:

+; FUNC: bl __trap

+ call void @llvm.debugtrap()

+ unreachable

+}

+

+declare void @llvm.debugtrap() nounwind

+; CHECK: vld1.32

+; CHECK-NEXT: vst1.32

+; CHECK-NEXT: vst1.32

+; CHECK-NEXT: vst1.32

+ %0 = load <4 x float>* undef, align 4

+ store <4 x float> zeroinitializer, <4 x float>* undef, align 4

+ store <4 x float> %0, <4 x float>* undef, align 4

+ store <4 x float> %1, <4 x float>* undef, align 4

+; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon -arm-strict-align -pre-RA-sched=source | FileCheck %s -check-prefix=EXPANDED

+

+define void @byte_word_ops(i32* %a, i32* %b) nounwind {

+entry:

+; EXPANDED: byte_word_ops:

+; EXPANDED: ldrb

+; EXPANDED: strb

+

+; UNALIGNED: byte_word_ops:

+; UNALIGNED-NOT: ldrb

+; UNALIGNED: ldr

+; UNALIGNED-NOT: strb

+; UNALIGNED: str

+ %tmp = load i32* %a, align 1

+ store i32 %tmp, i32* %b, align 1

+ ret void

+}

+;RUN: llc < %s -march=arm -mattr=+v7 -mattr=+neon | FileCheck %s

+

+;ALIGN = 1

+;SIZE = 64

+;TYPE = <8 x i8>

+define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v8i8_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <8 x i8>*

+ %vo = bitcast i8* %po to <8 x i8>*

+;CHECK: vld1.8

+ %v1 = load <8 x i8>* %vi, align 1

+;CHECK: vst1.8

+ store <8 x i8> %v1, <8 x i8>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 64

+;TYPE = <4 x i16>

+define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v4i16_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x i16>*

+ %vo = bitcast i8* %po to <4 x i16>*

+;CHECK: vld1.8

+ %v1 = load <4 x i16>* %vi, align 1

+;CHECK: vst1.8

+ store <4 x i16> %v1, <4 x i16>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 64

+;TYPE = <2 x i32>

+define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v2i32_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x i32>*

+ %vo = bitcast i8* %po to <2 x i32>*

+;CHECK: vld1.8

+ %v1 = load <2 x i32>* %vi, align 1

+;CHECK: vst1.8

+ store <2 x i32> %v1, <2 x i32>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 64

+;TYPE = <2 x float>

+define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v2f32_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x float>*

+ %vo = bitcast i8* %po to <2 x float>*

+;CHECK: vld1.8

+ %v1 = load <2 x float>* %vi, align 1

+;CHECK: vst1.8

+ store <2 x float> %v1, <2 x float>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 128

+;TYPE = <16 x i8>

+define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v16i8_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <16 x i8>*

+ %vo = bitcast i8* %po to <16 x i8>*

+;CHECK: vld1.8

+ %v1 = load <16 x i8>* %vi, align 1

+;CHECK: vst1.8

+ store <16 x i8> %v1, <16 x i8>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 128

+;TYPE = <8 x i16>

+define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v8i16_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <8 x i16>*

+ %vo = bitcast i8* %po to <8 x i16>*

+;CHECK: vld1.8

+ %v1 = load <8 x i16>* %vi, align 1

+;CHECK: vst1.8

+ store <8 x i16> %v1, <8 x i16>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 128

+;TYPE = <4 x i32>

+define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v4i32_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x i32>*

+ %vo = bitcast i8* %po to <4 x i32>*

+;CHECK: vld1.8

+ %v1 = load <4 x i32>* %vi, align 1

+;CHECK: vst1.8

+ store <4 x i32> %v1, <4 x i32>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 128

+;TYPE = <2 x i64>

+define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v2i64_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x i64>*

+ %vo = bitcast i8* %po to <2 x i64>*

+;CHECK: vld1.8

+ %v1 = load <2 x i64>* %vi, align 1

+;CHECK: vst1.8

+ store <2 x i64> %v1, <2 x i64>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 1

+;SIZE = 128

+;TYPE = <4 x float>

+define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v4f32_1:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x float>*

+ %vo = bitcast i8* %po to <4 x float>*

+;CHECK: vld1.8

+ %v1 = load <4 x float>* %vi, align 1

+;CHECK: vst1.8

+ store <4 x float> %v1, <4 x float>* %vo, align 1

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 64

+;TYPE = <8 x i8>

+define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v8i8_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <8 x i8>*

+ %vo = bitcast i8* %po to <8 x i8>*

+;CHECK: vld1.16

+ %v1 = load <8 x i8>* %vi, align 2

+;CHECK: vst1.16

+ store <8 x i8> %v1, <8 x i8>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 64

+;TYPE = <4 x i16>

+define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v4i16_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x i16>*

+ %vo = bitcast i8* %po to <4 x i16>*

+;CHECK: vld1.16

+ %v1 = load <4 x i16>* %vi, align 2

+;CHECK: vst1.16

+ store <4 x i16> %v1, <4 x i16>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 64

+;TYPE = <2 x i32>

+define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v2i32_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x i32>*

+ %vo = bitcast i8* %po to <2 x i32>*

+;CHECK: vld1.16

+ %v1 = load <2 x i32>* %vi, align 2

+;CHECK: vst1.16

+ store <2 x i32> %v1, <2 x i32>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 64

+;TYPE = <2 x float>

+define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v2f32_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x float>*

+ %vo = bitcast i8* %po to <2 x float>*

+;CHECK: vld1.16

+ %v1 = load <2 x float>* %vi, align 2

+;CHECK: vst1.16

+ store <2 x float> %v1, <2 x float>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 128

+;TYPE = <16 x i8>

+define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v16i8_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <16 x i8>*

+ %vo = bitcast i8* %po to <16 x i8>*

+;CHECK: vld1.16

+ %v1 = load <16 x i8>* %vi, align 2

+;CHECK: vst1.16

+ store <16 x i8> %v1, <16 x i8>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 128

+;TYPE = <8 x i16>

+define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v8i16_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <8 x i16>*

+ %vo = bitcast i8* %po to <8 x i16>*

+;CHECK: vld1.16

+ %v1 = load <8 x i16>* %vi, align 2

+;CHECK: vst1.16

+ store <8 x i16> %v1, <8 x i16>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 128

+;TYPE = <4 x i32>

+define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v4i32_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x i32>*

+ %vo = bitcast i8* %po to <4 x i32>*

+;CHECK: vld1.16

+ %v1 = load <4 x i32>* %vi, align 2

+;CHECK: vst1.16

+ store <4 x i32> %v1, <4 x i32>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 128

+;TYPE = <2 x i64>

+define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v2i64_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x i64>*

+ %vo = bitcast i8* %po to <2 x i64>*

+;CHECK: vld1.16

+ %v1 = load <2 x i64>* %vi, align 2

+;CHECK: vst1.16

+ store <2 x i64> %v1, <2 x i64>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 2

+;SIZE = 128

+;TYPE = <4 x float>

+define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v4f32_2:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x float>*

+ %vo = bitcast i8* %po to <4 x float>*

+;CHECK: vld1.16

+ %v1 = load <4 x float>* %vi, align 2

+;CHECK: vst1.16

+ store <4 x float> %v1, <4 x float>* %vo, align 2

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 64

+;TYPE = <8 x i8>

+define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v8i8_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <8 x i8>*

+ %vo = bitcast i8* %po to <8 x i8>*

+;CHECK: vldr

+ %v1 = load <8 x i8>* %vi, align 4

+;CHECK: vstr

+ store <8 x i8> %v1, <8 x i8>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 64

+;TYPE = <4 x i16>

+define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v4i16_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x i16>*

+ %vo = bitcast i8* %po to <4 x i16>*

+;CHECK: vldr

+ %v1 = load <4 x i16>* %vi, align 4

+;CHECK: vstr

+ store <4 x i16> %v1, <4 x i16>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 64

+;TYPE = <2 x i32>

+define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v2i32_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x i32>*

+ %vo = bitcast i8* %po to <2 x i32>*

+;CHECK: vldr

+ %v1 = load <2 x i32>* %vi, align 4

+;CHECK: vstr

+ store <2 x i32> %v1, <2 x i32>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 64

+;TYPE = <2 x float>

+define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v64_v2f32_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x float>*

+ %vo = bitcast i8* %po to <2 x float>*

+;CHECK: vldr

+ %v1 = load <2 x float>* %vi, align 4

+;CHECK: vstr

+ store <2 x float> %v1, <2 x float>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 128

+;TYPE = <16 x i8>

+define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v16i8_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <16 x i8>*

+ %vo = bitcast i8* %po to <16 x i8>*

+;CHECK: vld1.32

+ %v1 = load <16 x i8>* %vi, align 4

+;CHECK: vst1.32

+ store <16 x i8> %v1, <16 x i8>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 128

+;TYPE = <8 x i16>

+define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v8i16_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <8 x i16>*

+ %vo = bitcast i8* %po to <8 x i16>*

+;CHECK: vld1.32

+ %v1 = load <8 x i16>* %vi, align 4

+;CHECK: vst1.32

+ store <8 x i16> %v1, <8 x i16>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 128

+;TYPE = <4 x i32>

+define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v4i32_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x i32>*

+ %vo = bitcast i8* %po to <4 x i32>*

+;CHECK: vld1.32

+ %v1 = load <4 x i32>* %vi, align 4

+;CHECK: vst1.32

+ store <4 x i32> %v1, <4 x i32>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 128

+;TYPE = <2 x i64>

+define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v2i64_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <2 x i64>*

+ %vo = bitcast i8* %po to <2 x i64>*

+;CHECK: vld1.32

+ %v1 = load <2 x i64>* %vi, align 4

+;CHECK: vst1.32

+ store <2 x i64> %v1, <2 x i64>* %vo, align 4

+ ret void

+}

+

+

+;ALIGN = 4

+;SIZE = 128

+;TYPE = <4 x float>

+define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {

+;CHECK: v128_v4f32_4:

+entry:

+ %po = getelementptr i8* %out, i32 0

+ %pi = getelementptr i8* %in, i32 0

+ %vi = bitcast i8* %pi to <4 x float>*

+ %vo = bitcast i8* %po to <4 x float>*

+;CHECK: vld1.32

+ %v1 = load <4 x float>* %vi, align 4

+;CHECK: vst1.32

+ store <4 x float> %v1, <4 x float>* %vo, align 4

+ ret void

+}

+

+; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s

+;CHECK: vld1.32

+;CHECK: vld1.32

+;CHECK: vld1.32

+;CHECK: vld1.32

+;CHECK: vld1.32

+;CHECK: vld1.32

+;CHECK: vld1.32

+;CHECK: vld1.32

+;CHECK: vld1.64

+; rdar://12471808

+

+

+define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {

+; CHECK: f1:

+; CHECK: vbsl

+ %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind

+ ret <8 x i8> %vbsl.i

+}

+

+define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {

+; CHECK: f2:

+; CHECK: vbsl

+ %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind

+ ret <4 x i16> %vbsl3.i

+}

+

+define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {

+; CHECK: f3:

+; CHECK: vbsl

+ %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind

+ ret <2 x i32> %vbsl3.i

+}

+

+define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {

+; CHECK: f4:

+; CHECK: vbsl

+ %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind

+ ret <2 x float> %vbsl4.i

+}

+

+define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {

+; CHECK: g1:

+; CHECK: vbsl

+ %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind

+ ret <16 x i8> %vbsl.i

+}

+

+define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {

+; CHECK: g2:

+; CHECK: vbsl

+ %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind

+ ret <8 x i16> %vbsl3.i

+}

+

+define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {

+; CHECK: g3:

+; CHECK: vbsl

+ %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind

+ ret <4 x i32> %vbsl3.i

+}

+

+define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {

+; CHECK: g4:

+; CHECK: vbsl

+ %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind

+ ret <4 x float> %vbsl4.i

+}

+

+define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {

+; CHECK: test_vbsl_s64:

+; CHECK: vbsl d

+ %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind

+ ret <1 x i64> %vbsl3.i

+}

+

+define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {

+; CHECK: test_vbsl_u64:

+; CHECK: vbsl d

+ %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind

+ ret <1 x i64> %vbsl3.i

+}

+

+define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {

+; CHECK: test_vbslq_s64:

+; CHECK: vbsl q

+ %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind

+ ret <2 x i64> %vbsl3.i

+}

+

+define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {

+; CHECK: test_vbslq_u64:

+; CHECK: vbsl q

+ %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind

+ ret <2 x i64> %vbsl3.i

+}

+

+declare <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone

+declare <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone

+declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone

+declare <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone

+declare <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone

+declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone

+declare <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone

+declare <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone

+declare <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone

+declare <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone

+

+define <4 x i32> @tdupi(i32 %x, i32 %y) {

+;CHECK: tdupi

+;CHECK: vdup.32

+ %1 = insertelement <4 x i32> undef, i32 %x, i32 0

+ %2 = insertelement <4 x i32> %1, i32 %x, i32 1

+ %3 = insertelement <4 x i32> %2, i32 %x, i32 2

+ %4 = insertelement <4 x i32> %3, i32 %y, i32 3

+ ret <4 x i32> %4

+}

+

+define <4 x float> @tdupf(float %x, float %y) {

+;CHECK: tdupf

+;CHECK: vdup.32

+ %1 = insertelement <4 x float> undef, float %x, i32 0

+ %2 = insertelement <4 x float> %1, float %x, i32 1

+ %3 = insertelement <4 x float> %2, float %x, i32 2

+ %4 = insertelement <4 x float> %3, float %y, i32 3

+ ret <4 x float> %4

+}

+

+; This test checks that when splatting an element from a vector into another,

+; the value isn't moved out to GPRs first.

+define <4 x i32> @tduplane(<4 x i32> %invec) {

+;CHECK: tduplane

+;CHECK-NOT: vmov {{.*}}, d16[1]

+;CHECK: vdup.32 {{.*}}, d16[1]

+ %in = extractelement <4 x i32> %invec, i32 1

+ %1 = insertelement <4 x i32> undef, i32 %in, i32 0

+ %2 = insertelement <4 x i32> %1, i32 %in, i32 1

+ %3 = insertelement <4 x i32> %2, i32 %in, i32 2

+ %4 = insertelement <4 x i32> %3, i32 255, i32 3

+ ret <4 x i32> %4

+}

+

+define <2 x float> @check_f32(<4 x float> %v) nounwind {

+;CHECK: check_f32:

+;CHECK: vdup.32 {{.*}}, d{{..}}[1]

+ %x = extractelement <4 x float> %v, i32 3

+ %1 = insertelement <2 x float> undef, float %x, i32 0

+ %2 = insertelement <2 x float> %1, float %x, i32 1

+ ret <2 x float> %2

+}

+

+define <2 x i32> @check_i32(<4 x i32> %v) nounwind {

+;CHECK: check_i32:

+;CHECK: vdup.32 {{.*}}, d{{..}}[1]

+ %x = extractelement <4 x i32> %v, i32 3

+ %1 = insertelement <2 x i32> undef, i32 %x, i32 0

+ %2 = insertelement <2 x i32> %1, i32 %x, i32 1

+ ret <2 x i32> %2

+}

+

+define <4 x i16> @check_i16(<8 x i16> %v) nounwind {

+;CHECK: check_i16:

+;CHECK: vdup.16 {{.*}}, d{{..}}[3]

+ %x = extractelement <8 x i16> %v, i32 3

+ %1 = insertelement <4 x i16> undef, i16 %x, i32 0

+ %2 = insertelement <4 x i16> %1, i16 %x, i32 1

+ ret <4 x i16> %2

+}

+

+define <8 x i8> @check_i8(<16 x i8> %v) nounwind {

+;CHECK: check_i8:

+;CHECK: vdup.8 {{.*}}, d{{..}}[3]

+ %x = extractelement <16 x i8> %v, i32 3

+ %1 = insertelement <8 x i8> undef, i8 %x, i32 0

+ %2 = insertelement <8 x i8> %1, i8 %x, i32 1

+ ret <8 x i8> %2

+}

+; CHECK: j:

+define <4 x i32> @j(<4 x i8>* %in) nounwind {

+ ; CHECK: vld1

+ ; CHECK: vmovl.u8

+ ; CHECK: vmovl.u16

+ ; CHECK-NOT: vand

+ %1 = load <4 x i8>* %in, align 4

+ %2 = zext <4 x i8> %1 to <4 x i32>

+ ret <4 x i32> %2

+}

+

+define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {

+;CHECK: test_vextq_undef_op2:

+;CHECK: vext

+entry:

+ %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>

+ ret <16 x i8> %tmp1

+}

+

+define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {

+;CHECK: test_vextd_undef_op2:

+;CHECK: vext

+entry:

+ %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>

+ ret <8 x i8> %tmp1

+}

+

+

+define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {

+;CHECK: test_vextq_undef_op2_undef:

+;CHECK: vext

+entry:

+ %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>

+ ret <16 x i8> %tmp1

+}

+

+define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {

+;CHECK: test_vextd_undef_op2_undef:

+;CHECK: vext

+entry:

+ %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>

+ ret <8 x i8> %tmp1

+}

+

+;CHECK: vmov.32 d{{.*}}[1], r1

+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s

+; Make sure that ARM backend with NEON handles vselect.

+

+define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {

+; CHECK: vcgt.s32 [[QR:q[0-9]+]], [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]

+; CHECK: vbsl [[QR]], [[Q1]], [[Q2]]

+ %cmpres = icmp sgt <4 x i32> %a, %b

+ %maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b

+ store <4 x i32> %maxres, <4 x i32>* %m

+ ret void

+}

+

+; CHECK-NEXT: bi

+; CHECK: bi

+; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s

+

+; Make sure we have the correct weight attached to each successor.

+define i32 @test2(i32 %x) nounwind uwtable readnone ssp {

+; CHECK: Machine code for function test2:

+entry:

+ %conv = sext i32 %x to i64

+ switch i64 %conv, label %return [

+ i64 0, label %sw.bb

+ i64 1, label %sw.bb

+ i64 4, label %sw.bb

+ i64 5, label %sw.bb1

+ ], !prof !0

+; CHECK: BB#0: derived from LLVM BB %entry

+; CHECK: Successors according to CFG: BB#2(64) BB#4(14)

+; CHECK: BB#4: derived from LLVM BB %entry

+; CHECK: Successors according to CFG: BB#1(10) BB#5(4)

+; CHECK: BB#5: derived from LLVM BB %entry

+; CHECK: Successors according to CFG: BB#1(4) BB#3(7)

+

+sw.bb:

+ br label %return

+

+sw.bb1:

+ br label %return

+

+return:

+ %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]

+ ret i32 %retval.0

+}

+

+!0 = metadata !{metadata !"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}

+; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s

+; CHECK: r5 = #6

+; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s

+; Test fix for PR-13709.

+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s

+; CHECK: foo

+; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)

+; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)

+

+; Convert the sequence

+; r17:16 = lsr(r11:10, #32)

+; .. = r16

+; into

+; r17:16 = lsr(r11:10, #32)

+; .. = r11

+; This makes the lsr instruction dead and it gets removed subsequently

+; by a dead code removal pass.

+

+%union.vect64 = type { i64 }

+%union.vect32 = type { i32 }

+

+define void @foo(%union.vect64* nocapture %sss_extracted_bit_rx_data_ptr,

+ %union.vect32* nocapture %s_even, %union.vect32* nocapture %s_odd,

+ i8* nocapture %scr_s_even_code_ptr, i8* nocapture %scr_s_odd_code_ptr)

+ nounwind {

+entry:

+ %scevgep = getelementptr %union.vect64* %sss_extracted_bit_rx_data_ptr, i32 1

+ %scevgep28 = getelementptr %union.vect32* %s_odd, i32 1

+ %scevgep32 = getelementptr %union.vect32* %s_even, i32 1

+ %scevgep36 = getelementptr i8* %scr_s_odd_code_ptr, i32 1

+ %scevgep39 = getelementptr i8* %scr_s_even_code_ptr, i32 1

+ br label %for.body

+

+for.body: ; preds = %for.body, %entry

+ %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]

+ %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]

+ %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]

+ %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]

+ %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]

+ %lsr.iv = phi %union.vect64* [ %scevgep26, %for.body ], [ %scevgep, %entry ]

+ %predicate_1.023 = phi i8 [ undef, %entry ], [ %10, %for.body ]

+ %predicate.022 = phi i8 [ undef, %entry ], [ %9, %for.body ]

+ %val.021 = phi i64 [ undef, %entry ], [ %srcval, %for.body ]

+ %lsr.iv3335 = bitcast %union.vect32* %lsr.iv33 to i32*

+ %lsr.iv2931 = bitcast %union.vect32* %lsr.iv29 to i32*

+ %lsr.iv27 = bitcast %union.vect64* %lsr.iv to i64*

+ %0 = tail call i64 @llvm.hexagon.A2.vsubhs(i64 0, i64 %val.021)

+ %conv3 = sext i8 %predicate.022 to i32

+ %1 = trunc i64 %val.021 to i32

+ %2 = trunc i64 %0 to i32

+ %3 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv3, i32 %1, i32 %2)

+ store i32 %3, i32* %lsr.iv3335, align 4, !tbaa !0

+ %conv8 = sext i8 %predicate_1.023 to i32

+ %4 = lshr i64 %val.021, 32

+ %5 = trunc i64 %4 to i32

+ %6 = lshr i64 %0, 32

+ %7 = trunc i64 %6 to i32

+ %8 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv8, i32 %5, i32 %7)

+ store i32 %8, i32* %lsr.iv2931, align 4, !tbaa !0

+ %srcval = load i64* %lsr.iv27, align 8

+ %9 = load i8* %lsr.iv40, align 1, !tbaa !1

+ %10 = load i8* %lsr.iv37, align 1, !tbaa !1

+ %lftr.wideiv = trunc i32 %lsr.iv42 to i8

+ %exitcond = icmp eq i8 %lftr.wideiv, 32

+ %scevgep26 = getelementptr %union.vect64* %lsr.iv, i32 1

+ %scevgep30 = getelementptr %union.vect32* %lsr.iv29, i32 1

+ %scevgep34 = getelementptr %union.vect32* %lsr.iv33, i32 1

+ %scevgep38 = getelementptr i8* %lsr.iv37, i32 1

+ %scevgep41 = getelementptr i8* %lsr.iv40, i32 1

+ %lsr.iv.next = add i32 %lsr.iv42, 1

+ br i1 %exitcond, label %for.end, label %for.body

+

+for.end: ; preds = %for.body

+ ret void

+}

+

+declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) nounwind readnone

+

+declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) nounwind readnone

+

+!0 = metadata !{metadata !"long", metadata !1}

+!1 = metadata !{metadata !"omnipotent char", metadata !2}

+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}

+; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s

+; RUN: llc -O0 -disable-fp-elim < %s | FileCheck %s

+

+target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"

+target triple = "msp430---elf"

+

+define void @fp() nounwind {

+entry:

+; CHECK: fp:

+; CHECK: push.w r4

+; CHECK: mov.w r1, r4

+; CHECK: sub.w #2, r1

+ %i = alloca i16, align 2

+; CHECK: mov.w #0, -2(r4)

+ store i16 0, i16* %i, align 2

+; CHECK: pop.w r4

+ ret void

+}

+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16

+

+@iiii = global i32 25, align 4

+@jjjj = global i32 35, align 4

+@kkkk = global i32 100, align 4

+@t = global i32 25, align 4

+@riii = common global i32 0, align 4

+@rjjj = common global i32 0, align 4

+@rkkk = common global i32 0, align 4

+

+define void @temp(i32 %foo) nounwind {

+entry:

+ %foo.addr = alloca i32, align 4

+ store i32 %foo, i32* %foo.addr, align 4

+ %0 = load i32* %foo.addr, align 4

+ store i32 %0, i32* @t, align 4

+ ret void

+}

+

+define void @test() nounwind {

+entry:

+; 16: .frame $16,24,$ra

+; 16: save $ra, $s0, $s1, 24

+; 16: move $16, $sp

+; 16: move ${{[0-9]+}}, $sp

+; 16: subu $[[REGISTER:[0-9]+]], ${{[0-9]+}}, ${{[0-9]+}}

+; 16: move $sp, $[[REGISTER]]

+ %sssi = alloca i32, align 4

+ %ip = alloca i32*, align 4

+ %sssj = alloca i32, align 4

+ %0 = load i32* @iiii, align 4

+ store i32 %0, i32* %sssi, align 4

+ %1 = load i32* @kkkk, align 4

+ %mul = mul nsw i32 %1, 100

+ %2 = alloca i8, i32 %mul

+ %3 = bitcast i8* %2 to i32*

+ store i32* %3, i32** %ip, align 4

+ %4 = load i32* @jjjj, align 4

+ store i32 %4, i32* %sssj, align 4

+ %5 = load i32* @jjjj, align 4

+ %6 = load i32* @iiii, align 4

+ %7 = load i32** %ip, align 4

+ %arrayidx = getelementptr inbounds i32* %7, i32 %6

+ store i32 %5, i32* %arrayidx, align 4

+ %8 = load i32* @kkkk, align 4

+ %9 = load i32* @jjjj, align 4

+ %10 = load i32** %ip, align 4

+ %arrayidx1 = getelementptr inbounds i32* %10, i32 %9

+ store i32 %8, i32* %arrayidx1, align 4

+ %11 = load i32* @iiii, align 4

+ %12 = load i32* @kkkk, align 4

+ %13 = load i32** %ip, align 4

+ %arrayidx2 = getelementptr inbounds i32* %13, i32 %12

+ store i32 %11, i32* %arrayidx2, align 4

+ %14 = load i32** %ip, align 4

+ %arrayidx3 = getelementptr inbounds i32* %14, i32 25

+ %15 = load i32* %arrayidx3, align 4

+ store i32 %15, i32* @riii, align 4

+ %16 = load i32** %ip, align 4

+ %arrayidx4 = getelementptr inbounds i32* %16, i32 35

+ %17 = load i32* %arrayidx4, align 4

+ store i32 %17, i32* @rjjj, align 4

+ %18 = load i32** %ip, align 4

+ %arrayidx5 = getelementptr inbounds i32* %18, i32 100

+ %19 = load i32* %arrayidx5, align 4

+ store i32 %19, i32* @rkkk, align 4

+ %20 = load i32* @t, align 4

+ %21 = load i32** %ip, align 4

+ %arrayidx6 = getelementptr inbounds i32* %21, i32 %20

+ %22 = load i32* %arrayidx6, align 4

+; 16: save 16

+ call void @temp(i32 %22)

+; 16: restore 16

+ ret void

+}

+; RUN: llc -march=mipsel --disable-machine-licm < %s | FileCheck %s

+; CHECK: and $[[R18:[0-9]+]], $[[R9]], $[[R6]]

+; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]

+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16

+

+@.str = private unnamed_addr constant [8 x i8] c"%d, %d\0A\00", align 1

+

+define i32 @foo(i32* %mem, i32 %val, i32 %c) nounwind {

+entry:

+ %0 = atomicrmw add i32* %mem, i32 %val seq_cst

+ %add = add nsw i32 %0, %c

+ ret i32 %add

+; 16: foo:

+; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})

+; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})

+}

+

+define i32 @main() nounwind {

+entry:

+ %x = alloca i32, align 4

+ store volatile i32 0, i32* %x, align 4

+ %0 = atomicrmw add i32* %x, i32 1 seq_cst

+ %add.i = add nsw i32 %0, 2

+ %1 = load volatile i32* %x, align 4

+ %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %add.i, i32 %1) nounwind

+ %2 = cmpxchg i32* %x, i32 1, i32 2 seq_cst

+ %3 = load volatile i32* %x, align 4

+ %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3) nounwind

+ %4 = atomicrmw xchg i32* %x, i32 1 seq_cst

+ %5 = load volatile i32* %x, align 4

+ %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind

+; 16: main:

+; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})

+; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})

+; 16: lw ${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})

+; 16: lw ${{[0-9]+}}, %call16(__sync_lock_test_and_set_4)(${{[0-9]+}})

+

+ ret i32 0

+}

+

+declare i32 @printf(i8* nocapture, ...) nounwind

+

+

+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16

+

+@i = global i32 5, align 4

+@j = global i32 10, align 4

+@result = global i32 0, align 4

+

+define void @test() nounwind {

+entry:

+ %0 = load i32* @i, align 4

+ %1 = load i32* @j, align 4

+ %cmp = icmp eq i32 %0, %1

+; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}

+; 16: bteqz $[[LABEL:[0-9A-Ba-b_]+]]

+; 16: $[[LABEL]]:

+ br i1 %cmp, label %if.end, label %if.then

+

+if.then: ; preds = %entry

+ store i32 1, i32* @result, align 4

+ br label %if.end

+

+if.end: ; preds = %entry, %if.then

+ ret void

+}

+

+

+

+

+

+

+

+

+

+

+