From 6de2c08bc400b4aca9fb46684e8bdb56eed9b09f Mon Sep 17 00:00:00 2001 From: dim Date: Sun, 2 Dec 2012 13:10:19 +0000 Subject: Vendor import of llvm release_32 branch r168974 (effectively, 3.2 RC2): http://llvm.org/svn/llvm-project/llvm/branches/release_32@168974 --- test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll | 4 +- test/CodeGen/ARM/2010-12-07-PEIBug.ll | 2 +- test/CodeGen/ARM/2011-06-16-TailCallByVal.ll | 5 + test/CodeGen/ARM/2011-10-26-memset-with-neon.ll | 4 +- test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll | 135 ++- test/CodeGen/ARM/2012-05-04-vmov.ll | 11 + test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll | 14 + test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll | 129 ++ test/CodeGen/ARM/2012-08-30-select.ll | 18 + test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll | 11 + .../ARM/2012-09-25-InlineAsmScalarToVectorConv.ll | 11 + .../ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll | 11 + test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll | 56 + test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll | 19 + test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll | 16 + .../ARM/2012-10-18-PR14099-ByvalFrameAddress.ll | 29 + test/CodeGen/ARM/a15-mla.ll | 12 + test/CodeGen/ARM/a15.ll | 6 + test/CodeGen/ARM/atomic-op.ll | 10 + test/CodeGen/ARM/atomicrmw_minmax.ll | 21 + test/CodeGen/ARM/avoid-cpsr-rmw.ll | 1 + test/CodeGen/ARM/call-noret-minsize.ll | 27 + test/CodeGen/ARM/call-noret.ll | 31 + test/CodeGen/ARM/carry.ll | 13 + test/CodeGen/ARM/coalesce-subregs.ll | 294 ++++- test/CodeGen/ARM/constants.ll | 12 +- test/CodeGen/ARM/crash-shufflevector.ll | 10 + test/CodeGen/ARM/darwin-section-order.ll | 21 + test/CodeGen/ARM/deps-fix.ll | 22 + test/CodeGen/ARM/div.ll | 17 +- test/CodeGen/ARM/divmod.ll | 46 +- test/CodeGen/ARM/domain-conv-vmovs.ll | 100 ++ test/CodeGen/ARM/fabss.ll | 4 +- test/CodeGen/ARM/fadds.ll | 8 +- test/CodeGen/ARM/fast-isel-pic.ll | 61 + test/CodeGen/ARM/fast-isel.ll | 66 ++ test/CodeGen/ARM/fdivs.ll | 8 +- test/CodeGen/ARM/fmuls.ll | 8 +- test/CodeGen/ARM/fp-fast.ll | 60 + test/CodeGen/ARM/fp_convert.ll | 4 +- test/CodeGen/ARM/fsubs.ll | 6 +- test/CodeGen/ARM/ifcvt1.ll | 12 +- test/CodeGen/ARM/ifcvt12.ll | 15 + test/CodeGen/ARM/ifcvt5.ll | 12 +- test/CodeGen/ARM/indirectbr-2.ll | 46 + test/CodeGen/ARM/integer_insertelement.ll | 35 + test/CodeGen/ARM/ldr_post.ll | 1 + test/CodeGen/ARM/ldr_pre.ll | 1 + test/CodeGen/ARM/longMAC.ll | 44 + test/CodeGen/ARM/mls.ll | 12 + test/CodeGen/ARM/neon-fma.ll | 22 + test/CodeGen/ARM/neon_ld2.ll | 37 +- test/CodeGen/ARM/opt-shuff-tstore.ll | 4 +- test/CodeGen/ARM/reg_sequence.ll | 11 +- test/CodeGen/ARM/select.ll | 2 +- test/CodeGen/ARM/select_xform.ll | 65 +- test/CodeGen/ARM/struct_byval.ll | 44 + test/CodeGen/ARM/sub-cmp-peephole.ll | 21 + test/CodeGen/ARM/sub.ll | 2 +- test/CodeGen/ARM/subreg-remat.ll | 4 +- test/CodeGen/ARM/trap.ll | 12 + test/CodeGen/ARM/twoaddrinstr.ll | 16 +- test/CodeGen/ARM/unaligned_load_store.ll | 18 +- test/CodeGen/ARM/unaligned_load_store_vector.ll | 487 ++++++++ test/CodeGen/ARM/vbsl-constant.ll | 20 +- test/CodeGen/ARM/vbsl.ll | 97 ++ test/CodeGen/ARM/vdup.ll | 70 ++ test/CodeGen/ARM/vector-extend-narrow.ll | 11 + test/CodeGen/ARM/vext.ll | 33 + test/CodeGen/ARM/vget_lane.ll | 2 +- test/CodeGen/ARM/vselect_imax.ll | 12 + test/CodeGen/CellSPU/icmp16.ll | 4 +- test/CodeGen/Generic/MachineBranchProb.ll | 32 + test/CodeGen/Hexagon/args.ll | 4 +- test/CodeGen/Hexagon/newvaluestore.ll | 2 +- test/CodeGen/Hexagon/remove_lsr.ll | 80 ++ test/CodeGen/Hexagon/static.ll | 2 +- test/CodeGen/MSP430/fp.ll | 17 + test/CodeGen/Mips/alloca16.ll | 75 ++ test/CodeGen/Mips/atomic.ll | 5 +- test/CodeGen/Mips/atomicops.ll | 40 + test/CodeGen/Mips/brconeq.ll | 38 + test/CodeGen/Mips/brconeqk.ll | 22 + test/CodeGen/Mips/brconeqz.ll | 20 + test/CodeGen/Mips/brconge.ll | 37 + test/CodeGen/Mips/brcongt.ll | 25 + test/CodeGen/Mips/brconle.ll | 37 + test/CodeGen/Mips/brconlt.ll | 27 + test/CodeGen/Mips/brconne.ll | 26 + test/CodeGen/Mips/brconnek.ll | 25 + test/CodeGen/Mips/brconnez.ll | 24 + test/CodeGen/Mips/brdelayslot.ll | 34 +- test/CodeGen/Mips/brind.ll | 40 + test/CodeGen/Mips/check-noat.ll | 11 + test/CodeGen/Mips/div.ll | 18 + test/CodeGen/Mips/div_rem.ll | 21 + test/CodeGen/Mips/divu.ll | 18 + test/CodeGen/Mips/divu_remu.ll | 23 + test/CodeGen/Mips/dsp-r1.ll | 1241 ++++++++++++++++++++ test/CodeGen/Mips/dsp-r2.ll | 568 +++++++++ test/CodeGen/Mips/eh-dwarf-cfa.ll | 63 + test/CodeGen/Mips/helloworld.ll | 4 +- test/CodeGen/Mips/i32k.ll | 17 + test/CodeGen/Mips/init-array.ll | 14 + test/CodeGen/Mips/largeimm1.ll | 4 +- test/CodeGen/Mips/largeimmprinting.ll | 22 +- test/CodeGen/Mips/llcarry.ll | 51 + test/CodeGen/Mips/longbranch.ll | 10 +- test/CodeGen/Mips/mips64-sret.ll | 16 + test/CodeGen/Mips/misha.ll | 69 ++ test/CodeGen/Mips/mul.ll | 17 + test/CodeGen/Mips/mulll.ll | 21 + test/CodeGen/Mips/mulull.ll | 21 + test/CodeGen/Mips/null.ll | 2 +- test/CodeGen/Mips/o32_cc_byval.ll | 10 + test/CodeGen/Mips/rem.ll | 19 + test/CodeGen/Mips/remat-immed-load.ll | 51 + test/CodeGen/Mips/remu.ll | 18 + test/CodeGen/Mips/return-vector.ll | 244 ++++ test/CodeGen/Mips/selpat.ll | 350 ++++++ test/CodeGen/Mips/seteq.ll | 21 + test/CodeGen/Mips/seteqz.ll | 24 + test/CodeGen/Mips/setge.ll | 27 + test/CodeGen/Mips/setgek.ll | 18 + test/CodeGen/Mips/setle.ll | 26 + test/CodeGen/Mips/setlt.ll | 21 + test/CodeGen/Mips/setltk.ll | 20 + test/CodeGen/Mips/setne.ll | 20 + test/CodeGen/Mips/setuge.ll | 26 + test/CodeGen/Mips/setugt.ll | 21 + test/CodeGen/Mips/setule.ll | 26 + test/CodeGen/Mips/setult.ll | 21 + test/CodeGen/Mips/setultk.ll | 20 + test/CodeGen/Mips/small-section-reserve-gp.ll | 12 + test/CodeGen/Mips/stchar.ll | 90 ++ test/CodeGen/Mips/stldst.ll | 41 + test/CodeGen/Mips/tailcall.ll | 245 ++++ test/CodeGen/Mips/tls-alias.ll | 2 +- test/CodeGen/Mips/tls.ll | 12 +- test/CodeGen/Mips/tls16.ll | 13 + test/CodeGen/Mips/tls16_2.ll | 15 + test/CodeGen/Mips/uitofp.ll | 12 + test/CodeGen/Mips/ul1.ll | 15 + test/CodeGen/Mips/vector-load-store.ll | 27 + test/CodeGen/NVPTX/global-ordering.ll | 20 + test/CodeGen/NVPTX/param-align.ll | 25 + test/CodeGen/NVPTX/pr13291-i1-store.ll | 26 + test/CodeGen/NVPTX/ptx-version-30.ll | 6 + test/CodeGen/NVPTX/ptx-version-31.ll | 6 + test/CodeGen/NVPTX/sm-version-10.ll | 6 + test/CodeGen/NVPTX/sm-version-11.ll | 6 + test/CodeGen/NVPTX/sm-version-12.ll | 6 + test/CodeGen/NVPTX/sm-version-13.ll | 6 + test/CodeGen/NVPTX/sm-version-20.ll | 6 + test/CodeGen/NVPTX/sm-version-21.ll | 6 + test/CodeGen/NVPTX/sm-version-30.ll | 6 + test/CodeGen/NVPTX/sm-version-35.ll | 6 + test/CodeGen/PowerPC/2010-03-09-indirect-call.ll | 5 +- test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll | 27 + test/CodeGen/PowerPC/2012-10-11-dynalloc.ll | 18 + test/CodeGen/PowerPC/2012-10-12-bitcast.ll | 20 + test/CodeGen/PowerPC/asm-Zy.ll | 14 + test/CodeGen/PowerPC/big-endian-formal-args.ll | 4 +- test/CodeGen/PowerPC/bl8_elf_nop.ll | 16 - test/CodeGen/PowerPC/coalesce-ext.ll | 3 +- test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll | 26 + test/CodeGen/PowerPC/crsave.ll | 49 + test/CodeGen/PowerPC/emptystruct.ll | 51 + test/CodeGen/PowerPC/floatPSA.ll | 97 ++ test/CodeGen/PowerPC/fsl-e500mc.ll | 22 + test/CodeGen/PowerPC/fsl-e5500.ll | 22 + test/CodeGen/PowerPC/i64_fp_round.ll | 27 + test/CodeGen/PowerPC/inlineasm-copy.ll | 9 +- test/CodeGen/PowerPC/int-fp-conv-1.ll | 3 +- test/CodeGen/PowerPC/jaggedstructs.ll | 48 + test/CodeGen/PowerPC/misched.ll | 45 + test/CodeGen/PowerPC/novrsave.ll | 15 + test/CodeGen/PowerPC/ppc64-abi-extend.ll | 97 ++ test/CodeGen/PowerPC/ppc64-align-long-double.ll | 26 + test/CodeGen/PowerPC/ppc64-calls.ll | 63 + test/CodeGen/PowerPC/ppc64-ind-call.ll | 16 - test/CodeGen/PowerPC/ppc64-linux-func-size.ll | 1 + test/CodeGen/PowerPC/ppc64-toc.ll | 68 ++ test/CodeGen/PowerPC/ppc64-zext.ll | 11 + test/CodeGen/PowerPC/pr12757.ll | 14 + test/CodeGen/PowerPC/pr13641.ll | 11 + test/CodeGen/PowerPC/pr13891.ll | 27 + test/CodeGen/PowerPC/remat-imm.ll | 16 + test/CodeGen/PowerPC/structsinmem.ll | 227 ++++ test/CodeGen/PowerPC/structsinregs.ll | 213 ++++ test/CodeGen/PowerPC/varargs-struct-float.ll | 23 + test/CodeGen/PowerPC/vec_cmp.ll | 527 +++++++++ test/CodeGen/PowerPC/vec_conv.ll | 57 + test/CodeGen/PowerPC/vec_extload.ll | 155 +++ test/CodeGen/PowerPC/vec_sqrt.ll | 71 ++ test/CodeGen/PowerPC/vrspill.ll | 19 + test/CodeGen/SPARC/2011-01-11-CC.ll | 2 +- test/CodeGen/Thumb2/buildvector-crash.ll | 4 +- test/CodeGen/Thumb2/carry.ll | 13 + test/CodeGen/Thumb2/cortex-fp.ll | 6 +- test/CodeGen/Thumb2/div.ll | 10 + test/CodeGen/Thumb2/longMACt.ll | 44 + test/CodeGen/Thumb2/thumb2-mla.ll | 7 + test/CodeGen/Thumb2/thumb2-select_xform.ll | 4 +- test/CodeGen/Thumb2/thumb2-smla.ll | 4 + test/CodeGen/Thumb2/thumb2-uxtb.ll | 4 +- test/CodeGen/X86/2010-01-08-Atomic64Bug.ll | 19 +- test/CodeGen/X86/2012-01-18-vbitcast.ll | 4 +- test/CodeGen/X86/2012-03-15-build_vector_wl.ll | 2 +- test/CodeGen/X86/2012-04-26-sdglue.ll | 2 +- test/CodeGen/X86/2012-07-10-extload64.ll | 4 +- test/CodeGen/X86/2012-08-16-setcc.ll | 45 + test/CodeGen/X86/2012-08-28-UnsafeMathCrash.ll | 20 + test/CodeGen/X86/2012-09-13-dagco-fneg.ll | 21 + test/CodeGen/X86/2012-09-28-CGPBug.ll | 53 + test/CodeGen/X86/2012-10-02-DAGCycle.ll | 52 + test/CodeGen/X86/2012-10-03-DAGCycle.ll | 31 + test/CodeGen/X86/2012-10-18-crash-dagco.ll | 61 + test/CodeGen/X86/MergeConsecutiveStores.ll | 305 +++++ test/CodeGen/X86/StackColoring-dbg.ll | 30 + test/CodeGen/X86/StackColoring.ll | 410 +++++++ test/CodeGen/X86/add-of-carry.ll | 13 + test/CodeGen/X86/atom-bypass-slow-division.ll | 112 ++ test/CodeGen/X86/atom-shuf.ll | 9 + test/CodeGen/X86/atomic-minmax-i6432.ll | 67 ++ test/CodeGen/X86/atomic-pointer.ll | 22 + test/CodeGen/X86/atomic16.ll | 250 ++++ test/CodeGen/X86/atomic32.ll | 250 ++++ test/CodeGen/X86/atomic64.ll | 216 ++++ test/CodeGen/X86/atomic6432.ll | 208 ++++ test/CodeGen/X86/atomic8.ll | 250 ++++ test/CodeGen/X86/atomic_add.ll | 3 +- test/CodeGen/X86/atomic_op.ll | 11 +- test/CodeGen/X86/avx-basic.ll | 4 +- test/CodeGen/X86/avx-intel-ocl.ll | 107 ++ test/CodeGen/X86/avx-intrinsics-x86.ll | 52 +- test/CodeGen/X86/avx-shuffle.ll | 10 +- test/CodeGen/X86/avx-vextractf128.ll | 88 +- test/CodeGen/X86/avx2-shuffle.ll | 34 + test/CodeGen/X86/bitcast-i256.ll | 11 + test/CodeGen/X86/bool-simplify.ll | 18 +- test/CodeGen/X86/buildvec-insertvec.ll | 15 + test/CodeGen/X86/cmov-fp.ll | 451 +++++++ test/CodeGen/X86/crash.ll | 147 +++ test/CodeGen/X86/cvtv2f32.ll | 25 + test/CodeGen/X86/early-ifcvt-crash.ll | 32 + test/CodeGen/X86/early-ifcvt.ll | 77 +- test/CodeGen/X86/extract-concat.ll | 17 + test/CodeGen/X86/fast-cc-callee-pops.ll | 4 +- test/CodeGen/X86/fast-cc-merge-stack-adj.ll | 2 +- test/CodeGen/X86/fast-cc-pass-in-regs.ll | 4 +- test/CodeGen/X86/fast-isel-x86-64.ll | 21 +- test/CodeGen/X86/fma.ll | 16 +- test/CodeGen/X86/fma3-intrinsics.ll | 4 +- test/CodeGen/X86/fma4-intrinsics-x86_64.ll | 1 + test/CodeGen/X86/fma_patterns.ll | 103 +- test/CodeGen/X86/fold-load.ll | 4 +- test/CodeGen/X86/fp-fast.ll | 57 + test/CodeGen/X86/fp-load-trunc.ll | 61 + test/CodeGen/X86/fp-trunc.ll | 53 +- test/CodeGen/X86/handle-move.ll | 74 ++ test/CodeGen/X86/inline-asm-tied.ll | 9 + test/CodeGen/X86/inline-asm.ll | 7 + test/CodeGen/X86/inlineasm-sched-bug.ll | 13 + test/CodeGen/X86/jump_sign.ll | 56 +- test/CodeGen/X86/misched-balance.ll | 230 ++++ test/CodeGen/X86/misched-ilp.ll | 25 + test/CodeGen/X86/misched-new.ll | 28 +- test/CodeGen/X86/mmx-builtins.ll | 14 + test/CodeGen/X86/ms-inline-asm.ll | 63 + test/CodeGen/X86/mulx32.ll | 22 + test/CodeGen/X86/mulx64.ll | 22 + test/CodeGen/X86/phys_subreg_coalesce-3.ll | 6 +- test/CodeGen/X86/pic_jumptable.ll | 12 + test/CodeGen/X86/pmovext.ll | 22 + test/CodeGen/X86/pointer-vector.ll | 5 +- test/CodeGen/X86/pr11334.ll | 8 + test/CodeGen/X86/pr11985.ll | 19 + test/CodeGen/X86/pr12312.ll | 155 +++ test/CodeGen/X86/pr12359.ll | 10 + test/CodeGen/X86/pr13458.ll | 14 + test/CodeGen/X86/pr13859.ll | 28 + test/CodeGen/X86/pr13899.ll | 58 + test/CodeGen/X86/pr14088.ll | 25 + test/CodeGen/X86/pr14090.ll | 76 ++ test/CodeGen/X86/pr14098.ll | 23 + test/CodeGen/X86/pr14161.ll | 38 + test/CodeGen/X86/pr14204.ll | 15 + test/CodeGen/X86/pr14314.ll | 13 + test/CodeGen/X86/pr14333.ll | 12 + test/CodeGen/X86/pr5145.ll | 35 + test/CodeGen/X86/promote.ll | 2 +- test/CodeGen/X86/ptr-rotate.ll | 2 +- test/CodeGen/X86/red-zone2.ll | 7 +- test/CodeGen/X86/rot32.ll | 29 +- test/CodeGen/X86/rot64.ll | 31 +- test/CodeGen/X86/rotate2.ll | 2 +- test/CodeGen/X86/rtm.ll | 30 + test/CodeGen/X86/select.ll | 13 + test/CodeGen/X86/select_const.ll | 16 + test/CodeGen/X86/shift-bmi2.ll | 178 +++ test/CodeGen/X86/sincos.ll | 13 + test/CodeGen/X86/sjlj.ll | 60 + test/CodeGen/X86/smul-with-overflow.ll | 14 + test/CodeGen/X86/sse-intel-ocl.ll | 93 ++ test/CodeGen/X86/sse-minmax.ll | 80 +- test/CodeGen/X86/sse_partial_update.ll | 36 + test/CodeGen/X86/tailcall-64.ll | 67 +- test/CodeGen/X86/targetLoweringGeneric.ll | 2 +- test/CodeGen/X86/tls-pic.ll | 12 +- test/CodeGen/X86/trunc-ext-ld-st.ll | 15 +- test/CodeGen/X86/vec_compare-2.ll | 3 +- test/CodeGen/X86/vec_fabs.ll | 38 + test/CodeGen/X86/vec_floor.ll | 38 + test/CodeGen/X86/vec_fpext.ll | 32 +- test/CodeGen/X86/vec_shuffle-26.ll | 45 +- test/CodeGen/X86/vec_shuffle-30.ll | 14 +- test/CodeGen/X86/widen_cast-1.ll | 2 +- test/CodeGen/X86/widen_load-1.ll | 13 +- test/CodeGen/X86/widen_load-2.ll | 2 +- test/CodeGen/X86/xmulo.ll | 50 + 321 files changed, 14718 insertions(+), 463 deletions(-) create mode 100644 test/CodeGen/ARM/2012-05-04-vmov.ll create mode 100644 test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll create mode 100644 test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll create mode 100644 test/CodeGen/ARM/2012-08-30-select.ll create mode 100644 test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll create mode 100644 test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll create mode 100644 test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll create mode 100644 test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll create mode 100644 test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll create mode 100644 test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll create mode 100644 test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll create mode 100644 test/CodeGen/ARM/a15-mla.ll create mode 100644 test/CodeGen/ARM/a15.ll create mode 100644 test/CodeGen/ARM/atomicrmw_minmax.ll create mode 100644 test/CodeGen/ARM/call-noret-minsize.ll create mode 100644 test/CodeGen/ARM/call-noret.ll create mode 100644 test/CodeGen/ARM/crash-shufflevector.ll create mode 100644 test/CodeGen/ARM/darwin-section-order.ll create mode 100644 test/CodeGen/ARM/deps-fix.ll create mode 100644 test/CodeGen/ARM/domain-conv-vmovs.ll create mode 100644 test/CodeGen/ARM/fast-isel-pic.ll create mode 100644 test/CodeGen/ARM/fp-fast.ll create mode 100644 test/CodeGen/ARM/ifcvt12.ll create mode 100644 test/CodeGen/ARM/indirectbr-2.ll create mode 100644 test/CodeGen/ARM/integer_insertelement.ll create mode 100644 test/CodeGen/ARM/longMAC.ll create mode 100644 test/CodeGen/ARM/neon-fma.ll create mode 100644 test/CodeGen/ARM/unaligned_load_store_vector.ll create mode 100644 test/CodeGen/ARM/vselect_imax.ll create mode 100644 test/CodeGen/Generic/MachineBranchProb.ll create mode 100644 test/CodeGen/Hexagon/remove_lsr.ll create mode 100644 test/CodeGen/MSP430/fp.ll create mode 100644 test/CodeGen/Mips/alloca16.ll create mode 100644 test/CodeGen/Mips/atomicops.ll create mode 100644 test/CodeGen/Mips/brconeq.ll create mode 100644 test/CodeGen/Mips/brconeqk.ll create mode 100644 test/CodeGen/Mips/brconeqz.ll create mode 100644 test/CodeGen/Mips/brconge.ll create mode 100644 test/CodeGen/Mips/brcongt.ll create mode 100644 test/CodeGen/Mips/brconle.ll create mode 100644 test/CodeGen/Mips/brconlt.ll create mode 100644 test/CodeGen/Mips/brconne.ll create mode 100644 test/CodeGen/Mips/brconnek.ll create mode 100644 test/CodeGen/Mips/brconnez.ll create mode 100644 test/CodeGen/Mips/brind.ll create mode 100644 test/CodeGen/Mips/check-noat.ll create mode 100644 test/CodeGen/Mips/div.ll create mode 100644 test/CodeGen/Mips/div_rem.ll create mode 100644 test/CodeGen/Mips/divu.ll create mode 100644 test/CodeGen/Mips/divu_remu.ll create mode 100644 test/CodeGen/Mips/dsp-r1.ll create mode 100644 test/CodeGen/Mips/dsp-r2.ll create mode 100644 test/CodeGen/Mips/eh-dwarf-cfa.ll create mode 100644 test/CodeGen/Mips/i32k.ll create mode 100644 test/CodeGen/Mips/init-array.ll create mode 100644 test/CodeGen/Mips/llcarry.ll create mode 100644 test/CodeGen/Mips/mips64-sret.ll create mode 100644 test/CodeGen/Mips/misha.ll create mode 100644 test/CodeGen/Mips/mul.ll create mode 100644 test/CodeGen/Mips/mulll.ll create mode 100644 test/CodeGen/Mips/mulull.ll create mode 100644 test/CodeGen/Mips/rem.ll create mode 100644 test/CodeGen/Mips/remat-immed-load.ll create mode 100644 test/CodeGen/Mips/remu.ll create mode 100644 test/CodeGen/Mips/return-vector.ll create mode 100644 test/CodeGen/Mips/selpat.ll create mode 100644 test/CodeGen/Mips/seteq.ll create mode 100644 test/CodeGen/Mips/seteqz.ll create mode 100644 test/CodeGen/Mips/setge.ll create mode 100644 test/CodeGen/Mips/setgek.ll create mode 100644 test/CodeGen/Mips/setle.ll create mode 100644 test/CodeGen/Mips/setlt.ll create mode 100644 test/CodeGen/Mips/setltk.ll create mode 100644 test/CodeGen/Mips/setne.ll create mode 100644 test/CodeGen/Mips/setuge.ll create mode 100644 test/CodeGen/Mips/setugt.ll create mode 100644 test/CodeGen/Mips/setule.ll create mode 100644 test/CodeGen/Mips/setult.ll create mode 100644 test/CodeGen/Mips/setultk.ll create mode 100644 test/CodeGen/Mips/small-section-reserve-gp.ll create mode 100644 test/CodeGen/Mips/stchar.ll create mode 100644 test/CodeGen/Mips/stldst.ll create mode 100644 test/CodeGen/Mips/tailcall.ll create mode 100644 test/CodeGen/Mips/tls16.ll create mode 100644 test/CodeGen/Mips/tls16_2.ll create mode 100644 test/CodeGen/Mips/uitofp.ll create mode 100644 test/CodeGen/Mips/ul1.ll create mode 100644 test/CodeGen/Mips/vector-load-store.ll create mode 100644 test/CodeGen/NVPTX/global-ordering.ll create mode 100644 test/CodeGen/NVPTX/param-align.ll create mode 100644 test/CodeGen/NVPTX/pr13291-i1-store.ll create mode 100644 test/CodeGen/NVPTX/ptx-version-30.ll create mode 100644 test/CodeGen/NVPTX/ptx-version-31.ll create mode 100644 test/CodeGen/NVPTX/sm-version-10.ll create mode 100644 test/CodeGen/NVPTX/sm-version-11.ll create mode 100644 test/CodeGen/NVPTX/sm-version-12.ll create mode 100644 test/CodeGen/NVPTX/sm-version-13.ll create mode 100644 test/CodeGen/NVPTX/sm-version-20.ll create mode 100644 test/CodeGen/NVPTX/sm-version-21.ll create mode 100644 test/CodeGen/NVPTX/sm-version-30.ll create mode 100644 test/CodeGen/NVPTX/sm-version-35.ll create mode 100644 test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll create mode 100644 test/CodeGen/PowerPC/2012-10-11-dynalloc.ll create mode 100644 test/CodeGen/PowerPC/2012-10-12-bitcast.ll create mode 100644 test/CodeGen/PowerPC/asm-Zy.ll delete mode 100644 test/CodeGen/PowerPC/bl8_elf_nop.ll create mode 100644 test/CodeGen/PowerPC/cr1eq-no-extra-moves.ll create mode 100644 test/CodeGen/PowerPC/crsave.ll create mode 100644 test/CodeGen/PowerPC/emptystruct.ll create mode 100644 test/CodeGen/PowerPC/floatPSA.ll create mode 100644 test/CodeGen/PowerPC/fsl-e500mc.ll create mode 100644 test/CodeGen/PowerPC/fsl-e5500.ll create mode 100644 test/CodeGen/PowerPC/i64_fp_round.ll create mode 100644 test/CodeGen/PowerPC/jaggedstructs.ll create mode 100644 test/CodeGen/PowerPC/misched.ll create mode 100644 test/CodeGen/PowerPC/novrsave.ll create mode 100644 test/CodeGen/PowerPC/ppc64-abi-extend.ll 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test/CodeGen/X86/2012-08-16-setcc.ll create mode 100644 test/CodeGen/X86/2012-08-28-UnsafeMathCrash.ll create mode 100644 test/CodeGen/X86/2012-09-13-dagco-fneg.ll create mode 100644 test/CodeGen/X86/2012-09-28-CGPBug.ll create mode 100644 test/CodeGen/X86/2012-10-02-DAGCycle.ll create mode 100644 test/CodeGen/X86/2012-10-03-DAGCycle.ll create mode 100644 test/CodeGen/X86/2012-10-18-crash-dagco.ll create mode 100644 test/CodeGen/X86/MergeConsecutiveStores.ll create mode 100644 test/CodeGen/X86/StackColoring-dbg.ll create mode 100644 test/CodeGen/X86/StackColoring.ll create mode 100644 test/CodeGen/X86/atom-bypass-slow-division.ll create mode 100644 test/CodeGen/X86/atom-shuf.ll create mode 100644 test/CodeGen/X86/atomic-minmax-i6432.ll create mode 100644 test/CodeGen/X86/atomic-pointer.ll create mode 100644 test/CodeGen/X86/atomic16.ll create mode 100644 test/CodeGen/X86/atomic32.ll create mode 100644 test/CodeGen/X86/atomic64.ll create mode 100644 test/CodeGen/X86/atomic6432.ll create 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100644 test/CodeGen/X86/xmulo.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll index 99db637..36d1575 100644 --- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll +++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll @@ -13,12 +13,12 @@ ; BASIC-NEXT: 0x00000000 ; BASIC-NEXT: 0x00000000 ; BASIC-NEXT: 0x0000003c -; BASIC-NEXT: 0x00000020 +; BASIC-NEXT: 0x00000022 ; BASIC-NEXT: 0x00000000 ; BASIC-NEXT: 0x00000000 ; BASIC-NEXT: 0x00000001 ; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: '411f0000 00616561 62690001 15000000 06020801 09011401 15011703 18011901' +; BASIC-NEXT: '41210000 00616561 62690001 17000000 060a0741 08010902 14011501 17031801 1901' ; CORTEXA8: .ARM.attributes ; CORTEXA8-NEXT: 0x70000003 diff --git a/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/test/CodeGen/ARM/2010-12-07-PEIBug.ll index 770ad44..4879f4e 100644 --- a/test/CodeGen/ARM/2010-12-07-PEIBug.ll +++ b/test/CodeGen/ARM/2010-12-07-PEIBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s ; rdar://8728956 define hidden void @foo() nounwind ssp { diff --git a/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll index 3e78c46..101a913 100644 --- a/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll +++ b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll @@ -1,4 +1,9 @@ ; RUN: llc < %s -arm-tail-calls=1 | FileCheck %s + +; tail call inside a function where byval argument is splitted between +; registers and stack is currently unsupported. +; XFAIL: * + target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-ios" diff --git a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll index 42b1491..6e0ef96 100644 --- a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll +++ b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll @@ -9,8 +9,8 @@ entry: } ; Trigger multiple NEON stores. -; CHECK: vstmia -; CHECK-NEXT: vstmia +; CHECK: vst1.64 +; CHECK-NEXT: vst1.64 define void @f_0_40(i8* nocapture %c) nounwind optsize { entry: call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 40, i32 16, i1 false) diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index 89c01d5..f9ede74 100644 --- a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -8,12 +8,12 @@ define void @test_sqrt(<4 x float>* %X) nounwind { ; CHECK: movw r1, :lower16:{{.*}} ; CHECK: movt r1, :upper16:{{.*}} -; CHECK: vldmia r1 +; CHECK: vld1.64 {{.*}}, [r1, :128] ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 {{.*}} L.entry: %0 = load <4 x float>* @A, align 16 @@ -31,21 +31,21 @@ define void @test_cos(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}cosf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}cosf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}cosf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}cosf -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: %0 = load <4 x float>* @A, align 16 @@ -62,21 +62,21 @@ define void @test_exp(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}expf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}expf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}expf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}expf -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: %0 = load <4 x float>* @A, align 16 @@ -93,21 +93,21 @@ define void @test_exp2(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}exp2f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}exp2f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}exp2f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}exp2f -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: %0 = load <4 x float>* @A, align 16 @@ -124,21 +124,21 @@ define void @test_log10(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log10f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log10f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log10f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log10f -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: %0 = load <4 x float>* @A, align 16 @@ -155,21 +155,21 @@ define void @test_log(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}logf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}logf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}logf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}logf -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: %0 = load <4 x float>* @A, align 16 @@ -186,21 +186,21 @@ define void @test_log2(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log2f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log2f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log2f -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}log2f -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: %0 = load <4 x float>* @A, align 16 @@ -218,21 +218,21 @@ define void @test_pow(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}powf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}powf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}powf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}powf -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: @@ -252,10 +252,10 @@ define void @test_powi(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia [[reg0]], {{.*}} +; CHECK: vld1.64 {{.*}}, :128 ; CHECK: vmul.f32 {{.*}} -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: @@ -275,21 +275,21 @@ define void @test_sin(<4 x float>* %X) nounwind { ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} -; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} +; CHECK: vld1.64 -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}sinf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}sinf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}sinf -; CHECK: {{[mov|vmov.32]}} r0, +; CHECK: {{v?mov(.32)?}} r0, ; CHECK: bl {{.*}}sinf -; CHECK: vstmia {{.*}} +; CHECK: vst1.64 L.entry: %0 = load <4 x float>* @A, align 16 @@ -300,3 +300,34 @@ L.entry: declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly +define void @test_floor(<4 x float>* %X) nounwind { + +; CHECK: test_floor: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vld1.64 + +; CHECK: {{v?mov(.32)?}} r0, +; CHECK: bl {{.*}}floorf + +; CHECK: {{v?mov(.32)?}} r0, +; CHECK: bl {{.*}}floorf + +; CHECK: {{v?mov(.32)?}} r0, +; CHECK: bl {{.*}}floorf + +; CHECK: {{v?mov(.32)?}} r0, +; CHECK: bl {{.*}}floorf + +; CHECK: vst1.64 + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readonly + diff --git a/test/CodeGen/ARM/2012-05-04-vmov.ll b/test/CodeGen/ARM/2012-05-04-vmov.ll new file mode 100644 index 0000000..d52ef2c --- /dev/null +++ b/test/CodeGen/ARM/2012-05-04-vmov.ll @@ -0,0 +1,11 @@ +; RUN: llc -O1 -march=arm -mcpu=cortex-a9 < %s | FileCheck -check-prefix=A9-CHECK %s +; RUN: llc -O1 -march=arm -mcpu=swift < %s | FileCheck -check-prefix=SWIFT-CHECK %s +; Check that swift doesn't use vmov.32. . + +define <2 x i32> @testuvec(<2 x i32> %A, <2 x i32> %B) nounwind { +entry: + %div = udiv <2 x i32> %A, %B + ret <2 x i32> %div +; A9-CHECK: vmov.32 +; SWIFT-CHECK-NOT: vmov.32 +} diff --git a/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll b/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll new file mode 100644 index 0000000..dd67843 --- /dev/null +++ b/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=arm -mcpu=swift < %s | FileCheck %s +; + +define void @f(i32 %x, i32* %p) nounwind ssp { +entry: +; CHECK-NOT: vdup.32 + %vecinit.i = insertelement <2 x i32> undef, i32 %x, i32 0 + %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %x, i32 1 + %0 = bitcast i32* %p to i8* + tail call void @llvm.arm.neon.vst1.v2i32(i8* %0, <2 x i32> %vecinit1.i, i32 4) + ret void +} + +declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind diff --git a/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll new file mode 100644 index 0000000..ec7f72d --- /dev/null +++ b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll @@ -0,0 +1,129 @@ +; RUN: llc < %s -mcpu=cortex-a8 -march=thumb +; Test that this doesn't crash. +; + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios5.1.0" + +declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly + +declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind + +define void @findEdges(i8*) nounwind ssp { + %2 = icmp sgt i32 undef, 0 + br i1 %2, label %5, label %3 + +;