Replace a GPL'd header in the emu10k1 snd driver code.

This brings in the emuxkireg.h from NetBSD (dev/pci) which
is used for the same purpose but is smaller. The emu10k1
is now free from the GPL.

PR:		153901
Obtained from:	NetBSD
Approved by:	core (mentor implicit)
MFC after:	2 weeks

4 files changed, 1009 insertions, 248 deletions

diff --git a/sys/conf/files b/sys/conf/files
index 5e7f6d7..51780df 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -50,7 +50,7 @@ aic79xx_reg_print.c	optional ahd pci				   \
 aic79xx_reg_print.o		optional ahd pci ahd_reg_pretty_print	   \
 	compile-with	"${NORMAL_C}"					   \
 	no-implicit-rule local
-emu10k1-alsa%diked.h		optional snd_emu10k1 | snd_emu10kx	   \
+emu10k1-alsa%diked.h		optional snd_emu10kx	   \
 	dependency	"$S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/emu10k1-alsa.h" \
 	compile-with	"CC='${CC}' AWK=${AWK} sh $S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/emu10k1-alsa.h emu10k1-alsa%diked.h" \
 	no-obj no-implicit-rule before-depend				   \
@@ -1732,9 +1732,7 @@ dev/sound/pci/csa.c		optional snd_csa pci \
 	warning "kernel contains GPL contaminated csaimg.h header"
 dev/sound/pci/csapcm.c		optional snd_csa pci
 dev/sound/pci/ds1.c		optional snd_ds1 pci
-dev/sound/pci/emu10k1.c		optional snd_emu10k1 pci \
-	dependency "emu10k1-alsa%diked.h" \
-	warning "kernel contains GPL contaminated emu10k1 headers"
+dev/sound/pci/emu10k1.c		optional snd_emu10k1 pci
 dev/sound/pci/emu10kx.c		optional snd_emu10kx pci \
 	dependency "emu10k1-alsa%diked.h" \
 	dependency "p16v-alsa%diked.h" \
diff --git a/sys/dev/sound/pci/emu10k1.c b/sys/dev/sound/pci/emu10k1.c
index 4c02fa4..cbf89a0 100644
--- a/sys/dev/sound/pci/emu10k1.c
+++ b/sys/dev/sound/pci/emu10k1.c
@@ -32,7 +32,7 @@
 
 #include <dev/sound/pcm/sound.h>
 #include <dev/sound/pcm/ac97.h>
-#include "emu10k1-alsa%diked.h"
+#include <dev/sound/pci/emuxkireg.h>
 
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
@@ -66,12 +66,94 @@ SND_DECLARE_FILE("$FreeBSD$");
 
 #define	ENABLE		0xffffffff
 #define	DISABLE		0x00000000
-#define	ENV_ON		DCYSUSV_CHANNELENABLE_MASK
+#define	ENV_ON		EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK
 #define	ENV_OFF		0x00	/* XXX: should this be 1? */
 
-#define	A_IOCFG_GPOUT_A	0x40	/* Analog Output */
-#define	A_IOCFG_GPOUT_D	0x04	/* Digital Output */
-#define	A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D)  /* A_IOCFG_GPOUT0 */
+#define	EMU_A_IOCFG_GPOUT_A	0x40
+#define	EMU_A_IOCFG_GPOUT_D	0x04
+#define	EMU_A_IOCFG_GPOUT_AD (EMU_A_IOCFG_GPOUT_A|EMU_A_IOCFG_GPOUT_D)  /* EMU_A_IOCFG_GPOUT0 */
+
+#define	EMU_HCFG_GPOUT1		0x00000800
+
+/* instruction set */
+#define iACC3	 0x06
+#define iMACINT0 0x04
+#define iINTERP  0x0e
+
+#define C_00000000	0x40
+#define C_00000001	0x41
+#define C_00000004	0x44
+#define C_40000000	0x4d
+/* Audigy constants */
+#define A_C_00000000	0xc0
+#define A_C_40000000	0xcd
+
+/* GPRs */
+#define FXBUS(x)	(0x00 + (x))
+#define EXTIN(x)	(0x10 + (x))
+#define EXTOUT(x)	(0x20 + (x))
+
+#define GPR(x)		(EMU_FXGPREGBASE + (x))
+#define A_EXTIN(x)	(0x40 + (x))
+#define A_FXBUS(x)	(0x00 + (x))
+#define A_EXTOUT(x)	(0x60 + (x))
+#define A_GPR(x)	(EMU_A_FXGPREGBASE + (x))
+
+/* FX buses */
+#define FXBUS_PCM_LEFT		0x00
+#define FXBUS_PCM_RIGHT		0x01
+#define FXBUS_MIDI_LEFT		0x04
+#define FXBUS_MIDI_RIGHT	0x05
+#define FXBUS_MIDI_REVERB	0x0c
+#define FXBUS_MIDI_CHORUS	0x0d
+
+/* Inputs */
+#define EXTIN_AC97_L		0x00
+#define EXTIN_AC97_R		0x01
+#define EXTIN_SPDIF_CD_L	0x02
+#define EXTIN_SPDIF_CD_R	0x03
+#define EXTIN_TOSLINK_L		0x06
+#define EXTIN_TOSLINK_R		0x07
+#define EXTIN_COAX_SPDIF_L	0x0a
+#define EXTIN_COAX_SPDIF_R	0x0b
+/* Audigy Inputs */
+#define A_EXTIN_AC97_L		0x00
+#define A_EXTIN_AC97_R		0x01
+
+/* Outputs */
+#define EXTOUT_AC97_L	   0x00
+#define EXTOUT_AC97_R	   0x01
+#define EXTOUT_TOSLINK_L   0x02
+#define EXTOUT_TOSLINK_R   0x03
+#define EXTOUT_AC97_CENTER 0x04
+#define EXTOUT_AC97_LFE	   0x05
+#define EXTOUT_HEADPHONE_L 0x06
+#define EXTOUT_HEADPHONE_R 0x07
+#define EXTOUT_REAR_L	   0x08
+#define EXTOUT_REAR_R	   0x09
+#define EXTOUT_ADC_CAP_L   0x0a
+#define EXTOUT_ADC_CAP_R   0x0b
+#define EXTOUT_ACENTER	   0x11
+#define EXTOUT_ALFE	   0x12
+/* Audigy Outputs */
+#define A_EXTOUT_FRONT_L	0x00
+#define A_EXTOUT_FRONT_R	0x01
+#define A_EXTOUT_CENTER		0x02
+#define A_EXTOUT_LFE		0x03
+#define A_EXTOUT_HEADPHONE_L	0x04
+#define A_EXTOUT_HEADPHONE_R	0x05
+#define A_EXTOUT_REAR_L		0x06
+#define A_EXTOUT_REAR_R		0x07
+#define A_EXTOUT_AFRONT_L	0x08
+#define A_EXTOUT_AFRONT_R	0x09
+#define A_EXTOUT_ACENTER	0x0a
+#define A_EXTOUT_ALFE		0x0b
+#define A_EXTOUT_AREAR_L	0x0e
+#define A_EXTOUT_AREAR_R	0x0f
+#define A_EXTOUT_AC97_L		0x10
+#define A_EXTOUT_AC97_R		0x11
+#define A_EXTOUT_ADC_CAP_L	0x16
+#define A_EXTOUT_ADC_CAP_R	0x17
 
 struct emu_memblk {
 	SLIST_ENTRY(emu_memblk) link;
@@ -247,9 +329,9 @@ emu_rdptr(struct sc_info *sc, int chn, int reg)
 {
 	u_int32_t ptr, val, mask, size, offset;
 
-	ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
-	emu_wr(sc, PTR, ptr, 4);
-	val = emu_rd(sc, DATA, 4);
+	ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
+	emu_wr(sc, EMU_PTR, ptr, 4);
+	val = emu_rd(sc, EMU_DATA, 4);
 	if (reg & 0xff000000) {
 		size = (reg >> 24) & 0x3f;
 		offset = (reg >> 16) & 0x1f;
@@ -265,23 +347,23 @@ emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)
 {
 	u_int32_t ptr, mask, size, offset;
 
-	ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
-	emu_wr(sc, PTR, ptr, 4);
+	ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);
+	emu_wr(sc, EMU_PTR, ptr, 4);
 	if (reg & 0xff000000) {
 		size = (reg >> 24) & 0x3f;
 		offset = (reg >> 16) & 0x1f;
 		mask = ((1 << size) - 1) << offset;
 		data <<= offset;
 		data &= mask;
-		data |= emu_rd(sc, DATA, 4) & ~mask;
+		data |= emu_rd(sc, EMU_DATA, 4) & ~mask;
 	}
-	emu_wr(sc, DATA, data, 4);
+	emu_wr(sc, EMU_DATA, data, 4);
 }
 
 static void
 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data)
 {
-	pc += sc->audigy ? A_MICROCODEBASE : MICROCODEBASE;
+	pc += sc->audigy ? EMU_A_MICROCODEBASE : EMU_MICROCODEBASE;
 	emu_wrptr(sc, 0, pc, data);
 }
 
@@ -294,8 +376,8 @@ emu_rdcd(kobj_t obj, void *devinfo, int regno)
 {
 	struct sc_info *sc = (struct sc_info *)devinfo;
 
-	emu_wr(sc, AC97ADDRESS, regno, 1);
-	return emu_rd(sc, AC97DATA, 2);
+	emu_wr(sc, EMU_AC97ADDR, regno, 1);
+	return emu_rd(sc, EMU_AC97DATA, 2);
 }
 
 static int
@@ -303,8 +385,8 @@ emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
 {
 	struct sc_info *sc = (struct sc_info *)devinfo;
 
-	emu_wr(sc, AC97ADDRESS, regno, 1);
-	emu_wr(sc, AC97DATA, data, 2);
+	emu_wr(sc, EMU_AC97ADDR, regno, 1);
+	emu_wr(sc, EMU_AC97DATA, data, 2);
 	return 0;
 }
 
@@ -346,7 +428,7 @@ emu_settimer(struct sc_info *sc)
 	}
 	RANGE(rate, 48, 9600);
 	sc->timerinterval = 48000 / rate;
-	emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2);
+	emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2);
 
 	return sc->timerinterval;
 }
@@ -357,15 +439,15 @@ emu_enatimer(struct sc_info *sc, int go)
 	u_int32_t x;
 	if (go) {
 		if (sc->timer++ == 0) {
-			x = emu_rd(sc, INTE, 4);
-			x |= INTE_INTERVALTIMERENB;
-			emu_wr(sc, INTE, x, 4);
+			x = emu_rd(sc, EMU_INTE, 4);
+			x |= EMU_INTE_INTERTIMERENB;
+			emu_wr(sc, EMU_INTE, x, 4);
 		}
 	} else {
 		sc->timer = 0;
-		x = emu_rd(sc, INTE, 4);
-		x &= ~INTE_INTERVALTIMERENB;
-		emu_wr(sc, INTE, x, 4);
+		x = emu_rd(sc, EMU_INTE, 4);
+		x &= ~EMU_INTE_INTERTIMERENB;
+		emu_wr(sc, EMU_INTE, x, 4);
 	}
 	return 0;
 }
@@ -373,7 +455,7 @@ emu_enatimer(struct sc_info *sc, int go)
 static void
 emu_enastop(struct sc_info *sc, char channel, int enable)
 {
-	int reg = (channel & 0x20) ? SOLEH : SOLEL;
+	int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;
 	channel &= 0x1f;
 	reg |= 1 << 24;
 	reg |= channel << 16;
@@ -568,49 +650,49 @@ emu_vwrite(struct sc_info *sc, struct emu_voice *v)
 		r = v->ismaster ? 0 : r;
 	}
 
-	emu_wrptr(sc, v->vnum, CPF, v->stereo ? CPF_STEREO_MASK : 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, v->stereo ? EMU_CHAN_CPF_STEREO_MASK : 0);
 	val = v->stereo ? 28 : 30;
 	val *= v->b16 ? 1 : 2;
 	start = sa + val;
 
 	if (sc->audigy) {
-		emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1);
-		emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2);
-		emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0);
+		emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT1, v->fxrt1);
+		emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT2, v->fxrt2);
+		emu_wrptr(sc, v->vnum, EMU_A_CHAN_SENDAMOUNTS, 0);
 	}
 	else
-		emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_FXRT, v->fxrt1 << 16);
 
-	emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r);
-	emu_wrptr(sc, v->vnum, DSL, ea | (y << 24));
-	emu_wrptr(sc, v->vnum, PSST, sa | (l << 24));
-	emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT));
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX, (x << 8) | r);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_DSL, ea | (y << 24));
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PSST, sa | (l << 24));
+	emu_wrptr(sc, v->vnum, EMU_CHAN_CCCA, start | (v->b16 ? 0 : EMU_CHAN_CCCA_8BITSELECT));
 
-	emu_wrptr(sc, v->vnum, Z1, 0);
-	emu_wrptr(sc, v->vnum, Z2, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_Z1, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_Z2, 0);
 
 	silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1)
-	    | MAP_PTI_MASK;
-	emu_wrptr(sc, v->vnum, MAPA, silent_page);
-	emu_wrptr(sc, v->vnum, MAPB, silent_page);
-
-	emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK);
-	emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK);
-	emu_wrptr(sc, v->vnum, ATKHLDM, 0);
-	emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK);
-	emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000);
-	emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000);
-	emu_wrptr(sc, v->vnum, FMMOD, 0);
-	emu_wrptr(sc, v->vnum, TREMFRQ, 0);
-	emu_wrptr(sc, v->vnum, FM2FRQ2, 0);
-	emu_wrptr(sc, v->vnum, ENVVAL, 0x8000);
-
-	emu_wrptr(sc, v->vnum, ATKHLDV,
-	    ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK);
-	emu_wrptr(sc, v->vnum, ENVVOL, 0x8000);
-
-	emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f);
-	emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0);
+	    | EMU_CHAN_MAP_PTI_MASK;
+	emu_wrptr(sc, v->vnum, EMU_CHAN_MAPA, silent_page);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_MAPB, silent_page);
+
+	emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, EMU_CHAN_CVCF_CURRFILTER_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, EMU_CHAN_VTFT_FILTERTARGET_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDM, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSM, EMU_CHAN_DCYSUSM_DECAYTIME_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL1, 0x8000);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL2, 0x8000);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_FMMOD, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_TREMFRQ, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_FM2FRQ2, 0);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVAL, 0x8000);
+
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDV,
+	    EMU_CHAN_ATKHLDV_HOLDTIME_MASK | EMU_CHAN_ATKHLDV_ATTACKTIME_MASK);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVOL, 0x8000);
+
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_FILTERAMOUNT, 0x7f);
+	emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_PITCHAMOUNT, 0);
 
 	if (v->slave != NULL)
 		emu_vwrite(sc, v->slave);
@@ -631,29 +713,29 @@ emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go)
 		sample = v->b16 ? 0x00000000 : 0x80808080;
 
 		for (i = 0; i < cs; i++)
-			emu_wrptr(sc, v->vnum, CD0 + i, sample);
-		emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0);
-		emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra);
-		emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis);
-
-		emu_wrptr(sc, v->vnum, IFATN, 0xff00);
-		emu_wrptr(sc, v->vnum, VTFT, 0xffffffff);
-		emu_wrptr(sc, v->vnum, CVCF, 0xffffffff);
-		emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f);
+			emu_wrptr(sc, v->vnum, EMU_CHAN_CD0 + i, sample);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_READADDRESS, cra);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, ccis);
+
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xff00);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0xffffffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0xffffffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSV, 0x00007f7f);
 		emu_enastop(sc, v->vnum, 0);
 
 		pitch_target = emu_rate_to_linearpitch(v->speed);
 		initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
-		emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target);
-		emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target);
-		emu_wrptr(sc, v->vnum, IP, initial_pitch);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, pitch_target);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, pitch_target);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IP, initial_pitch);
 	} else {
-		emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0);
-		emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0);
-		emu_wrptr(sc, v->vnum, IFATN, 0xffff);
-		emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff);
-		emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff);
-		emu_wrptr(sc, v->vnum, IP, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, 0);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0x0000ffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0x0000ffff);
+		emu_wrptr(sc, v->vnum, EMU_CHAN_IP, 0);
 		emu_enastop(sc, v->vnum, 1);
 	}
 	if (v->slave != NULL)
@@ -666,7 +748,7 @@ emu_vpos(struct sc_info *sc, struct emu_voice *v)
 	int s, ptr;
 
 	s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0);
-	ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s;
+	ptr = (emu_rdptr(sc, v->vnum, EMU_CHAN_CCCA_CURRADDR) - (v->start >> s)) << s;
 	return ptr & ~0x0000001f;
 }
 
@@ -875,27 +957,27 @@ emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
 	ch->num = sc->rnum;
 	switch(sc->rnum) {
 	case 0:
-		ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX;
-		ch->basereg = ADCBA;
-		ch->sizereg = ADCBS;
-		ch->setupreg = ADCCR;
-		ch->irqmask = INTE_ADCBUFENABLE;
+		ch->idxreg = sc->audigy ? EMU_A_ADCIDX : EMU_ADCIDX;
+		ch->basereg = EMU_ADCBA;
+		ch->sizereg = EMU_ADCBS;
+		ch->setupreg = EMU_ADCCR;
+		ch->irqmask = EMU_INTE_ADCBUFENABLE;
 		break;
 
 	case 1:
-		ch->idxreg = FXIDX;
-		ch->basereg = FXBA;
-		ch->sizereg = FXBS;
-		ch->setupreg = FXWC;
-		ch->irqmask = INTE_EFXBUFENABLE;
+		ch->idxreg = EMU_FXIDX;
+		ch->basereg = EMU_FXBA;
+		ch->sizereg = EMU_FXBS;
+		ch->setupreg = EMU_FXWC;
+		ch->irqmask = EMU_INTE_EFXBUFENABLE;
 		break;
 
 	case 2:
-		ch->idxreg = MICIDX;
-		ch->basereg = MICBA;
-		ch->sizereg = MICBS;
+		ch->idxreg = EMU_MICIDX;
+		ch->basereg = EMU_MICBA;
+		ch->sizereg = EMU_MICBS;
 		ch->setupreg = 0;
-		ch->irqmask = INTE_MICBUFENABLE;
+		ch->irqmask = EMU_INTE_MICBUFENABLE;
 		break;
 	}
 	sc->rnum++;
@@ -967,27 +1049,27 @@ emurchan_trigger(kobj_t obj, void *data, int go)
 
 	switch(sc->bufsz) {
 	case 4096:
-		sz = ADCBS_BUFSIZE_4096;
+		sz = EMU_RECBS_BUFSIZE_4096;
 		break;
 
 	case 8192:
-		sz = ADCBS_BUFSIZE_8192;
+		sz = EMU_RECBS_BUFSIZE_8192;
 		break;
 
 	case 16384:
-		sz = ADCBS_BUFSIZE_16384;
+		sz = EMU_RECBS_BUFSIZE_16384;
 		break;
 
 	case 32768:
-		sz = ADCBS_BUFSIZE_32768;
+		sz = EMU_RECBS_BUFSIZE_32768;
 		break;
 
 	case 65536:
-		sz = ADCBS_BUFSIZE_65536;
+		sz = EMU_RECBS_BUFSIZE_65536;
 		break;
 
 	default:
-		sz = ADCBS_BUFSIZE_4096;
+		sz = EMU_RECBS_BUFSIZE_4096;
 	}
 
 	snd_mtxlock(sc->lock);
@@ -997,23 +1079,23 @@ emurchan_trigger(kobj_t obj, void *data, int go)
 		emu_wrptr(sc, 0, ch->sizereg, sz);
 		if (ch->num == 0) {
 			if (sc->audigy) {
-				val = A_ADCCR_LCHANENABLE;
+				val = EMU_ADCCR_LCHANENABLE;
 				if (AFMT_CHANNEL(ch->fmt) > 1)
-					val |= A_ADCCR_RCHANENABLE;
+					val |= EMU_ADCCR_RCHANENABLE;
 				val |= audigy_recval(ch->spd);
 			} else {
-				val = ADCCR_LCHANENABLE;
+				val = EMU_ADCCR_LCHANENABLE;
 				if (AFMT_CHANNEL(ch->fmt) > 1)
-					val |= ADCCR_RCHANENABLE;
+					val |= EMU_ADCCR_RCHANENABLE;
 				val |= emu_recval(ch->spd);
 			}
 
 			emu_wrptr(sc, 0, ch->setupreg, 0);
 			emu_wrptr(sc, 0, ch->setupreg, val);
 		}
-		val = emu_rd(sc, INTE, 4);
+		val = emu_rd(sc, EMU_INTE, 4);
 		val |= ch->irqmask;
-		emu_wr(sc, INTE, val, 4);
+		emu_wr(sc, EMU_INTE, val, 4);
 		break;
 
 	case PCMTRIG_STOP:
@@ -1022,9 +1104,9 @@ emurchan_trigger(kobj_t obj, void *data, int go)
 		emu_wrptr(sc, 0, ch->sizereg, 0);
 		if (ch->setupreg)
 			emu_wrptr(sc, 0, ch->setupreg, 0);
-		val = emu_rd(sc, INTE, 4);
+		val = emu_rd(sc, EMU_INTE, 4);
 		val &= ~ch->irqmask;
-		emu_wr(sc, INTE, val, 4);
+		emu_wr(sc, EMU_INTE, val, 4);
 		break;
 
 	case PCMTRIG_EMLDMAWR:
@@ -1122,9 +1204,9 @@ emu_midiattach(struct sc_info *sc)
 {
 	int i;
 
-	i = emu_rd(sc, INTE, 4);
-	i |= INTE_MIDIRXENABLE;
-	emu_wr(sc, INTE, i, 4);
+	i = emu_rd(sc, EMU_INTE, 4);
+	i |= EMU_INTE_MIDIRXENABLE;
+	emu_wr(sc, EMU_INTE, i, 4);
 
 	sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr);
 }
@@ -1139,52 +1221,52 @@ emu_intr(void *data)
 
 	snd_mtxlock(sc->lock);
 	while (1) {
-		stat = emu_rd(sc, IPR, 4);
+		stat = emu_rd(sc, EMU_IPR, 4);
 		if (stat == 0)
 			break;
 		ack = 0;
 
 		/* process irq */
-		if (stat & IPR_INTERVALTIMER)
-			ack |= IPR_INTERVALTIMER;
+		if (stat & EMU_IPR_INTERVALTIMER)
+			ack |= EMU_IPR_INTERVALTIMER;
 
-		if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL))
-			ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL);
+		if (stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL))
+			ack |= stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL);
 
-		if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL))
-			ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL);
+		if (stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL))
+			ack |= stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL);
 
-		if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL))
-			ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL);
+		if (stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL))
+			ack |= stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL);
 
-		if (stat & IPR_PCIERROR) {
-			ack |= IPR_PCIERROR;
+		if (stat & EMU_PCIERROR) {
+			ack |= EMU_PCIERROR;
 			device_printf(sc->dev, "pci error\n");
 			/* we still get an nmi with ecc ram even if we ack this */
 		}
-		if (stat & IPR_SAMPLERATETRACKER) {
-			ack |= IPR_SAMPLERATETRACKER;
+		if (stat & EMU_IPR_RATETRCHANGE) {
+			ack |= EMU_IPR_RATETRCHANGE;
 #ifdef EMUDEBUG
 			device_printf(sc->dev,
 			    "sample rate tracker lock status change\n");
 #endif
 		}
 
-	    if (stat & IPR_MIDIRECVBUFEMPTY)
+	    if (stat & EMU_IPR_MIDIRECVBUFE)
 		if (sc->mpu_intr) {
 		    (sc->mpu_intr)(sc->mpu);
-		    ack |= IPR_MIDIRECVBUFEMPTY | IPR_MIDITRANSBUFEMPTY;
+		    ack |= EMU_IPR_MIDIRECVBUFE | EMU_IPR_MIDITRANSBUFE;
  		}
 		if (stat & ~ack)
 			device_printf(sc->dev, "dodgy irq: %x (harmless)\n",
 			    stat & ~ack);
 
-		emu_wr(sc, IPR, stat, 4);
+		emu_wr(sc, EMU_IPR, stat, 4);
 
 		if (ack) {
 			snd_mtxunlock(sc->lock);
 
-			if (ack & IPR_INTERVALTIMER) {
+			if (ack & EMU_IPR_INTERVALTIMER) {
 				x = 0;
 				for (i = 0; i < sc->nchans; i++) {
 					if (sc->pch[i].run) {
@@ -1197,15 +1279,15 @@ emu_intr(void *data)
 			}
 
 
-			if (ack & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) {
+			if (ack & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) {
 				if (sc->rch[0].channel)
 					chn_intr(sc->rch[0].channel);
 			}
-			if (ack & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) {
+			if (ack & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) {
 				if (sc->rch[1].channel)
 					chn_intr(sc->rch[1].channel);
 			}
-			if (ack & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) {
+			if (ack & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) {
 				if (sc->rch[2].channel)
 					chn_intr(sc->rch[2].channel);
 			}
@@ -1378,12 +1460,12 @@ audigy_initefx(struct sc_info *sc)
 		audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc);
 
 	for (i = 0; i < 512; i++)
-		emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0);
+		emu_wrptr(sc, 0, EMU_A_FXGPREGBASE + i, 0x0);
 
 	pc = 16;
 
 	/* stop fx processor */
-	emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
+	emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
 
 	/* Audigy 2 (EMU10K2) DSP Registers:
 	   FX Bus
@@ -1518,7 +1600,7 @@ audigy_initefx(struct sc_info *sc)
 			A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc);
 
 	/* resume normal operations */
-	emu_wrptr(sc, 0, A_DBG, 0);
+	emu_wrptr(sc, 0, EMU_A_DBG, 0);
 }
 
 static void
@@ -1534,7 +1616,7 @@ emu_initefx(struct sc_info *sc)
 	}
 
 	for (i = 0; i < 256; i++)
-		emu_wrptr(sc, 0, FXGPREGBASE + i, 0);
+		emu_wrptr(sc, 0, EMU_FXGPREGBASE + i, 0);
 
 	/* FX-8010 DSP Registers:
 	   FX Bus
@@ -1654,7 +1736,7 @@ emu_initefx(struct sc_info *sc)
 			C_00000000, EXTIN(EXTIN_AC97_R), &pc);
 
 	/* resume normal operations */
-	emu_wrptr(sc, 0, DBG, 0);
+	emu_wrptr(sc, 0, EMU_DBG, 0);
 }
 
 /* Probe and attach the card */
@@ -1665,69 +1747,69 @@ emu_init(struct sc_info *sc)
 
 	if (sc->audigy) {
 		/* enable additional AC97 slots */
-		emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE);
+		emu_wrptr(sc, 0, EMU_AC97SLOT, EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE);
 	}
 
 	/* disable audio and lock cache */
-	emu_wr(sc, HCFG,
-	    HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
+	emu_wr(sc, EMU_HCFG,
+	    EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
 	    4);
 
 	/* reset recording buffers */
-	emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, MICBA, 0);
-	emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, FXBA, 0);
-	emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, ADCBA, 0);
+	emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_MICBA, 0);
+	emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_FXBA, 0);
+	emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_ADCBA, 0);
 
 	/* disable channel interrupt */
-	emu_wr(sc, INTE,
-	    INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE,
+	emu_wr(sc, EMU_INTE,
+	    EMU_INTE_INTERTIMERENB | EMU_INTE_SAMPLERATER | EMU_INTE_PCIERRENABLE,
 	    4);
-	emu_wrptr(sc, 0, CLIEL, 0);
-	emu_wrptr(sc, 0, CLIEH, 0);
-	emu_wrptr(sc, 0, SOLEL, 0);
-	emu_wrptr(sc, 0, SOLEH, 0);
+	emu_wrptr(sc, 0, EMU_CLIEL, 0);
+	emu_wrptr(sc, 0, EMU_CLIEH, 0);
+	emu_wrptr(sc, 0, EMU_SOLEL, 0);
+	emu_wrptr(sc, 0, EMU_SOLEH, 0);
 
 	/* wonder what these do... */
 	if (sc->audigy) {
-		emu_wrptr(sc, 0, SPBYPASS, 0xf00);
-		emu_wrptr(sc, 0, AC97SLOT, 0x3);
+		emu_wrptr(sc, 0, EMU_SPBYPASS, 0xf00);
+		emu_wrptr(sc, 0, EMU_AC97SLOT, 0x3);
 	}
 
 	/* init envelope engine */
 	for (ch = 0; ch < NUM_G; ch++) {
-		emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
-		emu_wrptr(sc, ch, IP, 0);
-		emu_wrptr(sc, ch, VTFT, 0xffff);
-		emu_wrptr(sc, ch, CVCF, 0xffff);
-		emu_wrptr(sc, ch, PTRX, 0);
-		emu_wrptr(sc, ch, CPF, 0);
-		emu_wrptr(sc, ch, CCR, 0);
-
-		emu_wrptr(sc, ch, PSST, 0);
-		emu_wrptr(sc, ch, DSL, 0x10);
-		emu_wrptr(sc, ch, CCCA, 0);
-		emu_wrptr(sc, ch, Z1, 0);
-		emu_wrptr(sc, ch, Z2, 0);
-		emu_wrptr(sc, ch, FXRT, 0xd01c0000);
-
-		emu_wrptr(sc, ch, ATKHLDM, 0);
-		emu_wrptr(sc, ch, DCYSUSM, 0);
-		emu_wrptr(sc, ch, IFATN, 0xffff);
-		emu_wrptr(sc, ch, PEFE, 0);
-		emu_wrptr(sc, ch, FMMOD, 0);
-		emu_wrptr(sc, ch, TREMFRQ, 24);	/* 1 Hz */
-		emu_wrptr(sc, ch, FM2FRQ2, 24);	/* 1 Hz */
-		emu_wrptr(sc, ch, TEMPENV, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
+		emu_wrptr(sc, ch, EMU_CHAN_IP, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0xffff);
+		emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0xffff);
+		emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CCR, 0);
+
+		emu_wrptr(sc, ch, EMU_CHAN_PSST, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_DSL, 0x10);
+		emu_wrptr(sc, ch, EMU_CHAN_CCCA, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_Z1, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_Z2, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_FXRT, 0xd01c0000);
+
+		emu_wrptr(sc, ch, EMU_CHAN_ATKHLDM, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_DCYSUSM, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_IFATN, 0xffff);
+		emu_wrptr(sc, ch, EMU_CHAN_PEFE, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_FMMOD, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_TREMFRQ, 24);	/* 1 Hz */
+		emu_wrptr(sc, ch, EMU_CHAN_FM2FRQ2, 24);	/* 1 Hz */
+		emu_wrptr(sc, ch, EMU_CHAN_TEMPENV, 0);
 
 		/*** these are last so OFF prevents writing ***/
-		emu_wrptr(sc, ch, LFOVAL2, 0);
-		emu_wrptr(sc, ch, LFOVAL1, 0);
-		emu_wrptr(sc, ch, ATKHLDV, 0);
-		emu_wrptr(sc, ch, ENVVOL, 0);
-		emu_wrptr(sc, ch, ENVVAL, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_LFOVAL2, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_LFOVAL1, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_ATKHLDV, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_ENVVOL, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_ENVVAL, 0);
 
 		if (sc->audigy) {
 			/* audigy cards need this to initialize correctly */
@@ -1736,9 +1818,9 @@ emu_init(struct sc_info *sc)
 			emu_wrptr(sc, ch, 0x4e, 0);
 			emu_wrptr(sc, ch, 0x4f, 0);
 			/* set default routing */
-			emu_wrptr(sc, ch, A_FXRT1, 0x03020100);
-			emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f);
-			emu_wrptr(sc, ch, A_SENDAMOUNTS, 0);
+			emu_wrptr(sc, ch, EMU_A_CHAN_FXRT1, 0x03020100);
+			emu_wrptr(sc, ch, EMU_A_CHAN_FXRT2, 0x3f3f3f3f);
+			emu_wrptr(sc, ch, EMU_A_CHAN_SENDAMOUNTS, 0);
 		}
 
 		sc->voice[ch].vnum = ch;
@@ -1769,13 +1851,13 @@ emu_init(struct sc_info *sc)
 	 *  AN                = 0     (Audio data)
 	 *  P                 = 0     (Consumer)
 	 */
-	spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
-	    SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
-	    SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
-	    SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
-	emu_wrptr(sc, 0, SPCS0, spcs);
-	emu_wrptr(sc, 0, SPCS1, spcs);
-	emu_wrptr(sc, 0, SPCS2, spcs);
+	spcs = EMU_SPCS_CLKACCY_1000PPM | EMU_SPCS_SAMPLERATE_48 |
+	    EMU_SPCS_CHANNELNUM_LEFT | EMU_SPCS_SOURCENUM_UNSPEC |
+	    EMU_SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
+	    EMU_SPCS_EMPHASIS_NONE | EMU_SPCS_COPYRIGHT;
+	emu_wrptr(sc, 0, EMU_SPCS0, spcs);
+	emu_wrptr(sc, 0, EMU_SPCS1, spcs);
+	emu_wrptr(sc, 0, EMU_SPCS2, spcs);
 
 	if (!sc->audigy)
 		emu_initefx(sc);
@@ -1786,8 +1868,8 @@ emu_init(struct sc_info *sc)
 		u_int32_t tmp;
 
 		/* Setup SRCMulti_I2S SamplingRate */
-		tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff;
-		emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400);
+		tmp = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff;
+		emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400);
 
 		/* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */
 		emu_wr(sc, 0x20, 0x00600000, 4);
@@ -1816,13 +1898,13 @@ emu_init(struct sc_info *sc)
 	for (i = 0; i < EMUMAXPAGES; i++)
 		sc->mem.ptb_pages[i] = tmp | i;
 
-	emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr));
-	emu_wrptr(sc, 0, TCB, 0);	/* taken from original driver */
-	emu_wrptr(sc, 0, TCBS, 0);	/* taken from original driver */
+	emu_wrptr(sc, 0, EMU_PTB, (sc->mem.ptb_pages_addr));
+	emu_wrptr(sc, 0, EMU_TCB, 0);	/* taken from original driver */
+	emu_wrptr(sc, 0, EMU_TCBS, 0);	/* taken from original driver */
 
 	for (ch = 0; ch < NUM_G; ch++) {
-		emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK);
-		emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK);
+		emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK);
+		emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK);
 	}
 
 	/* emu_memalloc(sc, EMUPAGESIZE); */
@@ -1850,19 +1932,19 @@ emu_init(struct sc_info *sc)
 	 */
 
 	if (sc->audigy) {
-		tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE;
+		tmp = EMU_HCFG_AUTOMUTE | EMU_HCFG_JOYENABLE;
 		if (sc->audigy2)	/* Audigy 2 */
-			tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF |
-			    HCFG_AC3ENABLE_GPSPDIF;
-		emu_wr(sc, HCFG, tmp, 4);
+			tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AC3ENABLE_CDSPDIF |
+			    EMU_HCFG_AC3ENABLE_GPSPDIF;
+		emu_wr(sc, EMU_HCFG, tmp, 4);
 
 		audigy_initefx(sc);
 
 		/* from ALSA initialization code: */
 
 		/* enable audio and disable both audio/digital outputs */
-		emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4);
-		emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD,
+		emu_wr(sc, EMU_HCFG, emu_rd(sc, EMU_HCFG, 4) | EMU_HCFG_AUDIOENABLE, 4);
+		emu_wr(sc, EMU_A_IOCFG, emu_rd(sc, EMU_A_IOCFG, 4) & ~EMU_A_IOCFG_GPOUT_AD,
 		    4);
 		if (sc->audigy2) {	/* Audigy 2 */
 			/* Unmute Analog.
@@ -1870,27 +1952,27 @@ emu_init(struct sc_info *sc)
 			 * init Alice3 I2SOut beyond 48kHz.
 			 * So, sequence is important.
 			 */
-			emu_wr(sc, A_IOCFG,
-			    emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4);
+			emu_wr(sc, EMU_A_IOCFG,
+			    emu_rd(sc, EMU_A_IOCFG, 4) | EMU_A_IOCFG_GPOUT_A, 4);
 		}
 	} else {
 		/* EMU10K1 initialization code */
-		tmp = HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK 
-		    | HCFG_AUTOMUTE;
+		tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_LOCKTANKCACHE_MASK 
+		    | EMU_HCFG_AUTOMUTE;
 		if (sc->rev >= 6)
-			tmp |= HCFG_JOYENABLE;
+			tmp |= EMU_HCFG_JOYENABLE;
 
-		emu_wr(sc, HCFG, tmp, 4);
+		emu_wr(sc, EMU_HCFG, tmp, 4);
 
 		/* TOSLink detection */
 		sc->tos_link = 0;
-		tmp = emu_rd(sc, HCFG, 4);
-		if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
-			emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4);
+		tmp = emu_rd(sc, EMU_HCFG, 4);
+		if (tmp & (EMU_HCFG_GPINPUT0 | EMU_HCFG_GPINPUT1)) {
+			emu_wr(sc, EMU_HCFG, tmp | EMU_HCFG_GPOUT1, 4);
 			DELAY(50);
-			if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) {
+			if (tmp != (emu_rd(sc, EMU_HCFG, 4) & ~EMU_HCFG_GPOUT1)) {
 				sc->tos_link = 1;
-				emu_wr(sc, HCFG, tmp, 4);
+				emu_wr(sc, EMU_HCFG, tmp, 4);
 			}
 		}
 	}
@@ -1903,42 +1985,42 @@ emu_uninit(struct sc_info *sc)
 {
 	u_int32_t ch;
 
-	emu_wr(sc, INTE, 0, 4);
+	emu_wr(sc, EMU_INTE, 0, 4);
 	for (ch = 0; ch < NUM_G; ch++)
-		emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
+		emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF);
 	for (ch = 0; ch < NUM_G; ch++) {
-		emu_wrptr(sc, ch, VTFT, 0);
-		emu_wrptr(sc, ch, CVCF, 0);
-		emu_wrptr(sc, ch, PTRX, 0);
-		emu_wrptr(sc, ch, CPF, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
+		emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
 	}
 
 	if (sc->audigy) {	/* stop fx processor */
-		emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
+		emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
 	}
 
 	/* disable audio and lock cache */
-	emu_wr(sc, HCFG,
-	    HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
+	emu_wr(sc, EMU_HCFG,
+	    EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE,
 	    4);
 
-	emu_wrptr(sc, 0, PTB, 0);
+	emu_wrptr(sc, 0, EMU_PTB, 0);
 	/* reset recording buffers */
-	emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, MICBA, 0);
-	emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, FXBA, 0);
-	emu_wrptr(sc, 0, FXWC, 0);
-	emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
-	emu_wrptr(sc, 0, ADCBA, 0);
-	emu_wrptr(sc, 0, TCB, 0);
-	emu_wrptr(sc, 0, TCBS, 0);
+	emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_MICBA, 0);
+	emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_FXBA, 0);
+	emu_wrptr(sc, 0, EMU_FXWC, 0);
+	emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
+	emu_wrptr(sc, 0, EMU_ADCBA, 0);
+	emu_wrptr(sc, 0, EMU_TCB, 0);
+	emu_wrptr(sc, 0, EMU_TCBS, 0);
 
 	/* disable channel interrupt */
-	emu_wrptr(sc, 0, CLIEL, 0);
-	emu_wrptr(sc, 0, CLIEH, 0);
-	emu_wrptr(sc, 0, SOLEL, 0);
-	emu_wrptr(sc, 0, SOLEH, 0);
+	emu_wrptr(sc, 0, EMU_CLIEL, 0);
+	emu_wrptr(sc, 0, EMU_CLIEH, 0);
+	emu_wrptr(sc, 0, EMU_SOLEL, 0);
+	emu_wrptr(sc, 0, EMU_SOLEH, 0);
 
 	/* init envelope engine */
 	if (!SLIST_EMPTY(&sc->mem.blocks))
@@ -1997,7 +2079,7 @@ emu_pci_attach(device_t dev)
 	sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID;
 	sc->audigy2 = (sc->audigy && sc->rev == 0x04);
 	sc->nchans = sc->audigy ? 8 : 4;
-	sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;
+	sc->addrmask = sc->audigy ? EMU_A_PTR_ADDR_MASK : EMU_PTR_ADDR_MASK;
 
 	data = pci_read_config(dev, PCIR_COMMAND, 2);
 	data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
diff --git a/sys/dev/sound/pci/emuxkireg.h b/sys/dev/sound/pci/emuxkireg.h
new file mode 100644
index 0000000..c743c8e
--- /dev/null
+++ b/sys/dev/sound/pci/emuxkireg.h
@@ -0,0 +1,689 @@
+/* $FreeBSD$ */
+/*	$NetBSD: emuxkireg.h,v 1.8 2008/04/28 20:23:54 martin Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Yannick Montulet.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_PCI_EMUXKIREG_H_
+#define _DEV_PCI_EMUXKIREG_H_
+
+/*
+ * Register values for Creative EMU10000. The register values have been
+ * taken from GPLed SBLive! header file published by Creative. The comments
+ * have been stripped to avoid GPL pollution in kernel. The Creative version
+ * including comments is available in Linux 2.4.* kernel as file
+ *	drivers/sound/emu10k1/8010.h
+ */
+
+/*
+ * Audigy specific registers contain an '_A_'
+ * Audigy2 specific registers contain an '_A2_'
+ */
+
+#define	EMU_MKSUBREG(sz, idx, reg)	(((sz) << 24) | ((idx) << 16) | (reg))
+
+#define EMU_PTR	0x00
+#define  EMU_PTR_CHNO_MASK	0x0000003f
+#define  EMU_PTR_ADDR_MASK	0x07ff0000
+#define  EMU_A_PTR_ADDR_MASK	0x0fff0000
+
+#define EMU_DATA	0x04
+
+#define EMU_IPR	0x08
+#define  EMU_IPR_RATETRCHANGE	0x01000000
+#define  EMU_IPR_FXDSP		0x00800000
+#define  EMU_IPR_FORCEINT	0x00400000
+#define  EMU_PCIERROR		0x00200000
+#define  EMU_IPR_VOLINCR	0x00100000
+#define  EMU_IPR_VOLDECR	0x00080000
+#define  EMU_IPR_MUTE		0x00040000
+#define  EMU_IPR_MICBUFFULL	0x00020000
+#define  EMU_IPR_MICBUFHALFFULL	0x00010000
+#define  EMU_IPR_ADCBUFFULL	0x00008000
+#define  EMU_IPR_ADCBUFHALFFULL	0x00004000
+#define  EMU_IPR_EFXBUFFULL	0x00002000
+#define  EMU_IPR_EFXBUFHALFFULL	0x00001000
+#define  EMU_IPR_GPSPDIFSTCHANGE 0x00000800
+#define  EMU_IPR_CDROMSTCHANGE	0x00000400
+#define  EMU_IPR_INTERVALTIMER	0x00000200
+#define  EMU_IPR_MIDITRANSBUFE	0x00000100
+#define  EMU_IPR_MIDIRECVBUFE	0x00000080
+#define  EMU_IPR_A_MIDITRANSBUFE2 0x10000000
+#define  EMU_IPR_A_MIDIRECBUFE2	0x08000000
+#define  EMU_IPR_CHANNELLOOP	0x00000040
+#define  EMU_IPR_CHNOMASK	0x0000003f
+
+#define EMU_INTE	0x0c
+
+#define  EMU_INTE_VSB_MASK	0xc0000000
+#define   EMU_INTE_VSB_220	0x00000000
+#define   EMU_INTE_VSB_240	0x40000000
+#define   EMU_INTE_VSB_260	0x80000000
+#define   EMU_INTE_VSB_280	0xc0000000
+
+#define  EMU_INTE_VMPU_MASK	0x30000000
+#define   EMU_INTE_VMPU_300	0x00000000
+#define   EMU_INTE_VMPU_310	0x10000000
+#define   EMU_INTE_VMPU_320	0x20000000
+#define   EMU_INTE_VMPU_330	0x30000000
+#define  EMU_INTE_MDMAENABLE	0x08000000
+#define  EMU_INTE_SDMAENABLE	0x04000000
+#define  EMU_INTE_MPICENABLE	0x02000000
+#define  EMU_INTE_SPICENABLE	0x01000000
+#define  EMU_INTE_VSBENABLE	0x00800000
+#define  EMU_INTE_ADLIBENABLE	0x00400000
+#define  EMU_INTE_MPUENABLE	0x00200000
+#define  EMU_INTE_FORCEINT	0x00100000
+#define  EMU_INTE_MRHANDENABLE	0x00080000
+#define  EMU_INTE_SAMPLERATER	0x00002000
+#define  EMU_INTE_FXDSPENABLE	0x00001000
+#define  EMU_INTE_PCIERRENABLE	0x00000800
+#define  EMU_INTE_VOLINCRENABLE	0x00000400
+#define  EMU_INTE_VOLDECRENABLE	0x00000200
+#define  EMU_INTE_MUTEENABLE	0x00000100
+#define  EMU_INTE_MICBUFENABLE	0x00000080
+#define  EMU_INTE_ADCBUFENABLE	0x00000040
+#define  EMU_INTE_EFXBUFENABLE	0x00000020
+#define  EMU_INTE_GPSPDIFENABLE	0x00000010
+#define  EMU_INTE_CDSPDIFENABLE	0x00000008
+#define  EMU_INTE_INTERTIMERENB	0x00000004
+#define  EMU_INTE_MIDITXENABLE	0x00000002
+#define  EMU_INTE_MIDIRXENABLE	0x00000001
+#define  EMU_INTE_A_MIDITXENABLE2 0x00020000
+#define  EMU_INTE_A_MIDIRXENABLE2 0x00010000
+
+#define EMU_WC	0x10
+#define  EMU_WC_SAMPLECOUNTER_MASK	0x03FFFFC0
+#define  EMU_WC_SAMPLECOUNTER		EMU_MKSUBREG(20, 6, EMU_WC)
+#define  EMU_WC_CURRENTCHANNEL		0x0000003F
+
+#define EMU_HCFG	0x14
+#define  EMU_HCFG_LEGACYFUNC_MASK	0xe0000000
+#define  EMU_HCFG_LEGACYFUNC_MPU	0x00000000
+#define  EMU_HCFG_LEGACYFUNC_SB		0x40000000
+#define  EMU_HCFG_LEGACYFUNC_AD		0x60000000
+#define  EMU_HCFG_LEGACYFUNC_MPIC	0x80000000
+#define  EMU_HCFG_LEGACYFUNC_MDMA	0xa0000000
+#define  EMU_HCFG_LEGACYFUNC_SPCI	0xc0000000
+#define  EMU_HCFG_LEGACYFUNC_SDMA	0xe0000000
+#define  EMU_HCFG_IOCAPTUREADDR		0x1f000000
+#define  EMU_HCFG_LEGACYWRITE		0x00800000
+#define  EMU_HCFG_LEGACYWORD		0x00400000
+#define  EMU_HCFG_LEGACYINT		0x00200000
+
+#define  EMU_HCFG_CODECFMT_MASK		0x00070000
+#define  EMU_HCFG_CODECFMT_AC97		0x00000000
+#define  EMU_HCFG_CODECFMT_I2S		0x00010000
+#define  EMU_HCFG_GPINPUT0		0x00004000
+#define  EMU_HCFG_GPINPUT1		0x00002000
+#define  EMU_HCFG_GPOUTPUT_MASK		0x00001c00
+#define  EMU_HCFG_JOYENABLE		0x00000200
+#define  EMU_HCFG_PHASETRACKENABLE	0x00000100
+#define  EMU_HCFG_AC3ENABLE_MASK	0x000000e0
+#define  EMU_HCFG_AC3ENABLE_ZVIDEO	0x00000080
+#define  EMU_HCFG_AC3ENABLE_CDSPDIF	0x00000040
+#define  EMU_HCFG_AC3ENABLE_GPSPDIF	0x00000020
+#define  EMU_HCFG_AUTOMUTE		0x00000010
+#define  EMU_HCFG_LOCKSOUNDCACHE	0x00000008
+#define  EMU_HCFG_LOCKTANKCACHE_MASK	0x00000004
+#define  EMU_HCFG_LOCKTANKCACHE		EMU_MKSUBREG(1, 2, EMU_HCFG)
+#define  EMU_HCFG_MUTEBUTTONENABLE	0x00000002
+#define  EMU_HCFG_AUDIOENABLE		0x00000001
+
+#define EMU_MUDATA	0x18
+#define EMU_MUCMD	0x19
+#define  EMU_MUCMD_RESET		0xff
+#define  EMU_MUCMD_ENTERUARTMODE	0x3f
+
+#define EMU_MUSTAT	EMU_MUCMD
+#define  EMU_MUSTAT_IRDYN		0x80
+#define  EMU_MUSTAT_ORDYN		0x40
+
+#define EMU_A_IOCFG			0x18
+#define EMU_A_GPINPUT_MASK		0xff00
+#define EMU_A_GPOUTPUT_MASK		0x00ff
+#define EMU_A_IOCFG_GPOUT0		0x0040
+#define EMU_A_IOCFG_GPOUT1		0x0004
+
+#define EMU_TIMER	0x1a
+#define  EMU_TIMER_RATE_MASK	0x000003ff
+#define  EMU_TIMER_RATE		EMU_MKSUBREG(10, 0, EMU_TIMER)
+
+#define EMU_AC97DATA	0x1c
+#define EMU_AC97ADDR	0x1e
+#define  EMU_AC97ADDR_RDY	0x80
+#define  EMU_AC97ADDR_ADDR	0x7f
+
+#define EMU_A2_PTR		0x20
+#define EMU_A2_DATA		0x24
+
+#define EMU_A2_SRCSEL			0x600000
+#define EMU_A2_SRCSEL_ENABLE_SPDIF	0x00000004
+#define EMU_A2_SRCSEL_ENABLE_SRCMULTI	0x00000010
+#define EMU_A2_SRCMULTI			0x6e0000
+#define EMU_A2_SRCMULTI_ENABLE_INPUT	0xff00ff00
+
+/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
+
+#define EMU_CHAN_CPF	0x00
+
+#define  EMU_CHAN_CPF_PITCH_MASK	0xffff0000
+#define  EMU_CHAN_CPF_PITCH	EMU_MKSUBREG(16, 16, EMU_CHAN_CPF)
+#define  EMU_CHAN_CPF_STEREO_MASK	0x00008000
+#define  EMU_CHAN_CPF_STEREO	EMU_MKSUBREG(1, 15, EMU_CHAN_CPF)
+#define  EMU_CHAN_CPF_STOP_MASK	0x00004000
+#define  EMU_CHAN_CPF_FRACADDRESS_MASK	0x00003fff
+
+
+#define EMU_CHAN_PTRX	0x01
+#define  EMU_CHAN_PTRX_PITCHTARGET_MASK	0xffff0000
+#define  EMU_CHAN_PTRX_PITCHTARGET	EMU_MKSUBREG(16, 16, EMU_CHAN_PTRX)
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_A_MASK	0x0000ff00
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_A EMU_MKSUBREG(8, 8, EMU_CHAN_PTRX)
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_B_MASK	0x000000ff
+#define  EMU_CHAN_PTRX_FXSENDAMOUNT_B EMU_MKSUBREG(8, 0, EMU_CHAN_PTRX)
+
+#define EMU_CHAN_CVCF	0x02
+#define  EMU_CHAN_CVCF_CURRVOL_MASK	0xffff0000
+#define  EMU_CHAN_CVCF_CURRVOL	EMU_MKSUBREG(16, 16, EMU_CHAN_CVCF)
+#define  EMU_CHAN_CVCF_CURRFILTER_MASK	0x0000ffff
+#define  EMU_CHAN_CVCF_CURRFILTER EMU_MKSUBREG(16, 0, EMU_CHAN_CVCF)
+
+#define EMU_CHAN_VTFT	0x03
+#define  EMU_CHAN_VTFT_VOLUMETARGET_MASK	0xffff0000
+#define  EMU_CHAN_VTFT_VOLUMETARGET	EMU_MKSUBREG(16, 16, EMU_CHAN_VTFT)
+#define  EMU_CHAN_VTFT_FILTERTARGET_MASK	0x0000ffff
+#define	 EMU_CHAN_VTFT_FILTERTARGET	EMU_MKSUBREG(16, 0, EMU_CHAN_VTFT)
+
+#define EMU_CHAN_Z1	0x05
+#define EMU_CHAN_Z2	0x04
+
+#define EMU_CHAN_PSST	0x06
+#define  EMU_CHAN_PSST_FXSENDAMOUNT_C_MASK	0xff000000
+#define  EMU_CHAN_PSST_FXSENDAMOUNT_C EMU_MKSUBREG(8, 24, EMU_CHAN_PSST)
+#define  EMU_CHAN_PSST_LOOPSTARTADDR_MASK	0x00ffffff
+#define  EMU_CHAN_PSST_LOOPSTARTADDR  EMU_MKSUBREG(24, 0, EMU_CHAN_PSST)
+
+#define EMU_CHAN_DSL	0x07
+#define  EMU_CHAN_DSL_FXSENDAMOUNT_D_MASK	0xff000000
+#define  EMU_CHAN_DSL_FXSENDAMOUNT_D  EMU_MKSUBREG(8, 24, EMU_CHAN_DSL)
+#define  EMU_CHAN_DSL_LOOPENDADDR_MASK	0x00ffffff
+#define  EMU_CHAN_DSL_LOOPENDADDR	 EMU_MKSUBREG(24, 0, EMU_CHAN_DSL)
+
+#define EMU_CHAN_CCCA	0x08
+#define  EMU_CHAN_CCCA_RESONANCE		0xf0000000
+#define  EMU_CHAN_CCCA_INTERPROMMASK		0x0e000000
+#define   EMU_CHAN_CCCA_INTERPROM_0		0x00000000
+#define   EMU_CHAN_CCCA_INTERPROM_1		0x02000000
+#define   EMU_CHAN_CCCA_INTERPROM_2		0x04000000
+#define   EMU_CHAN_CCCA_INTERPROM_3		0x06000000
+#define   EMU_CHAN_CCCA_INTERPROM_4		0x08000000
+#define   EMU_CHAN_CCCA_INTERPROM_5		0x0a000000
+#define   EMU_CHAN_CCCA_INTERPROM_6		0x0c000000
+#define   EMU_CHAN_CCCA_INTERPROM_7		0x0e000000
+#define   EMU_CHAN_CCCA_8BITSELECT		0x01000000
+#define  EMU_CHAN_CCCA_CURRADDR_MASK		0x00ffffff
+#define  EMU_CHAN_CCCA_CURRADDR	EMU_MKSUBREG(24, 0, EMU_CHAN_CCCA)
+
+#define EMU_CHAN_CCR	0x09
+#define  EMU_CHAN_CCR_CACHEINVALIDSIZE_MASK	0xfe000000
+#define  EMU_CHAN_CCR_CACHEINVALIDSIZE EMU_MKSUBREG(7, 25, EMU_CHAN_CCR)
+#define  EMU_CHAN_CCR_CACHELOOPFLAG		0x01000000
+#define  EMU_CHAN_CCR_INTERLEAVEDSAMPLES	0x00800000
+#define  EMU_CHAN_CCR_WORDSIZEDSAMPLES	0x00400000
+#define  EMU_CHAN_CCR_READADDRESS_MASK	0x003f0000
+#define  EMU_CHAN_CCR_READADDRESS	EMU_MKSUBREG(6, 16, EMU_CHAN_CCR)
+#define  EMU_CHAN_CCR_LOOPINVALSIZE	0x0000fe00
+#define  EMU_CHAN_CCR_LOOPFLAG		0x00000100
+#define  EMU_CHAN_CCR_CACHELOOPADDRHI	0x000000ff
+
+#define EMU_CHAN_CLP	0x0a
+#define  EMU_CHAN_CLP_CACHELOOPADDR	0x0000ffff
+
+#define EMU_CHAN_FXRT	0x0b
+#define  EMU_CHAN_FXRT_CHANNELA		0x000f0000
+#define  EMU_CHAN_FXRT_CHANNELB		0x00f00000
+#define  EMU_CHAN_FXRT_CHANNELC		0x0f000000
+#define  EMU_CHAN_FXRT_CHANNELD		0xf0000000
+
+#define EMU_CHAN_MAPA	0x0c
+#define EMU_CHAN_MAPB	0x0d
+
+#define  EMU_CHAN_MAP_PTE_MASK		0xffffe000
+#define  EMU_CHAN_MAP_PTI_MASK		0x00001fff
+
+
+#define EMU_CHAN_ENVVOL	0x10
+#define  EMU_CHAN_ENVVOL_MASK		0x0000ffff
+
+
+#define EMU_CHAN_ATKHLDV 0x11
+#define  EMU_CHAN_ATKHLDV_PHASE0	0x00008000
+#define  EMU_CHAN_ATKHLDV_HOLDTIME_MASK	0x00007f00
+#define  EMU_CHAN_ATKHLDV_ATTACKTIME_MASK	0x0000007f
+
+
+#define EMU_CHAN_DCYSUSV	0x12
+#define  EMU_CHAN_DCYSUSV_PHASE1_MASK		0x00008000
+#define  EMU_CHAN_DCYSUSV_SUSTAINLEVEL_MASK	0x00007f00
+#define  EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK	0x00000080
+#define  EMU_CHAN_DCYSUSV_DECAYTIME_MASK	0x0000007f
+
+
+#define EMU_CHAN_LFOVAL1	0x13
+#define  EMU_CHAN_LFOVAL_MASK		0x0000ffff
+
+#define EMU_CHAN_ENVVAL		0x14
+#define  EMU_CHAN_ENVVAL_MASK		0x0000ffff
+
+#define EMU_CHAN_ATKHLDM	0x15
+#define  EMU_CHAN_ATKHLDM_PHASE0	0x00008000
+#define  EMU_CHAN_ATKHLDM_HOLDTIME	0x00007f00
+#define  EMU_CHAN_ATKHLDM_ATTACKTIME	0x0000007f
+
+#define EMU_CHAN_DCYSUSM	0x16
+#define  EMU_CHAN_DCYSUSM_PHASE1_MASK		0x00008000
+#define  EMU_CHAN_DCYSUSM_SUSTAINLEVEL_MASK	0x00007f00
+#define  EMU_CHAN_DCYSUSM_DECAYTIME_MASK	0x0000007f
+
+#define EMU_CHAN_LFOVAL2	0x17
+#define  EMU_CHAN_LFOVAL2_MASK		0x0000ffff
+
+#define EMU_CHAN_IP		0x18
+#define  EMU_CHAN_IP_MASK			0x0000ffff
+#define  EMU_CHAN_IP_UNITY			0x0000e000
+
+#define EMU_CHAN_IFATN		0x19
+#define  EMU_CHAN_IFATN_FILTERCUTOFF_MASK	0x0000ff00
+#define  EMU_CHAN_IFATN_FILTERCUTOFF EMU_MKSUBREG(8, 8,	EMU_CHAN_IFATN)
+#define  EMU_CHAN_IFATN_ATTENUATION_MASK	0x000000ff
+#define  EMU_CHAN_IFATN_ATTENUATION	 EMU_MKSUBREG(8, 0, EMU_CHAN_IFATN)
+
+#define EMU_CHAN_PEFE		0x1a
+#define  EMU_CHAN_PEFE_PITCHAMOUNT_MASK	0x0000ff00
+#define  EMU_CHAN_PEFE_PITCHAMOUNT	EMU_MKSUBREG(8, 8, EMU_CHAN_PEFE)
+#define  EMU_CHAN_PEFE_FILTERAMOUNT_MASK	0x000000ff
+#define  EMU_CHAN_PEFE_FILTERAMOUNT	EMU_MKSUBREG(8, 0, EMU_CHAN_PEFE)
+
+#define EMU_CHAN_FMMOD	0x1b
+#define  EMU_CHAN_FMMOD_MODVIBRATO	0x0000ff00
+#define EMU_CHAN_FMMOD_MOFILTER		0x000000ff
+
+#define EMU_CHAN_TREMFRQ	0x1c
+#define  EMU_CHAN_TREMFRQ_DEPTH		0x0000ff00
+
+#define EMU_CHAN_FM2FRQ2	0x1d
+#define  EMU_CHAN_FM2FRQ2_DEPTH		0x0000ff00
+#define  EMU_CHAN_FM2FRQ2_FREQUENCY	0x000000ff
+
+#define EMU_CHAN_TEMPENV	0x1e
+#define  EMU_CHAN_TEMPENV_MASK		0x0000ffff
+
+#define EMU_CHAN_CD0	0x20
+#define EMU_CHAN_CD1	0x21
+#define EMU_CHAN_CD2	0x22
+#define EMU_CHAN_CD3	0x23
+#define EMU_CHAN_CD4	0x24
+#define EMU_CHAN_CD5	0x25
+#define EMU_CHAN_CD6	0x26
+#define EMU_CHAN_CD7	0x27
+#define EMU_CHAN_CD8	0x28
+#define EMU_CHAN_CD9	0x29
+#define EMU_CHAN_CDA	0x2a
+#define EMU_CHAN_CDB	0x2b
+#define EMU_CHAN_CDC	0x2c
+#define EMU_CHAN_CDD	0x2d
+#define EMU_CHAN_CDE	0x2e
+#define EMU_CHAN_CDF	0x2f
+
+/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
+
+#define EMU_PTB		0x40
+#define  EMU_PTB_MASK			0xfffff000
+
+#define EMU_TCB		0x41
+#define  EMU_TCB_MASK			0xfffff000
+
+#define EMU_ADCCR	0x42
+#define  EMU_ADCCR_RCHANENABLE		0x00000010
+#define  EMU_A_ADCCR_RCHANENABLE	0x00000020
+#define  EMU_ADCCR_LCHANENABLE		0x00000008
+#define  EMU_A_ADCCR_LCHANENABLE	0x00000010
+#define  EMU_ADCCR_SAMPLERATE_MASK	0x00000007
+#define  EMU_A_ADCCR_SAMPLERATE_MASK    0x0000000f
+#define   EMU_ADCCR_SAMPLERATE_48	0x00000000
+#define   EMU_ADCCR_SAMPLERATE_44	0x00000001
+#define   EMU_ADCCR_SAMPLERATE_32	0x00000002
+#define   EMU_ADCCR_SAMPLERATE_24	0x00000003
+#define   EMU_ADCCR_SAMPLERATE_22	0x00000004
+#define   EMU_ADCCR_SAMPLERATE_16	0x00000005
+#define   EMU_A_ADCCR_SAMPLERATE_12	0x00000006
+#define   EMU_ADCCR_SAMPLERATE_11	0x00000006
+#define   EMU_A_ADCCR_SAMPLERATE_11	0x00000007
+#define   EMU_ADCCR_SAMPLERATE_8	0x00000007
+#define   EMU_A_ADCCR_SAMPLERATE_8	0x00000008
+
+#define EMU_FXWC	0x43
+#define EMU_TCBS	0x44
+#define  EMU_TCBS_MASK			0x00000007
+#define   EMU_TCBS_BUFFSIZE_16K		0x00000000
+#define   EMU_TCBS_BUFFSIZE_32K		0x00000001
+#define   EMU_TCBS_BUFFSIZE_64K		0x00000002
+#define   EMU_TCBS_BUFFSIZE_128K	0x00000003
+#define   EMU_TCBS_BUFFSIZE_256K	0x00000004
+#define   EMU_TCBS_BUFFSIZE_512K	0x00000005
+#define   EMU_TCBS_BUFFSIZE_1024K	0x00000006
+#define   EMU_TCBS_BUFFSIZE_2048K	0x00000007
+
+#define EMU_MICBA	0x45
+#define EMU_ADCBA	0x46
+#define EMU_FXBA	0x47
+#define  EMU_RECBA_MASK			0xfffff000
+
+#define EMU_MICBS	0x49
+#define EMU_ADCBS	0x4a
+#define EMU_FXBS	0x4b
+#define  EMU_RECBS_BUFSIZE_NONE		0x00000000
+#define  EMU_RECBS_BUFSIZE_384		0x00000001
+#define  EMU_RECBS_BUFSIZE_448		0x00000002
+#define  EMU_RECBS_BUFSIZE_512		0x00000003
+#define  EMU_RECBS_BUFSIZE_640		0x00000004
+#define  EMU_RECBS_BUFSIZE_768		0x00000005
+#define  EMU_RECBS_BUFSIZE_896		0x00000006
+#define  EMU_RECBS_BUFSIZE_1024		0x00000007
+#define  EMU_RECBS_BUFSIZE_1280		0x00000008
+#define  EMU_RECBS_BUFSIZE_1536		0x00000009
+#define  EMU_RECBS_BUFSIZE_1792		0x0000000a
+#define  EMU_RECBS_BUFSIZE_2048		0x0000000b
+#define  EMU_RECBS_BUFSIZE_2560		0x0000000c
+#define  EMU_RECBS_BUFSIZE_3072		0x0000000d
+#define  EMU_RECBS_BUFSIZE_3584		0x0000000e
+#define  EMU_RECBS_BUFSIZE_4096		0x0000000f
+#define  EMU_RECBS_BUFSIZE_5120		0x00000010
+#define  EMU_RECBS_BUFSIZE_6144		0x00000011
+#define  EMU_RECBS_BUFSIZE_7168		0x00000012
+#define  EMU_RECBS_BUFSIZE_8192		0x00000013
+#define  EMU_RECBS_BUFSIZE_10240	0x00000014
+#define  EMU_RECBS_BUFSIZE_12288	0x00000015
+#define  EMU_RECBS_BUFSIZE_14366	0x00000016
+#define  EMU_RECBS_BUFSIZE_16384	0x00000017
+#define  EMU_RECBS_BUFSIZE_20480	0x00000018
+#define  EMU_RECBS_BUFSIZE_24576	0x00000019
+#define  EMU_RECBS_BUFSIZE_28672	0x0000001a
+#define  EMU_RECBS_BUFSIZE_32768	0x0000001b
+#define  EMU_RECBS_BUFSIZE_40960	0x0000001c
+#define  EMU_RECBS_BUFSIZE_49152	0x0000001d
+#define  EMU_RECBS_BUFSIZE_57344	0x0000001e
+#define  EMU_RECBS_BUFSIZE_65536	0x0000001f
+
+#define EMU_CDCS	0x50
+#define EMU_GPSCS	0x51
+
+#define EMU_DBG		0x52
+#define EMU_DBG_ZC			0x80000000
+#define  EMU_DBG_SATURATION_OCCURRED	0x02000000
+#define  EMU_DBG_SATURATION_ADDR	0x01ff0000
+#define  EMU_DBG_SINGLE_STEP		0x00008000
+#define  EMU_DBG_STEP			0x00004000
+#define  EMU_DBG_CONDITION_CODE		0x00003e00
+#define  EMU_DBG_SINGLE_STEP_ADDR	0x000001ff
+
+#define EMU_A_DBG			0x53
+#define EMU_A_DBG_SINGLE_STEP		0x00020000
+#define EMU_A_DBG_ZC			0x40000000
+#define EMU_A_DBG_STEP_ADDR		0x000003ff
+#define EMU_A_DBG_SATURATION_OCCRD	0x20000000
+#define EMU_A_DBG_SATURATION_ADDR	0x0ffc0000
+
+#define EMU_SPCS0	0x54
+#define EMU_SPCS1	0x55
+#define EMU_SPCS2	0x56
+#define  EMU_SPCS_CLKACCYMASK		0x30000000
+#define   EMU_SPCS_CLKACCY_1000PPM	0x00000000
+#define   EMU_SPCS_CLKACCY_50PPM	0x10000000
+#define   EMU_SPCS_CLKACCY_VARIABLE	0x20000000
+#define  EMU_SPCS_SAMPLERATEMASK	0x0f000000
+#define   EMU_SPCS_SAMPLERATE_44	0x00000000
+#define   EMU_SPCS_SAMPLERATE_48	0x02000000
+#define   EMU_SPCS_SAMPLERATE_32	0x03000000
+#define  EMU_SPCS_CHANNELNUMMASK	0x00f00000
+#define   EMU_SPCS_CHANNELNUM_UNSPEC	0x00000000
+#define   EMU_SPCS_CHANNELNUM_LEFT	0x00100000
+#define   EMU_SPCS_CHANNELNUM_RIGHT	0x00200000
+#define  EMU_SPCS_SOURCENUMMASK		0x000f0000
+#define   EMU_SPCS_SOURCENUM_UNSPEC	0x00000000
+#define  EMU_SPCS_GENERATIONSTATUS	0x00008000
+#define  EMU_SPCS_CATEGORYCODEMASK	0x00007f00
+#define  EMU_SPCS_MODEMASK		0x000000c0
+#define  EMU_SPCS_EMPHASISMASK		0x00000038
+#define   EMU_SPCS_EMPHASIS_NONE	0x00000000
+#define   EMU_SPCS_EMPHASIS_50_15	0x00000008
+#define  EMU_SPCS_COPYRIGHT		0x00000004
+#define  EMU_SPCS_NOTAUDIODATA		0x00000002
+#define  EMU_SPCS_PROFESSIONAL		0x00000001
+
+#define EMU_CLIEL	0x58
+#define EMU_CLIEH	0x59
+#define EMU_CLIPL	0x5a
+#define EMU_CLIPH	0x5b
+#define EMU_SOLEL	0x5c
+#define EMU_SOLEH	0x5d
+
+#define	EMU_SPBYPASS		0x5e
+#define	EMU_SPBYPASS_ENABLE	0x00000001
+#define	EMU_SPBYPASS_24_BITS	0x00000f00
+
+#define	EMU_AC97SLOT		0x5f
+#define	EMU_AC97SLOT_CENTER	0x00000010
+#define	EMU_AC97SLOT_LFE	0x00000020
+
+#define EMU_CDSRCS	0x60
+#define EMU_GPSRCS	0x61
+#define EMU_ZVSRCS	0x62
+#define  EMU_SRCS_SPDIFLOCKED		0x02000000
+#define  EMU_SRCS_RATELOCKED		0x01000000
+#define  EMU_SRCS_ESTSAMPLERATE		0x0007ffff
+
+#define EMU_MICIDX	0x63
+#define EMU_A_MICIDX	0x64
+#define EMU_ADCIDX	0x64
+#define EMU_A_ADCIDX	0x63
+#define EMU_FXIDX	0x65
+#define  EMU_RECIDX_MASK		0x0000ffff
+#define	 EMU_RECIDX(idxreg)	       (0x10000000|(idxreg))
+/*
+#define  EMU_MICIDX_IDX			0x10000063
+#define  EMU_ADCIDX_IDX			0x10000064
+#define  EMU_FXIDX_IDX			0x10000065
+*/
+
+#define EMU_A_MUDATA1		0x70
+#define EMU_A_MUCMD1		0x71
+#define EMU_A_MUSTAT1		EMU_A_MUCMD1
+#define EMU_A_MUDATA2		0x72
+#define EMU_A_MUCMD2		0x73
+#define EMU_A_MUSTAT2		EMU_A_MUCMD2
+#define EMU_A_FXWC1		0x74
+#define EMU_A_FXWC2		0x75
+#define EMU_A_SPDIF_SAMPLERATE	0x76
+#define EMU_A_SPDIF_48000	0x00000080
+#define EMU_A_SPDIF_44100	0x00000000
+#define EMU_A_SPDIF_96000	0x00000040
+#define EMU_A2_SPDIF_SAMPLERATE	EMU_MKSUBREG(3, 9, EMU_A_SPDIF_SAMPLERATE)
+#define EMU_A2_SPDIF_MASK	0x00000e00
+#define EMU_A2_SPDIF_UNKNOWN	0x2
+
+#define EMU_A_CHAN_FXRT2		0x7c
+#define EMU_A_CHAN_FXRT_CHANNELE	0x0000003f
+#define EMU_A_CHAN_FXRT_CHANNELF	0x00003f00
+#define EMU_A_CHAN_FXRT_CHANNELG	0x003f0000
+#define EMU_A_CHAN_FXRT_CHANNELH	0x3f000000
+#define EMU_A_CHAN_SENDAMOUNTS		0x7d
+#define EMU_A_CHAN_FXSENDAMOUNTS_E_MASK	0xff000000
+#define EMU_A_CHAN_FXSENDAMOUNTS_F_MASK	0x00ff0000
+#define EMU_A_CHAN_FXSENDAMOUNTS_G_MASK	0x0000ff00
+#define EMU_A_CHAN_FXSENDAMOUNTS_H_MASK	0x000000ff
+#define EMU_A_CHAN_FXRT1		0x7e
+#define EMU_A_CHAN_FXRT_CHANNELA	0x0000003f
+#define EMU_A_CHAN_FXRT_CHANNELB	0x00003f00
+#define EMU_A_CHAN_FXRT_CHANNELC	0x003f0000
+#define EMU_A_CHAN_FXRT_CHANNELD	0x3f000000
+
+#define EMU_FXGPREGBASE		0x100
+#define EMU_A_FXGPREGBASE	0x400
+
+#define EMU_TANKMEMDATAREGBASE	0x200
+#define  EMU_TANKMEMDATAREG_MASK	0x000fffff
+
+#define EMU_TANKMEMADDRREGBASE	0x300
+#define  EMU_TANKMEMADDRREG_ADDR_MASK	0x000fffff
+#define  EMU_TANKMEMADDRREG_CLEAR	0x00800000
+#define  EMU_TANKMEMADDRREG_ALIGN	0x00400000
+#define  EMU_TANKMEMADDRREG_WRITE	0x00200000
+#define  EMU_TANKMEMADDRREG_READ	0x00100000
+
+#define  EMU_MICROCODEBASE	0x400
+#define  EMU_A_MICROCODEBASE		0x600
+#define  EMU_DSP_LOWORD_OPX_MASK	0x000ffc00
+#define  EMU_DSP_LOWORD_OPY_MASK	0x000003ff
+#define  EMU_DSP_HIWORD_OPCODE_MASK	0x00f00000
+#define  EMU_DSP_HIWORD_RESULT_MASK	0x000ffc00
+#define  EMU_DSP_HIWORD_OPA_MASK	0x000003ff
+#define  EMU_A_DSP_LOWORD_OPX_MASK	0x007ff000
+#define  EMU_A_DSP_LOWORD_OPY_MASK	0x000007ff
+#define  EMU_A_DSP_HIWORD_OPCODE_MASK	0x0f000000
+#define  EMU_A_DSP_HIWORD_RESULT_MASK	0x007ff000
+#define  EMU_A_DSP_HIWORD_OPA_MASK	0x000007ff
+
+#define	EMU_DSP_OP_MACS		0x0
+#define	EMU_DSP_OP_MACS1	0x1
+#define	EMU_DSP_OP_MACW		0x2
+#define	EMU_DSP_OP_MACW1	0x3
+#define	EMU_DSP_OP_MACINTS	0x4
+#define	EMU_DSP_OP_MACINTW	0x5
+#define	EMU_DSP_OP_ACC3		0x6
+#define	EMU_DSP_OP_MACMV	0x7
+#define	EMU_DSP_OP_ANDXOR	0x8
+#define	EMU_DSP_OP_TSTNEG	0x9
+#define	EMU_DSP_OP_LIMIT	0xA
+#define	EMU_DSP_OP_LIMIT1	0xB
+#define	EMU_DSP_OP_LOG		0xC
+#define	EMU_DSP_OP_EXP		0xD
+#define	EMU_DSP_OP_INTERP	0xE
+#define	EMU_DSP_OP_SKIP		0xF
+
+
+#define	EMU_DSP_FX(num)	(num)
+
+#define	EMU_DSP_IOL(base, num)	(base + (num << 1))
+#define	EMU_DSP_IOR(base, num)	(EMU_DSP_IOL(base, num) + 1)
+
+#define	EMU_DSP_INL_BASE	0x010
+#define	EMU_DSP_INL(num)	(EMU_DSP_IOL(EMU_DSP_INL_BASE, num))
+#define	EMU_DSP_INR(num)	(EMU_DSP_IOR(EMU_DSP_INL_BASE, num))
+#define	EMU_A_DSP_INL_BASE	0x040
+#define	EMU_A_DSP_INL(num)	(EMU_DSP_IOL(EMU_A_DSP_INL_BASE, num))
+#define	EMU_A_DSP_INR(num)	(EMU_DSP_IOR(EMU_A_DSP_INL_BASE, num))
+#define	 EMU_DSP_IN_AC97	0
+#define	 EMU_DSP_IN_CDSPDIF	1
+#define  EMU_DSP_IN_ZOOM	2
+#define	 EMU_DSP_IN_TOSOPT	3
+#define	 EMU_DSP_IN_LVDLM1	4
+#define	 EMU_DSP_IN_LVDCOS	5
+#define	 EMU_DSP_IN_LVDLM2	6
+#define	EMU_DSP_IN_UNKNOWN	7
+
+#define	EMU_DSP_OUTL_BASE	0x020
+#define	EMU_DSP_OUTL(num)	(EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num))
+#define	EMU_DSP_OUTR(num)	(EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num))
+#define	EMU_DSP_OUT_A_FRONT	0
+#define	EMU_DSP_OUT_D_FRONT	1
+#define	EMU_DSP_OUT_D_CENTER	2
+#define	EMU_DSP_OUT_DRIVE_HP	3
+#define	EMU_DSP_OUT_AD_REAR	4
+#define	EMU_DSP_OUT_ADC		5
+#define	EMU_DSP_OUTL_MIC	6
+
+#define	EMU_A_DSP_OUTL_BASE	0x060
+#define	EMU_A_DSP_OUTL(num)	(EMU_DSP_IOL(EMU_A_DSP_OUTL_BASE, num))
+#define	EMU_A_DSP_OUTR(num)	(EMU_DSP_IOR(EMU_A_DSP_OUTL_BASE, num))
+#define	EMU_A_DSP_OUT_D_FRONT	0
+#define	EMU_A_DSP_OUT_D_CENTER	1
+#define	EMU_A_DSP_OUT_DRIVE_HP	2
+#define	EMU_A_DSP_OUT_DREAR	3
+#define	EMU_A_DSP_OUT_A_FRONT	4
+#define	EMU_A_DSP_OUT_A_CENTER	5
+#define	EMU_A_DSP_OUT_A_REAR	7
+#define EMU_A_DSP_OUT_ADC	11
+
+#define	EMU_DSP_CST_BASE	0x40
+#define	EMU_A_DSP_CST_BASE	0xc0
+#define	EMU_DSP_CST(num)	(EMU_DSP_CST_BASE + num)
+#define	EMU_A_DSP_CST(num)	(EMU_A_DSP_CST_BASE + num)
+/*
+00	= 0x00000000
+01	= 0x00000001
+02	= 0x00000002
+03	= 0x00000003
+04	= 0x00000004
+05	= 0x00000008
+06	= 0x00000010
+07	= 0x00000020
+08	= 0x00000100
+09	= 0x00010000
+0A	= 0x00080000
+0B	= 0x10000000
+0C	= 0x20000000
+0D	= 0x40000000
+0E	= 0x80000000
+0F	= 0x7FFFFFFF
+10	= 0xFFFFFFFF
+11	= 0xFFFFFFFE
+12	= 0xC0000000
+13	= 0x4F1BBCDC
+14	= 0x5A7EF9DB
+15	= 0x00100000
+*/
+
+#define	EMU_DSP_HWR_ACC		0x056
+#define EMU_DSP_HWR_CCR		0x057
+#define	 EMU_DSP_HWR_CCR_S	0x04
+#define	 EMU_DSP_HWR_CCR_Z	0x03
+#define	 EMU_DSP_HWR_CCR_M	0x02
+#define	 EMU_DSP_HWR_CCR_N	0x01
+#define	 EMU_DSP_HWR_CCR_B	0x00
+#define	EMU_DSP_HWR_NOISE0	0x058
+#define	EMU_DSP_HWR_NOISE1	0x059
+#define	EMU_DSP_HWR_INTR	0x05A
+#define	EMU_DSP_HWR_DBAC	0x05B
+
+#define EMU_DSP_GPR(num)	(EMU_FXGPREGBASE + num)
+#define EMU_A_DSP_GPR(num)	(EMU_A_FXGPREGBASE + num)
+
+#endif /* _DEV_PCI_EMUXKIREG_H_ */
diff --git a/sys/modules/sound/driver/emu10k1/Makefile b/sys/modules/sound/driver/emu10k1/Makefile
index 14fc0c9..ab745f8 100644
--- a/sys/modules/sound/driver/emu10k1/Makefile
+++ b/sys/modules/sound/driver/emu10k1/Makefile
@@ -4,16 +4,8 @@
        ${.CURDIR}/../../../../gnu/dev/sound/pci
 
 KMOD=	snd_emu10k1
-SRCS=	device_if.h bus_if.h pci_if.h emu10k1-alsa%diked.h
+SRCS=	device_if.h bus_if.h emuxkireg.h pci_if.h
 SRCS+= mpufoi_if.h
 SRCS+=	emu10k1.c
 
-CLEANFILES+= emu10k1-alsa%diked.h
-
-emu10k1-alsa%diked.h: emu10k1-alsa.h
-	grep -v '#include' ${.OODATE} | $(CC) -E -D__KERNEL__ -dM - \
-	    | awk -F"[ 	(]" '/define/ \
-	    { print "#ifndef " $$2 ; print ; print "#endif" }' \
-	    >${.TARGET}
-
 .include <bsd.kmod.mk>