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authorjchandra <jchandra@FreeBSD.org>2012-07-09 10:17:06 +0000
committerjchandra <jchandra@FreeBSD.org>2012-07-09 10:17:06 +0000
commitcb0efb3f8e42132a218817041245c4391fdb3173 (patch)
treed5fd267f879e02519b15932af85f52ab8f03a619 /sys
parent4eca468ef2ced3eadac43b69f7f926c443daefb9 (diff)
downloadFreeBSD-src-cb0efb3f8e42132a218817041245c4391fdb3173.zip
FreeBSD-src-cb0efb3f8e42132a218817041245c4391fdb3173.tar.gz
Fix PCIe hardware swap configuration for Netlogic XLP
The last 12 bits of the limit registers have to be set to 1. These bits are not significant in bridge BARs and are 0 on read, but the bits are valid in the swap limit register and needs to be set.
Diffstat (limited to 'sys')
-rw-r--r--sys/mips/nlm/xlp_pci.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/mips/nlm/xlp_pci.c b/sys/mips/nlm/xlp_pci.c
index bd4fd4c..0610a15 100644
--- a/sys/mips/nlm/xlp_pci.c
+++ b/sys/mips/nlm/xlp_pci.c
@@ -507,13 +507,13 @@ xlp_pcib_hardware_swap_enable(int node, int link)
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
- nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar);
+ nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
- nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar);
+ nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
}
static int
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