diff options
| author | simokawa <simokawa@FreeBSD.org> | 2003-03-03 04:10:56 +0000 |
|---|---|---|
| committer | simokawa <simokawa@FreeBSD.org> | 2003-03-03 04:10:56 +0000 |
| commit | ba9b8f5cfc005f6ee31fc335e9b1916a6e52a8e4 (patch) | |
| tree | e9a4b15c812b2454ce907f61d2c3ce027f02cf2f /sys | |
| parent | 23b4d02e5940bcb68418d72dfcceb0d203ae1755 (diff) | |
| download | FreeBSD-src-ba9b8f5cfc005f6ee31fc335e9b1916a6e52a8e4.zip FreeBSD-src-ba9b8f5cfc005f6ee31fc335e9b1916a6e52a8e4.tar.gz | |
Defer allowing async. requests after self ID's have received.
This should fix some problem of SBP2 device probing.
Prior to rev 1.41, we keep writing the register while bus reset phase.
But in rev 1.41, we ignore successive bus reset events and some chips seem to
clear the register after we write to it.
Tested by: Michael Reifenberger <root@nihil.reifenberger.com>
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/firewire/fwohci.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/sys/dev/firewire/fwohci.c b/sys/dev/firewire/fwohci.c index 6a6addb..b6db991 100644 --- a/sys/dev/firewire/fwohci.c +++ b/sys/dev/firewire/fwohci.c @@ -1783,13 +1783,6 @@ fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); #endif fw_busreset(fc); - - OWRITE(sc, OHCI_AREQHI, 1 << 31); - /* XXX insecure ?? */ - OWRITE(sc, OHCI_PREQHI, 0x7fffffff); - OWRITE(sc, OHCI_PREQLO, 0xffffffff); - OWRITE(sc, OHCI_PREQUPPER, 0x10000); - } busresetout: if((stat & OHCI_INT_DMA_IR )){ @@ -1857,6 +1850,12 @@ busresetout: #endif /* Enable bus reset interrupt */ OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); + /* Allow async. request to us */ + OWRITE(sc, OHCI_AREQHI, 1 << 31); + /* XXX insecure ?? */ + OWRITE(sc, OHCI_PREQHI, 0x7fffffff); + OWRITE(sc, OHCI_PREQLO, 0xffffffff); + OWRITE(sc, OHCI_PREQUPPER, 0x10000); /* ** Checking whether the node is root or not. If root, turn on ** cycle master. |
