diff options
author | gonzo <gonzo@FreeBSD.org> | 2009-04-15 02:28:26 +0000 |
---|---|---|
committer | gonzo <gonzo@FreeBSD.org> | 2009-04-15 02:28:26 +0000 |
commit | 2e9f960200f87530cd84a52990e6ba860eb6c295 (patch) | |
tree | 60983c081e4a042108494d5ad65f6b991b704ee1 /sys | |
parent | 7cef6c82d60a94b9e456159bbe5b5fc06151a91a (diff) | |
download | FreeBSD-src-2e9f960200f87530cd84a52990e6ba860eb6c295.zip FreeBSD-src-2e9f960200f87530cd84a52990e6ba860eb6c295.tar.gz |
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
Diffstat (limited to 'sys')
-rw-r--r-- | sys/conf/files.mips | 1 | ||||
-rw-r--r-- | sys/mips/adm5120/obio.c | 2 | ||||
-rw-r--r-- | sys/mips/adm5120/uart_cpu_adm5120.c | 4 | ||||
-rw-r--r-- | sys/mips/alchemy/obio.c | 2 | ||||
-rw-r--r-- | sys/mips/alchemy/uart_cpu_alchemy.c | 4 | ||||
-rw-r--r-- | sys/mips/idt/uart_bus_rc32434.c | 4 | ||||
-rw-r--r-- | sys/mips/idt/uart_cpu_rc32434.c | 4 | ||||
-rw-r--r-- | sys/mips/include/_bus.h | 2 | ||||
-rw-r--r-- | sys/mips/include/bus.h | 1374 | ||||
-rw-r--r-- | sys/mips/malta/gt_pci.c | 67 | ||||
-rw-r--r-- | sys/mips/malta/obio.c | 2 | ||||
-rw-r--r-- | sys/mips/malta/uart_bus_maltausart.c | 4 | ||||
-rw-r--r-- | sys/mips/malta/uart_cpu_maltausart.c | 8 | ||||
-rw-r--r-- | sys/mips/mips/bus_space_generic.c | 570 |
14 files changed, 1215 insertions, 833 deletions
diff --git a/sys/conf/files.mips b/sys/conf/files.mips index bbedd96..3ee1cc6 100644 --- a/sys/conf/files.mips +++ b/sys/conf/files.mips @@ -54,6 +54,7 @@ mips/mips/pm_machdep.c standard mips/mips/swtch.S standard mips/mips/tlb.S standard +mips/mips/bus_space_generic.c standard mips/mips/busdma_machdep.c standard mips/mips/cache.c standard mips/mips/cache_mipsNN.c standard diff --git a/sys/mips/adm5120/obio.c b/sys/mips/adm5120/obio.c index 03e098d..7e61ff5 100644 --- a/sys/mips/adm5120/obio.c +++ b/sys/mips/adm5120/obio.c @@ -269,7 +269,7 @@ obio_activate_resource(device_t bus, device_t child, int type, int rid, vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r)); rman_set_virtual(r, vaddr); - rman_set_bustag(r, MIPS_BUS_SPACE_MEM); + rman_set_bustag(r, &mips_bus_space_generic); rman_set_bushandle(r, (bus_space_handle_t)vaddr); } diff --git a/sys/mips/adm5120/uart_cpu_adm5120.c b/sys/mips/adm5120/uart_cpu_adm5120.c index 59bed5a..0828ea5 100644 --- a/sys/mips/adm5120/uart_cpu_adm5120.c +++ b/sys/mips/adm5120/uart_cpu_adm5120.c @@ -67,7 +67,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->ops = uart_getops(&uart_adm5120_uart_class); di->bas.chan = 0; - di->bas.bst = 0; + di->bas.bst = &mips_bus_space_generic; di->bas.regshft = 0; di->bas.rclk = 0; di->baudrate = 115200; @@ -76,7 +76,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->parity = UART_PARITY_NONE; uart_bus_space_io = 0; - uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(ADM5120_BASE_UART0); + uart_bus_space_mem = &mips_bus_space_generic; di->bas.bsh = MIPS_PHYS_TO_KSEG1(ADM5120_BASE_UART0); return (0); diff --git a/sys/mips/alchemy/obio.c b/sys/mips/alchemy/obio.c index 03e098d..7e61ff5 100644 --- a/sys/mips/alchemy/obio.c +++ b/sys/mips/alchemy/obio.c @@ -269,7 +269,7 @@ obio_activate_resource(device_t bus, device_t child, int type, int rid, vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r)); rman_set_virtual(r, vaddr); - rman_set_bustag(r, MIPS_BUS_SPACE_MEM); + rman_set_bustag(r, &mips_bus_space_generic); rman_set_bushandle(r, (bus_space_handle_t)vaddr); } diff --git a/sys/mips/alchemy/uart_cpu_alchemy.c b/sys/mips/alchemy/uart_cpu_alchemy.c index 931aed6..d38d4cd 100644 --- a/sys/mips/alchemy/uart_cpu_alchemy.c +++ b/sys/mips/alchemy/uart_cpu_alchemy.c @@ -63,7 +63,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; - di->bas.bst = 0; + di->bas.bst = &mips_bus_space_generic; di->bas.regshft = 0; di->bas.rclk = 0; di->baudrate = 115200; @@ -72,7 +72,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->parity = UART_PARITY_NONE; uart_bus_space_io = 0; - uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(UART0_BASE); + uart_bus_space_mem = &mips_bus_space_generic; di->bas.bsh = MIPS_PHYS_TO_KSEG1(UART0_BASE); return (0); diff --git a/sys/mips/idt/uart_bus_rc32434.c b/sys/mips/idt/uart_bus_rc32434.c index 35e937d..78edf62 100644 --- a/sys/mips/idt/uart_bus_rc32434.c +++ b/sys/mips/idt/uart_bus_rc32434.c @@ -88,10 +88,10 @@ uart_rc32434_probe(device_t dev) sc->sc_class = &uart_ns8250_class; bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); sc->sc_sysdev->bas.regshft = 2; - sc->sc_sysdev->bas.bst = 0; + sc->sc_sysdev->bas.bst = &mips_bus_space_generic; sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0); sc->sc_bas.regshft = 2; - sc->sc_bas.bst = 0; + sc->sc_bas.bst = &mips_bus_space_generic; sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0); return (uart_bus_probe(dev, 2, 330000000UL/2, 0, 0)); diff --git a/sys/mips/idt/uart_cpu_rc32434.c b/sys/mips/idt/uart_cpu_rc32434.c index 6bbc5bd..862c8bc 100644 --- a/sys/mips/idt/uart_cpu_rc32434.c +++ b/sys/mips/idt/uart_cpu_rc32434.c @@ -71,7 +71,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) /* Got it. Fill in the instance and return it. */ di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; - di->bas.bst = 0; + di->bas.bst = &mips_bus_space_generic; di->bas.regshft = 2; di->bas.rclk = 330000000UL/2; /* IPbus clock */ di->baudrate = 115200; @@ -79,7 +79,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->stopbits = 1; di->parity = UART_PARITY_NONE; uart_bus_space_io = 0; - uart_bus_space_mem = 0; + uart_bus_space_mem = &mips_bus_space_generic; di->bas.bsh = MIPS_PHYS_TO_KSEG1(maddr); return (0); } diff --git a/sys/mips/include/_bus.h b/sys/mips/include/_bus.h index 74865da..d29a9dc 100644 --- a/sys/mips/include/_bus.h +++ b/sys/mips/include/_bus.h @@ -43,7 +43,7 @@ typedef uintptr_t bus_size_t; /* * Access methods for bus resources and address space. */ -typedef long bus_space_tag_t; +typedef struct bus_space *bus_space_tag_t; typedef u_long bus_space_handle_t; #endif #endif /* MIPS_INCLUDE__BUS_H */ diff --git a/sys/mips/include/bus.h b/sys/mips/include/bus.h index 42ac1df..1136bce 100644 --- a/sys/mips/include/bus.h +++ b/sys/mips/include/bus.h @@ -1,8 +1,7 @@ -/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */ +/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */ + /*- - * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $ - * - * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. + * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation @@ -38,7 +37,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -/* +/*- * Copyright (c) 1996 Charles M. Hannum. All rights reserved. * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. * @@ -68,842 +67,657 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter * $FreeBSD$ -*/ + */ #ifndef _MACHINE_BUS_H_ -#define _MACHINE_BUS_H_ +#define _MACHINE_BUS_H_ -#ifdef TARGET_OCTEON -#include <machine/bus_octeon.h> -#else #include <machine/_bus.h> -#include <machine/cpufunc.h> + +struct bus_space { + /* cookie */ + void *bs_cookie; + + /* mapping/unmapping */ + int (*bs_map) (void *, bus_addr_t, bus_size_t, + int, bus_space_handle_t *); + void (*bs_unmap) (void *, bus_space_handle_t, bus_size_t); + int (*bs_subregion) (void *, bus_space_handle_t, + bus_size_t, bus_size_t, bus_space_handle_t *); + + /* allocation/deallocation */ + int (*bs_alloc) (void *, bus_addr_t, bus_addr_t, + bus_size_t, bus_size_t, bus_size_t, int, + bus_addr_t *, bus_space_handle_t *); + void (*bs_free) (void *, bus_space_handle_t, + bus_size_t); + + /* get kernel virtual address */ + /* barrier */ + void (*bs_barrier) (void *, bus_space_handle_t, + bus_size_t, bus_size_t, int); + + /* read (single) */ + u_int8_t (*bs_r_1) (void *, bus_space_handle_t, bus_size_t); + u_int16_t (*bs_r_2) (void *, bus_space_handle_t, bus_size_t); + u_int32_t (*bs_r_4) (void *, bus_space_handle_t, bus_size_t); + u_int64_t (*bs_r_8) (void *, bus_space_handle_t, bus_size_t); + + /* read multiple */ + void (*bs_rm_1) (void *, bus_space_handle_t, bus_size_t, + u_int8_t *, bus_size_t); + void (*bs_rm_2) (void *, bus_space_handle_t, bus_size_t, + u_int16_t *, bus_size_t); + void (*bs_rm_4) (void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t); + void (*bs_rm_8) (void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t); + + /* read region */ + void (*bs_rr_1) (void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t); + void (*bs_rr_2) (void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t); + void (*bs_rr_4) (void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t); + void (*bs_rr_8) (void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t); + + /* write (single) */ + void (*bs_w_1) (void *, bus_space_handle_t, + bus_size_t, u_int8_t); + void (*bs_w_2) (void *, bus_space_handle_t, + bus_size_t, u_int16_t); + void (*bs_w_4) (void *, bus_space_handle_t, + bus_size_t, u_int32_t); + void (*bs_w_8) (void *, bus_space_handle_t, + bus_size_t, u_int64_t); + + /* write multiple */ + void (*bs_wm_1) (void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t); + void (*bs_wm_2) (void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t); + void (*bs_wm_4) (void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t); + void (*bs_wm_8) (void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t); + + /* write region */ + void (*bs_wr_1) (void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t); + void (*bs_wr_2) (void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t); + void (*bs_wr_4) (void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t); + void (*bs_wr_8) (void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t); + + /* set multiple */ + void (*bs_sm_1) (void *, bus_space_handle_t, + bus_size_t, u_int8_t, bus_size_t); + void (*bs_sm_2) (void *, bus_space_handle_t, + bus_size_t, u_int16_t, bus_size_t); + void (*bs_sm_4) (void *, bus_space_handle_t, + bus_size_t, u_int32_t, bus_size_t); + void (*bs_sm_8) (void *, bus_space_handle_t, + bus_size_t, u_int64_t, bus_size_t); + + /* set region */ + void (*bs_sr_1) (void *, bus_space_handle_t, + bus_size_t, u_int8_t, bus_size_t); + void (*bs_sr_2) (void *, bus_space_handle_t, + bus_size_t, u_int16_t, bus_size_t); + void (*bs_sr_4) (void *, bus_space_handle_t, + bus_size_t, u_int32_t, bus_size_t); + void (*bs_sr_8) (void *, bus_space_handle_t, + bus_size_t, u_int64_t, bus_size_t); + + /* copy */ + void (*bs_c_1) (void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_2) (void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_4) (void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_c_8) (void *, bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + + /* read stream (single) */ + u_int8_t (*bs_r_1_s) (void *, bus_space_handle_t, bus_size_t); + u_int16_t (*bs_r_2_s) (void *, bus_space_handle_t, bus_size_t); + u_int32_t (*bs_r_4_s) (void *, bus_space_handle_t, bus_size_t); + u_int64_t (*bs_r_8_s) (void *, bus_space_handle_t, bus_size_t); + + /* read multiple stream */ + void (*bs_rm_1_s) (void *, bus_space_handle_t, bus_size_t, + u_int8_t *, bus_size_t); + void (*bs_rm_2_s) (void *, bus_space_handle_t, bus_size_t, + u_int16_t *, bus_size_t); + void (*bs_rm_4_s) (void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t); + void (*bs_rm_8_s) (void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t); + + /* read region stream */ + void (*bs_rr_1_s) (void *, bus_space_handle_t, + bus_size_t, u_int8_t *, bus_size_t); + void (*bs_rr_2_s) (void *, bus_space_handle_t, + bus_size_t, u_int16_t *, bus_size_t); + void (*bs_rr_4_s) (void *, bus_space_handle_t, + bus_size_t, u_int32_t *, bus_size_t); + void (*bs_rr_8_s) (void *, bus_space_handle_t, + bus_size_t, u_int64_t *, bus_size_t); + + /* write stream (single) */ + void (*bs_w_1_s) (void *, bus_space_handle_t, + bus_size_t, u_int8_t); + void (*bs_w_2_s) (void *, bus_space_handle_t, + bus_size_t, u_int16_t); + void (*bs_w_4_s) (void *, bus_space_handle_t, + bus_size_t, u_int32_t); + void (*bs_w_8_s) (void *, bus_space_handle_t, + bus_size_t, u_int64_t); + + /* write multiple stream */ + void (*bs_wm_1_s) (void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t); + void (*bs_wm_2_s) (void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t); + void (*bs_wm_4_s) (void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t); + void (*bs_wm_8_s) (void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t); + + /* write region stream */ + void (*bs_wr_1_s) (void *, bus_space_handle_t, + bus_size_t, const u_int8_t *, bus_size_t); + void (*bs_wr_2_s) (void *, bus_space_handle_t, + bus_size_t, const u_int16_t *, bus_size_t); + void (*bs_wr_4_s) (void *, bus_space_handle_t, + bus_size_t, const u_int32_t *, bus_size_t); + void (*bs_wr_8_s) (void *, bus_space_handle_t, + bus_size_t, const u_int64_t *, bus_size_t); +}; + /* - * Values for the mips bus space tag, not to be used directly by MI code. + * Utility macros; INTERNAL USE ONLY. */ -#define MIPS_BUS_SPACE_IO 0 /* space is i/o space */ -#define MIPS_BUS_SPACE_MEM 1 /* space is mem space */ +#define __bs_c(a,b) __CONCAT(a,b) +#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) + +#define __bs_rs(sz, t, h, o) \ + (*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o) +#define __bs_ws(sz, t, h, o, v) \ + (*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v) +#define __bs_nonsingle(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c) +#define __bs_set(type, sz, t, h, o, v, c) \ + (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c) +#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ + (*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt) + +#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s) +#define __bs_rs_s(sz, t, h, o) \ + (*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o) +#define __bs_ws_s(sz, t, h, o, v) \ + (*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v) +#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c) -#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF -#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF -#define BUS_SPACE_MAXSIZE 0xFFFFFFFF /* Maximum supported size */ -#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF -#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF -#define BUS_SPACE_MAXADDR 0xFFFFFFFF +/* + * Mapping and unmapping operations. + */ +#define bus_space_map(t, a, s, c, hp) \ + (*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp)) +#define bus_space_unmap(t, h, s) \ + (*(t)->bs_unmap)((t)->bs_cookie, (h), (s)) +#define bus_space_subregion(t, h, o, s, hp) \ + (*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp)) -#define BUS_SPACE_UNRESTRICTED (~0) /* - * Map a region of device bus space into CPU virtual address space. + * Allocation and deallocation operations. */ +#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \ + (*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \ + (c), (ap), (hp)) +#define bus_space_free(t, h, s) \ + (*(t)->bs_free)((t)->bs_cookie, (h), (s)) -__inline int bus_space_map(bus_space_tag_t t, bus_addr_t addr, - bus_size_t size, int flags, bus_space_handle_t *bshp); - -static __inline int -bus_space_map(bus_space_tag_t t __unused, bus_addr_t addr, - bus_size_t size __unused, int flags __unused, - bus_space_handle_t *bshp) -{ +/* + * Bus barrier operations. + */ +#define bus_space_barrier(t, h, o, l, f) \ + (*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f)) - *bshp = addr; - return (0); -} +#define BUS_SPACE_BARRIER_READ 0x01 +#define BUS_SPACE_BARRIER_WRITE 0x02 /* - * Unmap a region of device bus space. + * Bus read (single) operations. */ +#define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o)) +#define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o)) +#define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o)) +#define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o)) -void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, - bus_size_t size); +#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t), (h), (o)) +#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t), (h), (o)) +#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t), (h), (o)) +#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,8,(t),(h),(o)) /* - * Get a new handle for a subregion of an already-mapped area of bus space. + * Bus read multiple operations. */ +#define bus_space_read_multi_1(t, h, o, a, c) \ + __bs_nonsingle(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_2(t, h, o, a, c) \ + __bs_nonsingle(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_4(t, h, o, a, c) \ + __bs_nonsingle(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_8(t, h, o, a, c) \ + __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) + +#define bus_space_read_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c)) -int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, - bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp); /* - * Allocate a region of memory that is accessible to devices in bus space. + * Bus read region operations. */ +#define bus_space_read_region_1(t, h, o, a, c) \ + __bs_nonsingle(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_2(t, h, o, a, c) \ + __bs_nonsingle(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_4(t, h, o, a, c) \ + __bs_nonsingle(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_8(t, h, o, a, c) \ + __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) + +#define bus_space_read_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c)) -int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, - bus_addr_t rend, bus_size_t size, bus_size_t align, - bus_size_t boundary, int flags, bus_addr_t *addrp, - bus_space_handle_t *bshp); /* - * Free a region of bus space accessible memory. + * Bus write (single) operations. */ +#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v)) +#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v)) +#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v)) +#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v)) -void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, - bus_size_t size); +#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v)) +#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v)) +#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v)) +#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v)) /* - * Read a 1, 2, 4, or 8 byte quantity from bus space - * described by tag/handle/offset. + * Bus write multiple operations. */ -static __inline u_int8_t bus_space_read_1(bus_space_tag_t tag, - bus_space_handle_t handle, - bus_size_t offset); - -static __inline u_int16_t bus_space_read_2(bus_space_tag_t tag, - bus_space_handle_t handle, - bus_size_t offset); - -static __inline u_int32_t bus_space_read_4(bus_space_tag_t tag, - bus_space_handle_t handle, - bus_size_t offset); - -static __inline u_int8_t -bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t handle, - bus_size_t offset) -{ - - if (tag == MIPS_BUS_SPACE_IO) - return (inb(handle + offset)); - return (readb(handle + offset)); -} - -static __inline u_int16_t -bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t handle, - bus_size_t offset) -{ - - if (tag == MIPS_BUS_SPACE_IO) - return (inw(handle + offset)); - return (readw(handle + offset)); -} - -static __inline u_int32_t -bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t handle, - bus_size_t offset) -{ - - if (tag == MIPS_BUS_SPACE_IO) - return (inl(handle + offset)); - return (readl(handle + offset)); -} - -#if 0 /* Cause a link error for bus_space_read_8 */ -#define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!! -#endif +#define bus_space_write_multi_1(t, h, o, a, c) \ + __bs_nonsingle(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_2(t, h, o, a, c) \ + __bs_nonsingle(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_4(t, h, o, a, c) \ + __bs_nonsingle(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_8(t, h, o, a, c) \ + __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle/offset and copy into buffer provided. - */ -static __inline void bus_space_read_multi_1(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int8_t *addr, - size_t count); - -static __inline void bus_space_read_multi_2(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t *addr, - size_t count); - -static __inline void bus_space_read_multi_4(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t *addr, - size_t count); - -static __inline void -bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t *addr, size_t count) -{ - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - *addr++ = inb(bsh + offset); - else - while (count--) - *addr++ = readb(bsh + offset); -} - -static __inline void -bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - *addr++ = inw(baddr); - else - while (count--) - *addr++ = readw(baddr); -} - -static __inline void -bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - *addr++ = inl(baddr); - else - while (count--) - *addr++ = readl(baddr); -} - -#if 0 /* Cause a link error for bus_space_read_multi_8 */ -#define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!! -#endif +#define bus_space_write_multi_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c)) -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle and starting at `offset' and copy into - * buffer provided. - */ -static __inline void bus_space_read_region_1(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int8_t *addr, - size_t count); - -static __inline void bus_space_read_region_2(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t *addr, - size_t count); - -static __inline void bus_space_read_region_4(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t *addr, - size_t count); - - -static __inline void -bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) { - *addr++ = inb(baddr); - baddr += 1; - } - else - while (count--) { - *addr++ = readb(baddr); - baddr += 1; - } -} - -static __inline void -bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) { - *addr++ = inw(baddr); - baddr += 2; - } - else - while (count--) { - *addr++ = readw(baddr); - baddr += 2; - } -} - -static __inline void -bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) { - *addr++ = inl(baddr); - baddr += 4; - } - else - while (count--) { - *addr++ = readb(baddr); - baddr += 4; - } -} - -#if 0 /* Cause a link error for bus_space_read_region_8 */ -#define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!! -#endif /* - * Write the 1, 2, 4, or 8 byte value `value' to bus space - * described by tag/handle/offset. + * Bus write region operations. */ +#define bus_space_write_region_1(t, h, o, a, c) \ + __bs_nonsingle(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_2(t, h, o, a, c) \ + __bs_nonsingle(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_4(t, h, o, a, c) \ + __bs_nonsingle(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_8(t, h, o, a, c) \ + __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) + +#define bus_space_write_region_stream_1(t, h, o, a, c) \ + __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c)) -static __inline void bus_space_write_1(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int8_t value); - -static __inline void bus_space_write_2(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value); - -static __inline void bus_space_write_4(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value); - -static __inline void -bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t value) -{ - - if (tag == MIPS_BUS_SPACE_IO) - outb(bsh + offset, value); - else - writeb(bsh + offset, value); -} - -static __inline void -bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value) -{ - - if (tag == MIPS_BUS_SPACE_IO) - outw(bsh + offset, value); - else - writew(bsh + offset, value); -} - -static __inline void -bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value) -{ - - if (tag == MIPS_BUS_SPACE_IO) - outl(bsh + offset, value); - else - writel(bsh + offset, value); -} - -#if 0 /* Cause a link error for bus_space_write_8 */ -#define bus_space_write_8 !!! bus_space_write_8 not implemented !!! -#endif /* - * Write `count' 1, 2, 4, or 8 byte quantities from the buffer - * provided to bus space described by tag/handle/offset. + * Set multiple operations. */ +#define bus_space_set_multi_1(t, h, o, v, c) \ + __bs_set(sm,1,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_2(t, h, o, v, c) \ + __bs_set(sm,2,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_4(t, h, o, v, c) \ + __bs_set(sm,4,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_8(t, h, o, v, c) \ + __bs_set(sm,8,(t),(h),(o),(v),(c)) -static __inline void bus_space_write_multi_1(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int8_t *addr, - size_t count); -static __inline void bus_space_write_multi_2(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int16_t *addr, - size_t count); - -static __inline void bus_space_write_multi_4(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int32_t *addr, - size_t count); - -static __inline void -bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, const u_int8_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - outb(baddr, *addr++); - else - while (count--) - writeb(baddr, *addr++); -} - -static __inline void -bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, const u_int16_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - outw(baddr, *addr++); - else - while (count--) - writew(baddr, *addr++); -} - -static __inline void -bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, const u_int32_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - outl(baddr, *addr++); - else - while (count--) - writel(baddr, *addr++); -} - -#if 0 /* Cause a link error for bus_space_write_multi_8 */ -#define bus_space_write_multi_8(t, h, o, a, c) \ - !!! bus_space_write_multi_8 unimplemented !!! -#endif /* - * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided - * to bus space described by tag/handle starting at `offset'. + * Set region operations. */ +#define bus_space_set_region_1(t, h, o, v, c) \ + __bs_set(sr,1,(t),(h),(o),(v),(c)) +#define bus_space_set_region_2(t, h, o, v, c) \ + __bs_set(sr,2,(t),(h),(o),(v),(c)) +#define bus_space_set_region_4(t, h, o, v, c) \ + __bs_set(sr,4,(t),(h),(o),(v),(c)) +#define bus_space_set_region_8(t, h, o, v, c) \ + __bs_set(sr,8,(t),(h),(o),(v),(c)) -static __inline void bus_space_write_region_1(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int8_t *addr, - size_t count); -static __inline void bus_space_write_region_2(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int16_t *addr, - size_t count); -static __inline void bus_space_write_region_4(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int32_t *addr, - size_t count); - -static __inline void -bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, const u_int8_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) { - outb(baddr, *addr++); - baddr += 1; - } - else - while (count--) { - writeb(baddr, *addr++); - baddr += 1; - } -} - -static __inline void -bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, const u_int16_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) { - outw(baddr, *addr++); - baddr += 2; - } - else - while (count--) { - writew(baddr, *addr++); - baddr += 2; - } -} - -static __inline void -bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, const u_int32_t *addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) { - outl(baddr, *addr++); - baddr += 4; - } - else - while (count--) { - writel(baddr, *addr++); - baddr += 4; - } -} - -#if 0 /* Cause a link error for bus_space_write_region_8 */ -#define bus_space_write_region_8 \ - !!! bus_space_write_region_8 unimplemented !!! -#endif /* - * Write the 1, 2, 4, or 8 byte value `val' to bus space described - * by tag/handle/offset `count' times. + * Copy operations. */ - -static __inline void bus_space_set_multi_1(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - u_int8_t value, size_t count); -static __inline void bus_space_set_multi_2(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - u_int16_t value, size_t count); -static __inline void bus_space_set_multi_4(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, - u_int32_t value, size_t count); - -static __inline void -bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - outb(addr, value); - else - while (count--) - writeb(addr, value); -} - -static __inline void -bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - outw(addr, value); - else - while (count--) - writew(addr, value); -} - -static __inline void -bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - while (count--) - outl(addr, value); - else - while (count--) - writel(addr, value); -} - -#if 0 /* Cause a link error for bus_space_set_multi_8 */ -#define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!! -#endif +#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ + __bs_copy(1, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ + __bs_copy(2, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ + __bs_copy(4, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ + __bs_copy(8, t, h1, o1, h2, o2, c) /* - * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described - * by tag/handle starting at `offset'. + * Macros to provide prototypes for all the functions used in the + * bus_space structure */ -static __inline void bus_space_set_region_1(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int8_t value, - size_t count); -static __inline void bus_space_set_region_2(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value, - size_t count); -static __inline void bus_space_set_region_4(bus_space_tag_t tag, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value, - size_t count); - -static __inline void -bus_space_set_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - for (; count != 0; count--, addr++) - outb(addr, value); - else - for (; count != 0; count--, addr++) - writeb(addr, value); -} - -static __inline void -bus_space_set_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - for (; count != 0; count--, addr += 2) - outw(addr, value); - else - for (; count != 0; count--, addr += 2) - writew(addr, value); -} - -static __inline void -bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - if (tag == MIPS_BUS_SPACE_IO) - for (; count != 0; count--, addr += 4) - outl(addr, value); - else - for (; count != 0; count--, addr += 4) - writel(addr, value); -} - -#if 0 /* Cause a link error for bus_space_set_region_8 */ -#define bus_space_set_region_8 !!! bus_space_set_region_8 unimplemented !!! -#endif +#define bs_map_proto(f) \ +int __bs_c(f,_bs_map) (void *t, bus_addr_t addr, \ + bus_size_t size, int cacheable, bus_space_handle_t *bshp); -/* - * Copy `count' 1, 2, 4, or 8 byte values from bus space starting - * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. - */ +#define bs_unmap_proto(f) \ +void __bs_c(f,_bs_unmap) (void *t, bus_space_handle_t bsh, \ + bus_size_t size); -static __inline void bus_space_copy_region_1(bus_space_tag_t tag, - bus_space_handle_t bsh1, - bus_size_t off1, - bus_space_handle_t bsh2, - bus_size_t off2, size_t count); - -static __inline void bus_space_copy_region_2(bus_space_tag_t tag, - bus_space_handle_t bsh1, - bus_size_t off1, - bus_space_handle_t bsh2, - bus_size_t off2, size_t count); - -static __inline void bus_space_copy_region_4(bus_space_tag_t tag, - bus_space_handle_t bsh1, - bus_size_t off1, - bus_space_handle_t bsh2, - bus_size_t off2, size_t count); - -static __inline void -bus_space_copy_region_1(bus_space_tag_t tag, bus_space_handle_t bsh1, - bus_size_t off1, bus_space_handle_t bsh2, - bus_size_t off2, size_t count) -{ - bus_addr_t addr1 = bsh1 + off1; - bus_addr_t addr2 = bsh2 + off2; - - if (tag == MIPS_BUS_SPACE_IO) - { - if (addr1 >= addr2) { - /* src after dest: copy forward */ - for (; count != 0; count--, addr1++, addr2++) - outb(addr2, inb(addr1)); - } else { - /* dest after src: copy backwards */ - for (addr1 += (count - 1), addr2 += (count - 1); - count != 0; count--, addr1--, addr2--) - outb(addr2, inb(addr1)); - } - } else { - if (addr1 >= addr2) { - /* src after dest: copy forward */ - for (; count != 0; count--, addr1++, addr2++) - writeb(addr2, readb(addr1)); - } else { - /* dest after src: copy backwards */ - for (addr1 += (count - 1), addr2 += (count - 1); - count != 0; count--, addr1--, addr2--) - writeb(addr2, readb(addr1)); - } - } -} - -static __inline void -bus_space_copy_region_2(bus_space_tag_t tag, bus_space_handle_t bsh1, - bus_size_t off1, bus_space_handle_t bsh2, - bus_size_t off2, size_t count) -{ - bus_addr_t addr1 = bsh1 + off1; - bus_addr_t addr2 = bsh2 + off2; - - if (tag == MIPS_BUS_SPACE_IO) - { - if (addr1 >= addr2) { - /* src after dest: copy forward */ - for (; count != 0; count--, addr1 += 2, addr2 += 2) - outw(addr2, inw(addr1)); - } else { - /* dest after src: copy backwards */ - for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1); - count != 0; count--, addr1 -= 2, addr2 -= 2) - outw(addr2, inw(addr1)); - } - } else { - if (addr1 >= addr2) { - /* src after dest: copy forward */ - for (; count != 0; count--, addr1 += 2, addr2 += 2) - writew(addr2, readw(addr1)); - } else { - /* dest after src: copy backwards */ - for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1); - count != 0; count--, addr1 -= 2, addr2 -= 2) - writew(addr2, readw(addr1)); - } - } -} - -static __inline void -bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1, - bus_size_t off1, bus_space_handle_t bsh2, - bus_size_t off2, size_t count) -{ - bus_addr_t addr1 = bsh1 + off1; - bus_addr_t addr2 = bsh2 + off2; - - if (tag == MIPS_BUS_SPACE_IO) - { - if (addr1 >= addr2) { - /* src after dest: copy forward */ - for (; count != 0; count--, addr1 += 4, addr2 += 4) - outl(addr2, inl(addr1)); - } else { - /* dest after src: copy backwards */ - for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1); - count != 0; count--, addr1 -= 4, addr2 -= 4) - outl(addr2, inl(addr1)); - } - } else { - if (addr1 >= addr2) { - /* src after dest: copy forward */ - for (; count != 0; count--, addr1 += 4, addr2 += 4) - writel(addr2, readl(addr1)); - } else { - /* dest after src: copy backwards */ - for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1); - count != 0; count--, addr1 -= 4, addr2 -= 4) - writel(addr2, readl(addr1)); - } - } -} - - -#if 0 /* Cause a link error for bus_space_copy_8 */ -#define bus_space_copy_region_8 !!! bus_space_copy_region_8 unimplemented !!! -#endif +#define bs_subregion_proto(f) \ +int __bs_c(f,_bs_subregion) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, bus_size_t size, \ + bus_space_handle_t *nbshp); +#define bs_alloc_proto(f) \ +int __bs_c(f,_bs_alloc) (void *t, bus_addr_t rstart, \ + bus_addr_t rend, bus_size_t size, bus_size_t align, \ + bus_size_t boundary, int cacheable, bus_addr_t *addrp, \ + bus_space_handle_t *bshp); -/* - * Bus read/write barrier methods. - * - * void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, - * bus_size_t offset, bus_size_t len, int flags); - * - * - * Note that BUS_SPACE_BARRIER_WRITE doesn't do anything other than - * prevent reordering by the compiler; all Intel x86 processors currently - * retire operations outside the CPU in program order. - */ -#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ -#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ - -static __inline void -bus_space_barrier(bus_space_tag_t tag __unused, bus_space_handle_t bsh __unused, - bus_size_t offset __unused, bus_size_t len __unused, int flags) -{ -#if 0 -#ifdef __GNUCLIKE_ASM - if (flags & BUS_SPACE_BARRIER_READ) - __asm __volatile("lock; addl $0,0(%%rsp)" : : : "memory"); - else - __asm __volatile("" : : : "memory"); -#endif -#endif -} - -#ifdef BUS_SPACE_NO_LEGACY -#undef inb -#undef outb -#define inb(a) compiler_error -#define inw(a) compiler_error -#define inl(a) compiler_error -#define outb(a, b) compiler_error -#define outw(a, b) compiler_error -#define outl(a, b) compiler_error -#endif +#define bs_free_proto(f) \ +void __bs_c(f,_bs_free) (void *t, bus_space_handle_t bsh, \ + bus_size_t size); -#include <machine/bus_dma.h> +#define bs_barrier_proto(f) \ +void __bs_c(f,_bs_barrier) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, bus_size_t len, int flags); -/* - * Stream accesses are the same as normal accesses on amd64; there are no - * supported bus systems with an endianess different from the host one. +#define bs_r_1_proto(f) \ +u_int8_t __bs_c(f,_bs_r_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_2_proto(f) \ +u_int16_t __bs_c(f,_bs_r_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_4_proto(f) \ +u_int32_t __bs_c(f,_bs_r_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_8_proto(f) \ +u_int64_t __bs_c(f,_bs_r_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_1_s_proto(f) \ +u_int8_t __bs_c(f,_bs_r_1_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_2_s_proto(f) \ +u_int16_t __bs_c(f,_bs_r_2_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_r_4_s_proto(f) \ +u_int32_t __bs_c(f,_bs_r_4_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset); + +#define bs_w_1_proto(f) \ +void __bs_c(f,_bs_w_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value); + +#define bs_w_2_proto(f) \ +void __bs_c(f,_bs_w_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value); + +#define bs_w_4_proto(f) \ +void __bs_c(f,_bs_w_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value); + +#define bs_w_8_proto(f) \ +void __bs_c(f,_bs_w_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t value); + +#define bs_w_1_s_proto(f) \ +void __bs_c(f,_bs_w_1_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value); + +#define bs_w_2_s_proto(f) \ +void __bs_c(f,_bs_w_2_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value); + +#define bs_w_4_s_proto(f) \ +void __bs_c(f,_bs_w_4_s) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value); + +#define bs_rm_1_proto(f) \ +void __bs_c(f,_bs_rm_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t *addr, bus_size_t count); + +#define bs_rm_2_proto(f) \ +void __bs_c(f,_bs_rm_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t *addr, bus_size_t count); + +#define bs_rm_4_proto(f) \ +void __bs_c(f,_bs_rm_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t *addr, bus_size_t count); + +#define bs_rm_8_proto(f) \ +void __bs_c(f,_bs_rm_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t *addr, bus_size_t count); + +#define bs_wm_1_proto(f) \ +void __bs_c(f,_bs_wm_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int8_t *addr, bus_size_t count); + +#define bs_wm_2_proto(f) \ +void __bs_c(f,_bs_wm_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int16_t *addr, bus_size_t count); + +#define bs_wm_4_proto(f) \ +void __bs_c(f,_bs_wm_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int32_t *addr, bus_size_t count); + +#define bs_wm_8_proto(f) \ +void __bs_c(f,_bs_wm_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int64_t *addr, bus_size_t count); + +#define bs_rr_1_proto(f) \ +void __bs_c(f, _bs_rr_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t *addr, bus_size_t count); + +#define bs_rr_2_proto(f) \ +void __bs_c(f, _bs_rr_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t *addr, bus_size_t count); + +#define bs_rr_4_proto(f) \ +void __bs_c(f, _bs_rr_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t *addr, bus_size_t count); + +#define bs_rr_8_proto(f) \ +void __bs_c(f, _bs_rr_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t *addr, bus_size_t count); + +#define bs_wr_1_proto(f) \ +void __bs_c(f, _bs_wr_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int8_t *addr, bus_size_t count); + +#define bs_wr_2_proto(f) \ +void __bs_c(f, _bs_wr_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int16_t *addr, bus_size_t count); + +#define bs_wr_4_proto(f) \ +void __bs_c(f, _bs_wr_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int32_t *addr, bus_size_t count); + +#define bs_wr_8_proto(f) \ +void __bs_c(f, _bs_wr_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, const u_int64_t *addr, bus_size_t count); + +#define bs_sm_1_proto(f) \ +void __bs_c(f,_bs_sm_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value, bus_size_t count); + +#define bs_sm_2_proto(f) \ +void __bs_c(f,_bs_sm_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value, bus_size_t count); + +#define bs_sm_4_proto(f) \ +void __bs_c(f,_bs_sm_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value, bus_size_t count); + +#define bs_sm_8_proto(f) \ +void __bs_c(f,_bs_sm_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t value, bus_size_t count); + +#define bs_sr_1_proto(f) \ +void __bs_c(f,_bs_sr_1) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int8_t value, bus_size_t count); + +#define bs_sr_2_proto(f) \ +void __bs_c(f,_bs_sr_2) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int16_t value, bus_size_t count); + +#define bs_sr_4_proto(f) \ +void __bs_c(f,_bs_sr_4) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int32_t value, bus_size_t count); + +#define bs_sr_8_proto(f) \ +void __bs_c(f,_bs_sr_8) (void *t, bus_space_handle_t bsh, \ + bus_size_t offset, u_int64_t value, bus_size_t count); + +#define bs_c_1_proto(f) \ +void __bs_c(f,_bs_c_1) (void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define bs_c_2_proto(f) \ +void __bs_c(f,_bs_c_2) (void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define bs_c_4_proto(f) \ +void __bs_c(f,_bs_c_4) (void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define bs_c_8_proto(f) \ +void __bs_c(f,_bs_c_8) (void *t, bus_space_handle_t bsh1, \ + bus_size_t offset1, bus_space_handle_t bsh2, \ + bus_size_t offset2, bus_size_t count); + +#define DECLARE_BUS_SPACE_PROTOTYPES(f) \ + bs_map_proto(f); \ + bs_unmap_proto(f); \ + bs_subregion_proto(f); \ + bs_alloc_proto(f); \ + bs_free_proto(f); \ + bs_barrier_proto(f); \ + bs_r_1_proto(f); \ + bs_r_2_proto(f); \ + bs_r_4_proto(f); \ + bs_r_8_proto(f); \ + bs_r_1_s_proto(f); \ + bs_r_2_s_proto(f); \ + bs_r_4_s_proto(f); \ + bs_w_1_proto(f); \ + bs_w_2_proto(f); \ + bs_w_4_proto(f); \ + bs_w_8_proto(f); \ + bs_w_1_s_proto(f); \ + bs_w_2_s_proto(f); \ + bs_w_4_s_proto(f); \ + bs_rm_1_proto(f); \ + bs_rm_2_proto(f); \ + bs_rm_4_proto(f); \ + bs_rm_8_proto(f); \ + bs_wm_1_proto(f); \ + bs_wm_2_proto(f); \ + bs_wm_4_proto(f); \ + bs_wm_8_proto(f); \ + bs_rr_1_proto(f); \ + bs_rr_2_proto(f); \ + bs_rr_4_proto(f); \ + bs_rr_8_proto(f); \ + bs_wr_1_proto(f); \ + bs_wr_2_proto(f); \ + bs_wr_4_proto(f); \ + bs_wr_8_proto(f); \ + bs_sm_1_proto(f); \ + bs_sm_2_proto(f); \ + bs_sm_4_proto(f); \ + bs_sm_8_proto(f); \ + bs_sr_1_proto(f); \ + bs_sr_2_proto(f); \ + bs_sr_4_proto(f); \ + bs_sr_8_proto(f); \ + bs_c_1_proto(f); \ + bs_c_2_proto(f); \ + bs_c_4_proto(f); \ + bs_c_8_proto(f); + +#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) + +#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF +#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXADDR 0xFFFFFFFF +#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF +#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXSIZE 0xFFFFFFFF + +/* + * declare generic bus space, it suits all needs in */ -#define bus_space_read_stream_1(t, h, o) bus_space_read_1((t), (h), (o)) -#define bus_space_read_stream_2(t, h, o) bus_space_read_2((t), (h), (o)) -#define bus_space_read_stream_4(t, h, o) bus_space_read_4((t), (h), (o)) - -#define bus_space_read_multi_stream_1(t, h, o, a, c) \ - bus_space_read_multi_1((t), (h), (o), (a), (c)) -#define bus_space_read_multi_stream_2(t, h, o, a, c) \ - bus_space_read_multi_2((t), (h), (o), (a), (c)) -#define bus_space_read_multi_stream_4(t, h, o, a, c) \ - bus_space_read_multi_4((t), (h), (o), (a), (c)) - -#define bus_space_write_stream_1(t, h, o, v) \ - bus_space_write_1((t), (h), (o), (v)) -#define bus_space_write_stream_2(t, h, o, v) \ - bus_space_write_2((t), (h), (o), (v)) -#define bus_space_write_stream_4(t, h, o, v) \ - bus_space_write_4((t), (h), (o), (v)) - -#define bus_space_write_multi_stream_1(t, h, o, a, c) \ - bus_space_write_multi_1((t), (h), (o), (a), (c)) -#define bus_space_write_multi_stream_2(t, h, o, a, c) \ - bus_space_write_multi_2((t), (h), (o), (a), (c)) -#define bus_space_write_multi_stream_4(t, h, o, a, c) \ - bus_space_write_multi_4((t), (h), (o), (a), (c)) - -#define bus_space_set_multi_stream_1(t, h, o, v, c) \ - bus_space_set_multi_1((t), (h), (o), (v), (c)) -#define bus_space_set_multi_stream_2(t, h, o, v, c) \ - bus_space_set_multi_2((t), (h), (o), (v), (c)) -#define bus_space_set_multi_stream_4(t, h, o, v, c) \ - bus_space_set_multi_4((t), (h), (o), (v), (c)) - -#define bus_space_read_region_stream_1(t, h, o, a, c) \ - bus_space_read_region_1((t), (h), (o), (a), (c)) -#define bus_space_read_region_stream_2(t, h, o, a, c) \ - bus_space_read_region_2((t), (h), (o), (a), (c)) -#define bus_space_read_region_stream_4(t, h, o, a, c) \ - bus_space_read_region_4((t), (h), (o), (a), (c)) - -#define bus_space_write_region_stream_1(t, h, o, a, c) \ - bus_space_write_region_1((t), (h), (o), (a), (c)) -#define bus_space_write_region_stream_2(t, h, o, a, c) \ - bus_space_write_region_2((t), (h), (o), (a), (c)) -#define bus_space_write_region_stream_4(t, h, o, a, c) \ - bus_space_write_region_4((t), (h), (o), (a), (c)) - -#define bus_space_set_region_stream_1(t, h, o, v, c) \ - bus_space_set_region_1((t), (h), (o), (v), (c)) -#define bus_space_set_region_stream_2(t, h, o, v, c) \ - bus_space_set_region_2((t), (h), (o), (v), (c)) -#define bus_space_set_region_stream_4(t, h, o, v, c) \ - bus_space_set_region_4((t), (h), (o), (v), (c)) - -#define bus_space_copy_region_stream_1(t, h1, o1, h2, o2, c) \ - bus_space_copy_region_1((t), (h1), (o1), (h2), (o2), (c)) -#define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \ - bus_space_copy_region_2((t), (h1), (o1), (h2), (o2), (c)) -#define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \ - bus_space_copy_region_4((t), (h1), (o1), (h2), (o2), (c)) - -#endif /* !TARGET_OCTEON */ -#endif /* !_MACHINE_BUS_H_ */ +DECLARE_BUS_SPACE_PROTOTYPES(generic); +extern struct bus_space mips_bus_space_generic; +#include <machine/bus_dma.h> + +#endif /* _MACHINE_BUS_H_ */ diff --git a/sys/mips/malta/gt_pci.c b/sys/mips/malta/gt_pci.c index e8f7ffd..61e39b8 100644 --- a/sys/mips/malta/gt_pci.c +++ b/sys/mips/malta/gt_pci.c @@ -94,8 +94,6 @@ __FBSDID("$FreeBSD$"); struct gt_pci_softc { device_t sc_dev; bus_space_tag_t sc_st; - bus_space_tag_t sc_pciio; - bus_space_tag_t sc_pcimem; bus_space_handle_t sc_ioh_icu1; bus_space_handle_t sc_ioh_icu2; bus_space_handle_t sc_ioh_elcr; @@ -126,14 +124,14 @@ gt_pci_set_icus(struct gt_pci_softc *sc) else sc->sc_imask |= (1U << 2); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1, sc->sc_imask & 0xff); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, PIC_OCW1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1, (sc->sc_imask >> 8) & 0xff); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0, sc->sc_elcr & 0xff); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1, (sc->sc_elcr >> 8) & 0xff); } @@ -145,9 +143,9 @@ gt_pci_intr(void *v) int irq; for (;;) { - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3, OCW3_SEL | OCW3_P); - irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3); + irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3); if ((irq & OCW3_POLL_PENDING) == 0) { return FILTER_HANDLED; @@ -156,9 +154,9 @@ gt_pci_intr(void *v) irq = OCW3_POLL_IRQ(irq); if (irq == 2) { - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW3, OCW3_SEL | OCW3_P); - irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu2, + irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW3); if (irq & OCW3_POLL_PENDING) irq = OCW3_POLL_IRQ(irq) + 8; @@ -177,13 +175,13 @@ gt_pci_intr(void *v) /* Send a specific EOI to the 8259. */ if (irq > 7) { - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq & 7)); irq = 2; } - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW2, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq)); } @@ -208,8 +206,7 @@ gt_pci_attach(device_t dev) busno = 0; sc->sc_dev = dev; sc->sc_busno = busno; - sc->sc_pciio = MIPS_BUS_SPACE_IO; - sc->sc_pcimem = MIPS_BUS_SPACE_MEM; + sc->sc_st = &mips_bus_space_generic; /* Use KSEG1 to access IO ports for it is uncached */ sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE); @@ -239,11 +236,11 @@ gt_pci_attach(device_t dev) * Map the PIC/ELCR registers. */ #if 0 - if (bus_space_map(sc->sc_pciio, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0) + if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0) device_printf(dev, "unable to map ELCR registers\n"); - if (bus_space_map(sc->sc_pciio, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0) + if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0) device_printf(dev, "unable to map ICU1 registers\n"); - if (bus_space_map(sc->sc_pciio, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0) + if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0) device_printf(dev, "unable to map ICU2 registers\n"); #else sc->sc_ioh_elcr = sc->sc_io + 0x4d0; @@ -262,58 +259,58 @@ gt_pci_attach(device_t dev) * Initialize the 8259s. */ /* reset, program device, 4 bytes */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, ICW1_RESET | ICW1_IC4); /* * XXX: values from NetBSD's <dev/ic/i8259reg.h> */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 0/*XXX*/); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 1 << 2); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, OCW3_SEL | OCW3_RR); /* reset, program device, 4 bytes */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, ICW1_RESET | ICW1_IC4); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 0/*XXX*/); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 1 << 2); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, OCW3_SEL | OCW3_RR); /* * Default all interrupts to edge-triggered. */ - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0, sc->sc_elcr & 0xff); - bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1, (sc->sc_elcr >> 8) & 0xff); /* @@ -570,12 +567,12 @@ gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, break; case SYS_RES_MEMORY: rm = &sc->sc_mem_rman; - bt = sc->sc_pcimem; + bt = sc->sc_st; bh = sc->sc_mem; break; case SYS_RES_IOPORT: rm = &sc->sc_io_rman; - bt = sc->sc_pciio; + bt = sc->sc_st; bh = sc->sc_io; break; default: diff --git a/sys/mips/malta/obio.c b/sys/mips/malta/obio.c index ae486ed..1f00080 100644 --- a/sys/mips/malta/obio.c +++ b/sys/mips/malta/obio.c @@ -84,7 +84,7 @@ obio_attach(device_t dev) { struct obio_softc *sc = device_get_softc(dev); - sc->oba_st = MIPS_BUS_SPACE_IO; + sc->oba_st = &mips_bus_space_generic; sc->oba_addr = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); sc->oba_size = MALTA_PCIMEM3_SIZE; sc->oba_rman.rm_type = RMAN_ARRAY; diff --git a/sys/mips/malta/uart_bus_maltausart.c b/sys/mips/malta/uart_bus_maltausart.c index da266a8..57f8ce3 100644 --- a/sys/mips/malta/uart_bus_maltausart.c +++ b/sys/mips/malta/uart_bus_maltausart.c @@ -88,9 +88,9 @@ uart_malta_probe(device_t dev) sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); sc->sc_class = &uart_ns8250_class; bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - sc->sc_sysdev->bas.bst = 0; + sc->sc_sysdev->bas.bst = &mips_bus_space_generic; sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); - sc->sc_bas.bst = 0; + sc->sc_bas.bst = &mips_bus_space_generic; sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); return(uart_bus_probe(dev, 0, 0, 0, 0)); } diff --git a/sys/mips/malta/uart_cpu_maltausart.c b/sys/mips/malta/uart_cpu_maltausart.c index 758d9a7..d25ce5c 100644 --- a/sys/mips/malta/uart_cpu_maltausart.c +++ b/sys/mips/malta/uart_cpu_maltausart.c @@ -67,7 +67,8 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) { di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; - di->bas.bst = 0; + di->bas.bst = &mips_bus_space_generic; + di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); di->bas.regshft = 0; di->bas.rclk = 0; di->baudrate = 115200; @@ -75,8 +76,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->stopbits = 1; di->parity = UART_PARITY_NONE; - uart_bus_space_io = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); - uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); - di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR); + uart_bus_space_io = NULL; + uart_bus_space_mem = &mips_bus_space_generic; return (0); } diff --git a/sys/mips/mips/bus_space_generic.c b/sys/mips/mips/bus_space_generic.c new file mode 100644 index 0000000..981cc52 --- /dev/null +++ b/sys/mips/mips/bus_space_generic.c @@ -0,0 +1,570 @@ +/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */ +/*- + * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $ + * + * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1996 Charles M. Hannum. All rights reserved. + * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter + * $FreeBSD$ + */ +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/ktr.h> + +#include <vm/vm.h> +#include <vm/pmap.h> +#include <vm/vm_kern.h> +#include <vm/vm_extern.h> + +#include <machine/bus.h> +#include <machine/cache.h> + +struct bus_space mips_bus_space_generic = { + /* cookie */ + (void *) 0, + + /* mapping/unmapping */ + generic_bs_map, + generic_bs_unmap, + generic_bs_subregion, + + /* allocation/deallocation */ + NULL, + NULL, + + /* barrier */ + generic_bs_barrier, + + /* read (single) */ + generic_bs_r_1, + generic_bs_r_2, + generic_bs_r_4, + NULL, + + /* read multiple */ + generic_bs_rm_1, + generic_bs_rm_2, + generic_bs_rm_4, + NULL, + + /* read region */ + generic_bs_rr_1, + generic_bs_rr_2, + generic_bs_rr_4, + NULL, + + /* write (single) */ + generic_bs_w_1, + generic_bs_w_2, + generic_bs_w_4, + NULL, + + /* write multiple */ + generic_bs_wm_1, + generic_bs_wm_2, + generic_bs_wm_4, + NULL, + + /* write region */ + NULL, + generic_bs_wr_2, + generic_bs_wr_4, + NULL, + + /* set multiple */ + NULL, + NULL, + NULL, + NULL, + + /* set region */ + NULL, + generic_bs_sr_2, + generic_bs_sr_4, + NULL, + + /* copy */ + NULL, + generic_bs_c_2, + NULL, + NULL, + + /* read (single) stream */ + generic_bs_r_1, + generic_bs_r_2, + generic_bs_r_4, + NULL, + + /* read multiple stream */ + generic_bs_rm_1, + generic_bs_rm_2, + generic_bs_rm_4, + NULL, + + /* read region stream */ + generic_bs_rr_1, + generic_bs_rr_2, + generic_bs_rr_4, + NULL, + + /* write (single) stream */ + generic_bs_w_1, + generic_bs_w_2, + generic_bs_w_4, + NULL, + + /* write multiple stream */ + generic_bs_wm_1, + generic_bs_wm_2, + generic_bs_wm_4, + NULL, + + /* write region stream */ + NULL, + generic_bs_wr_2, + generic_bs_wr_4, + NULL, +}; + + + +int +generic_bs_map(void *t __unused, bus_addr_t addr, + bus_size_t size __unused, int flags __unused, + bus_space_handle_t *bshp) +{ + + *bshp = addr; + return (0); +} + +void +generic_bs_unmap(void *t __unused, bus_space_handle_t bh __unused, + bus_size_t size __unused) +{ + + /* Do nothing */ +} + +int +generic_bs_subregion(void *t __unused, bus_space_handle_t handle __unused, + bus_size_t offset __unused, bus_size_t size __unused, + bus_space_handle_t *nhandle __unused) +{ + + printf("SUBREGION?!?!?!\n"); + /* Do nothing */ + return (0); +} + +u_int8_t +generic_bs_r_1(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + + return (readb(handle + offset)); +} + +u_int16_t +generic_bs_r_2(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + + return (readw(handle + offset)); +} + +u_int32_t +generic_bs_r_4(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + + return (readl(handle + offset)); +} + + +void +generic_bs_rm_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t *addr, size_t count) +{ + + while (count--) + *addr++ = readb(bsh + offset); +} + +void +generic_bs_rm_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) + *addr++ = readw(baddr); +} + +void +generic_bs_rm_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) + *addr++ = readl(baddr); +} + + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle and starting at `offset' and copy into + * buffer provided. + */ +void +generic_bs_rr_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = readb(baddr); + baddr += 1; + } +} + +void +generic_bs_rr_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = readw(baddr); + baddr += 2; + } +} + +void +generic_bs_rr_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = readl(baddr); + baddr += 4; + } +} + +/* + * Write the 1, 2, 4, or 8 byte value `value' to bus space + * described by tag/handle/offset. + */ +void +generic_bs_w_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value) +{ + + writeb(bsh + offset, value); +} + +void +generic_bs_w_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value) +{ + + writew(bsh + offset, value); +} + +void +generic_bs_w_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value) +{ + + writel(bsh + offset, value); +} + +/* + * Write `count' 1, 2, 4, or 8 byte quantities from the buffer + * provided to bus space described by tag/handle/offset. + */ +void +generic_bs_wm_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int8_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) + writeb(baddr, *addr++); +} + +void +generic_bs_wm_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int16_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) + writew(baddr, *addr++); +} + +void +generic_bs_wm_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int32_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) + writel(baddr, *addr++); +} + +/* + * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided + * to bus space described by tag/handle starting at `offset'. + */ +void +generic_bs_wr_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int8_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + writeb(baddr, *addr++); + baddr += 1; + } +} + +void +generic_bs_wr_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int16_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + writew(baddr, *addr++); + baddr += 2; + } +} + +void +generic_bs_wr_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int32_t *addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + writel(baddr, *addr++); + baddr += 4; + } +} + +/* + * Write the 1, 2, 4, or 8 byte value `val' to bus space described + * by tag/handle/offset `count' times. + */ +void +generic_bs_sm_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + while (count--) + writeb(addr, value); +} + +void +generic_bs_sm_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + while (count--) + writew(addr, value); +} + +void +generic_bs_sm_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + while (count--) + writel(addr, value); +} + +/* + * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described + * by tag/handle starting at `offset'. + */ +void +generic_bs_sr_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr++) + writeb(addr, value); +} + +void +generic_bs_sr_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 2) + writew(addr, value); +} + +void +generic_bs_sr_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 4) + writel(addr, value); +} + +/* + * Copy `count' 1, 2, 4, or 8 byte values from bus space starting + * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. + */ +void +generic_bs_c_1(void *t, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, + bus_size_t off2, size_t count) +{ + bus_addr_t addr1 = bsh1 + off1; + bus_addr_t addr2 = bsh2 + off2; + + if (addr1 >= addr2) { + /* src after dest: copy forward */ + for (; count != 0; count--, addr1++, addr2++) + writeb(addr2, readb(addr1)); + } else { + /* dest after src: copy backwards */ + for (addr1 += (count - 1), addr2 += (count - 1); + count != 0; count--, addr1--, addr2--) + writeb(addr2, readb(addr1)); + } +} + +void +generic_bs_c_2(void *t, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, + bus_size_t off2, size_t count) +{ + bus_addr_t addr1 = bsh1 + off1; + bus_addr_t addr2 = bsh2 + off2; + + if (addr1 >= addr2) { + /* src after dest: copy forward */ + for (; count != 0; count--, addr1 += 2, addr2 += 2) + writew(addr2, readw(addr1)); + } else { + /* dest after src: copy backwards */ + for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1); + count != 0; count--, addr1 -= 2, addr2 -= 2) + writew(addr2, readw(addr1)); + } +} + +void +generic_bs_c_4(void *t, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, + bus_size_t off2, size_t count) +{ + bus_addr_t addr1 = bsh1 + off1; + bus_addr_t addr2 = bsh2 + off2; + + if (addr1 >= addr2) { + /* src after dest: copy forward */ + for (; count != 0; count--, addr1 += 4, addr2 += 4) + writel(addr2, readl(addr1)); + } else { + /* dest after src: copy backwards */ + for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1); + count != 0; count--, addr1 -= 4, addr2 -= 4) + writel(addr2, readl(addr1)); + } +} + +void +generic_bs_barrier(void *t __unused, + bus_space_handle_t bsh __unused, + bus_size_t offset __unused, bus_size_t len __unused, + int flags) +{ +#if 0 + if (flags & BUS_SPACE_BARRIER_WRITE) + mips_dcache_wbinv_all(); +#endif +} |