Always initialize the UPA target module id in the interrupt mapping

register to the one of the processor doing the interrupt setup. This
is required since this field is preinitialized to 0, but there exist
machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2
processors).

Add some more macros for handle the interrupt mapping registers, and
rename some existing ones for consistency.

Approved by:	re

3 files changed, 34 insertions, 33 deletions

diff --git a/sys/sparc64/include/bus_common.h b/sys/sparc64/include/bus_common.h
index 8d74ead..c8d7450 100644
--- a/sys/sparc64/include/bus_common.h
+++ b/sys/sparc64/include/bus_common.h
@@ -48,23 +48,24 @@
 #ifndef _MACHINE_BUS_COMMON_H_
 #define _MACHINE_BUS_COMMON_H_
 
-#define INTMAP_V	0x080000000LL	/* Interrupt valid (enabled) */
-#define INTMAP_TID	0x07c000000LL	/* UPA target ID mask */
-#define INTMAP_IGN	0x0000007c0LL	/* Interrupt group no (sbus only). */
-#define INTMAP_INO	0x00000003fLL	/* Interrupt number */
-#define INTMAP_INR	(INTMAP_IGN | INTMAP_INO)
-#define INTMAP_SBUSSLOT	0x000000018LL	/* SBUS slot # */
-#define INTMAP_PCIBUS	0x000000010LL	/* PCI bus number (A or B) */
-#define INTMAP_PCISLOT	0x00000000cLL	/* PCI slot # */
-#define INTMAP_PCIINT	0x000000003LL	/* PCI interrupt #A,#B,#C,#D */
-#define INTMAP_OBIO	0x000000020LL	/* Onboard device */
-#define INTMAP_LSHIFT	11		/* Encode level in vector */
-#define	INTLEVENCODE(x)	(((x) & 0x0f) << INTMAP_LSHIFT)
-#define INTLEV(x)	(((x) >> INTMAP_LSHIFT) & 0x0f)
-#define INTVEC(x)	((x) & INTMAP_INR)
-#define INTSLOT(x)	(((x) >> 3) & 0x7)
-#define	INTPRI(x)	((x) & 0x7)
-#define	INTINO(x)	((x) & INTMAP_INO)
+#define INTMAP_V		0x080000000LL	/* Interrupt valid (enabled) */
+#define INTMAP_TID_MASK		0x07c000000LL	/* UPA target ID */
+#define INTMAP_TID_SHIFT	26
+#define INTMAP_IGN_MASK		0x0000007c0LL	/* Interrupt group no. */
+#define INTMAP_IGN_SHIFT	6
+#define INTMAP_INO_MASK		0x00000003fLL	/* Interrupt number */
+#define INTMAP_INR_MASK		(INTMAP_IGN_MASK | INTMAP_INO_MASK)
+#define INTMAP_SBUSSLOT_MASK	0x000000018LL	/* SBUS slot # */
+#define INTMAP_PCIBUS_MASK	0x000000010LL	/* PCI bus number (A or B) */
+#define INTMAP_PCISLOT_MASK	0x00000000cLL	/* PCI slot # */
+#define INTMAP_PCIINT_MASK	0x000000003LL	/* PCI interrupt #A,#B,#C,#D */
+#define INTMAP_OBIO_MASK	0x000000020LL	/* Onboard device */
+#define INTVEC(x)		((x) & INTMAP_INR_MASK)
+#define INTSLOT(x)		(((x) >> 3) & 0x7)
+#define	INTPRI(x)		((x) & 0x7)
+#define	INTINO(x)		((x) & INTMAP_INO_MASK)
+#define	INTMAP_ENABLE(mr, mid) \
+	(((mr) & ~INTMAP_TID_MASK) | ((mid) << INTMAP_TID_SHIFT) | INTMAP_V)
 
 /* counter-timer support. */
 void sparc64_counter_init(bus_space_tag_t tag, bus_space_handle_t handle,
diff --git a/sys/sparc64/pci/psycho.c b/sys/sparc64/pci/psycho.c
index 33b3faf..79e2f09 100644
--- a/sys/sparc64/pci/psycho.c
+++ b/sys/sparc64/pci/psycho.c
@@ -43,6 +43,7 @@
 #include <sys/bus.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
+#include <sys/pcpu.h>
 
 #include <ofw/openfirm.h>
 #include <ofw/ofw_pci.h>
@@ -576,7 +577,7 @@ psycho_attach(device_t dev)
 		PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V);
 		for (i = 0; i < 4; i++)
 			PCICTL_WRITE8(sc, clr + i * 8, 0);
-		PSYCHO_WRITE8(sc, map, mr | INTMAP_V);
+		PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid)));
 	}
 	for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0;
 	     map < PSR_FFB0_INT_MAP; map += 8, clr += 8, n++) {
@@ -602,7 +603,7 @@ psycho_attach(device_t dev)
 			    psycho_intr_stray, sclr);
 		}
 #endif
-		PSYCHO_WRITE8(sc, map, mr | INTMAP_V);
+		PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid)));
 	}
 #endif
 
@@ -657,7 +658,7 @@ psycho_set_intr(struct psycho_softc *sc, int index,
 		panic("psycho_set_intr: failed to get interrupt");
 	bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags,
 	    handler, sc, &sc->sc_ihand[index]);
-	PSYCHO_WRITE8(sc, map, mr | INTMAP_V);
+	PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid)));
 }
 
 static int
@@ -1126,11 +1127,10 @@ psycho_setup_intr(device_t dev, device_t child,
 	 */
 	PSYCHO_WRITE8(sc, intrclrptr, 0);
 	/*
-	 * Enable the interrupt now we have the handler installed.
-	 * Read the current value as we can't change it besides the
-	 * valid bit so so make sure only this bit is changed.
+	 * Enable the interrupt and program the target module now we have the
+	 * handler installed.
 	 */
-	PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V);
+	PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid)));
 	return (error);
 }
 
diff --git a/sys/sparc64/sbus/sbus.c b/sys/sparc64/sbus/sbus.c
index 529859a..1e6038e 100644
--- a/sys/sparc64/sbus/sbus.c
+++ b/sys/sparc64/sbus/sbus.c
@@ -111,6 +111,7 @@
 #include <sys/bus.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
+#include <sys/pcpu.h>
 #include <sys/reboot.h>
 
 #include <ofw/openfirm.h>
@@ -318,7 +319,7 @@ sbus_probe(device_t dev)
 
 	if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1)
 		panic("sbus_probe: cannot get IGN");
-	sc->sc_ign = intr & INTMAP_IGN;		/* Find interrupt group no */
+	sc->sc_ign = intr & INTMAP_IGN_MASK;	/* Find interrupt group no */
 	sc->sc_cbustag = sbus_alloc_bustag(sc);
 
 	/*
@@ -429,7 +430,7 @@ sbus_probe(device_t dev)
 		panic("sbus_probe: failed to get temperature interrupt");
 	bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST,
 	    sbus_overtemp, sc, &sc->sc_ot_ihand);
-	SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, mr | INTMAP_V);
+	SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid)));
 	rid = 0;
 	mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP);
 	vec = INTVEC(mr);
@@ -438,7 +439,7 @@ sbus_probe(device_t dev)
 		panic("sbus_probe: failed to get power fail interrupt");
 	bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST,
 	    sbus_pwrfail, sc, &sc->sc_pf_ihand);
-	SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, mr | INTMAP_V);
+	SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid)));
 
 	/* Initialize the counter-timer. */
 	sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, SBR_TC0);
@@ -519,7 +520,7 @@ sbus_setup_dinfo(struct sbus_softc *sc, phandle_t node, char *name)
 			 * Sbus card devices need the slot number encoded into
 			 * the vector as this is generally not done.
 			 */
-			if ((iv & INTMAP_OBIO) == 0)
+			if ((iv & INTMAP_OBIO_MASK) == 0)
 				iv |= slot << 3;
 			/* Set the ign as appropriate. */
 			iv |= sc->sc_ign;
@@ -660,7 +661,7 @@ sbus_setup_intr(device_t dev, device_t child,
 	intrptr = intrmapptr = intrclrptr = 0;
 	intrmap = 0;
 	inr = INTVEC(vec);
-	if ((inr & INTMAP_OBIO) == 0) {
+	if ((inr & INTMAP_OBIO_MASK) == 0) {
 		/*
 		 * We're in an SBUS slot, register the map and clear
 		 * intr registers.
@@ -709,11 +710,10 @@ sbus_setup_intr(device_t dev, device_t child,
 	 */
 	SYSIO_WRITE8(sc, intrclrptr, 0);
 	/*
-	 * Enable the interrupt now we have the handler installed.
-	 * Read the current value as we can't change it besides the
-	 * valid bit so so make sure only this bit is changed.
+	 * Enable the interrupt and program the target module now we have the
+	 * handler installed.
 	 */
-	SYSIO_WRITE8(sc, intrmapptr, intrmap, PCPU_GET(mid));
+	SYSIO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(intrmap, PCPU_GET(mid)));
 	return (error);
 }